update openlane config

crolfes · Nov 6, 2023 · a981eeb · a981eeb
1 parent d4d225b
commit a981eeb
Show file tree

Hide file tree

Showing 3 changed files with 113 additions and 1 deletion.
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
@@ -4,8 +4,51 @@
 	"DESIGN_NAME": "user_proj_example",
 	"VERILOG_FILES": [
 		"dir::../../verilog/rtl/defines.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_ctrl_constants.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_csr_addr_map.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_hasti_constants.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_dmi_constants.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_arch_options.vh",
+		"dir::../../verilog/airisc_core_complex/src/rv32_opcodes.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_PC_mux.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_alu_ops.vh",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_alu.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_decompression.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_prebuf_fifo.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_fetch.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_core.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_csr_file.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_ctrl.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_dmem_latch.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_EX_pregs.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_WB_pregs.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_decode.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_debug_module.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_debug_rom.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_periph_mux.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_wb_src_mux.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_fpu/*.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_pipeline.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_custom/src/airi5c_custom.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_mul_div/src/airi5c_mul_div.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_src_a_mux.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_src_b_mux.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_imm_gen.v",
+		"dir::../../verilog/airisc_core_complex/src/airi5c_regfile.v",	
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_dtm/src/*.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_spi/src/*.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_uart/src/*.vh",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_uart/src/*.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_gpio/src/airi5c_gpio.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_timer/src/airi5c_timer.v",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_trng/src/airi5c_trng.v",
+		"dir::../../verilog/airisc_core_complex/tb/configs/airi5c_top_asic.v",
 		"dir::../../verilog/rtl/user_proj_example.v"
 	],
+	"VERILOG_INCLUDE_DIRS": [
+		"dir::../../verilog/airisc_core_complex/src/",
+		"dir::../../verilog/airisc_core_complex/src/modules/airi5c_uart/src/"
+	],
 	"DESIGN_IS_CORE": 0,
 	"CLOCK_PORT": "wb_clk_i",
 	"CLOCK_NET": "counter.clk",
@@ -27,5 +70,6 @@
     "BASE_SDC_FILE": "dir::base_user_proj_example.sdc",
 	"RUN_HEURISTIC_DIODE_INSERTION": 1,
 	"RUN_CVC": 1,
+	"RUN_LINTER": 1,
 	"QUIT_ON_LINTER_ERRORS": 0
 }
diff --git a/verilog/airisc_core_complex b/verilog/airisc_core_complex
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
@@ -115,6 +115,74 @@ module user_proj_example #(
         .count(count)
     );
 
+    airi5c_top_asic DUT(
+        .clk(CLK),
+        .nreset(nRESET),
+        .ext_interrupt(EXT_INT),
+
+        .tdi(tdi),
+        .tdo(tdo),
+        .tms(tms),
+        .tck(tck),
+
+        .testmode(testmode),
+        .sdi(sdi),
+        .sdo(sdo),
+        .sen(sen),
+
+        .imem_haddr(imem_haddr),
+        .imem_hwrite(imem_hwrite),
+        .imem_hsize(imem_hsize),
+        .imem_hburst(imem_hburst),
+        .imem_hmastlock(imem_hmastlock),
+        .imem_hprot(imem_hprot),
+        .imem_htrans(imem_htrans),
+        .imem_hwdata(imem_hwdata),
+        .imem_hrdata(imem_hrdata),
+        .imem_hready(imem_hready),
+        .imem_hresp(imem_hresp),
+
+        .dmem_haddr(dmem_haddr),
+        .dmem_hwrite(dmem_hwrite),
+        .dmem_hsize(dmem_hsize),
+        .dmem_hburst(dmem_hburst),
+        .dmem_hmastlock(dmem_hmastlock),
+        .dmem_hprot(dmem_hprot),
+        .dmem_htrans(dmem_htrans),
+        .dmem_hwdata(dmem_hwdata),
+        .dmem_hrdata(dmem_hrdata),
+        .dmem_hready(dmem_hready),
+        .dmem_hresp(dmem_hresp),
+
+      // GPIO 0
+        .gpio0_out(gpio0_out),
+        .gpio0_in(gpio0_in),
+        .gpio0_oe(gpio0_oe),
+
+      // UART 0
+        .uart0_tx(uart0_tx),
+        .uart0_rx(uart0_rx),
+
+      // SPI 0
+        .spi0_mosi_out(spi0_mosi_out),
+        .spi0_mosi_in(spi0_mosi_in),
+        .spi0_mosi_oe(spi0_mosi_oe),
+
+        .spi0_miso_out(spi0_miso_out),
+        .spi0_miso_in(spi0_miso_in),
+        .spi0_miso_oe(spi0_miso_oe),
+
+        .spi0_sclk_out(spi0_sclk_out),
+        .spi0_sclk_in(spi0_sclk_in),
+        .spi0_sclk_oe(spi0_sclk_oe),
+
+        .spi0_ss_out(spi0_ss_out),
+        .spi0_ss_in(spi0_ss_in),
+        .spi0_ss_oe(spi0_ss_oe),
+
+        .debug_out(debug_out)
+    );
+
 endmodule
 
 module counter #(