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Perhaps automatically debounce on flows through resistors to a capacitor #14

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cube1us opened this issue Mar 27, 2020 · 1 comment
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LogicSynth These issues relate to HDL logic synthesis todo These provide a laundry list of things that need to be done

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cube1us commented Mar 27, 2020

If a signal flows through a resistor to a capacitor on the other side, consider generating some kind of delay/debounce automagically.

@cube1us cube1us added LogicSynth These issues relate to HDL logic synthesis todo These provide a laundry list of things that need to be done labels Mar 27, 2020
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cube1us commented Jun 21, 2020

Leaning towards not fixing this, and doing debouncing on whatever provides switch settings.

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LogicSynth These issues relate to HDL logic synthesis todo These provide a laundry list of things that need to be done
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