DOT Functions from SDTRL vs DTL may not be right

[cube1us]

If a DOT function is fed from SDTRL NAND gates (S level) it is an
OR. If it is fed from DTL (NOR or NAND, depending on the diodes) gates (B Level)
it is an AND !!!!! [NEED TO RETHINK THIS. B Level? Y Level? It looks like for
Y level it would still be an OR.]

Related: Currently the DOT function type (AND vs OR) is kind of arbitrarily determined by looking at the logic blocks that feed it. As it stands, that information is certainly not good enough to depend on for logic synthesis. Once the first question is resolved, then a report might be generated to fix those up - though the issue of negative-logic vs. positive-logic DOT functions could confound any attempts to standardize it.

[cube1us]

Note that this "OR" and "AND" is just how the DOT function is labelled - it has nothing to do with the electrical behavior of the DOT function.

[cube1us]

DOT functions for SDTRL have been verified as "OR", i.e., if one gate is +S by turning its transistor on, then the other gates connected to its output will also be forced to +S.