Clean up generation in the presence of gates where HDL is disabled

[cube1us]

Sometimes one disables gates for HDL generation (example: Disabling gates for feature S10 (10K only memory) on an IBM 1410). When this is done, the generation code ignores that gate, but should also ignore all the connections from it and to it, including any sheet edge input signals which connect solely to that gate, any output signals originating solely at that gate, along with any gate to gate or gate to DOT function connections involving that gate, and issue messages relating to the connections removed.

So far, the fact that this is not done results in error messages but the HDL generation is satisfactory.