[HDL] Registerless Hardware Description

[soronpo]

Author(s): Oron Port and Yoav Etsion
Paper PDF: https://capra.cs.cornell.edu/latte21/paper/4.pdf
Talk Recording: https://youtu.be/_kpwAtg7TgI
More information: https://dfianthdl.github.io/intro/first-look/

[stephenneuendorffer]

It seems like an interesting use of 'pipe' is that in RTL, those registers don't need to be reset and could be initialized differently?

[soronpo]

Their initial values are derived from the dataflow dependency. E.g.:

val x = DFUInt(8) <> IN init 3
val out = DFUInt(8) <> OUT
out := (x.prev + x.prev(2)).pipe

Here out will first get the initial value 6.

[sampsyo]

Super cool project! Out of curiosity, have you tried using DFiant to teach any courses? I'm curious whether students would like it more than a traditional RTL language as a first brush with hardware design, or whether they'd miss the "directness" of knowing where the registers go.

[soronpo]

Thanks! Yes, we taught it long ago, at a more nubile state of the language. Most students liked the concept. Most complaints were about bugs that are now solved (but there are new bugs 😄) and lack of documentation (still an issue).