[Intel][ARL][IMC] DDR5: tWR = tWRPRE - tCWL - 10

cyring · Oct 15, 2024 · 2499c3c · 2499c3c
1 parent bd528a9
commit 2499c3c
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/x86_64/corefreqd.c b/x86_64/corefreqd.c
@@ -6183,7 +6183,7 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 		tWR_quantity = 4U;
 		break;
 	case 5:
-		tWR_quantity = 8U;
+		tWR_quantity = 10U;
 		break;
 	}
       if (RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.Timing.tWRPRE >=