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Update "unsigned" and "typedef" guidelines to ease MISRA conformance
Add MISRA analysis spreadsheet Signed-off-by: Dan Handley <[email protected]>
Add Coverity MISRA analysis page
Add link to Coverity MISRA analysis page
Updated link to latest CVE-2017-5715 mitigation specification
ACTLR typo
Updated variant 2 mitigation for Cortex-A8
Updated with link to PR1240
Add link to PR with Variant 2 workaround reference code on AArch32 EL3 systems
Create TFV-6
Add TFV-6 link
Add fix information for TFV-5
Fix advisory links
Create TFV-5
Add link to TFV-5
Add TFV-4 content
Add TFV-4 link
Remove contacts link
Destroyed ARM Trusted Firmware Contacts (markdown)
Adding Fix Version information
Add TFV-3
Fix TFV-2 links
Add TFV-2
Added CVE
Clarification that correct bl1_plat_mem_check() implentatation does not guarantee prevention of exploit
Updated with more Juno platform info and explanation for anamoly in "CPU_SUSPEND to power level 0 on all CPUs in parallel"
Add link to PSCI Performance on Juno page
Updated ARM Trusted Firmware PSCI Performance on Juno (markdown)