From 2e3b80b11435167906f78099c28d08b7afc1a776 Mon Sep 17 00:00:00 2001 From: Dan Smathers Date: Thu, 8 Feb 2024 21:16:29 -0700 Subject: [PATCH] Draft: Add m/s-mode CLIC interrupt testcases This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: https://github.com/riscv-software-src/riscv-config/pull/169, https://github.com/riscv-software-src/riscof/pull/106 https://github.com/riscv-software-src/riscv-isa-sim/pull/1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers --- coverage/rvi_smclic.cgf | 54 +++++++++++++++++++++++ coverage/rvi_ssclic.cgf | 96 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 coverage/rvi_smclic.cgf create mode 100644 coverage/rvi_ssclic.cgf diff --git a/coverage/rvi_smclic.cgf b/coverage/rvi_smclic.cgf new file mode 100644 index 000000000..19d397e09 --- /dev/null +++ b/coverage/rvi_smclic.cgf @@ -0,0 +1,54 @@ +clicdirect-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +cliclevel-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +cliclevel-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +cliclevel-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +cliclevel-04: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +clicnomint-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +clicnomint-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +clicnomint-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +clicwfi-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Smclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + diff --git a/coverage/rvi_ssclic.cgf b/coverage/rvi_ssclic.cgf new file mode 100644 index 000000000..214f65747 --- /dev/null +++ b/coverage/rvi_ssclic.cgf @@ -0,0 +1,96 @@ +sclicdeleg-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicmdisable-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicmdisable-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicmdisable-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicnodeleg-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicorder-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicorder-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicorder-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicorder-04: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicprivorder-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicprivorder-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicprivorder-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 + +sclicsdisable-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicsdisable-02: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicsdisable-03: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 0: 0 + +sclicwfi-01: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssclic.*); def rvtest_mtrap_routine=True + csr_comb: + mcause >> (xlen-1) == 1: 0 +