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Release 14.6 - platgen Xilinx EDK 14.6 Build EDK_P.68d
(nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc6slx45fgg676-2 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable
is set to '2100@licserver'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@licserver'.
INFO:Security:71 - If a license for part 'xc6slx45' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse D:/djole/FBless_2D_GPU/system.mhs ...
Read MPD definitions ...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ENDIANNESS value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 198
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ICACHE_USE_FSL value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 339
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_USE_FSL value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 369
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_BASEFAMILY value to spartan6 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock 'vga_periph_0_clk_i_pin' is
not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this
core and cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this
core and cores connected to it.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x00007fff) microblaze_0_d_bram_ctrl microblaze_0_dlmb
(0000000000-0x00007fff) microblaze_0_i_bram_ctrl microblaze_0_ilmb
(0x40600000-0x4060ffff) RS232 axi4lite_0
(0x41400000-0x4140ffff) debug_module axi4lite_0
(0x7de00000-0x7de0ffff) my_peripheral_0 axi4lite_0
(0xc0000000-0xc3ffffff) vga_periph_mem_0 axi4lite_0
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is
overriding PARAMETER C_MEMSIZE value to 0x8000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
ata\bram_block_v2_1_0.mpd line 78
Checking platform address map ...
Checking platform configuration ...
IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 4 slave(s)
WARNING:EDK:3977 - AXI4 protocol type BUSIF: S_AXI of IPINSTANCE:
vga_periph_mem_0 connected with AXI4LITE type BUSIF: M_AXI_DP of IPINSTANCE:
microblaze_0.
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -
tcl is overriding PARAMETER C_MASK value to 0x40000000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -
tcl is overriding PARAMETER C_MASK value to 0x40000000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_D_AXI value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 232
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ADDR_TAG_BITS value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 337
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_ADDR_TAG value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 367
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_BRK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 402
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_NM_BRK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 403
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: Setting timing constaints for microblaze_0_ilmb.
INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS
in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0_dlmb.
INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS
in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0.
INFO: The microblaze_0 core has constraints automatically generated by XPS in
implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:vga_periph_mem INSTANCE:vga_periph_mem_0 -
D:\djole\FBless_2D_GPU\system.mhs line 169 - Copying (BBD-specified) netlist
files.
Managing cache ...
Elaborating instances ...
IPNAME:bram_block INSTANCE:microblaze_0_bram_block -
D:\djole\FBless_2D_GPU\system.mhs line 79 - elaborating IP
IPNAME:clock_generator INSTANCE:clock_generator_0 -
D:\djole\FBless_2D_GPU\system.mhs line 122 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:proc_sys_reset_0 - D:\djole\FBless_2D_GPU\system.mhs line 34 - Running
XST synthesis
INSTANCE:microblaze_0_ilmb - D:\djole\FBless_2D_GPU\system.mhs line 47 - Running
XST synthesis
INSTANCE:microblaze_0_i_bram_ctrl - D:\djole\FBless_2D_GPU\system.mhs line 54 -
Running XST synthesis
INSTANCE:microblaze_0_dlmb - D:\djole\FBless_2D_GPU\system.mhs line 63 - Running
XST synthesis
INSTANCE:microblaze_0_d_bram_ctrl - D:\djole\FBless_2D_GPU\system.mhs line 70 -
Running XST synthesis
INSTANCE:microblaze_0_bram_block - D:\djole\FBless_2D_GPU\system.mhs line 79 -
Running XST synthesis
INSTANCE:microblaze_0 - D:\djole\FBless_2D_GPU\system.mhs line 86 - Running XST
synthesis
INSTANCE:debug_module - D:\djole\FBless_2D_GPU\system.mhs line 109 - Running XST
synthesis
INSTANCE:clock_generator_0 - D:\djole\FBless_2D_GPU\system.mhs line 122 -
Running XST synthesis
INSTANCE:axi4lite_0 - D:\djole\FBless_2D_GPU\system.mhs line 135 - Running XST
synthesis
INSTANCE:rs232 - D:\djole\FBless_2D_GPU\system.mhs line 143 - Running XST
synthesis
INSTANCE:my_peripheral_0 - D:\djole\FBless_2D_GPU\system.mhs line 158 - Running
XST synthesis
INSTANCE:vga_periph_mem_0 - D:\djole\FBless_2D_GPU\system.mhs line 169 - Running
XST synthesis
Running NGCBUILD ...
IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -
D:\djole\FBless_2D_GPU\system.mhs line 47 - Running NGCBUILD
IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -
D:\djole\FBless_2D_GPU\system.mhs line 63 - Running NGCBUILD
IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -
D:\djole\FBless_2D_GPU\system.mhs line 86 - Running NGCBUILD
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
D:\djole\FBless_2D_GPU\system.mhs line 122 - Running NGCBUILD
IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -
D:\djole\FBless_2D_GPU\system.mhs line 135 - Running NGCBUILD
IPNAME:system_vga_periph_mem_0_wrapper INSTANCE:vga_periph_mem_0 -
D:\djole\FBless_2D_GPU\system.mhs line 169 - Running NGCBUILD
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 134.00 seconds