From 0346e95f104d47e02d47e31272d71174b60ba253 Mon Sep 17 00:00:00 2001 From: Damien Pretet Date: Sun, 8 Oct 2023 20:17:03 +0200 Subject: [PATCH] Connect PMP/PMA excpetions --- README.md | 3 +- doc/privilege.md | 17 +++- doc/project_mgt_hw.md | 7 +- doc/project_mgt_sw.md | 23 +++-- rtl/friscv_control.sv | 81 ++++++++++++------ rtl/friscv_debug_h.sv | 64 +++++++------- rtl/friscv_h.sv | 35 ++++++-- rtl/friscv_memfy.sv | 38 ++++++--- rtl/friscv_processing.sv | 12 +-- rtl/friscv_rv32i_core.sv | 90 ++++++++++---------- test/common/friscv_testbench.sv | 4 +- test/priv_sec_testsuite/tests/rv64ui/test2.S | 4 +- 12 files changed, 237 insertions(+), 141 deletions(-) diff --git a/README.md b/README.md index 61fcf4f..d75feb7 100644 --- a/README.md +++ b/README.md @@ -24,8 +24,7 @@ FRISCV is a SystemVerilog implementation of the [RISCV ISA](https://riscv.org): - Privilege modes: - Machine-mode only for simple embedded system - User-mode for secure embedded system -- Physical memory protection (PMP) -- Physical memory attribute (PMA) +- Physical memory protection (PMP) & Physical Memory Attribute (PMA), up to 16 regions - External, software and timer interrupts - Support multiple (optional) extensions: - RV32I & RV32E architecture diff --git a/doc/privilege.md b/doc/privilege.md index e314ba2..1f9e6e1 100644 --- a/doc/privilege.md +++ b/doc/privilege.md @@ -81,7 +81,11 @@ The privilege modes support have been designed based on RISC-V ISA specification - mcountinhibit: stop a specific counter - Machine Environment Configuration Registers (menvcfg and menvcfgh) -## PMP +## PMP / PMA + +To support secure processing and contain faults, it is desirable to limit the physical addresses +accessible by software running on a hart. PMP violations are always trapped precisely at the +processor. PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit @@ -177,6 +181,17 @@ to TOR, address 0x00 is the lower bound) [Sifive slides](https://cdn2.hubspot.net/hubfs/3020607/SiFive-RISCVCoreIP.pdf?t=1512606290763) + +Test: +- read/execute instruction outside allowed regions (U-mode) +- read/write data in U-mode +- read/write data in M-mode with MPRV + MPP w/ U-mode + -> Store = store access-fault + -> Load = load access-fault + -> Execute = instruction access-fault +- all region configuration mode + + ## Interrupts - WFI: diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md index c62db81..156b8fa 100644 --- a/doc/project_mgt_hw.md +++ b/doc/project_mgt_hw.md @@ -97,7 +97,7 @@ Any new features should be carefully study to ensure a proper exception and inte - [ ] Out of order support in AXI (memfy if not using cache) -## Control +## Control / CSR - [ ] Detect IO requests to forward info for FENCE execution - [ ] Branch prediction @@ -107,6 +107,7 @@ Any new features should be carefully study to ensure a proper exception and inte - [ ] https://github.com/tommythorn/yarvi/blob/master/rtl/yarvi.v#L184 - [ ] https://danluu.com/branch-prediction - [ ] Rewind pipeline (L0 local cache) +- [ ] Pipeline PMP CSR up to MPU setup path and stop the core with csr_ready during few cycles ## Processing @@ -115,7 +116,7 @@ Any new features should be carefully study to ensure a proper exception and inte - [ ] Memfy: - If not ready, and request present, the FSM can’t drive further data - Manage RRESP/BRESP in the exception bus -- [ ] Support F extension +- [ ] Support F extension: https://bellard.org/softfp/ - [ ] Division - [ ] Save bandwidth by removing dead cycles - [ ] Manage pow2 division by shifting @@ -163,6 +164,8 @@ Any new features should be carefully study to ensure a proper exception and inte # Ideas / Applications +- [ ] Include a DMA in platform + - must respect PMP / PMA - [ ] Next CPU architecture: - Super scalar architecture - https://en.m.wikipedia.org/wiki/Instruction-level_parallelism diff --git a/doc/project_mgt_sw.md b/doc/project_mgt_sw.md index 0916e2d..ad6a702 100644 --- a/doc/project_mgt_sw.md +++ b/doc/project_mgt_sw.md @@ -9,13 +9,13 @@ - [ ] https://github.com/ssloy/tinyraytracer - [ ] Type conversion - [ ] Image resizer - - [ ] Generate images with lines, triangles, ray tracing… 24fps - - [ ] https://github.com/ssloy/tinyrenderer/wiki/Lesson-2:-Triangle-rasterization-and-back-face-culling - - [ ] https://gabrielgambetta.com/computer-graphics-from-scratch/07-filled-triangles.html - - [ ] https://github.com/OscarSaharoy/ascii-raytrace - - [ ] https://fabiensanglard.net/another_world_polygons/ - - [ ] Hash table https://github.com/PerformanC/tablec/tree/closed-addressing - - [ ] CoreMark https://github.com/eembc/coremark + - [ ] Generate images with lines, triangles, ray tracing… 24fps + - [ ] https://github.com/ssloy/tinyrenderer/wiki/Lesson-2:-Triangle-rasterization-and-back-face-culling + - [ ] https://gabrielgambetta.com/computer-graphics-from-scratch/07-filled-triangles.html + - [ ] https://github.com/OscarSaharoy/ascii-raytrace + - [ ] https://fabiensanglard.net/another_world_polygons/ + - [ ] Hash table https://github.com/PerformanC/tablec/tree/closed-addressing + - [ ] CoreMark https://github.com/eembc/coremark # BACKLOG @@ -65,7 +65,11 @@ Minimalistic Unix # Ideas / Applications -- [ ] Support Linux / FreeBSD / NetBSD: https://github.com/cnlohr/mini-rv32ima +- [ ] Try https://github.com/berry-lang/berry +- [ ] Try +- [ ] Support Linux / FreeBSD / NetBSD + - https://github.com/cnlohr/mini-rv32ima + - https://popovicu.com/posts/789-kb-linux-without-mmu-riscv/ - [ ] Code Pong with AI for auto game - [ ] Run Doom: https://www.youtube.com/watch?v=uZMNK17VCMU&list=WL&index=1&t=2s - [ ] Code the game of life @@ -86,7 +90,8 @@ Minimalistic Unix - Able to update the FPGA bitstream with the new program - [ ] Implement a neural network with the processor and TF lite - [ ] Retro gaming platform - +- [ ] Try Rust + - https://popovicu.com/posts/bare-metal-rust-risc-v-with-dynamic-memory/ DONE: - [X] Pool arena / malloc-free / integrated in benchmark diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index 0e81cbe..082bf11 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -73,7 +73,7 @@ module friscv_control input wire proc_ready, output logic [`INST_BUS_W -1:0] proc_instbus, input wire [4 -1:0] proc_fenceinfo, - input wire [2 -1:0] proc_exceptions, + input wire [`PROC_EXP_W -1:0] proc_exceptions, input wire proc_busy, // interface to activate teh CSR management output logic csr_en, @@ -90,8 +90,8 @@ module friscv_control output logic [5 -1:0] ctrl_rd_addr, output logic [XLEN -1:0] ctrl_rd_val, // PMP / PMA Check - output logic [AXI_ADDR_W -1:0] pmp_addr, - input wire [4 -1:0] pmp_allow, + output logic [AXI_ADDR_W -1:0] mpu_addr, + input wire [4 -1:0] mpu_allow, // CSR shared bus input wire [`CSR_SB_W -1:0] csr_sb, output logic [`CTRL_SB_W -1:0] ctrl_sb @@ -211,14 +211,21 @@ module friscv_control logic [XLEN -1:0] mtval_info; logic load_misaligned; logic store_misaligned; + logic inst_access_fault; logic illegal_instruction; - logic wfi_not_allowed; + logic wfi_tw; logic trap_occuring; logic sync_trap_occuring; logic async_trap_occuring; logic ecall_umode; logic ecall_mmode; logic [2 -1:0] priv_mode; + logic load_access_fault; + logic store_access_fault; + + logic [`EXP_INST_W-1:0] exp_inst; + logic [`EXP_ADDR_W-1:0] exp_addr; + logic [`EXP_PC_W -1:0] exp_pc; // Logger setup `ifdef USE_SVL @@ -462,17 +469,19 @@ module friscv_control assign csr_en = inst_ready && sys[`IS_CSR] & (cfsm==FETCH) & !proc_busy; - assign proc_instbus[`OPCODE +: `OPCODE_W] = opcode; - assign proc_instbus[`FUNCT3 +: `FUNCT3_W] = funct3; - assign proc_instbus[`FUNCT7 +: `FUNCT7_W] = funct7; - assign proc_instbus[`RS1 +: `RS1_W ] = rs1 ; - assign proc_instbus[`RS2 +: `RS2_W ] = rs2 ; - assign proc_instbus[`RD +: `RD_W ] = rd ; - assign proc_instbus[`ZIMM +: `ZIMM_W ] = zimm ; - assign proc_instbus[`IMM12 +: `IMM12_W ] = imm12 ; - assign proc_instbus[`IMM20 +: `IMM20_W ] = imm20 ; - assign proc_instbus[`CSR +: `CSR_W ] = csr ; - assign proc_instbus[`SHAMT +: `SHAMT_W ] = shamt ; + assign proc_instbus[`OPCODE +: `OPCODE_W ] = opcode; + assign proc_instbus[`FUNCT3 +: `FUNCT3_W ] = funct3; + assign proc_instbus[`FUNCT7 +: `FUNCT7_W ] = funct7; + assign proc_instbus[`RS1 +: `RS1_W ] = rs1 ; + assign proc_instbus[`RS2 +: `RS2_W ] = rs2 ; + assign proc_instbus[`RD +: `RD_W ] = rd ; + assign proc_instbus[`ZIMM +: `ZIMM_W ] = zimm ; + assign proc_instbus[`IMM12 +: `IMM12_W ] = imm12 ; + assign proc_instbus[`IMM20 +: `IMM20_W ] = imm20 ; + assign proc_instbus[`CSR +: `CSR_W ] = csr ; + assign proc_instbus[`SHAMT +: `SHAMT_W ] = shamt ; + assign proc_instbus[`INST +: `INST_W ] = instruction; + assign proc_instbus[`PC +: `PC_W ] = pc_reg; assign csr_instbus = proc_instbus; @@ -561,7 +570,7 @@ module friscv_control assign pc_val = pc_reg; - assign pmp_addr = pc_reg; + assign mpu_addr = pc_reg; assign flush_reqs = flush_pipe; @@ -1022,6 +1031,7 @@ module friscv_control // // ISA registers write stage // + //(inst_access_fault) ? exp_pc : /////////////////////////////////////////////////////////////////////////// // register source 1 & 2 read @@ -1148,20 +1158,31 @@ module friscv_control // illegal instruction exception. An implementation may have WFI always raise an illegal instruction // exception in less-privileged modes when TW=1, even if there are pending globally-disabled interrupts // when the instruction is executed. TW is read-only 0 when there are no modes less privileged than M. - assign wfi_not_allowed = 1'b0; - - assign load_misaligned = proc_exceptions[`LD_MA]; - assign store_misaligned = proc_exceptions[`ST_MA]; + assign wfi_tw = 1'b0; assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready; + assign inst_access_fault = (!mpu_allow[`PMA_X] | !mpu_allow[`PMA_R]) & (priv_mode == `UMODE); + + assign load_misaligned = proc_exceptions[`LDMA]; + + assign store_misaligned = proc_exceptions[`STMA]; + + assign load_access_fault = proc_exceptions[`LAF]; + + assign store_access_fault = proc_exceptions[`SAF]; + + assign exp_pc = proc_exceptions[`EXP_PC +: `EXP_PC_W]; + + assign exp_inst = proc_exceptions[`EXP_INST +: `EXP_INST_W]; + + assign exp_addr = proc_exceptions[`EXP_ADDR +: `EXP_ADDR_W]; + generate if (USER_MODE) begin: UMODE_EXPEC assign illegal_instruction = (priv_mode==`MMODE) ? '0 : (sys[`IS_MRET]) ? inst_ready : (sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready : - // Check if WFI must be trapped or not - // (sys[`IS_WFI] ) ? inst_ready : '0; end else begin : NO_UMODE assign illegal_instruction = '0; @@ -1213,6 +1234,9 @@ module friscv_control // | 3 | Environment break // | 3 | Load/Store/AMO address breakpoint // ------------------------------------------------------------------------ + // | 5 | Load access fault + // | 7 | Store access fault + // ------------------------------------------------------------------------ // | 6 | Store/AMO address misaligned // | 4 | Load address misaligned // ------------------------------------------------------------------------ @@ -1231,21 +1255,27 @@ module friscv_control (sb_mtip) ? {1'b1, {XLEN-5{1'b0}}, 4'h7} : (sb_meip) ? {1'b1, {XLEN-5{1'b0}}, 4'hB} : // then follow sync exceptions + (inst_access_fault) ? {{XLEN-4{1'b0}}, 4'h1} : (illegal_instruction) ? {{XLEN-4{1'b0}}, 4'h2} : (csr_ro_wr) ? {{XLEN-4{1'b0}}, 4'h2} : (inst_addr_misaligned) ? '0 : (ecall_umode) ? {{XLEN-4{1'b0}}, 4'h8} : (ecall_mmode) ? {{XLEN-4{1'b0}}, 4'hB} : (sys[`IS_EBREAK]) ? {{XLEN-4{1'b0}}, 4'h3} : - (store_misaligned) ? {{XLEN-4{1'b0}}, 4'h6} : + (load_access_fault) ? {{XLEN-4{1'b0}}, 4'h5} : + (store_access_fault) ? {{XLEN-4{1'b0}}, 4'h7} : (load_misaligned) ? {{XLEN-4{1'b0}}, 4'h4} : + (store_misaligned) ? {{XLEN-4{1'b0}}, 4'h6} : (inst_dec_error) ? {{XLEN-5{1'b0}}, 5'h18} : '0; // MTVAL: exception-specific information assign mtval_info = (inst_dec_error) ? instruction : - (wfi_not_allowed) ? instruction : + (wfi_tw) ? instruction : (illegal_instruction) ? instruction : + (inst_access_fault) ? pc_reg : + (load_access_fault) ? exp_pc : + (store_access_fault) ? exp_pc : (inst_dec_error) ? instruction : (csr_ro_wr) ? instruction : (inst_addr_misaligned) ? pc_reg : @@ -1262,6 +1292,9 @@ module friscv_control load_misaligned | illegal_instruction | store_misaligned | + inst_access_fault | + load_access_fault | + store_access_fault | inst_dec_error ; assign trap_occuring = async_trap_occuring | sync_trap_occuring; diff --git a/rtl/friscv_debug_h.sv b/rtl/friscv_debug_h.sv index b4a3cea..9dd0e61 100644 --- a/rtl/friscv_debug_h.sv +++ b/rtl/friscv_debug_h.sv @@ -4,37 +4,37 @@ `ifndef FRISCV_DEBUG `define FRISCV_DEBUG -`define PC 0 -`define X1 1 -`define X2 2 -`define X3 3 -`define X4 4 -`define X5 5 -`define X6 6 -`define X7 7 -`define X8 8 -`define X9 9 -`define X10 10 -`define X11 11 -`define X12 12 -`define X13 13 -`define X14 14 -`define X15 15 -`define X16 16 -`define X17 17 -`define X18 18 -`define X19 19 -`define X20 20 -`define X21 21 -`define X22 22 -`define X23 23 -`define X24 24 -`define X25 25 -`define X26 26 -`define X27 27 -`define X28 28 -`define X29 29 -`define X30 30 -`define X31 31 +`define DBG_PC 0 +`define DBG_X1 1 +`define DBG_X2 2 +`define DBG_X3 3 +`define DBG_X4 4 +`define DBG_X5 5 +`define DBG_X6 6 +`define DBG_X7 7 +`define DBG_X8 8 +`define DBG_X9 9 +`define DBG_X10 10 +`define DBG_X11 11 +`define DBG_X12 12 +`define DBG_X13 13 +`define DBG_X14 14 +`define DBG_X15 15 +`define DBG_X16 16 +`define DBG_X17 17 +`define DBG_X18 18 +`define DBG_X19 19 +`define DBG_X20 20 +`define DBG_X21 21 +`define DBG_X22 22 +`define DBG_X23 23 +`define DBG_X24 24 +`define DBG_X25 25 +`define DBG_X26 26 +`define DBG_X27 27 +`define DBG_X28 28 +`define DBG_X29 29 +`define DBG_X30 30 +`define DBG_X31 31 `endif diff --git a/rtl/friscv_h.sv b/rtl/friscv_h.sv index c84c1cd..45daf13 100644 --- a/rtl/friscv_h.sv +++ b/rtl/friscv_h.sv @@ -146,6 +146,8 @@ `define SHAMT_W 5 `define PRED_W 4 `define SUCC_W 4 +`define PC_W `XLEN +`define INST_W `XLEN // instruction bus fields's index `define OPCODE 0 @@ -159,15 +161,38 @@ `define IMM20 `IMM12 + `IMM12_W `define CSR `IMM20 + `IMM20_W `define SHAMT `CSR + `CSR_W +`define PC `SHAMT + `SHAMT_W +`define INST `PC + `PC_W // total length of ALU instruction bus `define INST_BUS_W `OPCODE_W + `FUNCT3_W + `FUNCT7_W + `RS1_W + `RS2_W + \ - `RD_W + `ZIMM_W + `IMM12_W + `IMM20_W + `CSR_W + `SHAMT_W + `RD_W + `ZIMM_W + `IMM12_W + `IMM20_W + `CSR_W + `SHAMT_W + \ + `PC_W + `INST_W -// Load misaligned in memfy -`define LD_MA 0 -// Store misaligned in memfy -`define ST_MA 1 +////////////////////////////////////////////////////////////////// +// Excpetion bus fron Memfy to Control unit +////////////////////////////////////////////////////////////////// + +`define EXP_PC_W `XLEN +`define EXP_INST_W `XLEN +`define EXP_ADDR_W `XLEN + +// PC raising the exception +`define EXP_PC 0 +// Instruction raising the expection +`define EXP_INST `EXP_PC + `EXP_PC_W +// Address raising hte exception +`define EXP_ADDR `EXP_INST + `EXP_INST_W +// Load misaligned +`define LDMA `EXP_ADDR + `EXP_ADDR_W +// Store misaligned +`define STMA `LDMA + 1 +// Load access fault +`define LAF `STMA + 1 +// Store access fault +`define SAF `LAF + 1 + +`define PROC_EXP_W `SAF + 1 ////////////////////////////////////////////////////////////////// // CSR Shared Bus Definition diff --git a/rtl/friscv_memfy.sv b/rtl/friscv_memfy.sv index 3a7f527..6a7a7bc 100644 --- a/rtl/friscv_memfy.sv +++ b/rtl/friscv_memfy.sv @@ -75,7 +75,7 @@ module friscv_memfy output logic [NB_INT_REG -1:0] memfy_regs_sts, output logic [4 -1:0] memfy_fenceinfo, input wire [`INST_BUS_W -1:0] memfy_instbus, - output logic [2 -1:0] memfy_exceptions, + output logic [`PROC_EXP_W -1:0] memfy_exceptions, // register source 1 query interface output logic [5 -1:0] memfy_rs1_addr, input wire [XLEN -1:0] memfy_rs1_val, @@ -88,8 +88,8 @@ module friscv_memfy output logic [XLEN -1:0] memfy_rd_val, output logic [XLEN/8 -1:0] memfy_rd_strb, // PMP / PMA Checks - output logic [AXI_ADDR_W -1:0] pmp_addr, - input wire [4 -1:0] pmp_allow, + output logic [AXI_ADDR_W -1:0] mpu_addr, + input wire [4 -1:0] mpu_allow, // data memory interface output logic awvalid, input wire awready, @@ -297,6 +297,8 @@ module friscv_memfy logic [`OPCODE_W -1:0] opcode_r; logic [`FUNCT3_W -1:0] funct3_r; logic [`RD_W -1:0] rd_r; + logic [`EXP_INST_W -1:0] inst; + logic [`EXP_PC_W -1:0] pc; logic load_misaligned; logic store_misaligned; @@ -335,12 +337,14 @@ module friscv_memfy // /////////////////////////////////////////////////////////////////////////// - assign opcode = memfy_instbus[`OPCODE +: `OPCODE_W]; - assign funct3 = memfy_instbus[`FUNCT3 +: `FUNCT3_W]; - assign rs1 = memfy_instbus[`RS1 +: `RS1_W ]; - assign rs2 = memfy_instbus[`RS2 +: `RS2_W ]; - assign rd = memfy_instbus[`RD +: `RD_W ]; - assign imm12 = memfy_instbus[`IMM12 +: `IMM12_W ]; + assign opcode = memfy_instbus[`OPCODE +: `OPCODE_W ]; + assign funct3 = memfy_instbus[`FUNCT3 +: `FUNCT3_W ]; + assign rs1 = memfy_instbus[`RS1 +: `RS1_W ]; + assign rs2 = memfy_instbus[`RS2 +: `RS2_W ]; + assign rd = memfy_instbus[`RD +: `RD_W ]; + assign imm12 = memfy_instbus[`IMM12 +: `IMM12_W ]; + assign pc = memfy_instbus[`EXP_PC +: `EXP_PC_W ]; + assign inst = memfy_instbus[`EXP_INST +: `EXP_INST_W]; /////////////////////////////////////////////////////////////////////////// @@ -705,7 +709,7 @@ module friscv_memfy // The address to access during a LOAD or a STORE assign addr = $signed({{(XLEN-12){imm12[11]}}, imm12}) + $signed(memfy_rs1_val); - assign pmp_addr = addr; + assign mpu_addr = addr; // Unused: information forwarded to control unit for FENCE execution: // bit 0: memory write @@ -814,9 +818,19 @@ module friscv_memfy (opcode==`STORE && funct3==`SW && addr[1:0]!=2'b0) ? 1'b1 : 1'b0 ; - assign memfy_exceptions[`LD_MA] = load_misaligned & memfy_valid & memfy_ready; + assign memfy_exceptions[`LAF] = memfy_valid & memfy_ready & (opcode==`LOAD) & !mpu_allow[`PMA_R]; - assign memfy_exceptions[`ST_MA] = store_misaligned & memfy_valid & memfy_ready; + assign memfy_exceptions[`SAF] = memfy_valid & memfy_ready & (opcode==`STORE) & !mpu_allow[`PMA_W]; + + assign memfy_exceptions[`LDMA] = memfy_valid & memfy_ready & load_misaligned; + + assign memfy_exceptions[`STMA] = memfy_valid & memfy_ready & store_misaligned; + + assign memfy_exceptions[`EXP_PC +: `EXP_PC_W] = pc; + + assign memfy_exceptions[`EXP_INST +: `EXP_INST_W] = inst; + + assign memfy_exceptions[`EXP_ADDR +: `EXP_ADDR_W] = addr; endmodule diff --git a/rtl/friscv_processing.sv b/rtl/friscv_processing.sv index a7703b3..d43984f 100644 --- a/rtl/friscv_processing.sv +++ b/rtl/friscv_processing.sv @@ -53,7 +53,7 @@ module friscv_processing input wire [`INST_BUS_W -1:0] proc_instbus, output logic [4 -1:0] proc_fenceinfo, output logic proc_busy, - output logic [2 -1:0] proc_exceptions, + output logic [`PROC_EXP_W -1:0] proc_exceptions, // ISA registers interface output logic [NB_UNIT*5 -1:0] proc_rs1_addr, input wire [NB_UNIT*XLEN -1:0] proc_rs1_val, @@ -64,8 +64,8 @@ module friscv_processing output logic [NB_UNIT*XLEN -1:0] proc_rd_val, output logic [NB_UNIT*XLEN/8 -1:0] proc_rd_strb, // PMP / PMA Checks - output logic [AXI_ADDR_W -1:0] pmp_addr, - input wire [4 -1:0] pmp_allow, + output logic [AXI_ADDR_W -1:0] mpu_addr, + input wire [4 -1:0] mpu_allow, // data memory interface output logic awvalid, input wire awready, @@ -340,8 +340,8 @@ module friscv_processing .memfy_rd_addr (proc_rd_addr[1*5+:5]), .memfy_rd_val (proc_rd_val[1*XLEN+:XLEN]), .memfy_rd_strb (proc_rd_strb[1*XLEN/8+:XLEN/8]), - .pmp_addr (pmp_addr), - .pmp_allow (pmp_allow), + .mpu_addr (mpu_addr), + .mpu_allow (mpu_allow), .awvalid (awvalid), .awready (awready), .awaddr (awaddr), @@ -412,7 +412,7 @@ module friscv_processing // /////////////////////////////////////////////////////////////////////////// - assign proc_exceptions[0+:2] = memfy_exceptions; + assign proc_exceptions = memfy_exceptions; endmodule diff --git a/rtl/friscv_rv32i_core.sv b/rtl/friscv_rv32i_core.sv index ce49675..f8caed7 100644 --- a/rtl/friscv_rv32i_core.sv +++ b/rtl/friscv_rv32i_core.sv @@ -223,7 +223,7 @@ module friscv_rv32i_core logic proc_ready; logic proc_busy; logic [4 -1:0] proc_fenceinfo; - logic [2 -1:0] proc_exceptions; + logic [`PROC_EXP_W -1:0] proc_exceptions; logic csr_en; logic [`INST_BUS_W -1:0] csr_instbus; @@ -278,10 +278,10 @@ module friscv_rv32i_core logic [`CTRL_SB_W -1:0] ctrl_sb; - logic [AXI_ADDR_W -1:0] imem_addr; - logic [AXI_ADDR_W -1:0] dmem_addr; - logic [4 -1:0] imem_allow; - logic [4 -1:0] dmem_allow; + logic [AXI_ADDR_W -1:0] mpu_imem_addr; + logic [AXI_ADDR_W -1:0] mpu_dmem_addr; + logic [4 -1:0] mpu_imem_allow; + logic [4 -1:0] mpu_dmem_allow; ////////////////////////////////////////////////////////////////////////// // Check parameters setup consistency and break up if not supported @@ -361,37 +361,37 @@ module friscv_rv32i_core .aclk (aclk), .aresetn (aresetn), .srst (srst), - .x1_ra (dbg_regs[ `X1*XLEN+:XLEN]), - .x2_sp (dbg_regs[ `X2*XLEN+:XLEN]), - .x3_gp (dbg_regs[ `X3*XLEN+:XLEN]), - .x4_tp (dbg_regs[ `X4*XLEN+:XLEN]), - .x5_t0 (dbg_regs[ `X5*XLEN+:XLEN]), - .x6_t1 (dbg_regs[ `X6*XLEN+:XLEN]), - .x7_t2 (dbg_regs[ `X7*XLEN+:XLEN]), - .x8_s0_fp (dbg_regs[ `X8*XLEN+:XLEN]), - .x9_s1 (dbg_regs[ `X9*XLEN+:XLEN]), - .x10_a0 (dbg_regs[`X10*XLEN+:XLEN]), - .x11_a1 (dbg_regs[`X11*XLEN+:XLEN]), - .x12_a2 (dbg_regs[`X12*XLEN+:XLEN]), - .x13_a3 (dbg_regs[`X13*XLEN+:XLEN]), - .x14_a4 (dbg_regs[`X14*XLEN+:XLEN]), - .x15_a5 (dbg_regs[`X15*XLEN+:XLEN]), - .x16_a6 (dbg_regs[`X16*XLEN+:XLEN]), - .x17_a7 (dbg_regs[`X17*XLEN+:XLEN]), - .x18_s2 (dbg_regs[`X18*XLEN+:XLEN]), - .x19_s3 (dbg_regs[`X19*XLEN+:XLEN]), - .x20_s4 (dbg_regs[`X20*XLEN+:XLEN]), - .x21_s5 (dbg_regs[`X21*XLEN+:XLEN]), - .x22_s6 (dbg_regs[`X22*XLEN+:XLEN]), - .x23_s7 (dbg_regs[`X23*XLEN+:XLEN]), - .x24_s8 (dbg_regs[`X24*XLEN+:XLEN]), - .x25_s9 (dbg_regs[`X25*XLEN+:XLEN]), - .x26_s10 (dbg_regs[`X26*XLEN+:XLEN]), - .x27_s11 (dbg_regs[`X27*XLEN+:XLEN]), - .x28_t3 (dbg_regs[`X28*XLEN+:XLEN]), - .x29_t4 (dbg_regs[`X29*XLEN+:XLEN]), - .x30_t5 (dbg_regs[`X30*XLEN+:XLEN]), - .x31_t6 (dbg_regs[`X31*XLEN+:XLEN]), + .x1_ra (dbg_regs[ `DBG_X1*XLEN+:XLEN]), + .x2_sp (dbg_regs[ `DBG_X2*XLEN+:XLEN]), + .x3_gp (dbg_regs[ `DBG_X3*XLEN+:XLEN]), + .x4_tp (dbg_regs[ `DBG_X4*XLEN+:XLEN]), + .x5_t0 (dbg_regs[ `DBG_X5*XLEN+:XLEN]), + .x6_t1 (dbg_regs[ `DBG_X6*XLEN+:XLEN]), + .x7_t2 (dbg_regs[ `DBG_X7*XLEN+:XLEN]), + .x8_s0_fp (dbg_regs[ `DBG_X8*XLEN+:XLEN]), + .x9_s1 (dbg_regs[ `DBG_X9*XLEN+:XLEN]), + .x10_a0 (dbg_regs[`DBG_X10*XLEN+:XLEN]), + .x11_a1 (dbg_regs[`DBG_X11*XLEN+:XLEN]), + .x12_a2 (dbg_regs[`DBG_X12*XLEN+:XLEN]), + .x13_a3 (dbg_regs[`DBG_X13*XLEN+:XLEN]), + .x14_a4 (dbg_regs[`DBG_X14*XLEN+:XLEN]), + .x15_a5 (dbg_regs[`DBG_X15*XLEN+:XLEN]), + .x16_a6 (dbg_regs[`DBG_X16*XLEN+:XLEN]), + .x17_a7 (dbg_regs[`DBG_X17*XLEN+:XLEN]), + .x18_s2 (dbg_regs[`DBG_X18*XLEN+:XLEN]), + .x19_s3 (dbg_regs[`DBG_X19*XLEN+:XLEN]), + .x20_s4 (dbg_regs[`DBG_X20*XLEN+:XLEN]), + .x21_s5 (dbg_regs[`DBG_X21*XLEN+:XLEN]), + .x22_s6 (dbg_regs[`DBG_X22*XLEN+:XLEN]), + .x23_s7 (dbg_regs[`DBG_X23*XLEN+:XLEN]), + .x24_s8 (dbg_regs[`DBG_X24*XLEN+:XLEN]), + .x25_s9 (dbg_regs[`DBG_X25*XLEN+:XLEN]), + .x26_s10 (dbg_regs[`DBG_X26*XLEN+:XLEN]), + .x27_s11 (dbg_regs[`DBG_X27*XLEN+:XLEN]), + .x28_t3 (dbg_regs[`DBG_X28*XLEN+:XLEN]), + .x29_t4 (dbg_regs[`DBG_X29*XLEN+:XLEN]), + .x30_t5 (dbg_regs[`DBG_X30*XLEN+:XLEN]), + .x31_t6 (dbg_regs[`DBG_X31*XLEN+:XLEN]), .ctrl_rs1_addr (ctrl_rs1_addr), .ctrl_rs1_val (ctrl_rs1_val), .ctrl_rs2_addr (ctrl_rs2_addr), @@ -442,7 +442,7 @@ module friscv_rv32i_core .srst (srst), .cache_ready (icache_ready & dcache_ready), .status (ctrl_status), - .pc_val (dbg_regs[`PC*XLEN+:XLEN]), + .pc_val (dbg_regs[`DBG_PC*XLEN+:XLEN]), .flush_reqs (flush_reqs), .flush_blocks (flush_blocks), .flush_ack (flush_ack), @@ -472,8 +472,8 @@ module friscv_rv32i_core .ctrl_rd_wr (ctrl_rd_wr), .ctrl_rd_addr (ctrl_rd_addr), .ctrl_rd_val (ctrl_rd_val), - .pmp_addr (imem_addr), - .pmp_allow (imem_allow), + .mpu_addr (mpu_imem_addr), + .mpu_allow (mpu_imem_allow), .csr_sb (csr_sb), .ctrl_sb (ctrl_sb) ); @@ -663,10 +663,10 @@ module friscv_rv32i_core .aclk (aclk), .aresetn (aresetn), .srst (srst), - .imem_addr (imem_addr), - .imem_allow (imem_allow), - .dmem_addr (dmem_addr), - .dmem_allow (dmem_allow), + .imem_addr (mpu_imem_addr), + .imem_allow (mpu_imem_allow), + .dmem_addr (mpu_dmem_addr), + .dmem_allow (mpu_dmem_allow), .csr_sb (csr_sb) ); @@ -714,8 +714,8 @@ module friscv_rv32i_core .proc_rd_addr (proc_rd_addr), .proc_rd_val (proc_rd_val), .proc_rd_strb (proc_rd_strb), - .pmp_addr (dmem_addr), - .pmp_allow (dmem_allow), + .mpu_addr (mpu_dmem_addr), + .mpu_allow (mpu_dmem_allow), .awvalid (memfy_awvalid), .awready (memfy_awready), .awaddr (memfy_awaddr), diff --git a/test/common/friscv_testbench.sv b/test/common/friscv_testbench.sv index c12a8bc..cb9f02f 100644 --- a/test/common/friscv_testbench.sv +++ b/test/common/friscv_testbench.sv @@ -786,11 +786,11 @@ module friscv_testbench( endtask - assign pc = dbg_regs[`PC*XLEN+:XLEN]; + assign pc = dbg_regs[`DBG_PC*XLEN+:XLEN]; `ifdef ERROR_STATUS_X31 if (`ERROR_STATUS_X31) - assign error_status_reg = (dbg_regs[`X31*XLEN+:XLEN] > 0) ? 1'b1 : 1'b0; + assign error_status_reg = (dbg_regs[`DBG_X31*XLEN+:XLEN] > 0) ? 1'b1 : 1'b0; else assign error_status_reg = 1'b0; `else diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S index eef8943..42fdbdd 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test2.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S @@ -9,7 +9,7 @@ # Test 2: PMP configuration and checking -# Configure PMP and check the 3 address matching are OK and out-of-range +# Configure PMP and check the address matching are OK and out-of-range # and forbidden access are correctly handled # # x31 is the error status register to trigger the testbench status @@ -22,6 +22,8 @@ .equ MEIE_ON, 0x00000800 .equ MEIE_OFF, 0xFFFFF7FF +.equ CFG0, 0x0 + RVTEST_RV64U RVTEST_CODE_BEGIN