diff --git a/doc/TODO.md b/doc/TODO.md
index 081e128..f1f4e92 100644
--- a/doc/TODO.md
+++ b/doc/TODO.md
@@ -46,27 +46,28 @@ U-mode
 
 Interrupt
 - [X] Do something within a loop with interrupt enabled, data needs to be OK
-- [ ] WFI in u-mode, interrupt enabled, trapped in m-mode
-- [ ] WFI in u-mode, interrupt disabled, NOP
+- [X] WFI in u-mode, interrupt enabled, trapped in m-mode
+- [X] WFI in u-mode, interrupt disabled, NOP
 - [ ] Add test for vector table
 - [ ] Test des exception load/store misaligned
-- [ ] test MSTATUS.TW
+- [ ] Test MSTATUS.TW
 
 MPU:
 - [X] configure registers
-- [ ] all region configuration mode: NA4 / NAPOT / TOR
+- [X] all region configuration mode: NA4 / NAPOT / TOR
 - [ ] multiple mixed region type and size
 - [ ] Access exceptions
-    -> Store = store access-fault
-    -> Load = load access-fault
-    -> Execute = instruction access-fault
-    - [ ] read/execute instruction outside allowed regions (U-mode)
-    - [ ] read/write data in U-mode
-    - [ ] read/write data in M-mode with MPRV + MPP w/ U-mode
+    - [X] execute instruction outside allowed regions (U-mode)
+    - [X] write data in U-mode
+    - [X] read data in U-mode
+    - [ ] read data in M-mode with MPRV + MPP w/ U-mode
+    - [ ] write data in M-mode with MPRV + MPP w/ U-mode
+    - [ ] execute in M-mode without X + locked region
 - [ ] locked access to change configuration
-- [ ] locked region accessed wrongly by m-mode
+- [ ] region's permissions overlap
 
 Final:
 - Pass compliance with U-mode
+- Run REPL app
 - Review testcases
 - Parse again the documentation
diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md
index 62c0ef1..d773ed1 100644
--- a/doc/project_mgt_hw.md
+++ b/doc/project_mgt_hw.md
@@ -6,7 +6,9 @@
     - [-] Support PMP/PMA
     - [ ] Atomic operations for single core
     - [ ] AXI Exception management with a CLIC
+        - maange all traps into it?
     - [ ] Zc extension
+    - [ ] https://github.com/eembc/coremark
 
 
 # BACKLOG
@@ -39,6 +41,7 @@ Any new features should be carefully study to ensure a proper exception and inte
     - raise an exception
     - methode AER-like pour les enregistrer: src, address, permission
     - trig an interrupt catched with PLIC controller
+    - https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html
 
 
 ## Cache Stages
@@ -55,6 +58,7 @@ Any new features should be carefully study to ensure a proper exception and inte
 - [ ] New cache associativity (2 / 4 / 8 ways configurable)
 - [ ] OoO read: miss could be stacked and served later waiting for cache fill and continue reading the next address
 - [ ] Fully concurrent read / write access (Issue #1)
+    - Split memfy in load unit & store unit
 
 
 ## Miscellanous
diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
index 3f8c4a8..3a4e04d 100644
--- a/rtl/friscv_control.sv
+++ b/rtl/friscv_control.sv
@@ -1229,9 +1229,9 @@ module friscv_control
     assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready;
 
     // Is fetching instruction on forbidden memory region 
-    assign inst_access_fault = (!mpu_allow[`ALW_X] | !mpu_allow[`ALW_R]) &
+    assign inst_access_fault = !mpu_allow[`ALW_X] &
                                   (priv_mode == `UMODE ||
-                                   priv_mode==`MMODE && mpu_allow[`ALW_L]);
+                                   priv_mode == `MMODE & mpu_allow[`ALW_L]);
 
     //////////////////////////////////////////////////////////////////////
     // Stores the incoming excpetions from processing. Can't handle 
diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
index 2f1d5e9..e61541c 100644
--- a/test/common/debug_platform_verilator.gtkw
+++ b/test/common/debug_platform_verilator.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed Nov  1 17:32:10 2023
+[*] Tue Nov  7 19:31:27 2023
 [*]
 [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd"
-[dumpfile_mtime] "Wed Nov  1 17:03:56 2023"
-[dumpfile_size] 9007697
+[dumpfile_mtime] "Sun Nov  5 19:46:50 2023"
+[dumpfile_size] 61559319
 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw"
-[timestart] 6058
-[size] 2560 1440
+[timestart] 1
+[size] 1440 900
 [pos] -1 -1
-*-5.355745 6239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-14.355745 29879 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.
@@ -24,10 +24,10 @@
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.
-[sst_width] 365
-[signals_width] 344
+[sst_width] 253
+[signals_width] 262
 [sst_expanded] 1
-[sst_vpaned_height] 365
+[sst_vpaned_height] 211
 @c00200
 -AXI4-lite RAM
 @22
@@ -104,7 +104,9 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg1[31:0]
+@23
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg2[31:0]
+@22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg3[31:0]
 @200
 -
@@ -125,34 +127,6 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr12[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr13[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr14[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr15[31:0]
-@200
--
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus_wr
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0]
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc_wr
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc[31:0]
-@200
--
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0]
-@200
--
-@28
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_rden
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_wren
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr[11:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.newval[31:0]
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.oldval[31:0]
-@200
--
-@22
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 @1000200
 -CSRs
 @800200
@@ -288,9 +262,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid
 -
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
-@29
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring
-@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring
 @200
 -
@@ -306,7 +278,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned
 @200
 -
-@c00200
+@800200
 -CSRs
 @c00022
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0]
@@ -413,6 +385,8 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk
 @200
 -
+@28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mie
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mcounteren[31:0]
 @28
@@ -431,13 +405,13 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtie
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtip
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtvec[31:0]
-@1401200
+@1000200
 -CSRs
 @200
 -
 @1000200
 -control
-@800200
+@c00200
 -Memfy
 @28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid
@@ -488,7 +462,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_access
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_misaligned
 @200
 -
-@1000200
+@1401200
 -Memfy
 @c00200
 -Registers
@@ -526,7 +500,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0]
 @1401200
 -Registers
-@800200
+@c00200
 -MPU
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.imem_addr[31:0]
@@ -617,6 +591,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKER
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_mask[31:0]
 @1000200
 -Region 1
+@1401200
 -MPU
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/test/common/functions.sh b/test/common/functions.sh
index 9f990f4..579b052 100755
--- a/test/common/functions.sh
+++ b/test/common/functions.sh
@@ -156,10 +156,10 @@ gather_result() {
     msg=$(grep -ni "ERROR:" tc.log)
 
     if [ "$2" -eq 1 ] || [ "$ec" != 0 ]; then
-        ts_res="${ts_res} - $1:\t❌\n"
+        ts_res="${ts_res}  ❌ $1\n"
         ts_res="${ts_res}$msg\n"
     else
-        ts_res="${ts_res} - $1:\t✅\n"
+        ts_res="${ts_res}  ✅ $1\n"
     fi
 }
 #------------------------------------------------------------------------------
diff --git a/test/priv_sec_testsuite/tests/env/pmp.S b/test/priv_sec_testsuite/tests/env/pmp.S
index dfaa9b0..da9060f 100644
--- a/test/priv_sec_testsuite/tests/env/pmp.S
+++ b/test/priv_sec_testsuite/tests/env/pmp.S
@@ -1,6 +1,18 @@
 # distributed under the mit license
 # https://opensource.org/licenses/mit-license.php
 
+.equ PMPADDR,   0xFFFFFFFF
+.equ PMPCFG,    0x77777777
+
+.equ S2MB,      0x200000
+.equ S1MB,      0x100000
+.equ S512K,     0x80000
+.equ S256K,     0x40000
+.equ S64KB,     0x10000
+.equ S16KB,     0x10000
+.equ S4KB,      0x4000
+.equ S1KB,      0x1000
+
 .equ OFF,       0
 .equ TOR_RWX,   0x0F
 .equ TOR_RW,    0x0B
@@ -9,8 +21,10 @@
 .equ NA4_RW,    0x13
 .equ NA4_RX,    0x15
 .equ NAPOT_RWX, 0x1F
-.equ NAPOT_RW , 0x1B
-.equ NAPOT_RX , 0x1D
+.equ NAPOT_RW,  0x1B
+.equ NAPOT_RX,  0x1D
+.equ NAPOT_R,   0x19
+.equ NAPOT_W,   0x1C
 
 .equ TOR_LRWX,   0x8F
 .equ TOR_LRW,    0x8B
diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S
index 6bf3ec7..e040132 100644
--- a/test/priv_sec_testsuite/tests/env/pmp_service.S
+++ b/test/priv_sec_testsuite/tests/env/pmp_service.S
@@ -214,11 +214,6 @@ INTP_SERVICE:
     csrw mie, t4
     j RET_ECALL
 
-EXP_SERVICE:
-    addi s0, s0, 1
-    # j RET_ECALL
-    mret
-
 ////////////////////////////////////////////
 # Configure a NAPOT / NA4 region
 ////////////////////////////////////////////
diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
index 2103ad3..2bfc10e 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v
@@ -1,67 +1,67 @@
 @00010000
-6F 00 40 0A 73 2F 20 34 93 0E 80 00 63 14 DF 01
-6F 20 40 53 93 0E 90 00 63 0E DF 1B 93 0E B0 00
-63 0E DF 1B 93 0E 20 00 63 0C DF 1B B7 0E 00 80
-93 8E BE 00 63 14 DF 01 6F 20 00 54 B7 0E 00 80
-93 8E 3E 00 63 14 DF 01 6F 20 00 53 B7 0E 00 80
-93 8E 7E 00 63 14 DF 01 6F 20 00 52 93 0E 50 00
-63 14 DF 01 6F 20 40 25 93 0E 70 00 63 14 DF 01
-6F 20 80 24 93 0E 10 00 63 14 DF 01 6F 20 C0 23
-13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34
-63 54 0F 00 6F 00 40 00 93 E1 91 53 17 1F 00 00
-23 22 3F F6 93 00 00 00 13 01 00 00 93 01 00 00
-13 02 00 00 93 02 00 00 13 03 00 00 93 03 00 00
-13 04 00 00 93 04 00 00 13 05 00 00 93 05 00 00
-13 06 00 00 93 06 00 00 13 07 00 00 93 07 00 00
-13 08 00 00 93 08 00 00 13 09 00 00 93 09 00 00
-13 0A 00 00 93 0A 00 00 13 0B 00 00 93 0B 00 00
-13 0C 00 00 93 0C 00 00 13 0D 00 00 93 0D 00 00
-13 0E 00 00 93 0E 00 00 13 0F 00 00 93 0F 00 00
-73 25 40 F1 63 10 05 00 97 02 00 00 93 82 02 01
-73 90 52 30 73 50 00 18 97 02 00 00 93 82 02 02
-73 90 52 30 B7 02 00 80 93 82 F2 FF 73 90 02 3B
-93 02 F0 01 73 90 02 3A 73 50 40 30 97 02 00 00
-93 82 42 01 73 90 52 30 73 50 20 30 73 50 30 30
-93 01 00 00 97 02 00 00 93 82 02 E9 73 90 52 30
-13 05 10 00 13 15 F5 01 63 4C 05 00 0F 00 F0 0F
-93 01 10 00 93 08 D0 05 13 05 00 00 73 00 10 00
-93 02 00 00 63 8A 02 00 73 90 52 10 B7 B2 00 00
-93 82 92 10 73 90 22 30 73 50 00 30 97 02 00 00
-93 82 42 01 73 90 12 34 73 25 40 F1 73 00 20 30
-6F 00 80 01 93 8F 1F 00 73 00 10 00 6F 20 C0 38
-93 8F 1F 00 73 00 10 00 93 08 00 00 73 00 00 00
-93 08 10 00 73 00 00 00 93 04 00 00 13 09 00 01
-33 85 04 00 B7 05 10 00 13 06 00 00 93 06 F0 00
-13 07 80 00 93 08 80 00 73 00 00 00 EF 00 40 15
-B7 02 10 00 23 20 50 00 03 23 00 00 63 9C 62 16
-23 AE 52 FE 03 A3 C2 FF 63 96 62 16 B7 02 10 00
-23 A0 02 00 13 00 00 00 13 00 00 00 13 00 00 00
-93 02 10 00 63 18 54 14 93 08 00 00 73 00 00 00
-13 04 00 00 93 84 14 00 E3 9C 24 F9 93 04 00 00
-13 09 00 01 33 85 04 00 93 05 00 00 37 06 10 00
-93 06 F0 01 13 07 80 01 93 08 80 00 73 00 00 00
-EF 00 00 0E B7 02 10 00 23 20 50 00 03 23 00 00
-63 92 62 10 23 AE 52 FE 03 A3 C2 FF 63 9C 62 0E
-B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00
-13 00 00 00 93 02 10 00 63 1E 54 0C 93 08 00 00
-73 00 00 00 13 04 00 00 93 84 14 00 E3 9C 24 F9
-13 05 00 00 93 05 00 00 37 06 04 00 93 06 F0 01
-13 07 80 01 93 08 80 00 73 00 00 00 13 05 10 00
-B7 05 08 00 13 06 40 00 93 06 70 01 13 07 00 01
-93 08 80 00 73 00 00 00 B7 02 08 00 23 A0 52 00
-03 A3 02 00 63 90 62 08 B7 02 08 00 23 AE 02 FE
+6F 00 80 09 73 2F 20 34 93 0E 80 00 63 14 DF 01
+6F 20 C0 52 93 0E 90 00 63 08 DF 1B 93 0E B0 00
+63 08 DF 1B 93 0E 20 00 63 06 DF 1B B7 0E 00 80
+93 8E BE 00 63 14 DF 01 6F 20 80 53 B7 0E 00 80
+93 8E 3E 00 63 14 DF 01 6F 20 80 52 B7 0E 00 80
+93 8E 7E 00 63 14 DF 01 6F 20 80 51 93 0E 50 00
+63 0E DF 17 93 0E 70 00 63 0A DF 17 93 0E 10 00
+63 06 DF 17 13 0F 00 00 63 04 0F 00 67 00 0F 00
+73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53
+17 1F 00 00 23 28 3F F6 93 00 00 00 13 01 00 00
+93 01 00 00 13 02 00 00 93 02 00 00 13 03 00 00
+93 03 00 00 13 04 00 00 93 04 00 00 13 05 00 00
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+93 07 00 00 13 08 00 00 93 08 00 00 13 09 00 00
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+93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00
+93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00
+93 0F 00 00 73 25 40 F1 63 10 05 00 97 02 00 00
+93 82 02 01 73 90 52 30 73 50 00 18 97 02 00 00
+93 82 02 02 73 90 52 30 B7 02 00 80 93 82 F2 FF
+73 90 02 3B 93 02 F0 01 73 90 02 3A 73 50 40 30
+97 02 00 00 93 82 42 01 73 90 52 30 73 50 20 30
+73 50 30 30 93 01 00 00 97 02 00 00 93 82 C2 E9
+73 90 52 30 13 05 10 00 13 15 F5 01 63 4C 05 00
+0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00
+73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10
+B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30
+97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1
+73 00 20 30 6F 00 00 02 93 8F 1F 00 73 00 10 00
+6F 20 00 39 93 8F 1F 00 73 00 10 00 13 04 14 00
+73 00 20 30 93 08 00 00 73 00 00 00 93 08 10 00
+73 00 00 00 93 04 00 00 13 09 00 01 33 85 04 00
+B7 05 10 00 13 06 00 00 93 06 F0 00 13 07 80 00
+93 08 80 00 73 00 00 00 EF 00 40 15 B7 02 10 00
+23 20 50 00 03 23 00 00 63 9C 62 16 23 AE 52 FE
+03 A3 C2 FF 63 96 62 16 B7 02 10 00 23 A0 02 00
 13 00 00 00 13 00 00 00 13 00 00 00 93 02 10 00
-63 12 54 06 B7 02 08 00 23 A2 02 00 13 00 00 00
-13 00 00 00 13 00 00 00 93 02 20 00 63 14 54 04
-93 08 00 00 73 00 00 00 13 04 00 00 6F 00 C0 05
-93 02 00 00 13 03 A0 00 93 03 00 00 13 0E 00 00
-B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00
-93 82 12 00 13 9E 22 00 E3 94 62 FE 67 80 00 00
-63 14 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00
-93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00
-73 00 10 00 73 00 10 00 0F 00 F0 0F 93 01 10 00
-93 08 D0 05 13 05 00 00 73 00 10 00 73 00 10 00
-73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00
+63 18 54 14 93 08 00 00 73 00 00 00 13 04 00 00
+93 84 14 00 E3 9C 24 F9 93 04 00 00 13 09 00 01
+33 85 04 00 93 05 00 00 37 06 10 00 93 06 F0 01
+13 07 80 01 93 08 80 00 73 00 00 00 EF 00 00 0E
+B7 02 10 00 23 20 50 00 03 23 00 00 63 92 62 10
+23 AE 52 FE 03 A3 C2 FF 63 9C 62 0E B7 02 10 00
+23 A0 02 00 13 00 00 00 13 00 00 00 13 00 00 00
+93 02 10 00 63 1E 54 0C 93 08 00 00 73 00 00 00
+13 04 00 00 93 84 14 00 E3 9C 24 F9 13 05 00 00
+93 05 00 00 37 06 04 00 93 06 F0 01 13 07 80 01
+93 08 80 00 73 00 00 00 13 05 10 00 B7 05 08 00
+13 06 40 00 93 06 70 01 13 07 00 01 93 08 80 00
+73 00 00 00 B7 02 08 00 23 A0 52 00 03 A3 02 00
+63 90 62 08 B7 02 08 00 23 AE 02 FE 13 00 00 00
+13 00 00 00 13 00 00 00 93 02 10 00 63 12 54 06
+B7 02 08 00 23 A2 02 00 13 00 00 00 13 00 00 00
+13 00 00 00 93 02 20 00 63 14 54 04 93 08 00 00
+73 00 00 00 13 04 00 00 6F 00 C0 05 93 02 00 00
+13 03 A0 00 93 03 00 00 13 0E 00 00 B3 83 53 00
+23 20 7E 00 93 83 13 00 83 23 0E 00 93 82 12 00
+13 9E 22 00 E3 94 62 FE 67 80 00 00 63 14 30 02
+0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00
+93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00
+73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05
+13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00
 @00011000
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -75,86 +75,86 @@ B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00
 73 10 40 3B 73 10 50 3B 73 10 60 3B 73 10 70 3B
 73 10 80 3B 73 10 90 3B 73 10 A0 3B 73 10 B0 3B
 73 10 C0 3B 73 10 D0 3B 73 10 E0 3B 73 10 F0 3B
-6F 00 80 51 93 02 00 00 B7 0E 00 00 93 8E FE FF
-73 90 0E 3B 73 2F 00 3B 63 84 EE 01 6F E0 8F B3
+6F 00 00 51 93 02 00 00 B7 0E 00 00 93 8E FE FF
+73 90 0E 3B 73 2F 00 3B 63 84 EE 01 6F E0 4F B3
 73 10 00 3B B7 0E 00 00 93 8E FE FF 73 90 1E 3B
-73 2F 10 3B 63 84 EE 01 6F E0 CF B1 73 10 10 3B
+73 2F 10 3B 63 84 EE 01 6F E0 8F B1 73 10 10 3B
 B7 0E 00 00 93 8E FE FF 73 90 2E 3B 73 2F 20 3B
-63 84 EE 01 6F E0 0F B0 73 10 20 3B B7 0E 00 00
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 93 8E FE FF 73 90 3E 3B 73 2F 30 3B 63 84 EE 01
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diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
index 22d9ef0..06c89e9 100755
--- a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
+++ b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v
@@ -9,8 +9,8 @@
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 03 22 05 01 83 22 45 01 03 23 85 01 83 23 C5 01
 03 24 05 02 83 24 45 02 83 25 C5 02 03 26 05 03
@@ -199,7 +199,7 @@ EF F0 1F 88 13 05 30 00 EF F0 1F 8E 73 10 00 3A
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@@ -230,56 +230,56 @@ EF F0 1F 88 13 05 30 00 EF F0 1F 8E 73 10 00 3A
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diff --git a/test/priv_sec_testsuite/tests/rv32ui/Makefrag b/test/priv_sec_testsuite/tests/rv32ui/Makefrag
index f241da0..91ff4c6 100644
--- a/test/priv_sec_testsuite/tests/rv32ui/Makefrag
+++ b/test/priv_sec_testsuite/tests/rv32ui/Makefrag
@@ -6,6 +6,7 @@ rv32ui_sc_tests = \
     test0 \
     test1 \
     test2 \
+    test3 \
 
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
 rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
index 0f91153..aa404dd 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v
@@ -1,67 +1,67 @@
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 00 00 00 00
 @00011000
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
index d1feb6f..f6b40ef 100755
--- a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
+++ b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v
@@ -9,8 +9,8 @@
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 03 32 05 02 83 32 85 02 03 33 05 03 83 33 85 03
 03 34 05 04 83 34 85 04 83 35 85 05 03 36 05 06
@@ -192,7 +192,7 @@ EF F0 5F 94 73 10 00 3A 73 10 10 3A 73 10 20 3A
 73 10 30 3B 73 10 40 3B 73 10 50 3B 73 10 60 3B
 73 10 70 3B 73 10 80 3B 73 10 90 3B 73 10 A0 3B
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@@ -222,62 +222,62 @@ EF F0 5F 94 73 10 00 3A 73 10 10 3A 73 10 20 3A
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diff --git a/test/priv_sec_testsuite/tests/rv64ui/Makefrag b/test/priv_sec_testsuite/tests/rv64ui/Makefrag
index e6a134e..9c40966 100644
--- a/test/priv_sec_testsuite/tests/rv64ui/Makefrag
+++ b/test/priv_sec_testsuite/tests/rv64ui/Makefrag
@@ -6,6 +6,7 @@ rv64ui_sc_tests = \
     test0 \
     test1 \
     test2 \
+    test3 \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S
index 8cd6449..db20ba8 100644
--- a/test/priv_sec_testsuite/tests/rv64ui/test2.S
+++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S
@@ -29,24 +29,6 @@
 .equ MEIE_ON,   0x00000800
 .equ MEIE_OFF,  0xFFFFF7FF
 
-.equ PMPCFG0,  0x0
-.equ PMPCFG1,  0x0
-.equ PMPCFG2,  0x0
-.equ PMPCFG3,  0x0
-.equ PMPADDR,  0xFFFFFFFF
-.equ PMPCFG,   0x77777777
-
-.equ S2MB,     0x200000
-.equ S1MB,     0x100000
-.equ S512K,    0x80000
-.equ S256K,    0x40000
-.equ S64KB,    0x10000
-.equ S16KB,    0x10000
-.equ S4KB,     0x4000
-.equ S1KB,     0x1000
-
-
-
 
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
@@ -80,6 +62,11 @@ ILLEGAL_INSTRUCTION:
     ebreak
 
 
+EXP_SERVICE:
+    addi s0, s0, 1
+    mret
+
+
 ##################################################
 #
 # Testcases
@@ -99,11 +86,11 @@ TEST2:
     li a7, 1
     ecall
 
+// TOR region - 1MB RWX
 TEST3_SETUP:
     li s1, 0
     li s2, 16
 
-// TOR region - 1MB RWX
 TEST3_1TOR:
     // Configure the region
     add a0, s1, zero // pmp number
@@ -151,11 +138,12 @@ TEST3_TEARDOWN:
     addi s1, s1, 1
     bne s1, s2, TEST3_1TOR
 
+
+// NAPOT region - 1MB RWX
 TEST4_SETUP:
     li s1, 0
     li s2, 16
 
-// NAPOT region - 1MB RWX
 TEST4_1NAPOT:
     // Configure the region
     add a0, s1, zero // pmp number