Fix: wba test8 updated, checking now WFI with MIE and without MEIE (NOP)

dpretet · Oct 22, 2023 · 95ea57b · 95ea57b
1 parent 8ba3fca
commit 95ea57b
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Showing 7 changed files with 149 additions and 78 deletions.
diff --git a/rtl/friscv_pmp_region.sv b/rtl/friscv_pmp_region.sv
@@ -21,7 +21,7 @@ module friscv_pmp_region
     )(
         // CSR registers
         input  wire  [XLEN         -1:0] pmp_addr,
-        input  wire  [XLEN         -1:0] pmp_cfg,
+        input  wire  [8            -1:0] pmp_cfg,
         // Region base addres and mask for NAPOT/NA4
         output logic [RLEN         -1:0] pmp_base,
         output logic [RLEN         -1:0] pmp_mask

diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Sun Oct 15 13:33:23 2023
+[*] Sun Oct 22 18:08:09 2023
 [*]
-[dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd"
-[dumpfile_mtime] "Sun Oct 15 13:31:53 2023"
-[dumpfile_size] 378696829
+[dumpfile] "/Users/damien/workspace/hdl/friscv/test/wba_testsuite/friscv_testbench.vcd"
+[dumpfile_mtime] "Sun Oct 22 18:07:49 2023"
+[dumpfile_size] 1961741
 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw"
-[timestart] 3234
+[timestart] 1937
 [size] 1440 900
 [pos] -1 -1
-*-5.598954 3329 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-5.496682 2106 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.
@@ -18,15 +18,12 @@
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.
-[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.
-[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].
-[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.
 [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.
 [sst_width] 255
-[signals_width] 373
+[signals_width] 263
 [sst_expanded] 1
-[sst_vpaned_height] 370
+[sst_vpaned_height] 234
 @c00200
 -AXI4-lite RAM
 @22
@@ -96,18 +93,18 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid
 -
 @1401200
 -Interconnect
-@c00200
+@c00201
 -CSRs
-@200
+@201
 -
-@22
+@23
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg1[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg2[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg3[31:0]
-@200
+@201
 -
-@22
+@23
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr0[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr1[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr2[31:0]
@@ -124,9 +121,17 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr12[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr13[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr14[31:0]
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr15[31:0]
-@200
+@201
 -
-@1401200
+@23
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0]
+@29
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus_wr
+@201
+-
+@23
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0]
+@1401201
 -CSRs
 @c00200
 -ISA Regsiters
@@ -250,16 +255,21 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ready
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid
 @200
 -
-@29
-friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
 @28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.store_misaligned
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.load_access_fault
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.load_misaligned
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_access_fault
 @200
 -
 @28
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_en
+@22
+friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mstatus[31:0]
+@200
+-
+@28
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.mstatus_wr
 @22
 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.mstatus[31:0]

diff --git a/test/wba_testsuite/tests/rv32ui-p-test8.v b/test/wba_testsuite/tests/rv32ui-p-test8.v
@@ -22,15 +22,23 @@
 73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10
 B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30
 97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1
-73 00 20 30 6F 00 40 00 93 01 00 00 93 01 10 00
-37 03 00 00 13 03 83 00 F3 22 00 30 B3 E2 62 00
-73 90 02 30 37 13 00 00 13 03 03 80 F3 22 40 30
-B3 E2 62 00 73 90 42 30 97 00 00 00 93 80 00 01
-73 90 50 30 73 00 50 10 63 14 00 00 63 12 30 02
+73 00 20 30 6F 00 C0 00 13 04 14 00 73 00 20 30
+93 01 00 00 97 00 00 00 93 80 40 FF 73 90 50 30
+93 01 10 00 37 13 00 00 13 03 03 80 F3 22 40 30
+B3 E2 62 00 73 90 42 30 37 03 00 00 13 03 83 00
+F3 22 00 30 B3 E2 62 00 73 90 02 30 93 02 10 00
+63 90 82 06 93 01 20 00 73 00 50 10 93 02 20 00
+63 98 82 04 93 01 30 00 37 03 00 00 13 03 73 FF
+F3 22 00 30 B3 F2 62 00 73 90 02 30 73 00 50 10
+73 10 40 30 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 73 00 50 10 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 63 14 00 00 63 12 30 02
 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00
 93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00
 0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00
-73 00 10 00 73 00 10 00 73 10 00 C0
+73 00 10 00 73 00 10 00 73 10 00 C0 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00
 @00011000
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/test/wba_testsuite/tests/rv32ui-v-test8.v b/test/wba_testsuite/tests/rv32ui-v-test8.v
@@ -121,11 +121,11 @@ E3 9C 07 FD 73 90 08 10 93 97 26 00 B3 06 F6 00
 63 94 E5 04 93 96 26 00 B3 06 D6 00 23 A0 F6 00
 73 00 05 12 83 20 C1 00 13 01 01 01 67 80 00 00
 93 E7 07 04 6F F0 1F FE 97 47 00 00 23 A4 07 AC
-6F F0 1F F0 17 05 00 00 13 05 85 50 EF F0 5F D0
-13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 85 53
+6F F0 1F F0 17 05 00 00 13 05 85 56 EF F0 5F D0
+13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 85 59
 EF F0 1F CF 13 05 30 00 EF F0 1F D5 17 05 00 00
-13 05 C5 56 EF F0 DF CD 13 05 30 00 EF F0 DF D3
-17 05 00 00 13 05 05 57 EF F0 9F CC 13 05 30 00
+13 05 C5 5C EF F0 DF CD 13 05 30 00 EF F0 DF D3
+17 05 00 00 13 05 05 5D EF F0 9F CC 13 05 30 00
 EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
 23 26 11 04 23 22 91 04 23 20 21 05 23 2E 31 03
 23 2C 41 03 23 2A 51 03 23 28 61 03 23 26 71 03
@@ -139,14 +139,14 @@ EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04
 03 2D 01 02 83 2D C1 01 13 01 01 05 6F D0 1F A8
 03 27 45 08 93 77 37 00 63 98 07 08 EF 07 80 00
 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 06
-13 05 10 04 97 05 00 00 93 85 85 4C 97 F6 FF FF
+13 05 10 04 97 05 00 00 93 85 85 52 97 F6 FF FF
 93 86 46 99 17 F6 FF FF 13 06 C6 9C 03 A7 06 00
 83 A7 46 00 13 08 05 00 93 85 15 00 33 67 F7 00
 B7 08 01 01 63 02 07 02 13 07 00 00 23 20 E6 00
 93 07 00 00 23 22 F6 00 03 A7 06 00 83 A7 46 00
 33 67 F7 00 E3 12 07 FE 03 C5 05 00 23 A0 06 01
 23 A2 16 01 E3 1C 05 FA 13 05 30 00 EF F0 DF BE
-13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 85 4E
+13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 85 54
 EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02
 37 1C 00 00 97 14 00 00 93 84 C4 90 97 2B 00 00
 93 8B 4B 90 37 0B 04 00 B7 0A C0 FF 97 4D 00 00
@@ -160,10 +160,10 @@ EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02
 93 FC 0C 08 83 25 C1 00 63 80 0C 04 37 16 00 00
 13 05 0C 00 EF F0 DF 86 B3 87 84 00 73 10 0D 10
 03 A7 0D 00 23 A0 07 00 E3 1E 07 F6 23 A0 FD 00
-23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 C5 42
-EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 45 3C
+23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 C5 48
+EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 45 42
 EF F0 1F A8 13 05 30 00 EF F0 1F AE 17 05 00 00
-13 05 C5 37 EF F0 DF A6 13 05 30 00 EF F0 DF AC
+13 05 C5 3D EF F0 DF A6 13 05 30 00 EF F0 DF AC
 13 05 09 00 EF F0 5F AC F3 27 40 F1 63 96 07 16
 17 36 00 00 13 06 06 80 93 57 C6 00 13 01 01 F6
 93 97 A7 00 23 2E 11 08 23 2C 81 08 97 15 00 00
@@ -193,16 +193,22 @@ EF F0 CF F1 B7 07 00 80 33 04 F4 00 13 05 01 00
 93 D6 17 00 B3 E6 D5 00 B3 C7 D7 00 93 97 E7 01
 B3 75 F5 00 13 57 17 00 93 87 06 00 33 E7 E5 00
 B3 F6 C7 00 93 F5 17 00 B3 86 06 01 E3 96 05 FC
-03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 85 24
+03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 85 2A
 EF F0 1F 88 13 05 30 00 EF F0 1F 8E 67 80 00 00
-6F 00 40 00 93 01 00 00 93 01 10 00 37 03 00 00
-13 03 83 00 F3 22 00 30 B3 E2 62 00 73 90 02 30
+6F 00 C0 00 13 04 14 00 73 00 20 30 93 01 00 00
+97 00 00 00 93 80 40 FF 73 90 50 30 93 01 10 00
 37 13 00 00 13 03 03 80 F3 22 40 30 B3 E2 62 00
-73 90 42 30 97 00 00 00 93 80 00 01 73 90 50 30
-73 00 50 10 63 14 00 00 63 1A 30 00 13 95 11 00
+73 90 42 30 37 03 00 00 13 03 83 00 F3 22 00 30
+B3 E2 62 00 73 90 02 30 93 02 10 00 63 90 82 06
+93 01 20 00 73 00 50 10 93 02 20 00 63 98 82 04
+93 01 30 00 37 03 00 00 13 03 73 FF F3 22 00 30
+B3 F2 62 00 73 90 02 30 73 00 50 10 73 10 40 30
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+73 00 50 10 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 63 14 00 00 63 1A 30 00 13 95 11 00
 63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00
 73 00 00 00 73 00 10 00 73 10 00 C0
-@80002A4C
+@80002AAC
 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64
 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C
 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20

diff --git a/test/wba_testsuite/tests/rv64ui-p-test8.v b/test/wba_testsuite/tests/rv64ui-p-test8.v
@@ -22,18 +22,22 @@
 13 05 00 00 73 00 10 00 93 02 00 00 63 8A 02 00
 73 90 52 10 B7 B2 00 00 9B 82 92 10 73 90 22 30
 73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34
-73 25 40 F1 73 00 20 30 6F 00 40 00 93 01 00 00
-93 01 10 00 37 03 00 00 13 03 83 00 F3 22 00 30
-B3 E2 62 00 73 90 02 30 37 13 00 00 13 03 03 80
-F3 22 40 30 B3 E2 62 00 73 90 42 30 97 00 00 00
-93 80 00 01 73 90 50 30 73 00 50 10 63 14 00 00
+73 25 40 F1 73 00 20 30 6F 00 C0 00 13 04 14 00
+73 00 20 30 93 01 00 00 97 00 00 00 93 80 40 FF
+73 90 50 30 93 01 10 00 37 13 00 00 13 03 03 80
+F3 22 40 30 B3 E2 62 00 73 90 42 30 37 03 00 00
+13 03 83 00 F3 22 00 30 B3 E2 62 00 73 90 02 30
+93 02 10 00 63 90 82 06 93 01 20 00 73 00 50 10
+93 02 20 00 63 98 82 04 93 01 30 00 37 03 00 00
+13 03 73 FF F3 22 00 30 B3 F2 62 00 73 90 02 30
+73 00 50 10 73 10 40 30 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 73 00 50 10 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 63 14 00 00
 63 12 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00
 93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00
 73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05
 13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00
 @00011000
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/test/wba_testsuite/tests/rv64ui-v-test8.v b/test/wba_testsuite/tests/rv64ui-v-test8.v
@@ -114,11 +114,11 @@ E3 9C 07 FD 73 90 08 10 93 97 36 00 B3 06 F6 00
 63 94 E5 04 93 96 36 00 B3 06 D6 00 23 B0 F6 00
 73 00 05 12 83 30 81 00 13 01 01 01 67 80 00 00
 93 E7 07 04 6F F0 1F FE 97 67 00 00 23 BC 07 B2
-6F F0 1F F0 17 05 00 00 13 05 45 50 EF F0 1F D8
-13 05 30 00 EF F0 1F DC 17 05 00 00 13 05 85 53
+6F F0 1F F0 17 05 00 00 13 05 45 56 EF F0 1F D8
+13 05 30 00 EF F0 1F DC 17 05 00 00 13 05 85 59
 EF F0 DF D6 13 05 30 00 EF F0 DF DA 17 05 00 00
-13 05 C5 56 EF F0 9F D5 13 05 30 00 EF F0 9F D9
-17 05 00 00 13 05 05 57 EF F0 5F D4 13 05 30 00
+13 05 C5 5C EF F0 9F D5 13 05 30 00 EF F0 9F D9
+17 05 00 00 13 05 05 5D EF F0 5F D4 13 05 30 00
 EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06
 23 3C 11 06 23 34 91 06 23 30 21 07 23 3C 31 05
 23 38 41 05 23 34 51 05 23 30 61 05 23 3C 71 03
@@ -132,12 +132,12 @@ EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06
 03 3D 01 02 83 3D 81 01 13 01 01 08 6F D0 1F AF
 03 37 85 10 93 77 37 00 63 98 07 06 EF 07 80 00
 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 04
-13 05 10 10 93 07 10 04 97 06 00 00 93 86 86 4C
+13 05 10 10 93 07 10 04 97 06 00 00 93 86 86 52
 17 F7 FF FF 13 07 07 A0 13 15 05 03 83 35 07 00
 93 86 16 00 33 E6 A7 00 63 8A 05 00 97 F7 FF FF
 23 B2 07 A2 83 37 07 00 E3 9A 07 FE 83 C7 06 00
 23 30 C7 00 E3 9C 07 FC 13 05 30 00 EF F0 9F C6
-13 05 10 00 EF F0 1F C6 17 05 00 00 13 05 85 51
+13 05 10 00 EF F0 1F C6 17 05 00 00 13 05 85 57
 EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05
 37 1C 00 00 97 14 00 00 93 84 C4 99 97 2B 00 00
 93 8B 4B 99 37 0B 04 00 B7 0A E0 FF 97 6D 00 00
@@ -151,10 +151,10 @@ EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05
 93 FC 0C 08 83 35 81 00 63 80 0C 04 37 16 00 00
 13 05 0C 00 EF F0 DF 8F B3 87 84 00 73 10 0D 10
 03 B7 0D 00 23 B0 07 00 E3 1E 07 F6 23 B0 FD 00
-23 30 FA 00 6F F0 9F F7 17 05 00 00 13 05 05 46
-EF F0 DF B2 6F F0 5F F0 17 05 00 00 13 05 05 3F
+23 30 FA 00 6F F0 9F F7 17 05 00 00 13 05 05 4C
+EF F0 DF B2 6F F0 5F F0 17 05 00 00 13 05 05 45
 EF F0 DF B1 13 05 30 00 EF F0 DF B5 17 05 00 00
-13 05 45 3A EF F0 9F B0 13 05 30 00 EF F0 9F B4
+13 05 45 40 EF F0 9F B0 13 05 30 00 EF F0 9F B4
 13 05 09 00 EF F0 1F B4 F3 27 40 F1 63 9A 07 18
 97 47 00 00 93 87 07 89 13 01 01 ED 93 D7 C7 00
 23 30 81 12 17 58 00 00 13 08 C8 87 13 04 05 00
@@ -186,16 +186,22 @@ E3 1A E3 FC 13 06 00 12 93 05 00 00 13 05 01 00
 2F 20 07 00 13 D7 17 00 B3 C7 E7 00 93 97 E7 03
 B3 F7 D7 00 B3 E7 E7 00 33 F7 C7 00 93 F5 17 00
 33 07 A7 00 E3 9E 05 FC 03 20 07 00 6F F0 9F FD
-17 05 00 00 13 05 85 26 EF F0 5F 90 13 05 30 00
-EF F0 5F 94 67 80 00 00 6F 00 40 00 93 01 00 00
-93 01 10 00 37 03 00 00 13 03 83 00 F3 22 00 30
-B3 E2 62 00 73 90 02 30 37 13 00 00 13 03 03 80
-F3 22 40 30 B3 E2 62 00 73 90 42 30 97 00 00 00
-93 80 00 01 73 90 50 30 73 00 50 10 63 14 00 00
+17 05 00 00 13 05 85 2C EF F0 5F 90 13 05 30 00
+EF F0 5F 94 67 80 00 00 6F 00 C0 00 13 04 14 00
+73 00 20 30 93 01 00 00 97 00 00 00 93 80 40 FF
+73 90 50 30 93 01 10 00 37 13 00 00 13 03 03 80
+F3 22 40 30 B3 E2 62 00 73 90 42 30 37 03 00 00
+13 03 83 00 F3 22 00 30 B3 E2 62 00 73 90 02 30
+93 02 10 00 63 90 82 06 93 01 20 00 73 00 50 10
+93 02 20 00 63 98 82 04 93 01 30 00 37 03 00 00
+13 03 73 FF F3 22 00 30 B3 F2 62 00 73 90 02 30
+73 00 50 10 73 10 40 30 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 73 00 50 10 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 63 14 00 00
 63 1A 30 00 13 95 11 00 63 00 05 00 13 65 15 00
 73 00 00 00 13 05 10 00 73 00 00 00 73 00 10 00
 73 10 00 C0
-@800029D8
+@80002A38
 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64
 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C
 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20