From 9ef343f5e403d2dba2b4702e3025828f8a3c6bf3 Mon Sep 17 00:00:00 2001
From: Damien Pretet <damien.pretet@me.com>
Date: Tue, 21 Nov 2023 20:49:31 +0100
Subject: [PATCH] Change: update REPL app to use config file

---
 doc/TODO.md              |  7 ++++++-
 rtl/friscv_control.sv    | 12 ++++++++++++
 test/apps/config.cfg     |  8 ++++++++
 test/apps/run.sh         |  8 +++++---
 test/common/functions.sh |  2 +-
 5 files changed, 32 insertions(+), 5 deletions(-)
 create mode 100644 test/apps/config.cfg

diff --git a/doc/TODO.md b/doc/TODO.md
index 5a5e8df..c1fa0c6 100644
--- a/doc/TODO.md
+++ b/doc/TODO.md
@@ -24,7 +24,8 @@
     - [X] if MIE/SIE=0, wait for any intp and move forward
     - [X] Support MSTATUS.TW (timeout platform-dependent)
 - [X] add FIFO for memory exceptions
-- [ ] mcounteren: accessibility to lower privilege modes
+- [X] Drive aprot[0] based on priviledge mode
+- [X] mcounteren: accessibility to lower privilege modes
     - Bit x = 1, lower privilege mode can read the counter
     - Bit x = 0, lower privilege mode access is forbidden and raise an illegal instruction exception
 
@@ -58,6 +59,10 @@ MPU:
     - [X] execute in M-mode without X + locked region
 - [X] locked access to change configuration
 
+MCOUNTER:
+- Bit x = 1, lower privilege mode can read the counter
+- Bit x = 0, lower privilege mode access is forbidden and raise an illegal instruction exception
+
 Final:
 - Pass compliance with U-mode
 - Run REPL app
diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
index 563a261..e3907f3 100644
--- a/rtl/friscv_control.sv
+++ b/rtl/friscv_control.sv
@@ -752,7 +752,9 @@ module friscv_control
                         if (jalr | branching) begin
 
                             if (!cant_jump) begin
+                                `ifdef USE_SVL
                                 print_instruction;
+                                `endif
                                 pc_reg <= pc;
                             end
 
@@ -773,7 +775,9 @@ module friscv_control
                                 log.info("JAL");
                             `endif
 
+                            `ifdef USE_SVL
                             print_instruction;
+                            `endif
                             pc_reg <= pc;
                             flush_pipe <= 1'b1;
 
@@ -844,20 +848,26 @@ module friscv_control
 
                             // CSR instructions
                             end else if (sys[`IS_CSR] && !cant_sys) begin
+                                `ifdef USE_SVL
                                 print_instruction;
+                                `endif
                                 flush_pipe <= 1'b0;
                                 pc_reg <= pc;
 
                             // FENCE instruction (not supported)
                             end else if (!proc_busy && csr_ready) begin
+                                `ifdef USE_SVL
                                 print_instruction;
+                                `endif
                                 flush_pipe <= 1'b0;
                                 pc_reg <= pc;
                             end
 
                         // LUI and AUIPC execution, done in this module
                         end else if (lui_auipc && !cant_lui_auipc) begin
+                            `ifdef USE_SVL
                             print_instruction;
+                            `endif
                             flush_pipe <= 1'b0;
                             pc_reg <= pc;
 
@@ -865,7 +875,9 @@ module friscv_control
                         end else if (processing) begin
 
                             if (!cant_process) begin
+                                `ifdef USE_SVL
                                 print_instruction;
+                                `endif
                                 flush_pipe <= 1'b0;
                                 pc_reg <= pc;
                             end
diff --git a/test/apps/config.cfg b/test/apps/config.cfg
new file mode 100644
index 0000000..1acdd4a
--- /dev/null
+++ b/test/apps/config.cfg
@@ -0,0 +1,8 @@
+XLEN,32
+CACHE_EN,1
+CACHE_BLOCK_W,128
+GEN_EIRQ,0
+ERROR_STATUS_X31,1
+USER_MODE,0
+CONTROL_VERBOSITY,0
+CONTROL_ROUTE,2
diff --git a/test/apps/run.sh b/test/apps/run.sh
index 1679a17..c4dfd0e 100755
--- a/test/apps/run.sh
+++ b/test/apps/run.sh
@@ -12,6 +12,8 @@ set -e
 # Variables and setup
 #------------------------------------------------------------------------------
 
+cfg_file="config.cfg"
+
 # Disable runtime timeout check for this testbench
 TIMEOUT=0
 
@@ -19,7 +21,7 @@ TIMEOUT=0
 MIN_PC=65692
 
 # Don't drop VCD, to avoid storing GB of raw data
-NO_VCD=1
+NO_VCD=0
 
 # Enable UART link to the processor (platform only)
 INTERACTIVE=1
@@ -96,11 +98,11 @@ main() {
 
     # If user specified a testcase, or a testsuite, use it
     if [[ -n $TC ]]; then
-        run_testsuite "$TC"
+        run_testsuite "$TC" "$cfg_file"
     # Else run all the supported testsuite
     else
         # Execute the testsuites
-        run_testsuite "./tests/*.v"
+        run_testsuite "./tests/*.v" "$cfg_file"
     fi
 
     # OK, sounds good, exit gently
diff --git a/test/common/functions.sh b/test/common/functions.sh
index 579b052..9e60223 100755
--- a/test/common/functions.sh
+++ b/test/common/functions.sh
@@ -73,7 +73,7 @@ read_config() {
     cen=0 # cache enable
     cw=32 # cache width
 
-    DEFINES="FRISV_SIM=1;USE_SVL=1;"
+    DEFINES="FRISV_SIM=1;USE_SVL=0;"
 
     while IFS=, read -r name value; do
         DEFINES="${DEFINES}${name}=${value};"