diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index 6ef25fc..770c15e 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -1220,9 +1220,9 @@ module friscv_control assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready; // Is fetching instruction on forbidden memory region - assign inst_access_fault = (!mpu_allow[`PMA_X] | !mpu_allow[`PMA_R]) & + assign inst_access_fault = (!mpu_allow[`ALW_X] | !mpu_allow[`ALW_R]) & (priv_mode == `UMODE || - priv_mode==`MMODE && mpu_allow[3] /*locked*/); + priv_mode==`MMODE && mpu_allow[`ALW_L]); ////////////////////////////////////////////////////////////////////// // Stores the incoming excpetions from processing. Can't handle diff --git a/rtl/friscv_h.sv b/rtl/friscv_h.sv index 2552da5..91d13c9 100644 --- a/rtl/friscv_h.sv +++ b/rtl/friscv_h.sv @@ -128,6 +128,11 @@ `define PMA_A 3 // 4:3 `define PMA_L 7 +`define ALW_R 0 +`define ALW_W 1 +`define ALW_X 2 +`define ALW_L 3 + ////////////////////////////////////////////////////////////////// // Instruction bus feeding ALUs ////////////////////////////////////////////////////////////////// diff --git a/rtl/friscv_memfy.sv b/rtl/friscv_memfy.sv index d524926..b5471cf 100644 --- a/rtl/friscv_memfy.sv +++ b/rtl/friscv_memfy.sv @@ -435,7 +435,7 @@ module friscv_memfy opcode_r <= opcode; // STORE - if (opcode==`STORE && mpu_allow[`PMA_W] && !store_misaligned) begin + if (opcode==`STORE && mpu_allow[`ALW_W] && !store_misaligned) begin if (waiting_rd_cpl || arvalid) begin state <= WAIT; @@ -460,7 +460,7 @@ module friscv_memfy arvalid <= 1'b0; // LOAD - end else if (opcode==`LOAD && mpu_allow[`PMA_R] && !load_misaligned) begin + end else if (opcode==`LOAD && mpu_allow[`ALW_R] && !load_misaligned) begin if (waiting_wr_cpl || awvalid) begin state <= WAIT; arvalid <= 1'b0; @@ -637,14 +637,14 @@ module friscv_memfy end else begin // Write xfers tracker - if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or) begin + if (memfy_valid && memfy_ready && opcode==`STORE && !bvalid && !max_wr_or && mpu_allow[`ALW_W]) begin wr_or_cnt <= wr_or_cnt + 1'b1; end else if (!(memfy_valid && memfy_ready && opcode==`STORE) && bvalid && bready && wr_or_cnt!={MAX_OR_W{1'b0}}) begin wr_or_cnt <= wr_or_cnt - 1'b1; end // Read xfers tracker - if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or) begin + if (memfy_valid && memfy_ready && opcode==`LOAD && !memfy_rd_wr && !max_rd_or && mpu_allow[`ALW_R]) begin rd_or_cnt <= rd_or_cnt + 1'b1; end else if (!(memfy_valid && memfy_ready && opcode==`LOAD) && memfy_rd_wr && rd_or_cnt!={MAX_OR_W{1'b0}}) begin rd_or_cnt <= rd_or_cnt - 1'b1; @@ -769,7 +769,7 @@ module friscv_memfy ------------------------------------------------------------------------------------------------ ACACHE | AWCACHE | ARCACHE - [3] [2] [1] [0] | | + [3] [2] [1] [0] | | ------------------------------------------------------------------------------------------------ 0 0 0 0 | Device Non-cacheable Non-bufferable | Device Non-cacheable Non-bufferable 0 0 0 1 | Device Non-cacheable Bufferable | Device Non-cacheable Bufferable @@ -781,7 +781,7 @@ module friscv_memfy | Write-Through Read-Allocate | ------------------------------------------------------------------------------------------------ 0 1 1 1 | Write-Back No-Allocate | Write-Back Read-Allocate - | Write-Back Read-Allocate | + | Write-Back Read-Allocate | ------------------------------------------------------------------------------------------------ 1 0 1 0 | Write-Through Write-Allocate | Write-Through No-Allocate | | Write-Through Write-Allocate @@ -843,10 +843,10 @@ module friscv_memfy 1'b0 ; // Load access outside am allowed region - assign load_access_fault = (opcode==`LOAD) & !mpu_allow[`PMA_R] & check_access & active_access; + assign load_access_fault = (opcode==`LOAD) & !mpu_allow[`ALW_R] & check_access & active_access; // Store access outside am allowed region - assign store_access_fault = (opcode==`STORE) & !mpu_allow[`PMA_W] & check_access & active_access; + assign store_access_fault = (opcode==`STORE) & !mpu_allow[`ALW_W] & check_access & active_access; // Shared bus routing back to control unit diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v index 7cfcfd9..717b5dd 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v @@ -1,9 +1,9 @@ @00010000 -6F 00 80 08 73 2F 20 34 93 0E 80 00 63 08 DF 6B +6F 00 80 08 73 2F 20 34 93 0E 80 00 63 02 DF 6D 93 0E 90 00 63 02 DF 1B 93 0E B0 00 63 02 DF 1B 93 0E 20 00 63 00 DF 1B B7 0E 00 80 93 8E BE 00 -63 00 DF 6D B7 0E 00 80 93 8E 3E 00 63 0A DF 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00 +13 04 00 00 13 05 00 00 93 05 00 00 37 06 10 00 +93 06 F0 09 93 06 80 01 93 08 80 00 73 00 00 00 +EF 00 00 05 B7 02 10 00 23 20 50 00 03 23 00 00 +63 9A 62 06 23 AE 52 FE 03 A3 C2 FF 63 94 62 06 B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00 -13 00 00 00 93 02 10 00 63 12 54 04 93 08 00 00 -73 00 00 00 6F 00 C0 05 93 02 00 00 13 03 A0 00 -93 03 00 00 13 0E 00 00 B3 83 53 00 23 20 7E 00 -93 83 13 00 83 23 0E 00 93 82 12 00 13 9E 22 00 -E3 94 62 FE 67 80 00 00 63 14 30 02 0F 00 F0 0F -63 80 01 00 93 91 11 00 93 E1 11 00 93 08 D0 05 -13 85 01 00 93 8F 1F 00 73 00 10 00 73 00 10 00 -0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00 -73 00 10 00 73 00 10 00 73 10 00 C0 00 00 00 00 +13 00 00 00 93 02 10 00 63 16 54 04 13 04 00 00 +93 08 00 00 73 00 00 00 13 04 00 00 6F 00 C0 05 +93 02 00 00 13 03 A0 00 93 03 00 00 13 0E 00 00 +B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00 +93 82 12 00 13 9E 22 00 E3 94 62 FE 67 80 00 00 +63 14 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00 +93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00 +73 00 10 00 73 00 10 00 0F 00 F0 0F 93 01 10 00 +93 08 D0 05 13 05 00 00 73 00 10 00 73 00 10 00 +73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @00011000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v index 84598d5..011d2ce 100755 --- a/test/priv_sec_testsuite/tests/rv64ui-v-test2.v +++ b/test/priv_sec_testsuite/tests/rv64ui-v-test2.v @@ -114,11 +114,11 @@ E3 9C 07 FD 73 90 08 10 93 97 36 00 B3 06 F6 00 63 94 E5 04 93 96 36 00 B3 06 D6 00 23 B0 F6 00 73 00 05 12 83 30 81 00 13 01 01 01 67 80 00 00 93 E7 07 04 6F F0 1F FE 97 77 00 00 23 BC 07 B2 -6F F0 1F F0 17 15 00 00 13 05 C5 B2 EF F0 1F D8 -13 05 30 00 EF F0 1F DC 17 15 00 00 13 05 05 B6 +6F F0 1F F0 17 15 00 00 13 05 45 B8 EF F0 1F D8 +13 05 30 00 EF F0 1F DC 17 15 00 00 13 05 85 BB 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C0 13 05 30 00 EF F0 DF C4 03 29 05 05 37 1C 00 00 97 24 00 00 93 84 C4 99 97 3B 00 00 93 8B 4B 99 37 0B 04 00 B7 0A E0 FF 97 7D 00 00 @@ -151,10 +151,10 @@ EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05 93 FC 0C 08 83 35 81 00 63 80 0C 04 37 16 00 00 13 05 0C 00 EF F0 DF 8F B3 87 84 00 73 10 0D 10 03 B7 0D 00 23 B0 07 00 E3 1E 07 F6 23 B0 FD 00 -23 30 FA 00 6F F0 9F F7 17 15 00 00 13 05 85 A8 -EF F0 DF B2 6F F0 5F F0 17 15 00 00 13 05 85 A1 +23 30 FA 00 6F F0 9F F7 17 15 00 00 13 05 05 AE +EF F0 DF B2 6F F0 5F F0 17 15 00 00 13 05 05 A7 EF F0 DF B1 13 05 30 00 EF F0 DF B5 17 15 00 00 -13 05 C5 9C EF F0 9F B0 13 05 30 00 EF F0 9F B4 +13 05 45 A2 EF F0 9F B0 13 05 30 00 EF F0 9F B4 13 05 09 00 EF F0 1F B4 F3 27 40 F1 63 9A 07 18 97 57 00 00 93 87 07 89 13 01 01 ED 93 D7 C7 00 23 30 81 12 17 68 00 00 13 08 C8 87 13 04 05 00 @@ -186,114 +186,120 @@ E3 1A E3 FC 13 06 00 12 93 05 00 00 13 05 01 00 2F 20 07 00 13 D7 17 00 B3 C7 E7 00 93 97 E7 03 B3 F7 D7 00 B3 E7 E7 00 33 F7 C7 00 93 F5 17 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00 +6F 00 80 32 13 04 14 00 73 00 20 30 6F 00 C0 31 +13 56 16 00 13 06 F6 FF B3 85 C5 00 93 D5 25 00 +6F 00 40 00 93 02 40 00 63 42 55 02 93 02 80 00 +63 40 55 0C 93 02 C0 00 63 4E 55 14 93 02 00 01 +63 4C 55 1E 13 05 10 00 6F 00 00 2E 93 D5 25 00 +73 23 00 3A 93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 93 02 30 00 -63 8E A2 04 73 90 45 3B 9B 02 10 00 93 92 02 02 -93 82 02 F0 33 73 53 00 6F 00 C0 05 73 90 55 3B +63 8E A2 04 73 90 05 3B 9B 02 10 00 93 92 02 02 +93 82 02 F0 33 73 53 00 6F 00 C0 05 73 90 15 3B B7 02 01 00 9B 82 F2 FF 93 92 02 01 93 82 F2 0F -33 73 53 00 93 96 86 00 6F 00 C0 03 73 90 65 3B +33 73 53 00 93 96 86 00 6F 00 C0 03 73 90 25 3B B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF -33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 75 3B +33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 35 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 -6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 80 19 +6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 C0 23 93 D5 25 00 73 23 10 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02 01 00 9B 82 12 F0 93 92 02 01 +93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 +73 90 A5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 73 90 B5 3B 33 63 D3 00 +73 10 03 3A 6F 00 40 0F 93 D5 25 00 73 23 30 3A +93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02 +93 02 20 00 63 82 A2 04 93 02 30 00 63 8E A2 04 +73 90 C5 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 +33 73 53 00 6F 00 C0 05 73 90 D5 3B B7 02 01 00 +9B 82 F2 FF 93 92 02 01 93 82 F2 0F 33 73 53 00 +93 96 86 00 6F 00 C0 03 73 90 E5 3B B7 02 01 00 +9B 82 12 F0 93 92 02 01 93 82 F2 FF 33 73 53 00 +93 96 06 01 6F 00 C0 01 73 90 F5 3B B7 02 00 01 +9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 +33 63 D3 00 73 10 33 3A 6F 00 00 05 93 02 00 00 +63 04 57 04 93 02 80 00 E3 0E 57 D2 93 02 00 01 +E3 0E 57 D0 93 02 80 01 E3 0C 57 D0 13 05 10 00 +6F 00 80 02 93 0E 00 00 E3 8C D8 A9 93 0E 10 00 +E3 82 D8 AF 93 0E 80 00 E3 82 D8 FD 93 0E 90 00 +E3 8C D8 CB 6F 00 40 00 F3 2E 10 34 93 8E 4E 00 +73 90 1E 34 73 00 20 30 13 0A 1A 00 73 00 20 30 +93 08 00 00 73 00 00 00 93 08 10 00 73 00 00 00 +13 05 00 00 B7 05 10 00 13 06 00 00 93 06 F0 08 +13 07 80 00 93 08 80 00 73 00 00 00 EF 00 40 0B +B7 02 10 00 23 20 50 00 03 23 00 00 63 9C 62 0C +23 AE 52 FE 03 A3 C2 FF 63 96 62 0C B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00 13 00 00 00 -93 02 10 00 63 14 54 08 93 08 00 00 73 00 00 00 -13 05 00 00 93 05 00 00 37 06 10 00 93 06 F0 09 -93 06 80 01 93 08 80 00 73 00 00 00 EF 00 C0 02 +93 02 10 00 63 18 54 0A 93 08 00 00 73 00 00 00 +13 04 00 00 13 05 00 00 93 05 00 00 37 06 10 00 +93 06 F0 09 93 06 80 01 93 08 80 00 73 00 00 00 +EF 00 00 05 B7 02 10 00 23 20 50 00 03 23 00 00 +63 9A 62 06 23 AE 52 FE 03 A3 C2 FF 63 94 62 06 B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00 -13 00 00 00 93 02 10 00 63 12 54 04 93 08 00 00 -73 00 00 00 6F 00 80 04 93 02 00 00 13 03 A0 00 -93 03 00 00 13 0E 00 00 B3 83 53 00 23 20 7E 00 -93 83 13 00 83 23 0E 00 93 82 12 00 13 9E 22 00 -E3 94 62 FE 67 80 00 00 63 1A 30 00 13 95 11 00 -63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00 -73 00 00 00 73 00 10 00 73 10 00 C0 -@80003000 +13 00 00 00 93 02 10 00 63 16 54 04 13 04 00 00 +93 08 00 00 73 00 00 00 13 04 00 00 6F 00 80 04 +93 02 00 00 13 03 A0 00 93 03 00 00 13 0E 00 00 +B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00 +93 82 12 00 13 9E 22 00 E3 94 62 FE 67 80 00 00 +63 1A 30 00 13 95 11 00 63 00 05 00 13 65 15 00 +73 00 00 00 13 05 10 00 73 00 00 00 73 00 10 00 +73 10 00 C0 +@80003058 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S index 46f3d89..bd90040 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test2.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S @@ -88,7 +88,6 @@ ILLEGAL_INSTRUCTION: ebreak - //////////////////////////////////////////// // Erase all PMP configurations //////////////////////////////////////////// @@ -308,8 +307,15 @@ EXP_SERVICE: # Configure a NAPOT / NA4 region //////////////////////////////////////////// SET_NA4: -SET_NAPOT: j RET_ECALL +SET_NAPOT: + # napot_size = ((size/2)-1) + srli a2, a2, 1 + addi a2, a2, -1 + # pmp_addr = (base + napot_size)>>2 + add a1, a1, a2 + srli a1, a1, 2 + j SET_PMP //////////////////////////////////////////// @@ -589,11 +595,20 @@ TEST3_1TOR: // Run some duties into the region TEST3_RW_ACCESS: call LD_ST_ARITH -// Try to access outside the memory region +// Try to access the extreme boundaries of the memory region +TEST3_BOUNDS: + li t0, S1MB + // Check lowest bound + sw t0, 0(zero) + lw t1, 0(zero) + bne t0, t1, fail + // Check highest bound + sw t0, -4(t0) + lw t1, -4(t0) + bne t0, t1, fail + TEST3_OUT_OF_BOUND: li t0, S1MB - # lui t0, %hi(S1MB) - # addi t0, t0, %lo(S1MB) sw x0, 0(t0) // raise an exception, which will increment s0 # bunch of nop to wait for exception handling nop @@ -606,7 +621,7 @@ TEST3_OUT_OF_BOUND: TEST3_TEARDOWN: li a7, 0 ecall - # j pass + li s0, 0 // NAPOT region - 1MB RWX TEST4_1NAPOT: @@ -621,6 +636,17 @@ TEST4_1NAPOT: // Run some duties into the region TEST4_RW_ACCESS: call LD_ST_ARITH +// Try to access the extreme boundaries of the memory region +TEST4_BOUNDS: + li t0, S1MB + // Check lowest bound + sw t0, 0(zero) + lw t1, 0(zero) + bne t0, t1, fail + // Check highest bound + sw t0, -4(t0) + lw t1, -4(t0) + bne t0, t1, fail // Try to access outside the memory region TEST4_OUT_OF_BOUND: li t0, S1MB @@ -634,10 +660,12 @@ TEST4_OUT_OF_BOUND: // Check the exception has been handled correctly li t0, 1 bne s0, t0, fail + li s0, 0 TEST4_TEARDOWN: li a7, 0 ecall + li s0, 0 j pass