Skip to content

Commit

Permalink
Reindent code by removing tabs
Browse files Browse the repository at this point in the history
  • Loading branch information
@dpretet
dpretet committed Nov 22, 2023
1 parent 9ef343f commit d86cceb
Show file tree
Hide file tree
Showing 4 changed files with 132 additions and 133 deletions.
1 change: 0 additions & 1 deletion doc/TODO.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,5 @@ MCOUNTER:

Final:
- Pass compliance with U-mode
- Run REPL app
- Review testcases
- Parse again the documentation
12 changes: 6 additions & 6 deletions rtl/friscv_div.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ module friscv_div
input wire aclk,
input wire aresetn,
input wire srst,
output logic div_pending,
output logic div_pending,
// Input interface
input wire i_valid, // AMBA-like handshake
output logic i_ready,
Expand Down Expand Up @@ -86,7 +86,7 @@ module friscv_div
o_valid <= 1'b0;
computing <= 1'b0;
step_cnt <= {CWIDTH{1'b0}};
div_pending <= 1'b0;
div_pending <= 1'b0;
end else if (srst) begin
zero_div <= 1'b0;
quot_sign <= 1'b0;
Expand All @@ -99,7 +99,7 @@ module friscv_div
o_valid <= 1'b0;
computing <= 1'b0;
step_cnt <= {CWIDTH{1'b0}};
div_pending <= 1'b0;
div_pending <= 1'b0;
end else begin

/////////////////////////////////
Expand Down Expand Up @@ -165,20 +165,20 @@ module friscv_div
i_ready <= 1'b1;
quot <= {WIDTH{1'b1}};
rem <= divd;
div_pending <= 1'b0;
div_pending <= 1'b0;
// Move to compute the division
end else begin
zero_div <= 1'b0;
o_valid <= 1'b0;
i_ready <= 1'b0;
computing <= 1'b1;
div_pending <= 1'b1;
div_pending <= 1'b1;
end

end else begin
i_ready <= 1'b1;
o_valid <= 1'b0;
div_pending <= 1'b0;
div_pending <= 1'b0;
end
end
end
Expand Down
92 changes: 46 additions & 46 deletions rtl/friscv_m_ext.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
module friscv_m_ext

#(
// Number of integer registers (RV32I = 32, RV32E = 16)
// Number of integer registers (RV32I = 32, RV32E = 16)
parameter NB_INT_REG = 32,
// Architecture selection
parameter XLEN = 32
Expand All @@ -22,8 +22,8 @@ module friscv_m_ext
input wire m_valid,
output logic m_ready,
input wire [`INST_BUS_W -1:0] m_instbus,
output logic [NB_INT_REG -1:0] m_regs_sts,
output logic div_pending,
output logic [NB_INT_REG -1:0] m_regs_sts,
output logic div_pending,
// register source 1 query interface
output logic [5 -1:0] m_rs1_addr,
input wire [XLEN -1:0] m_rs1_val,
Expand Down Expand Up @@ -67,10 +67,10 @@ module friscv_m_ext
logic m_valid_div;
logic signed_div;

localparam MAX_OR = 1;
localparam MAX_OR = 1;
localparam MAX_OR_W = $clog2(MAX_OR) + 1;

logic [MAX_OR_W -1:0] regs_or[NB_INT_REG-1:0];
logic [MAX_OR_W -1:0] regs_or[NB_INT_REG-1:0];


///////////////////////////////////////////////////////////////////////////
Expand All @@ -86,36 +86,36 @@ module friscv_m_ext
assign rs2 = m_instbus[`RS2 +: `RS2_W ];
assign rd = m_instbus[`RD +: `RD_W ];

////////////////////////////////////////////////////////////////////////
// Track which integer registers is used by an outstanding request
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Track which integer registers is used by an outstanding request
////////////////////////////////////////////////////////////////////////

always @ (posedge aclk or negedge aresetn) begin

if (!aresetn) regs_or[0] <= '0;
else regs_or[0] <= '0;
if (!aresetn) regs_or[0] <= '0;
else regs_or[0] <= '0;

for (int i=1;i<NB_INT_REG;i++) begin
if (!aresetn) begin
regs_or[i] <= '0;
end else begin
if ((m_valid && m_ready && rd == i[4:0]) &&
!(m_rd_wr && m_rd_addr==i[4:0]))
begin
regs_or[i] <= regs_or[i] + 1;

end else if (!(m_valid && m_ready && rd == i[4:0]) &&
(m_rd_wr && m_rd_addr==i[4:0]))
begin
regs_or[i] <= regs_or[i] - 1;
end
end
end
end
for (int i=1;i<NB_INT_REG;i++) begin
if (!aresetn) begin
regs_or[i] <= '0;
end else begin
if ((m_valid && m_ready && rd == i[4:0]) &&
!(m_rd_wr && m_rd_addr==i[4:0]))
begin
regs_or[i] <= regs_or[i] + 1;

end else if (!(m_valid && m_ready && rd == i[4:0]) &&
(m_rd_wr && m_rd_addr==i[4:0]))
begin
regs_or[i] <= regs_or[i] - 1;
end
end
end
end

for (genvar i=0;i<NB_INT_REG;i++) begin
assign m_regs_sts[i] = regs_or[i] == '0;
end
for (genvar i=0;i<NB_INT_REG;i++) begin
assign m_regs_sts[i] = regs_or[i] == '0;
end


///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -172,26 +172,26 @@ module friscv_m_ext
assign m_valid_div = m_valid & funct3[2];
assign signed_div = (funct3==`DIV) | (funct3==`REM);

friscv_div
friscv_div
#(
.WIDTH (XLEN)
)
div32
(
.aclk (aclk),
.aresetn (aresetn),
.srst (srst),
.div_pending (div_pending),
.i_valid (m_valid_div),
.i_ready (m_ready),
.signed_div (signed_div),
.divd (m_rs1_val),
.divs (m_rs2_val),
.o_valid (rd_wr_div),
.o_ready (1'b1),
.zero_div (),
.quot (quot),
.rem (rem)
.aclk (aclk),
.aresetn (aresetn),
.srst (srst),
.div_pending (div_pending),
.i_valid (m_valid_div),
.i_ready (m_ready),
.signed_div (signed_div),
.divd (m_rs1_val),
.divs (m_rs2_val),
.o_valid (rd_wr_div),
.o_ready (1'b1),
.zero_div (),
.quot (quot),
.rem (rem)
);


Expand Down Expand Up @@ -231,7 +231,7 @@ module friscv_m_ext
end else begin
m_rd_val <= (rd_wr_div && (funct3_r==`DIV || funct3_r==`DIVU)) ? quot :
(rd_wr_div && (funct3_r==`REM || funct3_r==`REMU)) ? rem :
(opcode==`MULDIVW) ? mul64 :
(opcode==`MULDIVW) ? mul64 :
mul32 ;
end
end
Expand Down
Loading

0 comments on commit d86cceb

Please sign in to comment.