diff --git a/doc/TODO.md b/doc/TODO.md index 081e128..b982424 100644 --- a/doc/TODO.md +++ b/doc/TODO.md @@ -46,27 +46,28 @@ U-mode Interrupt - [X] Do something within a loop with interrupt enabled, data needs to be OK -- [ ] WFI in u-mode, interrupt enabled, trapped in m-mode -- [ ] WFI in u-mode, interrupt disabled, NOP +- [X] WFI in u-mode, interrupt enabled, trapped in m-mode +- [X] WFI in u-mode, interrupt disabled, NOP - [ ] Add test for vector table - [ ] Test des exception load/store misaligned -- [ ] test MSTATUS.TW +- [ ] Test MSTATUS.TW MPU: - [X] configure registers -- [ ] all region configuration mode: NA4 / NAPOT / TOR -- [ ] multiple mixed region type and size -- [ ] Access exceptions - -> Store = store access-fault - -> Load = load access-fault - -> Execute = instruction access-fault - - [ ] read/execute instruction outside allowed regions (U-mode) - - [ ] read/write data in U-mode - - [ ] read/write data in M-mode with MPRV + MPP w/ U-mode +- [X] all region configuration mode: NA4 / NAPOT / TOR +- [X] multiple mixed region type and size +- [-] Access exceptions + - [X] execute instruction outside allowed regions (U-mode) + - [X] write data in U-mode + - [X] read data in U-mode + - [ ] read data in M-mode with MPRV=1 + MPP w/ U-mode + - [ ] write data in M-mode with MPRV=1 + MPP w/ U-mode + - [ ] execute in M-mode without X + locked region - [ ] locked access to change configuration -- [ ] locked region accessed wrongly by m-mode +- [ ] region's permissions overlap Final: - Pass compliance with U-mode +- Run REPL app - Review testcases - Parse again the documentation diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md index 62c0ef1..d773ed1 100644 --- a/doc/project_mgt_hw.md +++ b/doc/project_mgt_hw.md @@ -6,7 +6,9 @@ - [-] Support PMP/PMA - [ ] Atomic operations for single core - [ ] AXI Exception management with a CLIC + - maange all traps into it? - [ ] Zc extension + - [ ] https://github.com/eembc/coremark # BACKLOG @@ -39,6 +41,7 @@ Any new features should be carefully study to ensure a proper exception and inte - raise an exception - methode AER-like pour les enregistrer: src, address, permission - trig an interrupt catched with PLIC controller + - https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html ## Cache Stages @@ -55,6 +58,7 @@ Any new features should be carefully study to ensure a proper exception and inte - [ ] New cache associativity (2 / 4 / 8 ways configurable) - [ ] OoO read: miss could be stacked and served later waiting for cache fill and continue reading the next address - [ ] Fully concurrent read / write access (Issue #1) + - Split memfy in load unit & store unit ## Miscellanous diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index 3f8c4a8..1c8becf 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -659,7 +659,7 @@ module friscv_control // new instruction from memory: /////////////////////////////////////////////////////////// - // + // // Any trap handling, asynchronous and synchronous // if (trap_occuring) begin @@ -896,7 +896,7 @@ module friscv_control status <= 5'b0; flush_pipe <= 1'b1; if (USER_MODE && sb_mie) priv_mode <= `MMODE; - + if (sb_mie) begin arid <= next_id(arid, MAX_ID, AXI_ID_MASK); araddr <= mtvec; @@ -1190,7 +1190,7 @@ module friscv_control ) ? 1'b1 : 1'b0; // PC is not aligned with XLEN boundary - assign inst_addr_misaligned = (pc[1:0]!=2'b0) ? jump_branch : 1'b0; + assign inst_addr_misaligned = (pc[1:0]!=2'b0) ? inst_ready : 1'b0; ////////////////////////////////////////////////////////////////////// // WFI timeout management @@ -1228,13 +1228,13 @@ module friscv_control // Unsupported instruction assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready; - // Is fetching instruction on forbidden memory region - assign inst_access_fault = (!mpu_allow[`ALW_X] | !mpu_allow[`ALW_R]) & + // Is fetching instruction on forbidden memory region + assign inst_access_fault = !mpu_allow[`ALW_X] & (priv_mode == `UMODE || - priv_mode==`MMODE && mpu_allow[`ALW_L]); + priv_mode == `MMODE & mpu_allow[`ALW_L]); ////////////////////////////////////////////////////////////////////// - // Stores the incoming excpetions from processing. Can't handle + // Stores the incoming excpetions from processing. Can't handle // multiple exceptions on the same cycle but should not arrive ////////////////////////////////////////////////////////////////////// friscv_scfifo @@ -1266,7 +1266,7 @@ module friscv_control proc_exceptions[`SAF] ; // Pull when we trap for one the processing exceptions - assign pull_proc_exp = (trap_occuring && !cant_trap && + assign pull_proc_exp = (trap_occuring && !cant_trap && (mcause_code == 32'h5 || mcause_code == 32'h7 || mcause_code == 32'h4 || @@ -1298,11 +1298,11 @@ module friscv_control '0 ; assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR]) ? 1'b0 : - (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle - (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time - (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret - (csr[11:4]=='hFC) ? inst_ready : // Custom perf. registers - (csr[ 9:8]!=2'b00) ? inst_ready : // M-Mode only registers + (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle + (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time + (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret + (csr[11:4]=='hFC) ? inst_ready : // Custom perf. registers + (csr[ 9:8]!=2'b00) ? inst_ready : // M-Mode only registers 1'b0 ; end else begin : NO_UMODE diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw index 2f1d5e9..e61541c 100644 --- a/test/common/debug_platform_verilator.gtkw +++ b/test/common/debug_platform_verilator.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Wed Nov 1 17:32:10 2023 +[*] Tue Nov 7 19:31:27 2023 [*] [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd" -[dumpfile_mtime] "Wed Nov 1 17:03:56 2023" -[dumpfile_size] 9007697 +[dumpfile_mtime] "Sun Nov 5 19:46:50 2023" +[dumpfile_size] 61559319 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw" -[timestart] 6058 -[size] 2560 1440 +[timestart] 1 +[size] 1440 900 [pos] -1 -1 -*-5.355745 6239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-14.355745 29879 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] friscv_testbench. [treeopen] friscv_testbench.friscv_testbench. [treeopen] friscv_testbench.friscv_testbench.genblk2. @@ -24,10 +24,10 @@ [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks. -[sst_width] 365 -[signals_width] 344 +[sst_width] 253 +[signals_width] 262 [sst_expanded] 1 -[sst_vpaned_height] 365 +[sst_vpaned_height] 211 @c00200 -AXI4-lite RAM @22 @@ -104,7 +104,9 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg1[31:0] +@23 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg2[31:0] +@22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg3[31:0] @200 - @@ -125,34 +127,6 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr12[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr13[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr14[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpaddr15[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mstatus[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_rden -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_wren -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr[11:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.newval[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.oldval[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0] @1000200 -CSRs @800200 @@ -288,9 +262,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid - @28 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring -@29 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring -@28 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring @200 - @@ -306,7 +278,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned @200 - -@c00200 +@800200 -CSRs @c00022 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0] @@ -413,6 +385,8 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk @200 - +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mie @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mcounteren[31:0] @28 @@ -431,13 +405,13 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtie friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtip @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtvec[31:0] -@1401200 +@1000200 -CSRs @200 - @1000200 -control -@800200 +@c00200 -Memfy @28 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid @@ -488,7 +462,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_access friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_misaligned @200 - -@1000200 +@1401200 -Memfy @c00200 -Registers @@ -526,7 +500,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0] @1401200 -Registers -@800200 +@c00200 -MPU @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.imem_addr[31:0] @@ -617,6 +591,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKER friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_mask[31:0] @1000200 -Region 1 +@1401200 -MPU [pattern_trace] 1 [pattern_trace] 0 diff --git a/test/common/functions.sh b/test/common/functions.sh index 9f990f4..579b052 100755 --- a/test/common/functions.sh +++ b/test/common/functions.sh @@ -156,10 +156,10 @@ gather_result() { msg=$(grep -ni "ERROR:" tc.log) if [ "$2" -eq 1 ] || [ "$ec" != 0 ]; then - ts_res="${ts_res} - $1:\t❌\n" + ts_res="${ts_res} ❌ $1\n" ts_res="${ts_res}$msg\n" else - ts_res="${ts_res} - $1:\t✅\n" + ts_res="${ts_res} ✅ $1\n" fi } #------------------------------------------------------------------------------ diff --git a/test/priv_sec_testsuite/tests/env/pmp.S b/test/priv_sec_testsuite/tests/env/pmp.S index dfaa9b0..da9060f 100644 --- a/test/priv_sec_testsuite/tests/env/pmp.S +++ b/test/priv_sec_testsuite/tests/env/pmp.S @@ -1,6 +1,18 @@ # distributed under the mit license # https://opensource.org/licenses/mit-license.php +.equ PMPADDR, 0xFFFFFFFF +.equ PMPCFG, 0x77777777 + +.equ S2MB, 0x200000 +.equ S1MB, 0x100000 +.equ S512K, 0x80000 +.equ S256K, 0x40000 +.equ S64KB, 0x10000 +.equ S16KB, 0x10000 +.equ S4KB, 0x4000 +.equ S1KB, 0x1000 + .equ OFF, 0 .equ TOR_RWX, 0x0F .equ TOR_RW, 0x0B @@ -9,8 +21,10 @@ .equ NA4_RW, 0x13 .equ NA4_RX, 0x15 .equ NAPOT_RWX, 0x1F -.equ NAPOT_RW , 0x1B -.equ NAPOT_RX , 0x1D +.equ NAPOT_RW, 0x1B +.equ NAPOT_RX, 0x1D +.equ NAPOT_R, 0x19 +.equ NAPOT_W, 0x1C .equ TOR_LRWX, 0x8F .equ TOR_LRW, 0x8B diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S index 6bf3ec7..e040132 100644 --- a/test/priv_sec_testsuite/tests/env/pmp_service.S +++ b/test/priv_sec_testsuite/tests/env/pmp_service.S @@ -214,11 +214,6 @@ INTP_SERVICE: csrw mie, t4 j RET_ECALL -EXP_SERVICE: - addi s0, s0, 1 - # j RET_ECALL - mret - //////////////////////////////////////////// # Configure a NAPOT / NA4 region //////////////////////////////////////////// diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v index 2103ad3..2bfc10e 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v @@ -1,67 +1,67 @@ @00010000 -6F 00 40 0A 73 2F 20 34 93 0E 80 00 63 14 DF 01 -6F 20 40 53 93 0E 90 00 63 0E DF 1B 93 0E B0 00 -63 0E DF 1B 93 0E 20 00 63 0C DF 1B B7 0E 00 80 -93 8E BE 00 63 14 DF 01 6F 20 00 54 B7 0E 00 80 -93 8E 3E 00 63 14 DF 01 6F 20 00 53 B7 0E 00 80 -93 8E 7E 00 63 14 DF 01 6F 20 00 52 93 0E 50 00 -63 14 DF 01 6F 20 40 25 93 0E 70 00 63 14 DF 01 -6F 20 80 24 93 0E 10 00 63 14 DF 01 6F 20 C0 23 -13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34 -63 54 0F 00 6F 00 40 00 93 E1 91 53 17 1F 00 00 -23 22 3F F6 93 00 00 00 13 01 00 00 93 01 00 00 -13 02 00 00 93 02 00 00 13 03 00 00 93 03 00 00 -13 04 00 00 93 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61 69 6C 65 64 +3A 20 21 22 69 6C 6C 65 67 61 6C 20 69 6E 73 74 +72 75 63 74 69 6F 6E 22 0A 00 00 00 41 73 73 65 +72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 70 74 +5B 31 5D 5B 61 64 64 72 2F 28 31 55 4C 20 3C 3C +20 31 32 29 5D 20 26 20 30 78 30 34 30 0A 00 00 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 70 74 5B 31 5D 5B 61 64 64 72 2F 28 31 55 +4C 20 3C 3C 20 31 32 29 5D 20 26 20 30 78 30 38 +30 0A 00 00 41 73 73 65 72 74 69 6F 6E 20 66 61 +69 6C 65 64 3A 20 74 66 2D 3E 65 70 63 20 25 20 +34 20 3D 3D 20 30 0A 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 21 22 75 6E 65 78 +70 65 63 74 65 64 20 65 78 63 65 70 74 69 6F 6E +22 0A 00 00 41 73 73 65 72 74 69 6F 6E 20 66 61 +69 6C 65 64 3A 20 21 22 75 6E 73 75 70 70 6F 72 +74 65 64 20 73 61 74 70 20 6D 6F 64 65 22 0A 00 diff --git a/test/priv_sec_testsuite/tests/rv32ui/Makefrag b/test/priv_sec_testsuite/tests/rv32ui/Makefrag index f241da0..91ff4c6 100644 --- a/test/priv_sec_testsuite/tests/rv32ui/Makefrag +++ b/test/priv_sec_testsuite/tests/rv32ui/Makefrag @@ -6,6 +6,7 @@ rv32ui_sc_tests = \ test0 \ test1 \ test2 \ + test3 \ rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests)) diff --git a/test/priv_sec_testsuite/tests/rv32ui/test3.S b/test/priv_sec_testsuite/tests/rv32ui/test3.S new file mode 100644 index 0000000..8b98b9b --- /dev/null +++ b/test/priv_sec_testsuite/tests/rv32ui/test3.S @@ -0,0 +1,8 @@ +# distributed under the mit license +# https://opensource.org/licenses/mit-license.php + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/test3.S" diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v index 0f91153..aa404dd 100755 --- a/test/priv_sec_testsuite/tests/rv64ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv64ui-p-test2.v @@ -1,67 +1,67 @@ @00010000 -6F 00 40 0A 73 2F 20 34 93 0E 80 00 63 14 DF 01 -6F 20 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3B 63 96 EE 5F 73 10 50 3B B7 0E 00 00 +93 8E FE FF 73 90 6E 3B 73 2F 60 3B 63 9A EE 5D +73 10 60 3B B7 0E 00 00 93 8E FE FF 73 90 7E 3B +73 2F 70 3B 63 9E EE 5B 73 10 70 3B B7 0E 00 00 +93 8E FE FF 73 90 8E 3B 73 2F 80 3B 63 92 EE 5B +73 10 80 3B B7 0E 00 00 93 8E FE FF 73 90 9E 3B +73 2F 90 3B 63 96 EE 59 73 10 90 3B B7 0E 00 00 +93 8E FE FF 73 90 AE 3B 73 2F A0 3B 63 9A EE 57 +73 10 A0 3B B7 0E 00 00 93 8E FE FF 73 90 BE 3B +73 2F B0 3B 63 9E EE 55 73 10 B0 3B B7 0E 00 00 +93 8E FE FF 73 90 CE 3B 73 2F C0 3B 63 92 EE 55 +73 10 C0 3B B7 0E 00 00 93 8E FE FF 73 90 DE 3B +73 2F D0 3B 63 96 EE 53 73 10 D0 3B B7 0E 00 00 +93 8E FE FF 73 90 EE 3B 73 2F E0 3B 63 9A EE 51 +73 10 E0 3B B7 0E 00 00 93 8E FE FF 73 90 FE 3B +73 2F F0 3B 63 9E EE 4F 73 10 F0 3B B7 7E 77 77 +93 8E 7E 77 73 90 0E 3A 73 2F 00 3A 63 92 EE 4F +73 10 00 3A B7 7E 77 77 93 8E 7E 77 73 90 1E 3A +73 2F 10 3A 63 96 EE 4D 73 10 10 3A B7 7E 77 77 +93 8E 7E 77 73 90 2E 3A 73 2F 20 3A 63 9A EE 4B +73 10 20 3A B7 7E 77 77 93 8E 7E 77 73 90 3E 3A +73 2F 30 3A 63 9E EE 49 73 10 30 3A 6F 00 80 33 +37 0F 00 00 13 0F 0F 08 F3 2E 00 30 B3 EE EE 01 +73 90 0E 30 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 +B3 EE EE 01 73 90 4E 30 6F 00 C0 30 13 06 F6 FF +13 56 36 00 93 D5 25 00 B3 E5 C5 00 6F 00 80 00 +93 D5 25 00 93 02 40 00 63 40 55 02 93 02 80 00 +63 4C 55 0A 93 02 C0 00 63 48 55 14 93 02 00 01 +63 44 55 1E 6F 00 00 2D 73 23 00 3A 93 02 00 00 +63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00 +63 82 A2 04 93 02 30 00 63 8E A2 04 73 90 05 3B +9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 +6F 00 C0 05 73 90 15 3B B7 02 01 00 9B 82 F2 FF +93 92 02 01 93 82 F2 0F 33 73 53 00 93 96 86 00 +6F 00 C0 03 73 90 25 3B B7 02 01 00 9B 82 12 F0 +93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 +6F 00 C0 01 73 90 35 3B B7 02 00 01 9B 82 F2 FF +33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 +73 10 03 3A 6F 00 00 23 73 23 10 3A 93 02 40 00 +63 8E A2 00 93 02 50 00 63 86 A2 02 93 02 60 00 +63 82 A2 04 93 02 70 00 63 8E A2 04 73 90 45 3B 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02 02 93 82 02 F0 33 73 53 00 +6F 00 C0 05 73 90 D5 3B B7 02 01 00 9B 82 F2 FF +93 92 02 01 93 82 F2 0F 33 73 53 00 93 96 86 00 +6F 00 C0 03 73 90 E5 3B B7 02 01 00 9B 82 12 F0 +93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 +6F 00 C0 01 73 90 F5 3B B7 02 00 01 9B 82 F2 FF +33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 +73 10 33 3A 6F 00 00 05 93 02 00 00 63 04 57 04 +93 02 80 00 E3 06 57 D4 93 02 00 01 E3 08 57 D2 +93 02 80 01 E3 04 57 D2 13 05 10 00 6F 00 80 02 +93 0E 00 00 E3 88 D8 AB 93 0E 10 00 E3 8E D8 AF +93 0E 80 00 E3 82 D8 FD 93 0E 90 00 E3 8A D8 CD +6F 00 40 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34 +73 00 20 30 13 0A 1A 00 73 00 20 30 67 80 00 00 +6F 00 40 05 93 8F 1F 00 73 00 10 00 6F F0 9F FD +93 8F 1F 00 73 00 10 00 73 24 20 34 93 02 50 00 +63 0A 54 00 93 02 70 00 63 06 54 00 93 02 10 00 +63 04 54 00 73 00 20 30 13 09 19 00 93 02 10 00 +63 82 22 01 97 02 00 00 93 82 42 0B 73 90 12 34 +6F F0 5F FE 13 05 00 00 93 05 00 00 37 06 04 00 +93 06 F0 01 13 07 80 01 93 08 80 00 73 00 00 00 +13 04 00 00 13 05 10 00 B7 05 04 00 37 06 04 00 +93 06 90 01 13 07 80 01 93 08 80 00 73 00 00 00 +B7 02 04 00 23 A0 02 00 93 02 70 00 63 12 54 0A +13 04 00 00 13 05 10 00 B7 05 04 00 37 06 04 00 +93 06 C0 01 13 07 80 01 93 08 80 00 73 00 00 00 +B7 02 04 00 03 A0 02 00 93 02 50 00 63 1A 54 06 +13 04 00 00 13 05 10 00 B7 05 04 00 37 06 04 00 +93 06 B0 01 13 07 80 01 93 08 80 00 73 00 00 00 +B7 02 04 00 67 80 02 00 93 02 10 00 63 12 54 04 +13 04 10 00 63 1E 54 02 6F 00 80 04 93 02 00 00 +13 03 A0 00 93 03 00 00 13 0E 00 00 B3 83 53 00 +23 20 7E 00 93 83 13 00 83 23 0E 00 93 82 12 00 +13 9E 22 00 E3 94 62 FE 67 80 00 00 63 1A 30 00 +13 95 11 00 63 00 05 00 13 65 15 00 73 00 00 00 +13 05 10 00 73 00 00 00 73 00 10 00 73 10 00 C0 +@80003050 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C +3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 +36 33 20 2A 20 28 31 55 4C 20 3C 3C 20 31 32 29 +0A 00 00 00 00 00 00 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 21 28 70 74 5B 33 +5D 5B 61 64 64 72 2F 28 31 55 4C 20 3C 3C 20 31 +32 29 5D 20 26 20 30 78 30 38 30 29 20 26 26 20 +63 61 75 73 65 20 3D 3D 20 30 78 66 0A 00 00 00 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 6E 6F 64 65 0A 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 75 73 65 72 5F 6D +61 70 70 69 6E 67 5B 61 64 64 72 2F 28 31 55 4C +20 3C 3C 20 31 32 29 5D 2E 61 64 64 72 20 3D 3D +20 30 0A 00 00 00 00 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 21 22 69 6C 6C 65 +67 61 6C 20 69 6E 73 74 72 75 63 74 69 6F 6E 22 +0A 00 00 00 00 00 00 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 70 74 5B 33 5D 5B +61 64 64 72 2F 28 31 55 4C 20 3C 3C 20 31 32 29 +5D 20 26 20 30 78 30 34 30 0A 00 00 00 00 00 00 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 70 74 5B 33 5D 5B 61 64 64 72 2F 28 31 55 +4C 20 3C 3C 20 31 32 29 5D 20 26 20 30 78 30 38 +30 0A 00 00 00 00 00 00 41 73 73 65 72 74 69 6F +6E 20 66 61 69 6C 65 64 3A 20 74 66 2D 3E 65 70 +63 20 25 20 34 20 3D 3D 20 30 0A 00 00 00 00 00 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 21 22 75 6E 65 78 70 65 63 74 65 64 20 65 +78 63 65 70 74 69 6F 6E 22 0A 00 00 00 00 00 00 +41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 +3A 20 21 22 75 6E 73 75 70 70 6F 72 74 65 64 20 +73 61 74 70 20 6D 6F 64 65 22 0A 00 diff --git a/test/priv_sec_testsuite/tests/rv64ui/Makefrag b/test/priv_sec_testsuite/tests/rv64ui/Makefrag index e6a134e..9c40966 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/Makefrag +++ b/test/priv_sec_testsuite/tests/rv64ui/Makefrag @@ -6,6 +6,7 @@ rv64ui_sc_tests = \ test0 \ test1 \ test2 \ + test3 \ rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S index 8cd6449..db20ba8 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test2.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S @@ -29,24 +29,6 @@ .equ MEIE_ON, 0x00000800 .equ MEIE_OFF, 0xFFFFF7FF -.equ PMPCFG0, 0x0 -.equ PMPCFG1, 0x0 -.equ PMPCFG2, 0x0 -.equ PMPCFG3, 0x0 -.equ PMPADDR, 0xFFFFFFFF -.equ PMPCFG, 0x77777777 - -.equ S2MB, 0x200000 -.equ S1MB, 0x100000 -.equ S512K, 0x80000 -.equ S256K, 0x40000 -.equ S64KB, 0x10000 -.equ S16KB, 0x10000 -.equ S4KB, 0x4000 -.equ S1KB, 0x1000 - - - RVTEST_RV64U RVTEST_CODE_BEGIN @@ -80,6 +62,11 @@ ILLEGAL_INSTRUCTION: ebreak +EXP_SERVICE: + addi s0, s0, 1 + mret + + ################################################## # # Testcases @@ -99,11 +86,11 @@ TEST2: li a7, 1 ecall +// TOR region - 1MB RWX TEST3_SETUP: li s1, 0 li s2, 16 -// TOR region - 1MB RWX TEST3_1TOR: // Configure the region add a0, s1, zero // pmp number @@ -151,11 +138,12 @@ TEST3_TEARDOWN: addi s1, s1, 1 bne s1, s2, TEST3_1TOR + +// NAPOT region - 1MB RWX TEST4_SETUP: li s1, 0 li s2, 16 -// NAPOT region - 1MB RWX TEST4_1NAPOT: // Configure the region add a0, s1, zero // pmp number diff --git a/test/priv_sec_testsuite/tests/rv64ui/test3.S b/test/priv_sec_testsuite/tests/rv64ui/test3.S new file mode 100644 index 0000000..e155da2 --- /dev/null +++ b/test/priv_sec_testsuite/tests/rv64ui/test3.S @@ -0,0 +1,222 @@ +###################################################################### +# distributed under the mit license +# https://opensource.org/licenses/mit-license.php +###################################################################### + +#include "riscv_test.h" +#include "test_macros.h" +#include "pmp_service.S" +#include "pmp.S" + +###################################################################### +# Test 3: PMP permissions + +# Configure PMP and check permissions are correctly followed by the +# mpu and control/memfy units with U-mode +# +# x31 is the error status register to trigger the testbench status +# when encounter a problem during the testcase +###################################################################### + +###################################################################### +# Defines / Constants +###################################################################### + +# Machine interrupt enable (MSTATUS) +.equ MPIE_ON, 0x00000080 +.equ MPIE_OFF, 0xFFFFFFF7 +# Machine external interrupt enable (MIE) +.equ MEIE_ON, 0x00000800 +.equ MEIE_OFF, 0xFFFFF7FF + + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +j TEST + + +################################# +# Not supported for the moment +################################# +ECALL_SUPERVISOR_MODE: + add x31, x31, 1 + ebreak + +################################# +# No service for machine-mode +################################# +ECALL_MACHINE_MODE: + j RET_ECALL + + +################################# +# +# Services +# +################################# + +# Trap for malformed / unsupported instruction +ILLEGAL_INSTRUCTION: + add x31, x31, 1 + ebreak + + +EXP_SERVICE: + csrr s0, mcause + li t0, CAUSE_LOAD_ACCESS + beq s0, t0, EXP_MRET + li t0, CAUSE_STORE_ACCESS + beq s0, t0, EXP_MRET + li t0, CAUSE_FETCH_ACCESS + beq s0, t0, EXP_INST_FAULT + +EXP_MRET: + mret + +EXP_INST_FAULT: + // increment error + addi s2, s2, 1 + // move back to test4 + li t0, 1 + beq t0, s2, EXP_BACK4 +EXP_BACK4: + // replace mepc with TEST4_CHECK because + // it contains the access fault address + la t0, TEST4_CHECK + csrw mepc, t0 + j EXP_MRET + + + +################################################## +# +# Testcases +# +################################################## + +TEST: + +// Configure a NAPOT 256 KB for code +TEST_SETUP: + li a0, 0 // pmp number + li a1, 0 // base address + li a2, S256K // size + li a3, NAPOT_RWX // permissions + li a4, NAPOT // type + li a7, 8 + ecall + + +// Check store access fault +TEST2_SETUP: + + # Reset error flag + li s0, 0 + + // Configure a NAPOT 256 KB for data + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_R // permissions + li a4, NAPOT // type + li a7, 8 + ecall + +TEST2: + // raise an exception, which will increment s0 + li t0, S256K + sw x0, 0(t0) + + // Check the exception has been handled correctly + li t0, CAUSE_STORE_ACCESS + bne s0, t0, fail + +TEST2_TEARDOWN: + +// Check load access fault +TEST3_SETUP: + + # Reset error flag + li s0, 0 + + // Configure a NAPOT 256 KB for data + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_W // permissions + li a4, NAPOT // type + li a7, 8 + ecall + +TEST3: + // raise an exception, which will increment s0 + li t0, S256K + lw x0, 0(t0) + + // Check the exception has been handled correctly + li t0, CAUSE_LOAD_ACCESS + bne s0, t0, fail + +TEST3_TEARDOWN: + + +// Check execute access fault in u-mode +TEST4_SETUP: + + # Reset error flag + li s0, 0 + + // Configure a NAPOT 256 KB for data + li a0, 1 // pmp number + li a1, S256K // base address + li a2, S256K // size + li a3, NAPOT_RW // permissions + li a4, NAPOT // type + li a7, 8 + ecall + +TEST4: + // raise an exception, which will increment s0 + li t0, S256K + jalr x0, 0(t0) +TEST4_CHECK: + li t0, CAUSE_FETCH_ACCESS + bne s0, t0, fail + li s0, 1 + bne s0, t0, fail + +TEST4_TEARDOWN: + j pass + +////////////////////////////////////////////////////// +// Stupid loop to access the memory over a small range +////////////////////////////////////////////////////// +LD_ST_ARITH: + li t0, 0 + li t1, 10 + li t2, 0 + li t3, 0 +1: + add t2, t2, t0 + sw t2, 0(t3) + addi t2, t2, 1 + lw t2, 0(t3) + addi t0, t0, 1 + slli t3, t0, 2 + bne t0, t1, 1b + ret +////////////////////////////////////////////////////// + + +TEST_PASSFAIL + +RVTEST_CODE_END + +.data + +RVTEST_DATA_BEGIN + +TEST_DATA + +RVTEST_DATA_END