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llvm: Update baseline to b7423e94be572bac58b75d7b5e8dc502e9db7fcf
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github-actions[bot] committed Jan 22, 2025
1 parent 58ce8c5 commit a76bb2f
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 63 files
+6 −6 clang/include/clang/Basic/Builtins.td
+2 −0 clang/lib/AST/Expr.cpp
+24 −1 clang/lib/CodeGen/CGAtomic.cpp
+0 −141 clang/lib/CodeGen/CGBuiltin.cpp
+1 −1 clang/lib/Driver/ToolChains/HIPUtility.cpp
+1 −1 clang/lib/Driver/ToolChains/PS4CPU.cpp
+50 −15 clang/lib/Sema/SemaChecking.cpp
+345 −0 clang/test/CodeGen/atomic-test-and-set.c
+14 −13 clang/test/Driver/ps4-sdk-root.c
+10 −9 clang/test/Driver/ps5-linker.c
+14 −13 clang/test/Driver/ps5-sdk-root.c
+20 −2 clang/test/Sema/atomic-ops.c
+3 −3 compiler-rt/lib/builtins/arm/adddf3vfp.S
+3 −3 compiler-rt/lib/builtins/arm/aeabi_dcmp.S
+3 −3 compiler-rt/lib/builtins/arm/divdf3vfp.S
+2 −2 compiler-rt/lib/builtins/arm/eqdf2vfp.S
+1 −1 compiler-rt/lib/builtins/arm/extendsfdf2vfp.S
+1 −1 compiler-rt/lib/builtins/arm/fixdfsivfp.S
+1 −1 compiler-rt/lib/builtins/arm/fixunsdfsivfp.S
+1 −1 compiler-rt/lib/builtins/arm/floatsidfvfp.S
+1 −1 compiler-rt/lib/builtins/arm/floatunssidfvfp.S
+2 −2 compiler-rt/lib/builtins/arm/gedf2vfp.S
+2 −2 compiler-rt/lib/builtins/arm/gtdf2vfp.S
+2 −2 compiler-rt/lib/builtins/arm/ledf2vfp.S
+2 −2 compiler-rt/lib/builtins/arm/ltdf2vfp.S
+3 −3 compiler-rt/lib/builtins/arm/muldf3vfp.S
+2 −2 compiler-rt/lib/builtins/arm/nedf2vfp.S
+3 −3 compiler-rt/lib/builtins/arm/subdf3vfp.S
+1 −1 compiler-rt/lib/builtins/arm/truncdfsf2vfp.S
+2 −2 compiler-rt/lib/builtins/arm/unorddf2vfp.S
+12 −0 compiler-rt/lib/builtins/assembly.h
+42 −6 compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
+69 −0 compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
+11 −9 llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+16 −65 llvm/lib/CodeGen/RegisterCoalescer.cpp
+46 −46 llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+2 −2 llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
+5 −5 llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
+0 −51 llvm/test/CodeGen/AArch64/reduced-coalescer-issue.ll
+0 −23 llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
+3 −55 llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
+0 −4 llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
+0 −48 llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+0 −6 llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
+0 −1 llvm/test/CodeGen/PowerPC/combine-fneg.ll
+0 −6 llvm/test/CodeGen/PowerPC/fp-strict-round.ll
+0 −3 llvm/test/CodeGen/PowerPC/frem.ll
+0 −1 llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
+0 −2 llvm/test/CodeGen/PowerPC/ldexp.ll
+0 −4 llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
+0 −176 llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+0 −185 llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
+2 −2 llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
+0 −47 llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
+93 −44 llvm/test/CodeGen/X86/fixup-bw-inst.ll
+0 −79 llvm/test/CodeGen/X86/pr76416.ll
+2 −2 llvm/test/CodeGen/X86/subreg-fail.mir
+0 −372 llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
+78 −78 llvm/test/CodeGen/X86/vector-compress.ll
+0 −57 mlir/lib/Dialect/Vector/Transforms/LowerVectorTransfer.cpp
+8 −6 mlir/test/Conversion/GPUCommon/transfer_write.mlir
+23 −12 mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
+10 −14 mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir

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