From 0e76447377c608b896f1fb953be6f3258d478d19 Mon Sep 17 00:00:00 2001 From: Dylan Tuttle Date: Wed, 20 Sep 2023 12:37:38 -0700 Subject: [PATCH] Add default cases to power switch statements Fix AIX warnings concerning missing cases in switch statements by adding default cases Signed-off-by: Dylan Tuttle --- compiler/p/codegen/OMRCodeGenerator.cpp | 2 + compiler/p/codegen/OMRMachine.cpp | 51 +++++++++++++------- compiler/p/codegen/OMRPeephole.cpp | 2 + compiler/p/codegen/OMRRegisterDependency.cpp | 2 + compiler/p/codegen/PPCDebug.cpp | 2 + 5 files changed, 41 insertions(+), 18 deletions(-) diff --git a/compiler/p/codegen/OMRCodeGenerator.cpp b/compiler/p/codegen/OMRCodeGenerator.cpp index d5150d79362..d25185be123 100644 --- a/compiler/p/codegen/OMRCodeGenerator.cpp +++ b/compiler/p/codegen/OMRCodeGenerator.cpp @@ -2436,6 +2436,8 @@ OMR::Power::CodeGenerator::supportsNonHelper(TR::SymbolReferenceTable::CommonNon result = self()->comp()->target().is64Bit(); break; } + default: + break; } return result; diff --git a/compiler/p/codegen/OMRMachine.cpp b/compiler/p/codegen/OMRMachine.cpp index d4ca18ce56a..f6051a5a2b6 100644 --- a/compiler/p/codegen/OMRMachine.cpp +++ b/compiler/p/codegen/OMRMachine.cpp @@ -90,8 +90,9 @@ static int32_t spillSizeForRegister(TR::Register *virtReg) case TR_VSX_VECTOR: case TR_VRF: return 16; + default: + TR_ASSERT(false, "Unexpected register kind"); } - TR_ASSERT(false, "Unexpected register kind"); return 0; } @@ -252,6 +253,8 @@ TR::RealRegister *OMR::Power::Machine::findBestFreeRegister(TR::Instruction *cur case TR_VRF: maskI = TR::RealRegister::FirstVRF; break; + default: + break; } if (liveRegOn && preference!=0 && (interference & (1<<(preference-maskI)))) @@ -493,6 +496,8 @@ TR::RealRegister *OMR::Power::Machine::freeBestRegister(TR::Instruction *cur maskI = first = TR::RealRegister::FirstVRF; last = TR::RealRegister::LastVRF; break; + default: + break; } int32_t preference = 0, pref_favored = 0; @@ -724,6 +729,8 @@ TR::RealRegister *OMR::Power::Machine::freeBestRegister(TR::Instruction *cur location = self()->cg()->allocateSpill(16, false, NULL); } break; + default: + break; } if (rk == TR_CCR) @@ -844,6 +851,8 @@ TR::RealRegister *OMR::Power::Machine::freeBestRegister(TR::Instruction *cur reloadInstr = generateTrg1MemInstruction(self()->cg(), opCode, currentNode, best, tmemref, currentInstruction); self()->cg()->stopUsingRegister(tempIndexRegister); break; + default: + break; } self()->cg()->traceRegFreed(candidates[0], best); @@ -1081,6 +1090,8 @@ TR::RealRegister *OMR::Power::Machine::reverseSpillState(TR::Instruction *c spillInstr = generateMemSrc1Instruction(self()->cg(), opCode, currentNode, tmemref, targetRegister, currentInstruction); self()->cg()->stopUsingRegister(tempIndexRegister); break; + default: + break; } self()->cg()->traceRAInstruction(spillInstr); if (rk == TR_CCR) @@ -1755,6 +1766,8 @@ static void registerCopy(TR::Instruction *precedingInstruction, case TR_VRF: instr = generateTrg1Src2Instruction(cg, TR::InstOpCode::vor, currentNode, targetReg, sourceReg, sourceReg, precedingInstruction); break; + default: + break; } cg->traceRAInstruction(instr); } @@ -1779,23 +1792,25 @@ static void registerExchange(TR::Instruction *precedingInstruction, { TR::InstOpCode::Mnemonic opCode; switch (rk) - { - case TR_GPR: - opCode = TR::InstOpCode::XOR; - break; - case TR_FPR: - opCode = TR::InstOpCode::xxlxor; - break; - case TR_VSX_SCALAR: - case TR_VSX_VECTOR: - opCode = TR::InstOpCode::xxlxor; - break; - case TR_VRF: - opCode = TR::InstOpCode::vxor; - break; - case TR_CCR: - TR_ASSERT(0, "Cannot exchange CCR without a third reg"); - } + { + case TR_GPR: + opCode = TR::InstOpCode::XOR; + break; + case TR_FPR: + opCode = TR::InstOpCode::xxlxor; + break; + case TR_VSX_SCALAR: + case TR_VSX_VECTOR: + opCode = TR::InstOpCode::xxlxor; + break; + case TR_VRF: + opCode = TR::InstOpCode::vxor; + break; + case TR_CCR: + TR_ASSERT(0, "Cannot exchange CCR without a third reg"); + default: + break; + } cg->traceRAInstruction(generateTrg1Src2Instruction(cg, opCode, currentNode, targetReg, targetReg, sourceReg, precedingInstruction)); cg->traceRAInstruction(generateTrg1Src2Instruction(cg, opCode, currentNode, sourceReg, targetReg, sourceReg, precedingInstruction)); cg->traceRAInstruction(generateTrg1Src2Instruction(cg, opCode, currentNode, targetReg, targetReg, sourceReg, precedingInstruction)); diff --git a/compiler/p/codegen/OMRPeephole.cpp b/compiler/p/codegen/OMRPeephole.cpp index ca1ea891916..f7a8888571d 100644 --- a/compiler/p/codegen/OMRPeephole.cpp +++ b/compiler/p/codegen/OMRPeephole.cpp @@ -702,6 +702,8 @@ OMR::Power::Peephole::tryToRemoveRedundantMoveRegister() } break; } + default: + break; } } diff --git a/compiler/p/codegen/OMRRegisterDependency.cpp b/compiler/p/codegen/OMRRegisterDependency.cpp index e1765e2ef71..fcac317c87c 100644 --- a/compiler/p/codegen/OMRRegisterDependency.cpp +++ b/compiler/p/codegen/OMRRegisterDependency.cpp @@ -1088,6 +1088,8 @@ void OMR::Power::RegisterDependencyGroup::assignRegisters(TR::Instruction *cur case TR_VRF: depsBlocked = haveSpareVRFs; break; + default: + break; } assignContendedRegisters(currentInstruction, &_dependencies[i], map, depsBlocked, cg); } diff --git a/compiler/p/codegen/PPCDebug.cpp b/compiler/p/codegen/PPCDebug.cpp index 5bf183d26f5..ccc6a631b9e 100644 --- a/compiler/p/codegen/PPCDebug.cpp +++ b/compiler/p/codegen/PPCDebug.cpp @@ -290,6 +290,8 @@ TR_Debug::print(TR::FILE *pOutFile, TR::PPCLabelInstruction * instr) case TR::Snippet::IsArrayCopyCall: callSym = ((TR::PPCHelperCallSnippet *)snippet)->getDestination(); break; + default: + break; } if (callSym) trfprintf(pOutFile, "\t; Call \"%s\"", getName(callSym));