From 2c184a757771a5d8b49cc86bac2fbee657b64a74 Mon Sep 17 00:00:00 2001
From: erihsu <zhenyuxu163@163.com>
Date: Sun, 23 May 2021 20:56:21 +0800
Subject: [PATCH] fix bug in export verilog

---
 src/saver/mod.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/saver/mod.rs b/src/saver/mod.rs
index f497504..d61c6d5 100644
--- a/src/saver/mod.rs
+++ b/src/saver/mod.rs
@@ -36,6 +36,10 @@ impl<W: Default, N: Default, G: Default, P: Default> NetList<W, N, G, P> {
         }
         let mut p2n_list = Vec::new();
         for g in &self.gates {
+            // insert first node
+            let node = &self.nodes[g.first_node];
+            p2n_list.push((&node.name, &self.nets[node.connection].name));
+            // insert second node and so on
             for node_idx in self.get_gate_node(&g.name)?.into_iter() {
                 let node = &self.nodes[node_idx];
                 p2n_list.push((&node.name, &self.nets[node.connection].name));