Merge branch 'main' of https://github.com/edabk-hust/edabk_brain_soc …

…into main
edabk-hust · Feb 1, 2024 · d0d2ffc · d0d2ffc
2 parents 6afc209 + 0bee27a
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diff --git a/README.md b/README.md
@@ -2,6 +2,8 @@
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml)
 
+> Our Project proudly achieves **1st prize** of the  [**eFabless 3rd AI Generated Design Contest**](https://efabless.com/genai/challenges/3-winners)!
+
 A project dedicated to developing a hardware-software co-design for neurosynaptic core based on Spike Neural Network (SNN) architecture, integrated with RISC-V based SoC, powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
 
 ## Contributor

diff --git a/edabk-brain-architect.png b/edabk-brain-architect.png
diff --git a/verilog/dv/edabk_firmware_demo/C_data_struct_def.c b/verilog/dv/edabk_firmware_demo/C_data_struct_def.c
@@ -32,5 +32,5 @@ typedef struct {
 } Packet;
 
 // SNN data array initialization
-Packet packet_data[NUM_CORES][1000];
+Packet packet_data[1024];
 Core core_data[NUM_CORES];
diff --git a/verilog/dv/edabk_firmware_demo/edabk_firmware_demo_tb.v b/verilog/dv/edabk_firmware_demo/edabk_firmware_demo_tb.v
@@ -144,7 +144,7 @@ module edabk_firmware_demo_tb;
 		$dumpvars(0, edabk_firmware_demo_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (70) begin
+		repeat (700) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end

diff --git a/verilog/dv/firmware_demo/Makefile b/verilog/dv/firmware_demo/Makefile
diff --git a/verilog/dv/firmware_demo/README.md b/verilog/dv/firmware_demo/README.md
diff --git a/verilog/dv/firmware_demo/SNN_data.c b/verilog/dv/firmware_demo/SNN_data.c
diff --git a/verilog/dv/firmware_demo/SNN_data.h b/verilog/dv/firmware_demo/SNN_data.h
diff --git a/verilog/dv/firmware_demo/convert.c b/verilog/dv/firmware_demo/convert.c