arcem9d_wei_r16.tcf

<?xml version="1.0" encoding="UTF-8"?>
<config_list>
  <tool_config version="1.0.74" mwdt_version="O-2018.09" />
  <configuration name="BCRs" filename="bcr_contents.txt">
    <string><![CDATA[
	0x4	0x44		IDENTITY
	0x18	0x80000000	AUX_DCCM
	0x60	0x2		BCR_VER
	0x68	0x10		VECBASE_AC_BUILD
	0x6e	0x102		RF_BUILD
	0x74	0x10b04		DCCM_BUILD
	0x75	0x110704	TIMER_BUILD
	0x76	0x5		AP_BUILD
	0x78	0xb804		ICCM_BUILD
	0x79	0x3220		XY_BUILD
	0x7a	0x3521		DSP_BUILD
	0x7b	0x22206		MULTIPLY_BUILD
	0x7c	0x3		SWAP_BUILD
	0x7d	0x3		NORM_BUILD
	0x7e	0x2		MINMAX_BUILD
	0x7f	0x303		BARREL_BUILD
	0xc1	0x12447402	ISA_CONFIG
	0xc3	0xf0000012	DMP_PP_BUILD
	0xc5	0x2		STACK_REGION_BUILD
	0xc7	0x40000004	ERP_BUILD
	0xc8	0x4f03		FPU_BUILD
	0xc9	0x1		CPROT_BUILD
	0xcc	0x1988c02	AGU_BUILD
	0xcd	0x160f02	DMAC_BUILD
	0xf0	0x101083	SUBSYS_BUILD
	0xf1	0x101		CORE_CONFIG
	0xf3	0x116b9e01	IRQ_BUILD
	0xf7	0x102		PDM_DVFS_BUILD
	0xfe	0x302		IFQUEUE_BUILD
	0xff	0x8003		SMART_BUILD
	0x208	0x1000000	AUX_ICCM
	0x5f8	0x90000000	XCCM_BASE
	0x5f9	0xa0000000	YCCM_BASE
	0xa00	0x0		SUBSYS_DSP_0_BUILD
	0xa04	0x17100030	SUBSYS_IO_0_BUILD
	0xa05	0x0		SUBSYS_IO_1_BUILD
	0xa06	0x100		SUBSYS_IO_2_BUILD
	0xa1e	0x100000	SUBSYS_UAUX_OFFSET
	0xa1f	0x80000000	SUBSYS_APEX_OFFSET
]]></string>
  </configuration>
  <configuration name="build_version_info" filename="build_version_info.txt">
    <string><![CDATA[
Version Information:
    ARChitect O-2018.09
    IP Libraries:
        ARCv2EM            v5.0.37
        ARC Data Fusion IP Subsystem DSP  v1.1.8
        ARC Data Fusion IP Subsystem INFRA  v1.1.8
        ARC Data Fusion IP Subsystem IO  v1.1.8
        ARC Data Fusion IP Subsystem SPEECH  v1.1.8
        ARC Debug          v2.1.9
        ARC RTT            v2.0.37
        ARC xCAM           v4.3.8
        ARConnect          v2.1.26
        ARCv2_FPGA_RDF     v1.4.7
        ARCv2EM_CCT        v5.0.37
        ARCv2MSS           v2.2.10
        Implementation     v5.0.37
        Synopsys Based Reference Design Flow  v9.0.28
        Synopsys Clock Gate Replacement Flow  v3.0.7
        Synopsys Embed-it Integrator Flow  v7.0.20
        Synopsys SMS Integrator Flow  v2.0.11
        Tool Configuration  v1.0.74
]]></string>
  </configuration>
  <configuration name="mw_compiler" filename="ccac.arg">
    <string><![CDATA[
	-arcv2em
	-core4
	-HL
	-Xunaligned
	-Xcode_density
	-Xdiv_rem=radix2
	-Xswap
	-Xbitscan
	-Xmpy_option=mpyd
	-Xshift_assist
	-Xbarrel_shifter
	-Xdsp2
	-Xdsp_complex
	-Xdsp_divsqrt=radix2
	-Xdsp_itu
	-Xdsp_accshift=full
	-Xagu_large
	-Xxy
	-Xxy_config=dccm_x_y
	-Xfpus_div
	-Xfpu_mac
	-Xfpus_mpy_slow
	-Xfpus_div_slow
	-Xfpu_pipe_impl
	-Xtimer0
	-Xtimer1
	-Xrtc
	-Xstack_check
	-Hccm
	-Xdmac
]]></string>
  </configuration>
  <configuration name="mw_debugger" filename="mdb.arg">
    <string><![CDATA[
	-arcv2em 
	-core4 
	-rgf_num_banks=1 
	-rgf_num_wr_ports=2 
	-Xunaligned 
	-Xcode_density 
	-Xdiv_rem=radix2 
	-turbo_boost 
	-Xswap 
	-Xbitscan 
	-Xmpy_option=mpyd 
	-Xshift_assist 
	-Xbarrel_shifter 
	-Xdsp2 
	-Xdsp_complex 
	-Xdsp_divsqrt=radix2 
	-Xdsp_itu 
	-Xdsp_accshift=full 
	-Xagu_large 
	-Xagu_wb_depth=4 
	-Xagu_accord 
	-Xxy 
	-Xxy_config=dccm_x_y 
	-Xxy_size=32K 
	-Xxy_x_base=0x90000000 
	-Xxy_y_base=0xa0000000 
	-Xfpus_div 
	-Xfpu_mac 
	-Xfpus_mpy_slow 
	-Xfpus_div_slow 
	-Xfpu_pipe_impl 
	-Xtimer0 
	-Xtimer0_level=1 
	-Xtimer1 
	-Xtimer1_level=1 
	-Xrtc 
	-action_points=2 
	-ap_feature=1 
	-Xstack_check 
	-code_protection 
	-smart_stack_entries=32 
	-ifq_entries=8 
	-interrupts=158 
	-interrupt_priorities=2 
	-ext_interrupts=107 
	-firq 
	-interrupt_base=0x0 
	-dccm_size=0x80000 
	-dccm_base=0x80000000 
	-dccm_interleave 
	-iccm0_size=0x10000 
	-iccm1_size=0x80000 
	-iccm0_base=0x00000000 
	-iccm1_base=0x10000000 
	-error_prot_ver=4 
	-watchdog 
	-watchdog_size=32 
	-dmac 
	-dmac_channels=16 
	-dmac_registers=0 
	-dmac_fifo_depth=4 
	-dmac_int_config=multiple_internal 
	-power_domains 
]]></string>
  </configuration>
  <configuration name="nSIM" filename="nsim.props">
    <string><![CDATA[
	nsim_isa_family=av2em
	nsim_isa_core=4
	arcver=0x44
	nsim_isa_rgf_num_banks=1
	nsim_isa_rgf_num_regs=32
	nsim_isa_rgf_num_wr_ports=2
	nsim_isa_big_endian=0
	nsim_isa_lpc_size=32
	nsim_isa_pc_size=32
	nsim_isa_addr_size=32
	nsim_isa_unaligned_option=1
	nsim_isa_code_density_option=2
	nsim_isa_div_rem_option=1
	nsim_isa_turbo_boost=1
	nsim_isa_swap_option=1
	nsim_isa_bitscan_option=1
	nsim_isa_mpy_option=8
	nsim_isa_shift_option=3
	nsim_isa_dsp_option=2
	nsim_isa_dsp_complex_option=1
	nsim_isa_dsp_divsqrt_option=1
	nsim_isa_dsp_itu_option=1
	nsim_isa_dsp_accshift_option=2
	nsim_isa_agu_size=large
	nsim_isa_agu_wb_depth=4
	nsim_isa_agu_accord=1
	nsim_isa_xy=1
	nsim_isa_xy_config=dccm_x_y
	nsim_isa_xy_size=32K
	nsim_isa_xy_x_base=0x90000000
	nsim_isa_xy_y_base=0xa0000000
	nsim_isa_fpus_div_option=1
	nsim_isa_fpu_mac_option=1
	nsim_isa_fpu_fast_mpy_option=0
	nsim_isa_fpu_fast_div_option=0
	nsim_isa_fpu_pipe_impl=1
	nsim_isa_enable_timer_0=1
	nsim_isa_timer_0_int_level=1
	nsim_isa_enable_timer_1=1
	nsim_isa_timer_1_int_level=1
	nsim_isa_rtc_option=1
	nsim_isa_num_actionpoints=2
	nsim_isa_aps_feature=1
	nsim_isa_stack_checking=1
	nsim_isa_code_protect_mask=0x0
	nsim_isa_smart_stack_entries=32
	nsim_isa_ifq_size=8
	nsim_isa_number_of_interrupts=158
	nsim_isa_number_of_levels=2
	nsim_isa_number_of_external_interrupts=107
	nsim_isa_fast_irq=1
	nsim_isa_intvbase_preset=0x0
	dccm_size=0x80000
	dccm_base=0x80000000
	nsim_isa_dccm_interleave=1
	iccm0_size=0x10000
	iccm1_size=0x80000
	iccm0_base=0x00000000
	iccm1_base=0x10000000
	nsim_isa_error_prot=4
	nsim_isa_watchdog=1
	nsim_isa_watchdog_size=32
	nsim_isa_dmac_option=1
	nsim_isa_dmac_channels=16
	nsim_isa_dmac_registers=0
	nsim_isa_dmac_fifo_depth=4
	nsim_isa_dmac_int_config=multiple_internal
	nsim_isa_pdm_option=1
]]></string>
  </configuration>
  <configuration name="IDE" filename="ide.props">
    <string><![CDATA[
	processor.family=4
	processor.core_version=4
	processor.family_name=arcv2em
	processor.rgf_num_banks=1
	processor.rgf_num_wr_ports=2
	processor.endian=little
	processor.lpc_size=32
	processor.pc_size=32
	processor.addr_size=32
	processor.Xunaligned=1
	processor.Xcode_density=1
	processor.Xdiv_rem=radix2
	processor.turbo_boost=1
	processor.Xswap=1
	processor.Xbitscan=1
	processor.Xmpy_option=mpyd
	processor.Xshift_assist=1
	processor.Xbarrel_shifter=1
	processor.Xdsp2=1
	processor.Xdsp_complex=1
	processor.Xdsp_divsqrt=radix2
	processor.Xdsp_itu=1
	processor.Xdsp_accshift=full
	processor.Xagu_large=1
	processor.Xagu_wb_depth=4
	processor.Xagu_accord=1
	processor.Xxy=1
	processor.Xxy_config=dccm_x_y
	processor.Xxy_size=32K
	processor.Xxy_x_base=0x90000000
	processor.Xxy_y_base=0xa0000000
	processor.Xfpus_div=1
	processor.Xfpu_mac=1
	processor.Xfpus_mpy_slow=1
	processor.Xfpus_div_slow=1
	processor.Xfpu_pipe_impl=1
	processor.Xtimer0=1
	processor.Xtimer0_level=1
	processor.Xtimer1=1
	processor.Xtimer1_level=1
	processor.Xrtc=1
	processor.action_points=2
	processor.ap_feature=1
	processor.Xstack_check=1
	processor.code_protection=1
	processor.smart_stack_entries=32
	processor.ifq_entries=8
	processor.interrupts=158
	processor.interrupt_priorities=2
	processor.ext_interrupts=107
	processor.firq=1
	processor.interrupt_base=0x0
	processor.dccm_size=0x80000
	processor.dccm_base=0x80000000
	processor.dccm_interleave=1
	processor.Hccm=1
	processor.iccm0_size=0x10000
	processor.iccm1_size=0x80000
	processor.iccm0_base=0x00000000
	processor.iccm1_base=0x10000000
	processor.error_prot_ver=4
	processor.watchdog=1
	processor.watchdog_size=32
	processor.dmac=1
	processor.dmac_channels=16
	processor.dmac_registers=0
	processor.dmac_fifo_depth=4
	processor.dmac_int_config=multiple_internal
	processor.power_domains=1
	processor.tcf_include1=apexextensions.h
	processor.tcf_include2=alb_mss_clkctrl_regmap.h
	processor.tcf_include3=alb_mss_fab_system_memmap.h
	processor.tcf_include4=core_config.h
]]></string>
  </configuration>
  <configuration name="architect" filename="build_configuration.txt">
    <string><![CDATA[
######## EM9D_0722_XYsingle --- com.arc.templates.project.Empty.1_0 ########

# BuildHTMLDocs --- Creates custom HTML documentation in the 'docs' directory.
-build_html_docs true

# BuildSoftware --- Creates software under the Software directory.
-build_software true

# BuildTestCode --- Creates test source code under the 'tests' directory.
-build_test_code true

# BuildScripts --- Creates synthesis scripts and configuration files, which are required for hierarchy generation.
-build_scripts true

# BuildHDL --- Creates the behavioural and synthesisable HDL source code.
-build_hdl true

# CompileTestCode --- Compiles and assembles the test code.
-compile_test_code true

# GenerateStructuralHDL --- Generate the necessary structural HDL
-generate_structural_hdl true

# CompileForHDLSimulation --- Compile the HDL ready for simulation, using the selected Simulator.
-compile_hdl_for_simulation true

# BuildXCAM --- 
# When true, build the XCAM cycle accurate model from HDL.
# This happens only when the VTOC component (in the XCAM library) has been added to the design.
# 
-build_xcam true

# RunARCsyn --- Synthesize design using ARCsyn
-run_arcsyn false

# RunSEIF --- Run Synopsys Embedit Integrator Flow to generate configured memory instances
-run_seif false

# RunARCrams --- Run ARCrams on the current build, this will stitch in vendor supplied RAM models and update the synthesis and simulation environment to use the models.
-run_arcrams false

# RunARCformal --- Formal Verification using ARCformal
-run_arcformal false

# RunARCpower --- Run the Power Analysis using RTL simulation to derive the activity
-run_arcpower false

# compile_nsim_user_extensions --- Build nSIM extensions for any APEX components in the current design using their C Models.
-compile_nsim_user_extension false

# compile_translated_nsim_extensions --- Converts APEX extensions from Verilog to C++ and compiles the model for nSIM.
-compile_translated_nsim_extensions false


######## System --- com.arc.hardware.System.1_0 ########

# Create System
-create com.arc.hardware.System.1_0 System

# Testbench --- 
# Only the rascal testbench is supported, and is required by ARCtest.
# 	
-testbench rascal

# SynthesisLevel --- 
# Sets the top level module name for synthesis.  
# 
# If not using core_sys: for single-core designs, cpu_isle is used; for multicore designs, archipelago is used.
# 	
-synthesislevel cpu_isle/archipelago

# GateLevelSim --- When selected the gate level sim test code and scripts would be installed to run ARCgatesim
-gatesim true

# UserLibraryName --- The name for your HDL library
-library_name user

# OPTION_SimulatorName --- The name of the simulator you wish to use
-simulator vcs

# sim64 --- When selected, the 64-bit version of the simulator is used.  Be sure you have the 64-bit-capable simulator installed  and $ARCHITECT_ROOT/lib/linux_x86_64/ added to your LD_LIBRARY_PATH.
# The setting of this option affects the content of the generated makefile_interface_*_verilog, where * is the simulator name.
-sim64 true

# verilog_2001 --- Enable Verilog 2001 file-io syntax (if false: use pli)
-verilog_2001 true

# export_srams_to --- Where to place srams, if not cpu_top
-export_srams_to none

# copy_prefix --- 
# A Copy Prefix P causes creation of a separate copy of the entire Verilog build where each Verilog filename, module, and `define is prefixed with P and copied to a separate directory named P.
# 	
-copy_prefix ""


######## Tool Configuration --- cgen.1_0 ########

# Create Tool Configuration
-create cgen.1_0 "System.Tool Configuration"

# mwdt_version --- Selects the MetaWare version to be used with the TCF file.
# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools.
-mwdt_version O-2018.09

# code_base_addr --- 
# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build.  This value is ignored when there is an ICCM.
# 
-code_base_addr 0x0

# data_base_addr --- 
# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM.  This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used.
# 
# A value of 0xffffffff means that the data segment will not be mapped to any specific address.
# 
-data_base_addr 0xffff_ffff

# underscores_in_numbers --- Use underscores in hex numbers to improve readability.
-underscores_in_numbers false

# tcf_rebrand --- Alternate branding of TCF (not used)
-rebrand false


######## CPUisle --- com.arc.hardware.CPU_isle.1_0 ########

# Create CPUisle
-create com.arc.hardware.CPU_isle.1_0 System.CPUisle

# unique_name --- verilog module modifier prefix
-unique_name ""

# ArcNum --- The processor number as read back in the ARCNUM field of the IDENTITY register.
-arc_num 0

# instances --- 
# The number of instantiations of this core.
# 
-instances 1

# CPUFloorplan --- Floorplan giving relative placement of the RAMs  for the given configuration of ARCv2HS or ARCv2EM in this CPUisle
-cpu_floorplan none

# userCPUFloorplanPath --- Pathname of user floorplan for the CPU when using a hierarchical implementation
-usercpufloorplan_path ""

# pinLocationConstraintsFile --- Pathname+filename of the physical pin location constraints file or just "side1" (all pins on l.h.s) or "side2" (pins on top only) or "side3" (pins on r.h.s. only) or "side4" (pins on bottom only) to get a template file generated
-pin_location_constraints_file ""


######## ARCv2EM --- com.arc.hardware.ARCv2EM.1_0 ########

# Create ARCv2EM
-create com.arc.hardware.ARCv2EM.1_0 System.CPUisle.ARCv2EM

# arcv2em --- Description to follow
-arcv2em true

# def_div2ref --- This specifies the clock division factor at reset. It is used for mss clock controller to generate core clock, and the value N means core is running at (1/N) x ref_clk.
-def_div2ref 1

# addr_size --- This defines the address bus width (in bits).
-addr_size 32

# pc_size --- This defines the program counter (in bits).
-pc_size 32

# lpc_size --- This defines the size of the loop counter (in bits).
-lpc_size 32

# halt_on_reset --- This defines whether the core is halted initially on reset.
-halt_on_reset false

# byte_order --- This defines the endianness of the core.
-byte_order little

# code_density_option --- This reduces the size of program memory by adding instructions that condense commonly used instruction patterns with some marginal increase in processor gate count. The added instructions are ENTER_S, LEAVE_S, JLI_S, BI, BIH.
-code_density_option true

# bitscan_option --- This adds instructions for efficient search of bits within a 32 bit word, including normalize (NORM, NORMH, NORMW) and find first or last set bit (FFS, FLS) instructions.
-bitscan_option true

# shift_option --- The Shift ISA option adds variable and multi-length shift rotation instructions:  (0) No shift/rotation instructions (1) ASR16, ASR8, LSR8, LSL8, ROL8, ROR8 (2) ASRM, ASLM, LSRM, RORM (3) ASR16, ASR8, LSR8, LSL8, ROL8, ROR8, ASRM, ASLM, LSRM, RORM
-shift_option 3

# swap_option --- This adds two instructions used to swap half-words or bytes in a 32b word. Useful for converting between little to big endianess and vice-versa.
-swap_option true

# div_rem_option --- The DIV/REM option adds non-blocking multi-cycle implementation of integer divide/remainder functions. Added instructions are DIV, DIVU (integer divide), REM and REMU (integer divide remainder).radix2 takes 33 cycles.  radix4_enhanced takes 3 to 19 cycles per operation.
-div_rem_option none

# mpy_option --- The Multiplier ISA option allows selection between several multiplier configurations to tradeoff performance with silicon area.
# For select multiply options, when the DIV/REM option is also selected, some datapath resources will be shared between the multiply and divide pipeline to minimize total area.
# 
# Cycle count (16-bit, lower 32-bit or upper 32-bit) for the different configurations is as follows:
# <pre>
# 
# option  16/L32/U32  Instructions
# ------  ----------  ---------------------
#       
# none	  -/-/-     None
# wlh1	  1/1/1     MPYW/U, MPY/U, MPYH/U
# wlh2	  2/2/2     MPYW/U, MPY/U, MPYH/U
# wlh3	  2/3/3     MPYW/U, MPY/U, MPYH/U
# wlh4	  2/4/5     MPYW/U, MPY/U, MPYH/U
# wlh5	  5/9/9     MPYW/U, MPY/U, MPYH/U
# </pre>
# 
-mpy_option none

# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually.  This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region.  An attempt to access a protected region raises an EV_ProtV exception.
-code_protection true

# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected.
-stack_checking true

# unaligned_option --- This enables unaligned loads and stores.
-unaligned_option true

# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE.
-intvbase_preset 0x0

# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled.
-intvbase_preset_s 0x0

# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in.
-intvbase_ext false

# nmi_option --- add Non-maskable external exception support
-nmi_option false

# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro.
-rgf_impl flip_flops

# rgf_num_regs --- This defines the size (in 32b register) of the processor register file.
-rgf_num_regs 32

# rgf_wr_ports --- This defines the number of write ports on the register file.
-rgf_wr_ports 2

# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not.
-rgf_num_banks 1

# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank.
-rgf_banked_regs 32

# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions.
-turbo_boost true

# infer_alu_adder --- infer: datapath is described as behavioral code: A + B
# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder.  It is generally preferable to use the infer option and add directives for your target synthesizer. 
-infer_alu_adder infer

# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs)
# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. 
-infer_mpy_wtree instantiate

# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time
-scantest_ram_bypass_mux false

# logic_bist --- This option will OR LBIST_EN with test_mode
-logic_bist false

# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts
-power_domains true

# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core
-dvfs false

# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present.
-mem_bus_option AHB

# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered.
-mem_bus_reg_interface true

# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle.
-dmi_burst_option false

# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost.
-has_dmp_peripheral true

# per0_base --- This option specifies the memory region assignment for this peripheral aperture
-per0_base 15

# per0_limit --- This option specifies the end of this peripheral aperture
-per0_limit 0

# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite.
-per_bus_option APB

# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered.
-per_bus_reg_interface false

# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power.
-clock_gating true

# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases.
-back_compat false

# byte_parity --- If parity protection on the CCMs or Cache is configured, this option enables parity protection on a per-byte basis. Otherwise, parity is per word basis
-byte_parity false

# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection
-prot_pipelined true

# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration.
-cct_test_ena false

# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt.
-err_prot_ehce false


######## io_i2c_mst0 --- com.arc.hardware.dfss.io_i2c_mst0.1_0 ########

# Create io_i2c_mst0
-create com.arc.hardware.dfss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0

# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'.
-io_i2c_mst0 true

# io_i2c_mst0_fs --- RX/TX FIFO size
-io_i2c_mst0_fs 16

# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included
-io_i2c_mst0_dma_support None

# io_i2c_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
-io_i2c_mst0_cdc_included 1

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_i2c_mst1 --- com.arc.hardware.dfss.io_i2c_mst1.1_0 ########

# Create io_i2c_mst1
-create com.arc.hardware.dfss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1

# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'.
-io_i2c_mst1 true

# io_i2c_mst1_fs --- RX/TX FIFO size
-io_i2c_mst1_fs 16

# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included
-io_i2c_mst1_dma_support Memory-Based

# io_i2c_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
-io_i2c_mst1_cdc_included 1

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_i2c_mst2 --- com.arc.hardware.dfss.io_i2c_mst2.1_0 ########

# Create io_i2c_mst2
-create com.arc.hardware.dfss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2

# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'.
-io_i2c_mst2 true

# io_i2c_mst2_fs --- RX/TX FIFO size
-io_i2c_mst2_fs 16

# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included
-io_i2c_mst2_dma_support None

# io_i2c_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
-io_i2c_mst2_cdc_included 1

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_i2c_slv0 --- com.arc.hardware.dfss.io_i2c_slv0.1_0 ########

# Create io_i2c_slv0
-create com.arc.hardware.dfss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0

# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'.
-io_i2c_slv0 true

# io_i2c_slv0_fs --- RX/TX FIFO size
-io_i2c_slv0_fs 16

# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included
-io_i2c_slv0_dma_support Memory-Based

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_pdm_rx0 --- com.arc.hardware.dfss.io_pdm_rx0.1_0 ########

# Create io_pdm_rx0
-create com.arc.hardware.dfss.io_pdm_rx0.1_0 System.CPUisle.ARCv2EM.io_pdm_rx0

# io_pdm_rx0 --- Command line option for APEX extension component 'io_pdm_rx0'.
-io_pdm_rx0 true

# io_pdm_rx0_ch --- Number of Stereo Channels
-io_pdm_rx0_ch 1

# io_pdm_rx0_fs --- RX FIFO size
-io_pdm_rx0_fs 8

# io_pdm_rx0_ns --- Maximum number of CIC stages
-io_pdm_rx0_ns 4

# io_pdm_rx0_ds --- Maximum delay in the COMB filter of the CIC filter
-io_pdm_rx0_ds 2

# io_pdm_rx0_dma_support --- Specifies whether the DMA handshake interface is included
-io_pdm_rx0_dma_support Memory-Based

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_spi_slv0 --- com.arc.hardware.dfss.io_spi_slv0.1_0 ########

# Create io_spi_slv0
-create com.arc.hardware.dfss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0

# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'.
-io_spi_slv0 true

# io_spi_slv0_fz --- RX/TX FIFO depth
-io_spi_slv0_fs 32

# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width.
-io_spi_slv0_max_xfer_size 32

# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
-io_spi_slv0_dma_support Memory-Based

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_uart0 --- com.arc.hardware.dfss.io_uart0.1_0 ########

# Create io_uart0
-create com.arc.hardware.dfss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0

# io_uart0 --- Command line option for EIA extension component 'io_uart0'.
-io_uart0 true

# io_uart0_fifo_mode --- Set the UART FIFO mode
-io_uart0_fifo_mode 16

# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
-io_uart0_dma_support Memory-Based

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## io_uart1 --- com.arc.hardware.dfss.io_uart1.1_0 ########

# Create io_uart1
-create com.arc.hardware.dfss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1

# io_uart1 --- Command line option for EIA extension component 'io_uart1'.
-io_uart1 true

# io_uart1_fifo_mode --- Set the UART FIFO mode
-io_uart1_fifo_mode 16

# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
-io_uart1_dma_support Memory-Based

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## subsys_bcr --- com.arc.hardware.dfss.subsys_bcr.1_0 ########

# Create subsys_bcr
-create com.arc.hardware.dfss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr

# assign_xpubit --- 
#       
# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
# <p>
# By default an extension is not assigned a bit in this register.  This means the extension is always available.
# <p>
# If you wish to assign an XPU bit number, select this option.
# 
# 
-assign_xpubit false

# xpubit --- 
# The XPU bit number for this extension.
# 
-xpubit 0


######## AGU --- com.arc.hardware.AGU.1_0 ########

# Create AGU
-create com.arc.hardware.AGU.1_0 System.CPUisle.ARCv2EM.AGU

# agu_size --- Predefined configurations of modifiers, address 
# pointers and offset registers                   
# <pre>
# 
#         address     address                     
#         pointers    offset regs      modifiers  
#        ----------- --------------- ------------ 
# small:     4           2                 4      
# medium:    8           4                 12     
# large:     12          8                 24     
# </pre>
# 
-agu_size large

# agu_accord --- Enable the accordion stage if operating frequency is critical
-agu_accord true

# agu_wb_depth --- Write buffer depth
-agu_wb_depth 4


######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ########

# Create Actionpoints
-create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints

# num_actionpoints --- This is the number of trigger events available.
-num_actionpoints 2

# aps_feature --- Selects Actionpoint feature set
-aps_feature full


######## DCCM --- com.arc.hardware.DCCM.1_0 ########

# Create DCCM
-create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM

# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes
-dccm_size 524288

# dccm_base --- Sets the initial memory region assignment for DCCM
-dccm_base 8

# dccm_interleave --- Split DCCM into even/odd memory banks.
-dccm_interleave true

# dccm_prot --- Specifies the type of protection built for the DCCM.
-dccm_prot None

# dccm_prot_level --- Specifies the level protection.
-dccm_prot_level Data_Only

# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM
-dccm_prot_exceptions false

# dccm_sec_lvl --- Specifies the level of secure DCCM.
-dccm_sec_lvl Non_Secure

# dccm_dmi --- This enables external access through a DMI (direct memory interface) port.
-dccm_dmi false


######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ########

# Create DMA Controller
-create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller"

# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller
-dmac_channels 16

# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words.
-dmac_fifo_depth 4

# dmac_int_config --- None: the DMA controller cannot raise an interrupt
# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy
# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy
# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core
# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core
-dmac_int_config Multiple-Internal

# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space.
-dmac_registers 0

# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface.
-dmac_mem_if separate

# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc.
# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface.
-dmac_per_if 0xf800


######## DSP --- com.arc.hardware.DSP.1_0 ########

# Create DSP
-create com.arc.hardware.DSP.1_0 System.CPUisle.ARCv2EM.DSP

# dsp_complex --- Enable/disable support for single cycle 16b+16b complex instructions and butterfly operations, else 2-cycle complex instructions only without butterfly support
-dsp_complex true

# dsp_itu --- Enable/disable support for ITU bit-accurate 1 bit fractional shift before accumulation, else 1-bit fractional shift result after accumulation only
-dsp_itu true

# dsp_divsqrt --- Enable/disable support for divide and square root operations: DIV(U), REM(U), SQRT
-dsp_divsqrt radix2

# dsp_accshift --- Select support for accumulator shift operations: no supported, limited shift support only or full shift support and convergent rounding
-dsp_accshift full

# dsp_impl --- The datapath components may be inferred from Verilog for better area or optimized using carry-save components for better timing
-dsp_impl inferred


######## Data Memory Initiator --- com.arc.hardware.Data_Memory_Initiator.1_0 ########

# Create Data Memory Initiator
-create com.arc.hardware.Data_Memory_Initiator.1_0 "System.CPUisle.ARCv2EM.Data Memory Initiator"

######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ########

# Create Debug Interface
-create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface"

# dbg_en_option --- Adds an enable pin to the existing debug interface
-dbg_en_option false

# scdbg_aux_unlk --- An internal demo module will be included when enable
-scdbg_aux_unlk false

# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one
-dbg_apb_option false


######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ########

# Create Floating-point unit
-create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit"

# fpu_dp_assist --- This enables double-precision acceleration instructions.
-fpu_dp_assist false

# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions.
-fpu_fma_option true

# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed.
-fpu_mas_cycles 2

# fpu_pipe_impl --- FPU pipelined implementation
-fpu_pipe_impl true

# fpu_div_option --- This enables divide & square-root acceleration
-fpu_div_option true

# fpu_div_cycles --- Controls div/sqrt implementation.
-fpu_div_cycles 17


######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ########

# Create ICCM0
-create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0

# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states.
-iccm0_size 65536

# iccm0_base --- Sets the initial memory region assignment for ICCM0
-iccm0_base 0

# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses.
-iccm0_wide false

# iccm0_prot --- Specifies the type of protection built for ICCM0.
-iccm0_prot None

# iccm0_prot_level --- Specifies the level of protection.
-iccm0_prot_level Data_Only

# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0
-iccm0_prot_exceptions true

# iccm0_sec_lvl --- Specifies the level of secure ICCM0.
-iccm0_sec_lvl Non_Secure

# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port.
-iccm0_dmi false


######## ICCM1 --- com.arc.hardware.ICCM1.1_0 ########

# Create ICCM1
-create com.arc.hardware.ICCM1.1_0 System.CPUisle.ARCv2EM.ICCM1

# iccm1_size --- This defines the size of ICCM1 in bytes.This ICCM has 1 wait states.
-iccm1_size 524288

# iccm1_base --- Sets the initial memory region assignment for ICCM1
-iccm1_base 1

# iccm1_banking --- With dual memory banks, the ICCM has better cycle performance.
-iccm1_banking true

# iccm1_sec_lvl --- Specifies the level of secure ICCM1.
-iccm1_sec_lvl Non_Secure

# iccm1_dmi --- This enables external access through a DMI (direct memory interface) port.
-iccm1_dmi false


######## Instruction Fetch Queue --- com.arc.hardware.Instruction_Fetch_Queue.1_0 ########

# Create Instruction Fetch Queue
-create com.arc.hardware.Instruction_Fetch_Queue.1_0 "System.CPUisle.ARCv2EM.Instruction Fetch Queue"

# ifqueue_size --- This defines the number of entires in the Instruction Fetch Queue.
-ifqueue_size 8

# ifqueue_burst_size --- This sets the burst size for bus data transfers (in 32-bit words).  It cannot exceed the number of entries.
-ifqueue_burst_size 2


######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ########

# Create Interrupt Controller
-create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller"

# number_of_interrupts --- This is the total number of interrupts available to the core.  Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts).  For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual.
-number_of_interrupts 158

# number_of_levels --- Priority levels in the interrupt controller.
-number_of_levels 2

# external_interrupts --- This is the total number of interrupt pins available for external system components.  This parameter must be less than the total number of interrupts.
-external_interrupts 107

# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory.
-firq_option true


######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ########

# Create JTAG Interface
-create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface"

######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ########

# Create Real-time Counter
-create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter"

######## SmaRT --- com.arc.hardware.SmaRT.1_0 ########

# Create SmaRT
-create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT

# smart_stack_entries --- This specifies the number of entries in the trace buffer.
-smart_stack_entries 32

# smart_implementation --- Flip-flop = FF-based design.  Memory = memory-based design (provides better density for larger trace buffers).
-smart_implementation flip-flop


######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ########

# Create Timer 0
-create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0"

# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0.
-timer_0_int_level 1


######## Timer 1 --- com.arc.hardware.Timer_1.1_0 ########

# Create Timer 1
-create com.arc.hardware.Timer_1.1_0 "System.CPUisle.ARCv2EM.Timer 1"

# timer_1_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 1.
-timer_1_int_level 1


######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ########

# Create Watchdog Timer
-create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer"

# watchdog_size --- Specifies the bit width of timer's internal counter.
-watchdog_size 32

# watchdog_clk --- Specifies whether the timer should be driven from a separate clock.
-watchdog_clk false


######## XY --- com.arc.hardware.XY.1_0 ########

# Create XY
-create com.arc.hardware.XY.1_0 System.CPUisle.ARCv2EM.XY

# xy_config --- XY memory configuration:
# One memory: DCCM only.
# Two memories: DCCM + Y.
# Three memories: DCCM + X + Y.
-xy_config dccm_x_y

# xy_size --- Size of X and Y memories if included.
# X and Y memories both have the same configured size.
-xy_size 32768

# xy_interleave --- Split XY memories into odd/even instances to enable single cycle unaligned access.
-xy_interleave false

# xy_x_base --- Base region for X memory. All accesses to this region will initiate a transfer on the X memory.
-xy_x_base 9

# xy_y_base --- Base region for Y memory. All accesses to this region will initiate a transfer on the Y memory.
-xy_y_base 10


######## ARCv2EM CCT --- cct.1_0 ########

# Create ARCv2EM CCT
-create cct.1_0 "System.ARCv2EM CCT"

# cct --- 
# 	Option used to add a CCT to the design for command-line builds
# 	Without this architect can't add this component to a build
# 	via a cmdline -create command.  
# 	with old scripts.
# 	
-cct true

# no_hostlink --- 
# This prevents the inclusion of the hostlink library when compiling
# C or C++ programs.  The resultant executable, if it contains printfs,
# will print to an internal fixed buffer __mwwrite_buf.  
# Other hostlink operations that require debugger assistance, such as file
# opens, will fail.
# 
# Hostlink references incur memory cycles at unpredictable times and 
# so can perturb cycle-timing results.  Without hostlink,
# the debugger will not in any way interfere with the target while it is running.  
# Therefore this option is useful for simulation in which you want precisely the
# same cycle timing to occur each time you run, or for accurate power consumption results.
# 	
-cct_no_hostlink false


######## BusFabric --- com.arc.hardware.ARCv2MSS.BusFabric.1_0 ########

# Create BusFabric
-create com.arc.hardware.ARCv2MSS.BusFabric.1_0 System.BusFabric

# alb_mss_fab_def_div2ref --- This specifies the clock division factor at reset. It is used for mss clock controller to generate mss fabric clock, and the value N means mss fabric is running at (1/N) x ref_clk.
-alb_mss_fab_def_div2ref 1

# alb_mss_fab_lat --- This specifies the maximum latency in the master latency units.
-alb_mss_fab_lat 0

# alb_mss_fab_def_lat --- This specifies the latency after reset for the master latency units.
-alb_mss_fab_def_lat 0

# alb_mss_fab_def_wr_bw --- This specifies the write channel bandwidth parameter after reset for the master bandwidth control units.
-alb_mss_fab_def_wr_bw 0

# alb_mss_fab_def_rd_bw --- This specifies the read channel bandwidth parameter after reset for the master bandwidth control units.
-alb_mss_fab_def_rd_bw 0

# alb_mss_ccm_base --- This specifies the base address at which the ICCM and DCCM DMIs will be placed in the memory map. The address should be divided by 4KB i.e. do not specify the lower 12 bits of the address.
-alb_mss_ccm_base 0x4_0000


######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ########

# Create ClkCtrl
-create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl

# alb_mss_clkctrl_base_addr --- This specifies the clock controller base address in the memory map, divided by 4KB i.e. do not specify the lower 12 bits of the address.
-alb_mss_clkctrl_base_addr 0xc00

# alb_mss_clkctrl_bypass_mode --- If true then all clock dividers/gaters in the clock controller are bypassed, clock ratio is not supported and the division options/registers are overriden
-alb_mss_clkctrl_bypass_mode false


######## DSP Software --- com.arc.software.dfss.sw_dsp.1_0 ########

# Create DSP Software
-create com.arc.software.dfss.sw_dsp.1_0 "System.DSP Software"

# sw_dsp --- Command line option for Software element 'DSP Software'
-sw_dsp true


######## Generic ASIC Library Data --- com.synopsys.GenericTechnologyLibrary.1_0 ########

# Create Generic ASIC Library Data
-create com.synopsys.GenericTechnologyLibrary.1_0 "System.Generic ASIC Library Data"

# Geometry --- The desired ASIC geometry used for synthesis.
-geometry 0.045

# DontUseList --- List of synthesis library cells NOT to be used.
-dont_use_list ""

# DrivingCellName --- The name of the driving cell used to set the context for synthesis.
-driving_cell_name SEN_BUF_8

# DrivingCellPin --- The name of the ouput pin on the driving cell.
-driving_cell_pin X

# LoadPin --- The load pin of the driving cell.
-load_pin A

# TechLibPath --- The path to the synthesis technology library (i.e. where *.db files are located) 
-tech_lib_path "/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/liberty/logic_synth /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npksdst/latest/liberty/logic_synth /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkspdt/latest/liberty/logic_synth"

# TechCellFile --- The path and file name of the Verilog technology library cell file.
-tech_cell_path "/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/verilog/3.0/ts40npkldst.v /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npksdst/latest/verilog/3.0/ts40npksdst.v /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkspdt/latest/verilog/3.0/ts40npkspdt.v"

# TechCellLef --- A comma separated list of LEF files. The first file must contain the LEF technology information in addition to any macros defined. Subsequent files may contain additional macro definitions e.g. definitions of the standard cells.
-tech_cell_lef /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/lef/5.6/ts40npkldst_m07f0f2_RDL.lef,/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/lef/5.6/ts40npkldst.lef,/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npksdst/latest/lef/5.6/ts40npksdst.lef,/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkspdt/latest/lef/5.6/ts40npkspdt.lef

# SymbolLib --- The name of the file that contains the symbol library for synthesis.
-symbol_lib ""

# MaxLibFile --- The file name of the max synthesis library
-max_lib_file "ts40npkldst_ss0p99v125c.db  ts40npksdst_ss0p99v125c.db   ts40npkspdt_ss0p99v125c.db ts40npkspdt_pg_ss0p99v125c.db ts40npkspdt_dlvl_ss0p99v125c.db ts40npkspdt_dlvl_ss0p99v125c_i1p08v.db ts40npkspdt_dlvl_ss0p99v125c_i1p1v.db ts40npkspdt_ulvl_ss0p99v125c.db ts40npkspdt_ulvl_ss0p99v125c_i0p66v.db ts40npkspdt_ulvl_ss0p99v125c_i0p81v.db ts40npkspdt_ulvl_ss0p99v125c_i0p88v.db"

# MaxLibName --- The name of the max library used for synthesis.
-max_lib_name "ts40npkldst_ss0p99v125c  ts40npksdst_ss0p99v125c  ts40npkspdt_ss0p99v125c ts40npkspdt_pg_ss0p99v125c ts40npkspdt_dlvl_ss0p99v125c ts40npkspdt_dlvl_ss0p99v125c_i1p08v ts40npkspdt_dlvl_ss0p99v125c_i1p1v ts40npkspdt_ulvl_ss0p99v125c ts40npkspdt_ulvl_ss0p99v125c_i0p66v ts40npkspdt_ulvl_ss0p99v125c_i0p81v ts40npkspdt_ulvl_ss0p99v125c_i0p88v"

# MinLibFile --- The name of the file containing the min synthesis library.
-min_lib_file "ts40npkldst_ff1p21vn40c.db  ts40npksdst_ff1p21vn40c.db  ts40npkspdt_ff1p21vn40c.db ts40npkspdt_pg_ff1p21vn40c.db ts40npkspdt_dlvl_ff1p21vn40c.db ts40npkspdt_dlvl_ff1p21vn40c_i1p26v.db ts40npkspdt_ulvl_ff1p21vn40c.db ts40npkspdt_ulvl_ff1p21vn40c_i0p99v.db"

# MinLibName --- The name of the min synthesis library.
-min_lib_name "ts40npkldst_ff1p21vn40c ts40npksdst_ff1p21vn40c  ts40npkspdt_ff1p21vn40c ts40npkspdt_pg_ff1p21vn40c ts40npkspdt_dlvl_ff1p21vn40c ts40npkspdt_dlvl_ff1p21vn40c_i1p26v ts40npkspdt_ulvl_ff1p21vn40c ts40npkspdt_ulvl_ff1p21vn40c_i0p99v"

# TypLibFile --- The name of the file containing the typical synthesis library.
-typ_lib_file "ts40npkldst_tt1p1v25c.db  ts40npksdst_tt1p1v25c.db ts40npkspdt_tt1p1v25c.db ts40npkspdt_pg_tt1p1v25c.db ts40npkspdt_dlvl_tt1p1v25c.db ts40npkspdt_ulvl_tt1p1v25c.db ts40npkspdt_ulvl_tt1p1v25c_i0p9v.db"

# TypLibName --- The name of the typical synthesis library.
-typ_lib_name "ts40npkldst_tt1p1v25c  ts40npksdst_tt1p1v25c ts40npkspdt_tt1p1v25c ts40npkspdt_pg_tt1p1v25c ts40npkspdt_dlvl_tt1p1v25c ts40npkspdt_ulvl_tt1p1v25c ts40npkspdt_ulvl_tt1p1v25c_i0p9v"

# SynOperatingCon --- The synthesis operating conditions.
-syn_operating_con SS0P99V125C

# LibraryList --- List of library names used in this component. Order must be same as ,db model names
-library_list "ts40npkldst  ts40npksdst ts40npkspdt ts40npkspdt_pg ts40npkspdt_dlvl ts40npkspdt_ulvl ts40npkspdt_ulvl"

# PtSlowOpCons --- The operating conditions to be used for worst case static timing analysis
-pt_slow_op_cons SS0P99V125C

# PtFastOpCons --- The operating conditions to be used for best case static timing analysis.
-pt_fast_op_cons FF1P21VN40C

# PtTypicalOpCons --- The operating conditions to be used for typical case static timing analysis.
-pt_typical_op_cons TT1P1V25C

# PhysLibPath --- The path to the Synopsys physical synthesis libraries.
-phys_lib_path ""

# PhysLib --- The Synopsys physical synthesis library name.
-phys_lib ""

# DataBasePath --- The path and name of the 'map file' located at the top level of the DataBase containing the pre-compiled Vendor RAM models and wrapper files.
-data_base_path arcrams_lib/map_file.txt

# CapTable --- File containing lookup tables for fast estimation of parasitics in Cadence's FirstEncounter tool
-cap_table ""

# BufFootprint --- The names of the footprints in the library that represent buffers
-buf_footprint SST_BUF

# InvFootprint --- The names of the footprints in the library that represent inverters
-inv_footprint SST_INV

# DelFootprint --- The names of the footprints in the library that represent delay cells
-del_footprint SST_DEL_L4

# ClockGatingCell --- Name of clock gating cell to be used as architectural clock gate or as RTL-inferred ICG
-clock_gating_cell SEL_CKGTPLT_V5_8

# ClockNGatingCell --- Name of the negedge clock gating cell to be used as architectural clock gate or as RTL-inferred ICG
-clockn_gating_cell SEL_CKGTNLT_V5_8

# DecapCells --- list of decap cells for this library
-decap_cells "SEL_DCAP64 SEL_DCAP32 SEL_DCAP16 SEL_DCAP8 SEL_DCAP4"

# FillerCells --- list of filler cells for this library
-filler_cells "SEL_FILL64 SEL_FILL32 SEL_FILL16 SEL_FILL12 SEL_FILL8 SEL_FILL6 SEL_FILL5  SEL_FILL4  SEL_FILL3 SEL_FILL2  SEL_FILL1"

# AntDiodeCells --- list of antenna diode protection cells for this library
-ant_diode_cells SEL_TIEDIN_1

# MinWellTapDistance --- Minimum required distance between well-tap cells ( in microns ) 
-min_nwell_tap_distance 110

# NwellTapCell --- Name of nwell tap cell to be used
-nwell_tap_cell SEL_TAPDS1T5

# NwellAoTapCell --- Name of nwell always-on tap cell to be used
-nwell_ao_tap_cell PEL_TAPPP

# EndCapCellLeft --- Name of end cap cells to be used at left side of row
-end_cap_cell_left SEL_CAPL8

# EndCapCellRight --- Name of end cap cells to be used at right side of row
-end_cap_cell_right SEL_CAPR8

# EndCapCellTop --- Name of end cap cells to be used at top side of row
-end_cap_cell_top ""

# EndCapCellBottom --- Name of end cap cells to be used at bottom side of row
-end_cap_cell_bottom ""

# EndCapCellTopLeftOutside --- Name of end cap cells to be used at top left outside corner
-end_cap_cell_top_left_outside ""

# EndCapCellTopRightOutside --- Name of end cap cells to be used at top right outside corner
-end_cap_cell_top_right_outside ""

# EndCapCellBottomLeftOutside --- Name of end cap cells to be used at bottom left outside corner
-end_cap_cell_bottom_left_outside ""

# EndCapCellBottomRightOutside --- Name of end cap cells to be used at bottom right outside corner
-end_cap_cell_bottom_right_outside ""

# EndCapCellTopLeftInside --- Name of end cap cells to be used at top left inside corner
-end_cap_cell_top_left_inside ""

# EndCapCellTopRightInside --- Name of end cap cells to be used at top right inside corner
-end_cap_cell_top_right_inside ""

# EndCapCellBottomLeftInside --- Name of end cap cells to be used at bottom left inside corner
-end_cap_cell_bottom_left_inside ""

# EndCapCellBottomRightInside --- Name of end cap cells to be used at bottom right inside corner
-end_cap_cell_bottom_right_inside ""

# GdsLayerMapFile --- Name of file mapping layers names to GDS2 layer numbers
-gds_layer_map_file ""

# MetalFillDeck --- Name of file ICV/Hercules deck for doing metal fill on GDS2 view
-metal_fill_deck ""

# AntRuleDeck --- Name of file ICV/Hercules deck for doing Antenna rule checking
-ant_rule_deck ""

# DrcRuleDeck --- Name of file ICV/Hercules deck for doing DRC checking
-drc_rule_deck ""

# LvsRuleDeck --- Name of file ICV/Hercules deck for doing LVS checking
-lvs_rule_deck ""

# AntRuleFile --- Name of file TCL rule file for doing Antenna fixing
-ant_rule_file /remote/arc/arc6000/libext/stdcell/28HPC/ts28_hpc_lvt_gate_30nm_hd_base/latest/milkyway/antenna/antenna_rule_db_update_m10f2f0f2_RDL.tcl

# EmRuleFile --- Name of file ALF rule file for doing ElectoMigration Analysis
-em_rule_file /remote/arc/arc6000/libext/stdcell/28HPC/ts28_hpc_lvt_gate_30nm_hd_base/latest/milkyway/alf/ts28nchllogl30hdl140f_m10f2f0f2_RDL.alf

# DblViaOrderFile --- Name of file with foundry-preferred order of doubled vias when doing via doubling
-dbl_via_order_file /remote/arc/arc6000/libext/stdcell/28HPC/ts28_hpc_lvt_gate_30nm_uhd_base/latest/demo/pnr/ICC/cmds/ts28.rvi.map

# ClockBufferCells --- A list of buffers and inverters in the library that may be used in the construction of a clock tree
-clock_buffers "SEL_BUF_S_2 SEL_BUF_S_4 SEL_BUF_S_6 SEL_BUF_S_8 SEL_BUF_S_12 SEL_INV_S_2 SEL_INV_S_4 SEL_INV_S_6 SEL_INV_S_8 SEL_INV_S_12"

# ClockTransition --- The maximum transition time allowed on clock nets
-clock_transition 0.3

# QxTechnology --- Technology file for Cadence's 3D extraction engine, QX
-qx_techfile /remote/arc/arc6000/libext/iclibs/TSMC45/PcC040LP_CRN45SHRINK_7M4X0Y2Z0UPDK/0.2/tools/cadence_ext/7.1.2/GXL/LP/GXL_LP_rcworst/qrcTechFile

# QxLibrary --- The location of the QX library data
-qx_library /remote/arc/arc6000/libext/iclibs/TSMC45/PcC045LP_CRN45_7M4X0Y2Z0UPDK/1.1.1/tools/cadence_anls/xtc

# RAMWePolarity --- Defines the polarity of the write enable signals for all RAMs in the ARC700.
-ram_we_polarity 0

# RAMCkPolarity --- Defines the polarity of the clock enable signals for all RAMs in the ARC700.
-ram_ck_polarity 0

# MilkywayTechFile --- The path to the technology file for milkyway libraries.
-mw_tech_file /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tf/ts40npkldst_m10f2f2_RDL.tf

# MilkywaySearchPath --- A comma separated list of directories to use when searching for milkyway libraries
-mw_search_path "/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npksdst/latest/milkyway /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkspdt/latest/milkyway"

# MilkywayCellLibraries --- A comma separated list of milkyway databases to be found on the search path
-mw_cell_libs "/remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/ts40npkldst_m10f2f2_RDL  /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npksdst/latest/milkyway/ts40npksdst_m10f2f2_RDL /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkspdt/latest/milkyway/ts40npkspdt_m10f2f2_RDL"

# MilkywayPowerNet --- The name of the power net needed by write_milkyway
-mw_power_net VDD

# MilkywayGroundNet --- The name of the ground net needed by write_milkyway
-mw_ground_net VSS

# TLUPlusMaxFile --- The TLU+ file which contains the parameters for max extraction
-tluplus_max_file /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tlup/tsmc_cln40lp_1p10m+alrdl_5x2y2z_cworst_1.1_1p1.tluplus

# TLUPlusMinFile --- The TLU+ file which contains the parameters for min extraction
-tluplus_min_file /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tlup/tsmc_cln40lp_1p10m+alrdl_5x2y2z_cbest_1.1_1p1.nxtgrd

# TLUMapFile --- The TLU+ map file to map layers names to the Milkyway layer names
-tluplus_map_file /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tlup/layers.map

# max_NXTGRD --- The NXTGRD file is used for parasitic extraction with StarRC
-max_nxtgrd /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tlup/tsmc_cln40lp_1p10m+alrdl_5x2y2z_cworst_1.1_1p1.nxtgrd

# min_NXTGRD --- The NXTGRD file is used for parasitic extraction with StarRC
-min_nxtgrd /remote/arc/arc6000/libext/stdcell/40LP/HighDensity/ts40npkldst/latest/milkyway/tlup/tsmc_cln40lp_1p10m+alrdl_5x2y2z_cbest_1.1_1p1.nxtgrd

# IcgCellCkPinName --- Name of clock input pin on integrated clock gating cell
-icgcell_ck_pin_name CK

# IcgCellQPinName --- Name of gated clock output pin on integrated clock gating cell
-icgcell_q_pin_name Q

# IcgCellFEPinName --- Name of the functional enable pin on integrated clock gating cell
-icgcell_fe_pin_name EN

# IcgCellTEPinName --- Name of the test enable pin on integrated clock gating cell
-icgcell_te_pin_name SE

# SupplyVolt_wc --- Worst-case operating voltage
-supply_volt_wc 0.99

# SupplyVolt_bc --- Best-case operating voltage
-supply_volt_bc 1.21

# IsoCellClampHigh --- Name of isolation cell to be used as clamp high
-iso_cell_clamp_high PEN_ISOS0CL1_*

# IsoCellClampLow --- Name of isolation cell to be used as clamp low
-iso_cell_clamp_low PEN_ISOS1CL0_*

# PwrSwitchCell --- Name of power switch cell to be used
-pwr_switch_cell PEN_PGATDRV_OW_12

# PwrSwitchCellResWc --- Worst case power switch cell resistance
-power_switch_cell_res_wc 233.4

# PwrSwitchCellPinLayers --- Primary and secondary (=always on and gated) power pins and associated layer names
-power_switch_cell_pin_layers "VDDP M2 VDDC M2"

# SupplyVoltULP_wc --- Worst-case ultra low power operating voltage for std cell parts
-supply_volt_ulp_wc 0.63

# LSCellHigh2Low --- Level shifter cell from high to low voltage domain
-ls_cell_high_2_low "PTQ_LVLDBUF_DP_* PTQ_LVLDBUF_D_*"

# LSCellLow2High --- level shifter cell from low to high voltage domain
-ls_cell_low_2_high "PTQ_LVLDBUF_PU_* PTQ_LVLDBUF_U_* PTQ_LVLDBUF_PY2_* PTQ_LVLDBUF_Y2_*"

# SingleFfSyncCell --- Single flip-flop synchronizer cell
-single_ff_sync_cell ""

# SingleFfSyncCellRstLowPol --- Defines the polarity of the reset signal for single flip-flop synchronizer cell.
-single_ff_sync_cell_rst_low_pol 0

# SingleFfSyncCellCkPinName --- Name of clock pin on single flip-flop synchronizer cell
-single_ff_sync_cell_ck_pin_name ""

# SingleFfSyncCellDPinName --- Name of data input pin on single flip-flop synchronizer cell
-single_ff_sync_cell_d_pin_name ""

# SingleFfSyncCellRstPinName --- Name of reset pin on single flip-flop synchronizer cell
-single_ff_sync_cell_rst_pin_name ""

# SingleFfSyncCellQPinName --- Name of data output pin on single flip-flop synchronizer cell
-single_ff_sync_cell_q_pin_name ""

# SingleNegEdgeFfSyncCell --- Single negative edge triggered flip-flop synchronizer cell
-single_negedge_ff_sync_cell ""

# SingleNegEdgeFfSyncCellRstLowPol --- Defines the polarity of the reset signal for single negative edge triggered flip-flop synchronizer cell.
-single_negedge_ff_sync_cell_rst_low_pol 0

# SingleNegEdgeFfSyncCellCkPinName --- Name of clock pin on single negative edge triggered flip-flop synchronizer cell
-single_negedge_ff_sync_cell_ck_pin_name ""

# SingleNegEdgeFfSyncCellDPinName --- Name of data input pin on single negative edge triggered flip-flop synchronizer cell
-single_negedge_ff_sync_cell_d_pin_name ""

# SingleNegEdgeFfSyncCellRstPinName --- Name of reset pin on single negative edge triggered flip-flop synchronizer cell
-single_negedge_ff_sync_cell_rst_pin_name ""

# SingleNegEdgeFfSyncCellQPinName --- Name of data output pin on single negative edge triggered flip-flop synchronizer cell
-single_negedge_ff_sync_cell_q_pin_name ""

# DoubleFfSyncCell --- Double flip-flop synchronizer cell
-double_ff_sync_cell ""

# DoubleFfSyncCellRstLowPol --- Defines the polarity of the reset signal for double flip-flop synchronizer cell.
-double_ff_sync_cell_rst_low_pol 0

# DoubleFfSyncCellCkPinName --- Name of clock pin on double flip-flop synchronizer cell
-double_ff_sync_cell_ck_pin_name ""

# DoubleFfSyncCellDPinName --- Name of data input pin on double flip-flop synchronizer cell
-double_ff_sync_cell_d_pin_name ""

# DoubleFfSyncCellRstPinName --- Name of reset pin on double flip-flop synchronizer cell
-double_ff_sync_cell_rst_pin_name ""

# DoubleFfSyncCellQPinName --- Name of data output pin on double flip-flop synchronizer cell
-double_ff_sync_cell_q_pin_name ""


######## IO Software --- com.arc.software.dfss.sw_io.1_0 ########

# Create IO Software
-create com.arc.software.dfss.sw_io.1_0 "System.IO Software"

# sw_io --- Command line option for Software element 'IO Software'
-sw_io true


######## Implementation --- com.arc.hardware.implementation.1_0 ########

# Create Implementation
-create com.arc.hardware.implementation.1_0 System.Implementation

# ClockSpeed --- Target clock speed of the system
-clock_speed 400

# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio
# 2x
# 3x
# 4x
-ddr2_clk_ratio 3x

# ClockSkew --- The clock skew for the system
-clock_skew 0.5

# HoldMargin --- Margin for hold time checks
-hold_margin 0.05

# Floorplan --- Floorplan definition for relative placement of  RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level)
-floorplan em9d_xyccm

# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz).
# 
# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid.
# 
# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads.
# 
# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2)
# 
# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock.
# 
-jtag_tclk 10

# execution_trace_level --- 
# This traces committed instructions as they execute, and gathers statistics
# visible in the debugger for counting instructions & cycle delays.
# At the "stats" level ony the statistics are gathered and no trace is printed.
# "file" is equivalent to "full", but the results go to a trace .txt file instead.
# 
-execution_trace_level file

# generate_ipxact --- 
# Generate ipxact.xml file describing the CPUisle or archipelago frontier
# 
-generate_ipxact true

# ipxact_relative_path_names --- 
# Use relative path names for Verilog files in the ipxact.
# Otherwise, absolute path names are used.
# 
-ipxact_relative_path_names true

# optional_encryption --- 
# When selected, encrypted RTL output is generated.
# 	
-optional_encryption false

# ignore_encrypt_license --- 
# When selected, pretend the encryption license is missing.  For testing.
# 	
-ignore_encrypt_license false

# ignore_clear_license --- 
# When selected, pretend the cleartest license is missing.  For testing.
# 	
-ignore_clear_license false


######## Infrastructure Software --- com.arc.software.dfss.sw_infra.1_0 ########

# Create Infrastructure Software
-create com.arc.software.dfss.sw_infra.1_0 "System.Infrastructure Software"

# sw_infra --- Command line option for Software element 'Infrastructure Software'
-sw_infra true


######## JTAG2Wire --- com.arc.hardware.JTAG2Wire.1_0 ########

# Create JTAG2Wire
-create com.arc.hardware.JTAG2Wire.1_0 System.JTAG2Wire

# jtag_node_id --- 
# This sets the value of the tap controller node id.
# It is an 8-bit hexadecimal number.
#       
-jtag_node_id 0x0


######## SRAMCtrl --- com.arc.hardware.ARCv2MSS.SRAMCtrl.1_0 ########

# Create SRAMCtrl
-create com.arc.hardware.ARCv2MSS.SRAMCtrl.1_0 System.SRAMCtrl

# alb_mss_mem_region_num --- The number of regions supported in SRAMCtrl component
-alb_mss_mem_region_num 1

# alb_mss_mem0_base_addr --- This specifies the base address of memory region 0 in the memory map, divided by 4KB i.e. do no specify the lower 12 bits of the address.
-alb_mss_mem0_base_addr 0

# alb_mss_mem0_size --- This specifies the memory size of memory region 0.
-alb_mss_mem0_size 1MB

# alb_mss_mem0_attr --- This specifies the memory access attribute of memory region 0.
-alb_mss_mem0_attr Read-Write

# alb_mss_mem0_secure --- This specifies the memory secure attribute of memory region 0.
-alb_mss_mem0_secure Non-Secure

# alb_mss_mem0_lat --- This specifies the maximum latency of memory region 0 .
-alb_mss_mem0_lat 0

# alb_mss_mem0_def_lat --- This specifies the latency after reset of memory region 0.
-alb_mss_mem0_def_lat 0

# alb_mss_mem1_base_addr --- This specifies the base address of memory region 1 in the memory map, divided by 4KB i.e. do no specify the lower 12 bits of the address.
-alb_mss_mem1_base_addr 1048576

# alb_mss_mem1_size --- This specifies the memory size of memory region 1.
-alb_mss_mem1_size 1MB

# alb_mss_mem1_attr --- This specifies the memory access attribute of memory region 1.
-alb_mss_mem1_attr Read-Write

# alb_mss_mem1_secure --- This specifies the memory secure attribute of memory region 1.
-alb_mss_mem1_secure Non-Secure

# alb_mss_mem1_lat --- This specifies the maximum latency of memory region 1 .
-alb_mss_mem1_lat 0

# alb_mss_mem1_def_lat --- This specifies the latency after reset of memory region 1.
-alb_mss_mem1_def_lat 0

# alb_mss_mem2_base_addr --- This specifies the base address of memory region 2 in the memory map, divided by 4KB i.e. do no specify the lower 12 bits of the address.
-alb_mss_mem2_base_addr 1048576

# alb_mss_mem2_size --- This specifies the memory size of memory region 2.
-alb_mss_mem2_size 1MB

# alb_mss_mem2_attr --- This specifies the memory access attribute of memory region 2.
-alb_mss_mem2_attr Read-Write

# alb_mss_mem2_secure --- This specifies the memory secure attribute of memory region 2.
-alb_mss_mem2_secure Non-Secure

# alb_mss_mem2_lat --- This specifies the maximum latency of memory region 2 .
-alb_mss_mem2_lat 0

# alb_mss_mem2_def_lat --- This specifies the latency after reset of memory region 2.
-alb_mss_mem2_def_lat 0

# alb_mss_mem3_base_addr --- This specifies the base address of memory region 3 in the memory map, divided by 4KB i.e. do no specify the lower 12 bits of the address.
-alb_mss_mem3_base_addr 1048576

# alb_mss_mem3_size --- This specifies the memory size of memory region 3.
-alb_mss_mem3_size 1MB

# alb_mss_mem3_attr --- This specifies the memory access attribute of memory region 3.
-alb_mss_mem3_attr Read-Write

# alb_mss_mem3_secure --- This specifies the memory secure attribute of memory region 3.
-alb_mss_mem3_secure Non-Secure

# alb_mss_mem3_lat --- This specifies the maximum latency of memory region 3 .
-alb_mss_mem3_lat 0

# alb_mss_mem3_def_lat --- This specifies the latency after reset of memory region 3.
-alb_mss_mem3_def_lat 0

# alb_mss_mem_is_default_slave --- If true then all transactions without destination will be routed here.
-alb_mss_mem_is_default_slave true

# alb_mss_mem_default_space --- This specifies the memory space width of the system.
-alb_mss_mem_default_space 32

# alb_mss_mem_data_width --- This specifies the memory data width
-alb_mss_mem_data_width 64


######## Synopsys Power Analysis --- com.synopsys.PowerAnalysis.1_0 ########

# Create Synopsys Power Analysis
-create com.synopsys.PowerAnalysis.1_0 "System.Synopsys Power Analysis"

# DcPowerAnalysis --- Command line option to enable power analysis in DC
-synopsys_power_analysis true


######## Synopsys RM Physical Flow --- com.synopsys.PhysicalFlow_RM.1_0 ########

# Create Synopsys RM Physical Flow
-create com.synopsys.PhysicalFlow_RM.1_0 "System.Synopsys RM Physical Flow"

# SynopsysPhysicalRM --- Add the Synopsys Physical Full Design Flow component
-synopsys_physical_rm true

# UsefulSkew --- Allow the clock paths to macros to be deliberately skewed in order to redistribute available slack on reg2mem and mem2reg path
-useful_skew false

# EnhancedUsefulSkew --- Skew values are calculated via special script that takes acount of multi-cycle path groups
-enhanced_useful_skew false

# ScanChainsReorder --- Instruct the design flow to automatically reorder the scan chain structures.
-scan_reorder true

# userFloorplanPath --- Pathname of user floorplan
-userfloorplan_path ""

# toplevelpinLocationConstraintsFile --- Pathname+filename of the physical pin location constraints file for top-level design
-toplevel_pin_location_constraints_file ""

# MetalFill --- Metal fill step
# NONE
# ICC
# ICV
-metal_fill NONE

# CreateGDS --- Enable GDS streamout
-create_gds false

# AdvancedNode --- Enable Advanced Node routing optimizations
-advanced_node false

# TwoPassFlow --- Two-pass Flow
-two_pass_flow false

# OCVMargin --- OCV Margin (as percentage ratio, default 10%)
-ocv_margin 0.1


######## Synopsys XG Formal Verification Flow --- com.synopsys.FormalVerification_XG.1_0 ########

# Create Synopsys XG Formal Verification Flow
-create com.synopsys.FormalVerification_XG.1_0 "System.Synopsys XG Formal Verification Flow"

# SynopsysFormal --- Use this option to generate the scripts necessary to run formal verification in Formality
-synopsys_xg_formal true

# IntelMCCSpecific --- When true allows some Intel-MCC specific changes to scripts to be built
-intel_mcc_specific false


######## Synopsys XG Synthesis Flow --- com.synopsys.SynthesisFlow_XG.1_0 ########

# Create Synopsys XG Synthesis Flow
-create com.synopsys.SynthesisFlow_XG.1_0 "System.Synopsys XG Synthesis Flow"

# synopsysSynthesisFlow --- Add the synopsys SynthesisFlow component
-synopsys_xg_synthesis true

# Inbound12FFCopt --- 0:no limit imposed; 1-20 : the %number of cells which are allowed to be inbound 12-T
-inbound_12ffc_opt 0

# Retiming --- Instruct the design flow to retime modules as specified in retime_module_list
-enable_retiming false

# RetimeModuleList --- List of modules to be retimed
-retime_module_list ""

# InsertScanChains --- Instruct the design flow to automatically add in the scan chain structures.
-insert_scan_chains true

# ScanChains --- Indicates the number of scan chains to be used when stitching the scan registers;
# 	This option replaces the obsolete ScanChains option in implementation/System component.
-scan_chains 4

# InsertLogicBist --- Instruct the design flow to automatically add in the logic BIST structures.
-insert_logic_bist false

# LogicBistChains --- Indicates the number of logic BIST chains to be used when inserting Logic BIST
-logic_bist_chains 96

# PatternCounterWidth --- Indicates the width of logic BIST pattern counter
-pattern_counter_width 16

# InsertTestPoints --- Instruct the design flow to automatically add test points when inserting DfT structures.
-insert_test_points false

# PowerRampUp --- Specifies whether to run power ramp-up patterns prior to self-test.
-power_ramp_up false

# TestPointMethod --- Test Point Method
# DesignCompiler
# SpyGlassADV
-test_point_method DesignCompiler

# AutoUngroup --- Instruct the synthesis compile step to enable auto-ungrouping
-auto_ungroup false

# InsertClockGating --- When set this will cause Clock Gating Logic to be inserted during synthesis.
-insert_clock_gating true

# UPF --- When set this will cause UPF flow (isolation cell insertion) to be configured during synthesis.
-upf false

# DcUltra --- Enables Ultra optimization during synthesis.
-dc_ultra true

# MBFF --- Enables Targeting of multibit flops assuming library has them. Can cause performance drop but may give area/power saving
-mbff false

# DCTopographicMode --- Use DC Topographic mode for placement aware synthesis.
-dc_topographic true

# Hierarchical --- Enables hierarchical implementation flow.
-hierarchical false


######## SynopsysVC_Static_LP_Flow --- com.synopsys.SynopsysVC_Static_LP_Flow.1_0 ########

# Create SynopsysVC_Static_LP_Flow
-create com.synopsys.SynopsysVC_Static_LP_Flow.1_0 System.SynopsysVC_Static_LP_Flow

# SynopsysVC_Static_LP_Flow --- Add the Synopsys VC Static LP Flow Component
-vc_static_lp_flow true


######## subsys_infra --- com.arc.hardware.dfss.subsys_infra.1_0 ########

# Create subsys_infra
-create com.arc.hardware.dfss.subsys_infra.1_0 System.subsys_infra

# subsys_infra --- Command line option for EIA glue logic.
-subsys_infra true

# internal_interrupt --- Connect the IO interrupts internally
-internal_interrupt true

# internal_dma_handshake --- Connect the DMA handshake signals internally
-internal_dma_handshake true

# subsys_apex_offset --- Subsystem APEX address offset in the AUX address space. The aperture used by the subsystem is fixed to 0x0010_0000. In general, the APEX address offset must be in the range from 0x0010_0000 to 0xFFF0_0000. However, if your design includes the "UAUX Interface" component, then the APEX address offset must be in the range from 0x0010_0000 to 0x7FF0_0000 to avoid address conflicts with any UAUX components.
-subsys_apex_offset 0x8000_0000

# subsys_uaux_offset --- Subsystem UAUX address offset in the UAUX address space. The UAUX address offset must be an integer multiple of 0x0010_0000 in the range from 0x0000_0000 to 0x7FF0_0000. The aperture reserved for the subsystem is fixed to 0x0010_0000.
-subsys_uaux_offset 0x10_0000


]]></string>
  </configuration>
  <configuration name="assembler_defines" filename="core_config.s">
    <string><![CDATA[
.ifndef __core_config_s
	.define __core_config_s, 1
	.define _TOOL_CONFIG_VER, 10074
	.define	core_config_cir_identity,0x00000044
	.define	core_config_cir_identity_chipid,0
	.define	core_config_cir_identity_arcnum,0
	.define	core_config_cir_identity_arcver,68
	.define	core_config_cir_identity_family,4
	.define	core_config_cir_identity_corever,4
	.define	core_config_cir_aux_dccm,0x80000000
	.define	core_config_bcr_bcr_ver,0x00000002
	.define	core_config_bcr_bcr_ver_version,2
	.define	core_config_bcr_vecbase_ac_build,0x00000010
	.define	core_config_bcr_vecbase_ac_build_version,4
	.define	core_config_bcr_vecbase_ac_build_vector_config,0
	.define	core_config_bcr_vecbase_ac_build_addr,0
	.define	core_config_bcr_rf_build,0x00000102
	.define	core_config_bcr_rf_build_version,2
	.define	core_config_bcr_rf_build_p,1
	.define	core_config_bcr_rf_build_e,0
	.define	core_config_bcr_rf_build_r,0
	.define	core_config_bcr_rf_build_b,0
	.define	core_config_bcr_rf_build_d,0
	.define	core_config_bcr_dccm_build,0x00010b04
	.define	core_config_bcr_dccm_build_w,0
	.define	core_config_bcr_dccm_build_cycles,0
	.define	core_config_bcr_dccm_build_interleave,1
	.define	core_config_bcr_dccm_build_size1,0
	.define	core_config_bcr_dccm_build_size0,11
	.define	core_config_bcr_dccm_build_version,4
	.define	core_config_bcr_timer_build,0x00110704
	.define	core_config_bcr_timer_build_sp1,0
	.define	core_config_bcr_timer_build_sp0,0
	.define	core_config_bcr_timer_build_p1,1
	.define	core_config_bcr_timer_build_p0,1
	.define	core_config_bcr_timer_build_st1,0
	.define	core_config_bcr_timer_build_st0,0
	.define	core_config_bcr_timer_build_rtc,1
	.define	core_config_bcr_timer_build_rtsc_ver,17
	.define	core_config_bcr_timer_build_rtsc,0
	.define	core_config_bcr_timer_build_t0,1
	.define	core_config_bcr_timer_build_t1,1
	.define	core_config_bcr_timer_build_version,4
	.define	core_config_bcr_ap_build,0x00000005
	.define	core_config_bcr_ap_build_version,5
	.define	core_config_bcr_ap_build_type,0
	.define	core_config_bcr_iccm_build,0x0000b804
	.define	core_config_bcr_iccm_build_w0,0
	.define	core_config_bcr_iccm_build_iccm1_size1,0
	.define	core_config_bcr_iccm_build_iccm0_size1,0
	.define	core_config_bcr_iccm_build_iccm1_size0,11
	.define	core_config_bcr_iccm_build_iccm0_size0,8
	.define	core_config_bcr_iccm_build_version,4
	.define	core_config_bcr_xy_build,0x00003220
	.define	core_config_bcr_xy_build_memsize,3
	.define	core_config_bcr_xy_build_interleaved,0
	.define	core_config_bcr_xy_build_config,2
	.define	core_config_bcr_xy_build_version,32
	.define	core_config_bcr_dsp_build,0x00003521
	.define	core_config_bcr_dsp_build_wide,0
	.define	core_config_bcr_dsp_build_itu_pa,1
	.define	core_config_bcr_dsp_build_acc_shift,2
	.define	core_config_bcr_dsp_build_comp,1
	.define	core_config_bcr_dsp_build_divsqrt,1
	.define	core_config_bcr_dsp_build_version,33
	.define	core_config_bcr_multiply_build,0x00022206
	.define	core_config_bcr_multiply_build_version16x16,2
	.define	core_config_bcr_multiply_build_dsp,2
	.define	core_config_bcr_multiply_build_cyc,0
	.define	core_config_bcr_multiply_build_type,2
	.define	core_config_bcr_multiply_build_version32x32,6
	.define	core_config_bcr_swap_build,0x00000003
	.define	core_config_bcr_swap_build_version,3
	.define	core_config_bcr_norm_build,0x00000003
	.define	core_config_bcr_norm_build_version,3
	.define	core_config_bcr_minmax_build,0x00000002
	.define	core_config_bcr_minmax_build_version,2
	.define	core_config_bcr_barrel_build,0x00000303
	.define	core_config_bcr_barrel_build_version,3
	.define	core_config_bcr_barrel_build_shift_option,3
	.define	core_config_bcr_isa_config,0x12447402
	.define	core_config_bcr_isa_config_res1,0
	.define	core_config_bcr_isa_config_d,1
	.define	core_config_bcr_isa_config_res2,0
	.define	core_config_bcr_isa_config_f,0
	.define	core_config_bcr_isa_config_c,2
	.define	core_config_bcr_isa_config_l,0
	.define	core_config_bcr_isa_config_n,1
	.define	core_config_bcr_isa_config_a,0
	.define	core_config_bcr_isa_config_b,0
	.define	core_config_bcr_isa_config_addr_size,4
	.define	core_config_bcr_isa_config_lpc_size,7
	.define	core_config_bcr_isa_config_pc_size,4
	.define	core_config_bcr_isa_config_version,2
	.define	core_config_bcr_dmp_pp_build,0xf0000012
	.define	core_config_bcr_stack_region_build,0x00000002
	.define	core_config_bcr_erp_build,0x40000004
	.define	core_config_bcr_erp_build_l,0
	.define	core_config_bcr_erp_build_wd,2
	.define	core_config_bcr_erp_build_c,0
	.define	core_config_bcr_erp_build_mmu,0
	.define	core_config_bcr_erp_build_rf,0
	.define	core_config_bcr_erp_build_pc,0
	.define	core_config_bcr_erp_build_ic,0
	.define	core_config_bcr_erp_build_dc,0
	.define	core_config_bcr_erp_build_ip,0
	.define	core_config_bcr_erp_build_dp,0
	.define	core_config_bcr_erp_build_version,4
	.define	core_config_bcr_fpu_build,0x00004f03
	.define	core_config_bcr_fpu_build_da,0
	.define	core_config_bcr_fpu_build_hp,0
	.define	core_config_bcr_fpu_build_dd,0
	.define	core_config_bcr_fpu_build_dc,0
	.define	core_config_bcr_fpu_build_df,0
	.define	core_config_bcr_fpu_build_dp,0
	.define	core_config_bcr_fpu_build_fd_v1,2
	.define	core_config_bcr_fpu_build_pi,1
	.define	core_config_bcr_fpu_build_fd,0
	.define	core_config_bcr_fpu_build_fm,0
	.define	core_config_bcr_fpu_build_sd,1
	.define	core_config_bcr_fpu_build_sc,1
	.define	core_config_bcr_fpu_build_sf,1
	.define	core_config_bcr_fpu_build_sp,1
	.define	core_config_bcr_fpu_build_version,3
	.define	core_config_bcr_cprot_build,0x00000001
	.define	core_config_bcr_agu_build,0x01988c02
	.define	core_config_bcr_agu_build_accordian,1
	.define	core_config_bcr_agu_build_wb_size,4
	.define	core_config_bcr_agu_build_num_modifier,24
	.define	core_config_bcr_agu_build_num_offset,8
	.define	core_config_bcr_agu_build_num_addr,12
	.define	core_config_bcr_agu_build_version,2
	.define	core_config_bcr_dmac_build,0x00160f02
	.define	core_config_bcr_dmac_build_int_cfg,2
	.define	core_config_bcr_dmac_build_fifo,3
	.define	core_config_bcr_dmac_build_chan_mem,0
	.define	core_config_bcr_dmac_build_channels,15
	.define	core_config_bcr_dmac_build_version,2
	.define	core_config_bcr_subsys_build,0x00101083
	.define	core_config_bcr_subsys_build_version_major,0
	.define	core_config_bcr_subsys_build_version_minor,2
	.define	core_config_bcr_subsys_build_version_build,8
	.define	core_config_bcr_subsys_build_type,3
	.define	core_config_bcr_core_config,0x00000101
	.define	core_config_bcr_core_config_turbo_boost,1
	.define	core_config_bcr_core_config_version,1
	.define	core_config_bcr_irq_build,0x116b9e01
	.define	core_config_bcr_irq_build_raz,0
	.define	core_config_bcr_irq_build_nmi,0
	.define	core_config_bcr_irq_build_f,1
	.define	core_config_bcr_irq_build_p,1
	.define	core_config_bcr_irq_build_exts,107
	.define	core_config_bcr_irq_build_irqs,158
	.define	core_config_bcr_irq_build_version,1
	.define	core_config_bcr_pdm_dvfs_build,0x00000102
	.define	core_config_bcr_pdm_dvfs_build_dvfs,0
	.define	core_config_bcr_pdm_dvfs_build_pdm,1
	.define	core_config_bcr_pdm_dvfs_build_version,2
	.define	core_config_bcr_ifqueue_build,0x00000302
	.define	core_config_bcr_ifqueue_build_bd,3
	.define	core_config_bcr_ifqueue_build_version,2
	.define	core_config_bcr_smart_build,0x00008003
	.define	core_config_bcr_smart_build_version,3
	.define	core_config_bcr_smart_build_stack_size,32
	.define	core_config_cir_aux_iccm,0x01000000
	.define	core_config_cir_xccm_base,0x90000000
	.define	core_config_cir_yccm_base,0xa0000000
	.define	core_config_cir_subsys_dsp_0_build,0x00000000
	.define	core_config_cir_subsys_io_0_build,0x17100030
	.define	core_config_cir_subsys_io_1_build,0x00000000
	.define	core_config_cir_subsys_io_2_build,0x00000100
	.define	core_config_cir_subsys_uaux_offset,0x00100000
	.define	core_config_cir_subsys_apex_offset,0x80000000
	.define	core_config_family,4
	.define	core_config_core_version,4
	.define	core_config_family_name,"arcv2em"
	.define	core_config_rgf_num_banks,1
	.define	core_config_rgf_num_wr_ports,2
	.define	core_config_endian,"little"
	.define	core_config_endian_little,1
	.define	core_config_endian_big,0
	.define	core_config_lpc_size,32
	.define	core_config_pc_size,32
	.define	core_config_addr_size,32
	.define	core_config_unaligned,1
	.define	core_config_code_density,1
	.define	core_config_div_rem,"radix2"
	.define	core_config_div_rem_radix2,1
	.define	core_config_turbo_boost,1
	.define	core_config_swap,1
	.define	core_config_bitscan,1
	.define	core_config_mpy_option,"mpyd"
	.define	core_config_mpy_option_num,8
	.define	core_config_shift_assist,1
	.define	core_config_barrel_shifter,1
	.define	core_config_dsp,1
	.define	core_config_dsp2,1
	.define	core_config_dsp_complex,1
	.define	core_config_dsp_divsqrt,"radix2"
	.define	core_config_dsp_divsqrt_radix2,1
	.define	core_config_dsp_itu,1
	.define	core_config_dsp_accshift,"full"
	.define	core_config_dsp_accshift_full,1
	.define	core_config_agu_large,1
	.define	core_config_agu_wb_depth,4
	.define	core_config_agu_accord,1
	.define	core_config_xy,1
	.define	core_config_xy_config,"dccm_x_y"
	.define	core_config_xy_config_dccm_x_y,1
	.define	core_config_xy_size,32768
	.define	core_config_xy_size_KM,"32K"
	.define	core_config_xy_x_base,0x90000000
	.define	core_config_xy_y_base,0xa0000000
	.define	core_config_fpus_div,1
	.define	core_config_fpu_mac,1
	.define	core_config_fpus_mpy_slow,1
	.define	core_config_fpus_div_slow,1
	.define	core_config_fpu_pipe_impl,1
	.define	core_config_timer0,1
	.define	core_config_timer0_level,1
	.define	core_config_timer0_vector,16
	.define	core_config_timer1,1
	.define	core_config_timer1_level,1
	.define	core_config_timer1_vector,17
	.define	core_config_rtc,1
	.define	core_config_action_points,2
	.define	core_config_ap_feature,1
	.define	core_config_stack_check,1
	.define	core_config_code_protection,1
	.define	core_config_smart_stack_entries,32
	.define	core_config_ifq_present,1
	.define	core_config_ifq_entries,8
	.define	core_config_interrupts_present,1
	.define	core_config_interrupts_number,158
	.define	core_config_interrupts_priorities,2
	.define	core_config_interrupts_externals,107
	.define	core_config_interrupts,158
	.define	core_config_interrupt_priorities,2
	.define	core_config_ext_interrupts,107
	.define	core_config_interrupts_firq,1
	.define	core_config_interrupts_base,0x0
	.define	core_config_dccm_present,1
	.define	core_config_dccm_size,0x80000
	.define	core_config_dccm_base,0x80000000
	.define	core_config_dccm_interleave,1
	.define	core_config_iccm_present,1
	.define	core_config_iccm0_present,1
	.define	core_config_iccm_size,0x10000
	.define	core_config_iccm0_size,0x10000
	.define	core_config_iccm1_present,1
	.define	core_config_iccm1_size,0x80000
	.define	core_config_iccm_base,0x00000000
	.define	core_config_iccm0_base,0x00000000
	.define	core_config_iccm1_base,0x10000000
	.define	core_config_error_prot_ver,4
	.define	core_config_watchdog,1
	.define	core_config_watchdog_size,32
	.define	core_config_dmac,1
	.define	core_config_dmac_channels,16
	.define	core_config_dmac_registers,0
	.define	core_config_dmac_fifo_depth,4
	.define	core_config_dmac_int_config,"multiple_internal"
	.define	core_config_power_domains,1
	.define	core_config_clock_speed,400
.endif ; __core_config_s

]]></string>
  </configuration>
  <configuration name="C_defines" filename="core_config.h">
    <string><![CDATA[
#ifndef __core_config_h
	#define __core_config_h  1
	#define _TOOL_CONFIG_VER 10074
	#define	core_config_cir_identity	0x00000044
	#define	core_config_cir_identity_chipid	0
	#define	core_config_cir_identity_arcnum	0
	#define	core_config_cir_identity_arcver	68
	#define	core_config_cir_identity_family	4
	#define	core_config_cir_identity_corever	4
	#define	core_config_cir_aux_dccm	0x80000000
	#define	core_config_bcr_bcr_ver	0x00000002
	#define	core_config_bcr_bcr_ver_version	2
	#define	core_config_bcr_vecbase_ac_build	0x00000010
	#define	core_config_bcr_vecbase_ac_build_version	4
	#define	core_config_bcr_vecbase_ac_build_vector_config	0
	#define	core_config_bcr_vecbase_ac_build_addr	0
	#define	core_config_bcr_rf_build	0x00000102
	#define	core_config_bcr_rf_build_version	2
	#define	core_config_bcr_rf_build_p	1
	#define	core_config_bcr_rf_build_e	0
	#define	core_config_bcr_rf_build_r	0
	#define	core_config_bcr_rf_build_b	0
	#define	core_config_bcr_rf_build_d	0
	#define	core_config_bcr_dccm_build	0x00010b04
	#define	core_config_bcr_dccm_build_w	0
	#define	core_config_bcr_dccm_build_cycles	0
	#define	core_config_bcr_dccm_build_interleave	1
	#define	core_config_bcr_dccm_build_size1	0
	#define	core_config_bcr_dccm_build_size0	11
	#define	core_config_bcr_dccm_build_version	4
	#define	core_config_bcr_timer_build	0x00110704
	#define	core_config_bcr_timer_build_sp1	0
	#define	core_config_bcr_timer_build_sp0	0
	#define	core_config_bcr_timer_build_p1	1
	#define	core_config_bcr_timer_build_p0	1
	#define	core_config_bcr_timer_build_st1	0
	#define	core_config_bcr_timer_build_st0	0
	#define	core_config_bcr_timer_build_rtc	1
	#define	core_config_bcr_timer_build_rtsc_ver	17
	#define	core_config_bcr_timer_build_rtsc	0
	#define	core_config_bcr_timer_build_t0	1
	#define	core_config_bcr_timer_build_t1	1
	#define	core_config_bcr_timer_build_version	4
	#define	core_config_bcr_ap_build	0x00000005
	#define	core_config_bcr_ap_build_version	5
	#define	core_config_bcr_ap_build_type	0
	#define	core_config_bcr_iccm_build	0x0000b804
	#define	core_config_bcr_iccm_build_w0	0
	#define	core_config_bcr_iccm_build_iccm1_size1	0
	#define	core_config_bcr_iccm_build_iccm0_size1	0
	#define	core_config_bcr_iccm_build_iccm1_size0	11
	#define	core_config_bcr_iccm_build_iccm0_size0	8
	#define	core_config_bcr_iccm_build_version	4
	#define	core_config_bcr_xy_build	0x00003220
	#define	core_config_bcr_xy_build_memsize	3
	#define	core_config_bcr_xy_build_interleaved	0
	#define	core_config_bcr_xy_build_config	2
	#define	core_config_bcr_xy_build_version	32
	#define	core_config_bcr_dsp_build	0x00003521
	#define	core_config_bcr_dsp_build_wide	0
	#define	core_config_bcr_dsp_build_itu_pa	1
	#define	core_config_bcr_dsp_build_acc_shift	2
	#define	core_config_bcr_dsp_build_comp	1
	#define	core_config_bcr_dsp_build_divsqrt	1
	#define	core_config_bcr_dsp_build_version	33
	#define	core_config_bcr_multiply_build	0x00022206
	#define	core_config_bcr_multiply_build_version16x16	2
	#define	core_config_bcr_multiply_build_dsp	2
	#define	core_config_bcr_multiply_build_cyc	0
	#define	core_config_bcr_multiply_build_type	2
	#define	core_config_bcr_multiply_build_version32x32	6
	#define	core_config_bcr_swap_build	0x00000003
	#define	core_config_bcr_swap_build_version	3
	#define	core_config_bcr_norm_build	0x00000003
	#define	core_config_bcr_norm_build_version	3
	#define	core_config_bcr_minmax_build	0x00000002
	#define	core_config_bcr_minmax_build_version	2
	#define	core_config_bcr_barrel_build	0x00000303
	#define	core_config_bcr_barrel_build_version	3
	#define	core_config_bcr_barrel_build_shift_option	3
	#define	core_config_bcr_isa_config	0x12447402
	#define	core_config_bcr_isa_config_res1	0
	#define	core_config_bcr_isa_config_d	1
	#define	core_config_bcr_isa_config_res2	0
	#define	core_config_bcr_isa_config_f	0
	#define	core_config_bcr_isa_config_c	2
	#define	core_config_bcr_isa_config_l	0
	#define	core_config_bcr_isa_config_n	1
	#define	core_config_bcr_isa_config_a	0
	#define	core_config_bcr_isa_config_b	0
	#define	core_config_bcr_isa_config_addr_size	4
	#define	core_config_bcr_isa_config_lpc_size	7
	#define	core_config_bcr_isa_config_pc_size	4
	#define	core_config_bcr_isa_config_version	2
	#define	core_config_bcr_dmp_pp_build	0xf0000012
	#define	core_config_bcr_stack_region_build	0x00000002
	#define	core_config_bcr_erp_build	0x40000004
	#define	core_config_bcr_erp_build_l	0
	#define	core_config_bcr_erp_build_wd	2
	#define	core_config_bcr_erp_build_c	0
	#define	core_config_bcr_erp_build_mmu	0
	#define	core_config_bcr_erp_build_rf	0
	#define	core_config_bcr_erp_build_pc	0
	#define	core_config_bcr_erp_build_ic	0
	#define	core_config_bcr_erp_build_dc	0
	#define	core_config_bcr_erp_build_ip	0
	#define	core_config_bcr_erp_build_dp	0
	#define	core_config_bcr_erp_build_version	4
	#define	core_config_bcr_fpu_build	0x00004f03
	#define	core_config_bcr_fpu_build_da	0
	#define	core_config_bcr_fpu_build_hp	0
	#define	core_config_bcr_fpu_build_dd	0
	#define	core_config_bcr_fpu_build_dc	0
	#define	core_config_bcr_fpu_build_df	0
	#define	core_config_bcr_fpu_build_dp	0
	#define	core_config_bcr_fpu_build_fd_v1	2
	#define	core_config_bcr_fpu_build_pi	1
	#define	core_config_bcr_fpu_build_fd	0
	#define	core_config_bcr_fpu_build_fm	0
	#define	core_config_bcr_fpu_build_sd	1
	#define	core_config_bcr_fpu_build_sc	1
	#define	core_config_bcr_fpu_build_sf	1
	#define	core_config_bcr_fpu_build_sp	1
	#define	core_config_bcr_fpu_build_version	3
	#define	core_config_bcr_cprot_build	0x00000001
	#define	core_config_bcr_agu_build	0x01988c02
	#define	core_config_bcr_agu_build_accordian	1
	#define	core_config_bcr_agu_build_wb_size	4
	#define	core_config_bcr_agu_build_num_modifier	24
	#define	core_config_bcr_agu_build_num_offset	8
	#define	core_config_bcr_agu_build_num_addr	12
	#define	core_config_bcr_agu_build_version	2
	#define	core_config_bcr_dmac_build	0x00160f02
	#define	core_config_bcr_dmac_build_int_cfg	2
	#define	core_config_bcr_dmac_build_fifo	3
	#define	core_config_bcr_dmac_build_chan_mem	0
	#define	core_config_bcr_dmac_build_channels	15
	#define	core_config_bcr_dmac_build_version	2
	#define	core_config_bcr_subsys_build	0x00101083
	#define	core_config_bcr_subsys_build_version_major	0
	#define	core_config_bcr_subsys_build_version_minor	2
	#define	core_config_bcr_subsys_build_version_build	8
	#define	core_config_bcr_subsys_build_type	3
	#define	core_config_bcr_core_config	0x00000101
	#define	core_config_bcr_core_config_turbo_boost	1
	#define	core_config_bcr_core_config_version	1
	#define	core_config_bcr_irq_build	0x116b9e01
	#define	core_config_bcr_irq_build_raz	0
	#define	core_config_bcr_irq_build_nmi	0
	#define	core_config_bcr_irq_build_f	1
	#define	core_config_bcr_irq_build_p	1
	#define	core_config_bcr_irq_build_exts	107
	#define	core_config_bcr_irq_build_irqs	158
	#define	core_config_bcr_irq_build_version	1
	#define	core_config_bcr_pdm_dvfs_build	0x00000102
	#define	core_config_bcr_pdm_dvfs_build_dvfs	0
	#define	core_config_bcr_pdm_dvfs_build_pdm	1
	#define	core_config_bcr_pdm_dvfs_build_version	2
	#define	core_config_bcr_ifqueue_build	0x00000302
	#define	core_config_bcr_ifqueue_build_bd	3
	#define	core_config_bcr_ifqueue_build_version	2
	#define	core_config_bcr_smart_build	0x00008003
	#define	core_config_bcr_smart_build_version	3
	#define	core_config_bcr_smart_build_stack_size	32
	#define	core_config_cir_aux_iccm	0x01000000
	#define	core_config_cir_xccm_base	0x90000000
	#define	core_config_cir_yccm_base	0xa0000000
	#define	core_config_cir_subsys_dsp_0_build	0x00000000
	#define	core_config_cir_subsys_io_0_build	0x17100030
	#define	core_config_cir_subsys_io_1_build	0x00000000
	#define	core_config_cir_subsys_io_2_build	0x00000100
	#define	core_config_cir_subsys_uaux_offset	0x00100000
	#define	core_config_cir_subsys_apex_offset	0x80000000
	#define	core_config_family	4
	#define	core_config_core_version	4
	#define	core_config_family_name	"arcv2em"
	#define	core_config_rgf_num_banks	1
	#define	core_config_rgf_num_wr_ports	2
	#define	core_config_endian	"little"
	#define	core_config_endian_little	1
	#define	core_config_endian_big	0
	#define	core_config_lpc_size	32
	#define	core_config_pc_size	32
	#define	core_config_addr_size	32
	#define	core_config_unaligned	1
	#define	core_config_code_density	1
	#define	core_config_div_rem	"radix2"
	#define	core_config_div_rem_radix2	1
	#define	core_config_turbo_boost	1
	#define	core_config_swap	1
	#define	core_config_bitscan	1
	#define	core_config_mpy_option	"mpyd"
	#define	core_config_mpy_option_num	8
	#define	core_config_shift_assist	1
	#define	core_config_barrel_shifter	1
	#define	core_config_dsp	1
	#define	core_config_dsp2	1
	#define	core_config_dsp_complex	1
	#define	core_config_dsp_divsqrt	"radix2"
	#define	core_config_dsp_divsqrt_radix2	1
	#define	core_config_dsp_itu	1
	#define	core_config_dsp_accshift	"full"
	#define	core_config_dsp_accshift_full	1
	#define	core_config_agu_large	1
	#define	core_config_agu_wb_depth	4
	#define	core_config_agu_accord	1
	#define	core_config_xy	1
	#define	core_config_xy_config	"dccm_x_y"
	#define	core_config_xy_config_dccm_x_y	1
	#define	core_config_xy_size	32768
	#define	core_config_xy_size_KM	"32K"
	#define	core_config_xy_x_base	0x90000000
	#define	core_config_xy_y_base	0xa0000000
	#define	core_config_fpus_div	1
	#define	core_config_fpu_mac	1
	#define	core_config_fpus_mpy_slow	1
	#define	core_config_fpus_div_slow	1
	#define	core_config_fpu_pipe_impl	1
	#define	core_config_timer0	1
	#define	core_config_timer0_level	1
	#define	core_config_timer0_vector	16
	#define	core_config_timer1	1
	#define	core_config_timer1_level	1
	#define	core_config_timer1_vector	17
	#define	core_config_rtc	1
	#define	core_config_action_points	2
	#define	core_config_ap_feature	1
	#define	core_config_stack_check	1
	#define	core_config_code_protection	1
	#define	core_config_smart_stack_entries	32
	#define	core_config_ifq_present	1
	#define	core_config_ifq_entries	8
	#define	core_config_interrupts_present	1
	#define	core_config_interrupts_number	158
	#define	core_config_interrupts_priorities	2
	#define	core_config_interrupts_externals	107
	#define	core_config_interrupts	158
	#define	core_config_interrupt_priorities	2
	#define	core_config_ext_interrupts	107
	#define	core_config_interrupts_firq	1
	#define	core_config_interrupts_base	0x0
	#define	core_config_dccm_present	1
	#define	core_config_dccm_size	0x80000
	#define	core_config_dccm_base	0x80000000
	#define	core_config_dccm_interleave	1
	#define	core_config_iccm_present	1
	#define	core_config_iccm0_present	1
	#define	core_config_iccm_size	0x10000
	#define	core_config_iccm0_size	0x10000
	#define	core_config_iccm1_present	1
	#define	core_config_iccm1_size	0x80000
	#define	core_config_iccm_base	0x00000000
	#define	core_config_iccm0_base	0x00000000
	#define	core_config_iccm1_base	0x10000000
	#define	core_config_error_prot_ver	4
	#define	core_config_watchdog	1
	#define	core_config_watchdog_size	32
	#define	core_config_dmac	1
	#define	core_config_dmac_channels	16
	#define	core_config_dmac_registers	0
	#define	core_config_dmac_fifo_depth	4
	#define	core_config_dmac_int_config	"multiple_internal"
	#define	core_config_power_domains	1
	#define	core_config_clock_speed	400
#endif /* __core_config_h */

]]></string>
  </configuration>
  <configuration name="core" filename="core.props">
    <string><![CDATA[
	core_config.cir.identity=0x00000044
	core_config.cir.identity.chipid=0
	core_config.cir.identity.arcnum=0
	core_config.cir.identity.arcver=68
	core_config.cir.identity.family=4
	core_config.cir.identity.corever=4
	core_config.cir.aux_dccm=0x80000000
	core_config.bcr.bcr_ver=0x00000002
	core_config.bcr.bcr_ver.version=2
	core_config.bcr.vecbase_ac_build=0x00000010
	core_config.bcr.vecbase_ac_build.version=4
	core_config.bcr.vecbase_ac_build.vector_config=0
	core_config.bcr.vecbase_ac_build.addr=0
	core_config.bcr.rf_build=0x00000102
	core_config.bcr.rf_build.version=2
	core_config.bcr.rf_build.p=1
	core_config.bcr.rf_build.e=0
	core_config.bcr.rf_build.r=0
	core_config.bcr.rf_build.b=0
	core_config.bcr.rf_build.d=0
	core_config.bcr.dccm_build=0x00010b04
	core_config.bcr.dccm_build.w=0
	core_config.bcr.dccm_build.cycles=0
	core_config.bcr.dccm_build.interleave=1
	core_config.bcr.dccm_build.size1=0
	core_config.bcr.dccm_build.size0=11
	core_config.bcr.dccm_build.version=4
	core_config.bcr.timer_build=0x00110704
	core_config.bcr.timer_build.sp1=0
	core_config.bcr.timer_build.sp0=0
	core_config.bcr.timer_build.p1=1
	core_config.bcr.timer_build.p0=1
	core_config.bcr.timer_build.st1=0
	core_config.bcr.timer_build.st0=0
	core_config.bcr.timer_build.rtc=1
	core_config.bcr.timer_build.rtsc_ver=17
	core_config.bcr.timer_build.rtsc=0
	core_config.bcr.timer_build.t0=1
	core_config.bcr.timer_build.t1=1
	core_config.bcr.timer_build.version=4
	core_config.bcr.ap_build=0x00000005
	core_config.bcr.ap_build.version=5
	core_config.bcr.ap_build.type=0
	core_config.bcr.iccm_build=0x0000b804
	core_config.bcr.iccm_build.w0=0
	core_config.bcr.iccm_build.iccm1_size1=0
	core_config.bcr.iccm_build.iccm0_size1=0
	core_config.bcr.iccm_build.iccm1_size0=11
	core_config.bcr.iccm_build.iccm0_size0=8
	core_config.bcr.iccm_build.version=4
	core_config.bcr.xy_build=0x00003220
	core_config.bcr.xy_build.memsize=3
	core_config.bcr.xy_build.interleaved=0
	core_config.bcr.xy_build.config=2
	core_config.bcr.xy_build.version=32
	core_config.bcr.dsp_build=0x00003521
	core_config.bcr.dsp_build.wide=0
	core_config.bcr.dsp_build.itu_pa=1
	core_config.bcr.dsp_build.acc_shift=2
	core_config.bcr.dsp_build.comp=1
	core_config.bcr.dsp_build.divsqrt=1
	core_config.bcr.dsp_build.version=33
	core_config.bcr.multiply_build=0x00022206
	core_config.bcr.multiply_build.version16x16=2
	core_config.bcr.multiply_build.dsp=2
	core_config.bcr.multiply_build.cyc=0
	core_config.bcr.multiply_build.type=2
	core_config.bcr.multiply_build.version32x32=6
	core_config.bcr.swap_build=0x00000003
	core_config.bcr.swap_build.version=3
	core_config.bcr.norm_build=0x00000003
	core_config.bcr.norm_build.version=3
	core_config.bcr.minmax_build=0x00000002
	core_config.bcr.minmax_build.version=2
	core_config.bcr.barrel_build=0x00000303
	core_config.bcr.barrel_build.version=3
	core_config.bcr.barrel_build.shift_option=3
	core_config.bcr.isa_config=0x12447402
	core_config.bcr.isa_config.res1=0
	core_config.bcr.isa_config.d=1
	core_config.bcr.isa_config.res2=0
	core_config.bcr.isa_config.f=0
	core_config.bcr.isa_config.c=2
	core_config.bcr.isa_config.l=0
	core_config.bcr.isa_config.n=1
	core_config.bcr.isa_config.a=0
	core_config.bcr.isa_config.b=0
	core_config.bcr.isa_config.addr_size=4
	core_config.bcr.isa_config.lpc_size=7
	core_config.bcr.isa_config.pc_size=4
	core_config.bcr.isa_config.version=2
	core_config.bcr.dmp_pp_build=0xf0000012
	core_config.bcr.stack_region_build=0x00000002
	core_config.bcr.erp_build=0x40000004
	core_config.bcr.erp_build.l=0
	core_config.bcr.erp_build.wd=2
	core_config.bcr.erp_build.c=0
	core_config.bcr.erp_build.mmu=0
	core_config.bcr.erp_build.rf=0
	core_config.bcr.erp_build.pc=0
	core_config.bcr.erp_build.ic=0
	core_config.bcr.erp_build.dc=0
	core_config.bcr.erp_build.ip=0
	core_config.bcr.erp_build.dp=0
	core_config.bcr.erp_build.version=4
	core_config.bcr.fpu_build=0x00004f03
	core_config.bcr.fpu_build.da=0
	core_config.bcr.fpu_build.hp=0
	core_config.bcr.fpu_build.dd=0
	core_config.bcr.fpu_build.dc=0
	core_config.bcr.fpu_build.df=0
	core_config.bcr.fpu_build.dp=0
	core_config.bcr.fpu_build.fd_v1=2
	core_config.bcr.fpu_build.pi=1
	core_config.bcr.fpu_build.fd=0
	core_config.bcr.fpu_build.fm=0
	core_config.bcr.fpu_build.sd=1
	core_config.bcr.fpu_build.sc=1
	core_config.bcr.fpu_build.sf=1
	core_config.bcr.fpu_build.sp=1
	core_config.bcr.fpu_build.version=3
	core_config.bcr.cprot_build=0x00000001
	core_config.bcr.agu_build=0x01988c02
	core_config.bcr.agu_build.accordian=1
	core_config.bcr.agu_build.wb_size=4
	core_config.bcr.agu_build.num_modifier=24
	core_config.bcr.agu_build.num_offset=8
	core_config.bcr.agu_build.num_addr=12
	core_config.bcr.agu_build.version=2
	core_config.bcr.dmac_build=0x00160f02
	core_config.bcr.dmac_build.int_cfg=2
	core_config.bcr.dmac_build.fifo=3
	core_config.bcr.dmac_build.chan_mem=0
	core_config.bcr.dmac_build.channels=15
	core_config.bcr.dmac_build.version=2
	core_config.bcr.subsys_build=0x00101083
	core_config.bcr.subsys_build.version_major=0
	core_config.bcr.subsys_build.version_minor=2
	core_config.bcr.subsys_build.version_build=8
	core_config.bcr.subsys_build.type=3
	core_config.bcr.core_config=0x00000101
	core_config.bcr.core_config.turbo_boost=1
	core_config.bcr.core_config.version=1
	core_config.bcr.irq_build=0x116b9e01
	core_config.bcr.irq_build.raz=0
	core_config.bcr.irq_build.nmi=0
	core_config.bcr.irq_build.f=1
	core_config.bcr.irq_build.p=1
	core_config.bcr.irq_build.exts=107
	core_config.bcr.irq_build.irqs=158
	core_config.bcr.irq_build.version=1
	core_config.bcr.pdm_dvfs_build=0x00000102
	core_config.bcr.pdm_dvfs_build.dvfs=0
	core_config.bcr.pdm_dvfs_build.pdm=1
	core_config.bcr.pdm_dvfs_build.version=2
	core_config.bcr.ifqueue_build=0x00000302
	core_config.bcr.ifqueue_build.bd=3
	core_config.bcr.ifqueue_build.version=2
	core_config.bcr.smart_build=0x00008003
	core_config.bcr.smart_build.version=3
	core_config.bcr.smart_build.stack_size=32
	core_config.cir.aux_iccm=0x01000000
	core_config.cir.xccm_base=0x90000000
	core_config.cir.yccm_base=0xa0000000
	core_config.cir.subsys_dsp_0_build=0x00000000
	core_config.cir.subsys_io_0_build=0x17100030
	core_config.cir.subsys_io_1_build=0x00000000
	core_config.cir.subsys_io_2_build=0x00000100
	core_config.cir.subsys_uaux_offset=0x00100000
	core_config.cir.subsys_apex_offset=0x80000000
	core_config.family=4
	core_config.core_version=4
	core_config.family_name=arcv2em
	core_config.rgf_num_banks=1
	core_config.rgf_num_wr_ports=2
	core_config.endian=little
	core_config.endian_little=1
	core_config.endian_big=0
	core_config.lpc_size=32
	core_config.pc_size=32
	core_config.addr_size=32
	core_config.unaligned=1
	core_config.code_density=1
	core_config.div_rem=radix2
	core_config.div_rem_radix2=1
	core_config.turbo_boost=1
	core_config.swap=1
	core_config.bitscan=1
	core_config.mpy_option=mpyd
	core_config.mpy_option_num=8
	core_config.shift_assist=1
	core_config.barrel_shifter=1
	core_config.dsp=1
	core_config.dsp2=1
	core_config.dsp_complex=1
	core_config.dsp_divsqrt=radix2
	core_config.dsp_divsqrt_radix2=1
	core_config.dsp_itu=1
	core_config.dsp_accshift=full
	core_config.dsp_accshift_full=1
	core_config.agu_large=1
	core_config.agu_wb_depth=4
	core_config.agu_accord=1
	core_config.xy=1
	core_config.xy_config=dccm_x_y
	core_config.xy_config_dccm_x_y=1
	core_config.xy_size=32K
	core_config.xy_x_base=0x90000000
	core_config.xy_y_base=0xa0000000
	core_config.fpus_div=1
	core_config.fpu_mac=1
	core_config.fpus_mpy_slow=1
	core_config.fpus_div_slow=1
	core_config.fpu_pipe_impl=1
	core_config.timer0=1
	core_config.timer0_level=1
	core_config.timer0.vector=16
	core_config.timer1=1
	core_config.timer1_level=1
	core_config.timer1.vector=17
	core_config.rtc=1
	core_config.action_points=2
	core_config.ap_feature=1
	core_config.stack_check=1
	core_config.code_protection=1
	core_config.smart_stack_entries=32
	core_config.ifq.present=1
	core_config.ifq_entries=8
	core_config.interrupts.present=1
	core_config.interrupts.number=158
	core_config.interrupts.priorities=2
	core_config.interrupts.externals=107
	core_config.interrupts=158
	core_config.interrupt_priorities=2
	core_config.ext_interrupts=107
	core_config.interrupts.firq=1
	core_config.interrupts.base=0x0
	core_config.dccm.present=1
	core_config.dccm_size=0x80000
	core_config.dccm_base=0x80000000
	core_config.dccm_interleave=1
	core_config.iccm.present=1
	core_config.iccm0.present=1
	core_config.iccm.size=0x10000
	core_config.iccm0.size=0x10000
	core_config.iccm1.present=1
	core_config.iccm1.size=0x80000
	core_config.iccm.base=0x00000000
	core_config.iccm0.base=0x00000000
	core_config.iccm1.base=0x10000000
	core_config.error_prot_ver=4
	core_config.watchdog=1
	core_config.watchdog_size=32
	core_config.dmac=1
	core_config.dmac_channels=16
	core_config.dmac_registers=0
	core_config.dmac_fifo_depth=4
	core_config.dmac_int_config=multiple_internal
	core_config.power_domains=1
	core_config.clock_speed=400
]]></string>
  </configuration>
  <configuration name="gcc_compiler" filename="gcc.arg">
    <string><![CDATA[
	-mcpu=em4_fpus
	-mlittle-endian
	-mcode-density
	-mdiv-rem
	-mswap
	-mnorm
	-mmpy-option=6
	-mbarrel-shifter
	-mfpu=fpus_all
]]></string>
  </configuration>
  <configuration name="linker_command_file" filename="link_cmd.txt">
    <string><![CDATA[
# SYSTEM memory regions indicate where external memory might be located.
#   The TCF has no specific knowledge of whether SYSTEM regions contain 
#   external memory or not.
# CCMWRAP memory regions indicate unusable portions of the address space
#   due to CCM memory wrapping into upper addresses beyond its size

MEMORY {
    ICCM0   : ORIGIN = 0x00000000, LENGTH = 0x00010000
#   CCMWRAP0: ORIGIN = 0x00010000, LENGTH = 0x0fff0000
    ICCM1   : ORIGIN = 0x10000000, LENGTH = 0x00080000
#   CCMWRAP1: ORIGIN = 0x10080000, LENGTH = 0x0ff80000
#   SYSTEM0 : ORIGIN = 0x20000000, LENGTH = 0x60000000
    DCCM    : ORIGIN = 0x80000000, LENGTH = 0x00080000
#   CCMWRAP2: ORIGIN = 0x80080000, LENGTH = 0x0ff80000
    XCCM    : ORIGIN = 0x90000000, LENGTH = 0x00008000
#   CCMWRAP3: ORIGIN = 0x90008000, LENGTH = 0x0fff8000
    YCCM    : ORIGIN = 0xa0000000, LENGTH = 0x00008000
#   CCMWRAP4: ORIGIN = 0xa0008000, LENGTH = 0x0fff8000
#   SYSTEM1 : ORIGIN = 0xb0000000, LENGTH = 0x50000000
    }
SECTIONS {
    GROUP BLOCK(4): {
        .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:1124): {}
	.text? : { *('.text$crt*') }
        * (TEXT): {}
    	* (LIT): {}
	} > ICCM0

    GROUP BLOCK(4): {
	/* _SDA_BASE_ computed implicitly */
        .sdata?: {}
        .sbss?: {}
        * (DATA): {}
        * (BSS): {}
       .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {}
       .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {}
	} > DCCM
    GROUP BLOCK(4): {
        .Xdata? : {}
        } > XCCM
    GROUP BLOCK(4): {
        .Ydata? : {}
        } > YCCM
    }

]]></string>
  </configuration>
  <configuration name="gnu_linker_command_file" filename="memory.x">
    <string><![CDATA[
MEMORY {
    ICCM0    : ORIGIN = 0x00000000, LENGTH = 0x00010000
    CCMWRAP0 : ORIGIN = 0x00010000, LENGTH = 0x0fff0000
    ICCM1    : ORIGIN = 0x10000000, LENGTH = 0x00080000
    CCMWRAP1 : ORIGIN = 0x10080000, LENGTH = 0x0ff80000
    SYSTEM0  : ORIGIN = 0x20000000, LENGTH = 0x60000000
    DCCM     : ORIGIN = 0x80000000, LENGTH = 0x00080000
    CCMWRAP2 : ORIGIN = 0x80080000, LENGTH = 0x0ff80000
    XCCM     : ORIGIN = 0x90000000, LENGTH = 0x00008000
    CCMWRAP3 : ORIGIN = 0x90008000, LENGTH = 0x0fff8000
    YCCM     : ORIGIN = 0xa0000000, LENGTH = 0x00008000
    CCMWRAP4 : ORIGIN = 0xa0008000, LENGTH = 0x0fff8000
    SYSTEM1  : ORIGIN = 0xb0000000, LENGTH = 0x50000000
    }
REGION_ALIAS("startup", ICCM0)
REGION_ALIAS("text", ICCM0)
REGION_ALIAS("data", DCCM)
REGION_ALIAS("sdata", DCCM)
PROVIDE (__stack_top = (0x8007ffff & -4 ));
PROVIDE (__end_heap =  (0x8007ffff ));
]]></string>
  </configuration>
  <configuration name="apex_header" filename="apexextensions.h">
    <string><![CDATA[

/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
 *
 * Description: Header file declaring the compiler extensions for apex components 
 */

#ifndef _apexextensions_H_
#define _apexextensions_H_

#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT	1

// User extension aux register io_i2c_mst0_clken
#define AR_IO_I2C_MST0_CLKEN 0x800120c0
#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken")

// User extension aux register io_i2c_mst0_con
#define AR_IO_I2C_MST0_CON 0x80012000
#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con")

// User extension aux register io_i2c_mst0_tar
#define AR_IO_I2C_MST0_TAR 0x80012004
#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar")

// User extension aux register io_i2c_mst0_data_cmd
#define AR_IO_I2C_MST0_DATA_CMD 0x80012010
#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd")

// User extension aux register io_i2c_mst0_ss_scl_hcnt
#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014
#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt")

// User extension aux register io_i2c_mst0_ss_scl_lcnt
#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018
#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt")

// User extension aux register io_i2c_mst0_fs_scl_hcnt
#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c
#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt")

// User extension aux register io_i2c_mst0_fs_scl_lcnt
#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020
#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt")

// User extension aux register io_i2c_mst0_intr_stat
#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c
#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat")

// User extension aux register io_i2c_mst0_intr_mask
#define AR_IO_I2C_MST0_INTR_MASK 0x80012030
#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask")

// User extension aux register io_i2c_mst0_raw_intr_stat
#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034
#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat")

// User extension aux register io_i2c_mst0_rx_tl
#define AR_IO_I2C_MST0_RX_TL 0x80012038
#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl")

// User extension aux register io_i2c_mst0_tx_tl
#define AR_IO_I2C_MST0_TX_TL 0x8001203c
#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl")

// User extension aux register io_i2c_mst0_clr_intr
#define AR_IO_I2C_MST0_CLR_INTR 0x80012040
#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr")

// User extension aux register io_i2c_mst0_clr_rx_under
#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044
#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under")

// User extension aux register io_i2c_mst0_clr_rx_over
#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048
#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over")

// User extension aux register io_i2c_mst0_clr_tx_over
#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c
#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over")

// User extension aux register io_i2c_mst0_clr_tx_abrt
#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054
#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt")

// User extension aux register io_i2c_mst0_clr_activity
#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c
#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity")

// User extension aux register io_i2c_mst0_clr_stop_det
#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060
#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det")

// User extension aux register io_i2c_mst0_clr_start_det
#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064
#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det")

// User extension aux register io_i2c_mst0_enable
#define AR_IO_I2C_MST0_ENABLE 0x8001206c
#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable")

// User extension aux register io_i2c_mst0_status
#define AR_IO_I2C_MST0_STATUS 0x80012070
#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status")

// User extension aux register io_i2c_mst0_txflr
#define AR_IO_I2C_MST0_TXFLR 0x80012074
#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr")

// User extension aux register io_i2c_mst0_rxflr
#define AR_IO_I2C_MST0_RXFLR 0x80012078
#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr")

// User extension aux register io_i2c_mst0_sda_hold
#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c
#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold")

// User extension aux register io_i2c_mst0_tx_abrt_source
#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080
#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source")

// User extension aux register io_i2c_mst0_enable_status
#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c
#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status")

// User extension aux register io_i2c_mst0_fs_spklen
#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0
#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT	1

// User extension aux register io_i2c_mst1_clken
#define AR_IO_I2C_MST1_CLKEN 0x800121c0
#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken")

// User extension aux register io_i2c_mst1_con
#define AR_IO_I2C_MST1_CON 0x80012100
#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con")

// User extension aux register io_i2c_mst1_tar
#define AR_IO_I2C_MST1_TAR 0x80012104
#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar")

// User extension aux register io_i2c_mst1_data_cmd
#define AR_IO_I2C_MST1_DATA_CMD 0x80012110
#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd")

// User extension aux register io_i2c_mst1_ss_scl_hcnt
#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114
#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt")

// User extension aux register io_i2c_mst1_ss_scl_lcnt
#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118
#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt")

// User extension aux register io_i2c_mst1_fs_scl_hcnt
#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c
#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt")

// User extension aux register io_i2c_mst1_fs_scl_lcnt
#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120
#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt")

// User extension aux register io_i2c_mst1_intr_stat
#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c
#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat")

// User extension aux register io_i2c_mst1_intr_mask
#define AR_IO_I2C_MST1_INTR_MASK 0x80012130
#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask")

// User extension aux register io_i2c_mst1_raw_intr_stat
#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134
#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat")

// User extension aux register io_i2c_mst1_rx_tl
#define AR_IO_I2C_MST1_RX_TL 0x80012138
#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl")

// User extension aux register io_i2c_mst1_tx_tl
#define AR_IO_I2C_MST1_TX_TL 0x8001213c
#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl")

// User extension aux register io_i2c_mst1_clr_intr
#define AR_IO_I2C_MST1_CLR_INTR 0x80012140
#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr")

// User extension aux register io_i2c_mst1_clr_rx_under
#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144
#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under")

// User extension aux register io_i2c_mst1_clr_rx_over
#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148
#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over")

// User extension aux register io_i2c_mst1_clr_tx_over
#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c
#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over")

// User extension aux register io_i2c_mst1_clr_tx_abrt
#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154
#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt")

// User extension aux register io_i2c_mst1_clr_activity
#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c
#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity")

// User extension aux register io_i2c_mst1_clr_stop_det
#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160
#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det")

// User extension aux register io_i2c_mst1_clr_start_det
#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164
#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det")

// User extension aux register io_i2c_mst1_enable
#define AR_IO_I2C_MST1_ENABLE 0x8001216c
#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable")

// User extension aux register io_i2c_mst1_status
#define AR_IO_I2C_MST1_STATUS 0x80012170
#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status")

// User extension aux register io_i2c_mst1_txflr
#define AR_IO_I2C_MST1_TXFLR 0x80012174
#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr")

// User extension aux register io_i2c_mst1_rxflr
#define AR_IO_I2C_MST1_RXFLR 0x80012178
#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr")

// User extension aux register io_i2c_mst1_sda_hold
#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c
#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold")

// User extension aux register io_i2c_mst1_tx_abrt_source
#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180
#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source")

// User extension aux register io_i2c_mst1_enable_status
#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c
#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status")

// User extension aux register io_i2c_mst1_fs_spklen
#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0
#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT	1

// User extension aux register io_i2c_mst2_clken
#define AR_IO_I2C_MST2_CLKEN 0x800122c0
#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken")

// User extension aux register io_i2c_mst2_con
#define AR_IO_I2C_MST2_CON 0x80012200
#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con")

// User extension aux register io_i2c_mst2_tar
#define AR_IO_I2C_MST2_TAR 0x80012204
#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar")

// User extension aux register io_i2c_mst2_data_cmd
#define AR_IO_I2C_MST2_DATA_CMD 0x80012210
#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd")

// User extension aux register io_i2c_mst2_ss_scl_hcnt
#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214
#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt")

// User extension aux register io_i2c_mst2_ss_scl_lcnt
#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218
#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt")

// User extension aux register io_i2c_mst2_fs_scl_hcnt
#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c
#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt")

// User extension aux register io_i2c_mst2_fs_scl_lcnt
#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220
#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt")

// User extension aux register io_i2c_mst2_intr_stat
#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c
#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat")

// User extension aux register io_i2c_mst2_intr_mask
#define AR_IO_I2C_MST2_INTR_MASK 0x80012230
#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask")

// User extension aux register io_i2c_mst2_raw_intr_stat
#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234
#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat")

// User extension aux register io_i2c_mst2_rx_tl
#define AR_IO_I2C_MST2_RX_TL 0x80012238
#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl")

// User extension aux register io_i2c_mst2_tx_tl
#define AR_IO_I2C_MST2_TX_TL 0x8001223c
#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl")

// User extension aux register io_i2c_mst2_clr_intr
#define AR_IO_I2C_MST2_CLR_INTR 0x80012240
#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr")

// User extension aux register io_i2c_mst2_clr_rx_under
#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244
#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under")

// User extension aux register io_i2c_mst2_clr_rx_over
#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248
#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over")

// User extension aux register io_i2c_mst2_clr_tx_over
#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c
#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over")

// User extension aux register io_i2c_mst2_clr_tx_abrt
#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254
#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt")

// User extension aux register io_i2c_mst2_clr_activity
#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c
#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity")

// User extension aux register io_i2c_mst2_clr_stop_det
#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260
#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det")

// User extension aux register io_i2c_mst2_clr_start_det
#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264
#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det")

// User extension aux register io_i2c_mst2_enable
#define AR_IO_I2C_MST2_ENABLE 0x8001226c
#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable")

// User extension aux register io_i2c_mst2_status
#define AR_IO_I2C_MST2_STATUS 0x80012270
#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status")

// User extension aux register io_i2c_mst2_txflr
#define AR_IO_I2C_MST2_TXFLR 0x80012274
#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr")

// User extension aux register io_i2c_mst2_rxflr
#define AR_IO_I2C_MST2_RXFLR 0x80012278
#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr")

// User extension aux register io_i2c_mst2_sda_hold
#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c
#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold")

// User extension aux register io_i2c_mst2_tx_abrt_source
#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280
#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source")

// User extension aux register io_i2c_mst2_enable_status
#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c
#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status")

// User extension aux register io_i2c_mst2_fs_spklen
#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0
#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT	1

// User extension aux register io_i2c_slv0_clken
#define AR_IO_I2C_SLV0_CLKEN 0x800130c0
#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken")

// User extension aux register io_i2c_slv0_con
#define AR_IO_I2C_SLV0_CON 0x80013000
#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con")

// User extension aux register io_i2c_slv0_sar
#define AR_IO_I2C_SLV0_SAR 0x80013008
#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar")

// User extension aux register io_i2c_slv0_data_cmd
#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010
#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd")

// User extension aux register io_i2c_slv0_intr_stat
#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c
#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat")

// User extension aux register io_i2c_slv0_intr_mask
#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030
#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask")

// User extension aux register io_i2c_slv0_raw_intr_stat
#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034
#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat")

// User extension aux register io_i2c_slv0_rx_tl
#define AR_IO_I2C_SLV0_RX_TL 0x80013038
#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl")

// User extension aux register io_i2c_slv0_tx_tl
#define AR_IO_I2C_SLV0_TX_TL 0x8001303c
#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl")

// User extension aux register io_i2c_slv0_clr_intr
#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040
#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr")

// User extension aux register io_i2c_slv0_clr_rx_under
#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044
#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under")

// User extension aux register io_i2c_slv0_clr_rx_over
#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048
#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over")

// User extension aux register io_i2c_slv0_clr_tx_over
#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c
#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over")

// User extension aux register io_i2c_slv0_clr_rd_req
#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050
#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req")

// User extension aux register io_i2c_slv0_clr_tx_abrt
#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054
#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt")

// User extension aux register io_i2c_slv0_clr_rx_done
#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058
#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done")

// User extension aux register io_i2c_slv0_clr_activity
#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c
#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity")

// User extension aux register io_i2c_slv0_clr_stop_det
#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060
#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det")

// User extension aux register io_i2c_slv0_clr_start_det
#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064
#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det")

// User extension aux register io_i2c_slv0_enable
#define AR_IO_I2C_SLV0_ENABLE 0x8001306c
#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable")

// User extension aux register io_i2c_slv0_status
#define AR_IO_I2C_SLV0_STATUS 0x80013070
#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status")

// User extension aux register io_i2c_slv0_txflr
#define AR_IO_I2C_SLV0_TXFLR 0x80013074
#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr")

// User extension aux register io_i2c_slv0_rxflr
#define AR_IO_I2C_SLV0_RXFLR 0x80013078
#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr")

// User extension aux register io_i2c_slv0_sda_hold
#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c
#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold")

// User extension aux register io_i2c_slv0_tx_abrt_source
#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080
#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source")

// User extension aux register io_i2c_slv0_sda_setup
#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094
#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup")

// User extension aux register io_i2c_slv0_enable_status
#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c
#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status")

// User extension aux register io_i2c_slv0_fs_spklen
#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0
#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen")

// User extension aux register io_i2c_slv0_clr_restart_det
#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8
#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT	1

// User extension aux register io_pdm_rx0_pdm_en
#define AR_IO_PDM_RX0_PDM_EN 0x8001b000
#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en")

// User extension aux register io_pdm_rx0_pdm_ren
#define AR_IO_PDM_RX0_PDM_REN 0x8001b004
#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren")

// User extension aux register io_pdm_rx0_cer
#define AR_IO_PDM_RX0_CER 0x8001b00c
#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer")

// User extension aux register io_pdm_rx0_rxffr
#define AR_IO_PDM_RX0_RXFFR 0x8001b014
#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr")

// User extension aux register io_pdm_rx0_rer0
#define AR_IO_PDM_RX0_RER0 0x8001b028
#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0")

// User extension aux register io_pdm_rx0_isr
#define AR_IO_PDM_RX0_ISR 0x8001b038
#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr")

// User extension aux register io_pdm_rx0_imr
#define AR_IO_PDM_RX0_IMR 0x8001b03c
#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr")

// User extension aux register io_pdm_rx0_ror
#define AR_IO_PDM_RX0_ROR 0x8001b040
#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror")

// User extension aux register io_pdm_rx0_rfcr
#define AR_IO_PDM_RX0_RFCR 0x8001b048
#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr")

// User extension aux register io_pdm_rx0_rxdma
#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0
#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma")

// User extension aux register io_pdm_rx0_pdm_rr
#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0
#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr")

// User extension aux register io_pdm_rx0_cic_n
#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4
#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n")

// User extension aux register io_pdm_rx0_cic_d
#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8
#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d")

// User extension aux register io_pdm_rx0_dcrc
#define AR_IO_PDM_RX0_DCRC 0x8001b1dc
#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc")

// User extension aux register io_pdm_rx0_brc_b0
#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0
#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0")

// User extension aux register io_pdm_rx0_brc_clp
#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0
#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT	1

// User extension aux register io_spi_slv0_ctrlr0
#define AR_IO_SPI_SLV0_CTRLR0 0x80011000
#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0")

// User extension aux register io_spi_slv0_spien
#define AR_IO_SPI_SLV0_SPIEN 0x80011002
#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien")

// User extension aux register io_spi_slv0_txftlr
#define AR_IO_SPI_SLV0_TXFTLR 0x80011006
#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr")

// User extension aux register io_spi_slv0_rxftlr
#define AR_IO_SPI_SLV0_RXFTLR 0x80011007
#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr")

// User extension aux register io_spi_slv0_txflr
#define AR_IO_SPI_SLV0_TXFLR 0x80011008
#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr")

// User extension aux register io_spi_slv0_rxflr
#define AR_IO_SPI_SLV0_RXFLR 0x80011009
#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr")

// User extension aux register io_spi_slv0_sr
#define AR_IO_SPI_SLV0_SR 0x8001100a
#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr")

// User extension aux register io_spi_slv0_imr
#define AR_IO_SPI_SLV0_IMR 0x8001100b
#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr")

// User extension aux register io_spi_slv0_isr
#define AR_IO_SPI_SLV0_ISR 0x8001100c
#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr")

// User extension aux register io_spi_slv0_risr
#define AR_IO_SPI_SLV0_RISR 0x8001100d
#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr")

// User extension aux register io_spi_slv0_txoicr
#define AR_IO_SPI_SLV0_TXOICR 0x8001100e
#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr")

// User extension aux register io_spi_slv0_rxoicr
#define AR_IO_SPI_SLV0_RXOICR 0x8001100f
#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr")

// User extension aux register io_spi_slv0_rxuicr
#define AR_IO_SPI_SLV0_RXUICR 0x80011010
#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr")

// User extension aux register io_spi_slv0_icr
#define AR_IO_SPI_SLV0_ICR 0x80011012
#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr")

// User extension aux register io_spi_slv0_clken
#define AR_IO_SPI_SLV0_CLKEN 0x80011016
#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken")

// User extension aux register io_spi_slv0_dr
#define AR_IO_SPI_SLV0_DR 0x80011018
#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT	1

// User extension aux register io_uart0_clken
#define AR_IO_UART0_CLKEN 0x800140c0
#pragma Aux_register(0x800140c0, name=>"io_uart0_clken")

// User extension aux register io_uart0_rbr_thr_dll
#define AR_IO_UART0_RBR_THR_DLL 0x80014000
#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll")

// User extension aux register io_uart0_ier_dlh
#define AR_IO_UART0_IER_DLH 0x80014004
#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh")

// User extension aux register io_uart0_iir_fcr
#define AR_IO_UART0_IIR_FCR 0x80014008
#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr")

// User extension aux register io_uart0_lcr
#define AR_IO_UART0_LCR 0x8001400c
#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr")

// User extension aux register io_uart0_mcr
#define AR_IO_UART0_MCR 0x80014010
#pragma Aux_register(0x80014010, name=>"io_uart0_mcr")

// User extension aux register io_uart0_lsr
#define AR_IO_UART0_LSR 0x80014014
#pragma Aux_register(0x80014014, name=>"io_uart0_lsr")

// User extension aux register io_uart0_msr
#define AR_IO_UART0_MSR 0x80014018
#pragma Aux_register(0x80014018, name=>"io_uart0_msr")

// User extension aux register io_uart0_usr
#define AR_IO_UART0_USR 0x8001407c
#pragma Aux_register(0x8001407c, name=>"io_uart0_usr")
#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT	1

// User extension aux register io_uart1_clken
#define AR_IO_UART1_CLKEN 0x800141c0
#pragma Aux_register(0x800141c0, name=>"io_uart1_clken")

// User extension aux register io_uart1_rbr_thr_dll
#define AR_IO_UART1_RBR_THR_DLL 0x80014100
#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll")

// User extension aux register io_uart1_ier_dlh
#define AR_IO_UART1_IER_DLH 0x80014104
#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh")

// User extension aux register io_uart1_iir_fcr
#define AR_IO_UART1_IIR_FCR 0x80014108
#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr")

// User extension aux register io_uart1_lcr
#define AR_IO_UART1_LCR 0x8001410c
#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr")

// User extension aux register io_uart1_mcr
#define AR_IO_UART1_MCR 0x80014110
#pragma Aux_register(0x80014110, name=>"io_uart1_mcr")

// User extension aux register io_uart1_lsr
#define AR_IO_UART1_LSR 0x80014114
#pragma Aux_register(0x80014114, name=>"io_uart1_lsr")

// User extension aux register io_uart1_msr
#define AR_IO_UART1_MSR 0x80014118
#pragma Aux_register(0x80014118, name=>"io_uart1_msr")

// User extension aux register io_uart1_usr
#define AR_IO_UART1_USR 0x8001417c
#pragma Aux_register(0x8001417c, name=>"io_uart1_usr")
#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT	1

// User extension aux register SUBSYS_BUILD
#define AR_SUBSYS_BUILD 0xf0
#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD")

// User extension aux register SUBSYS_DSP_0_BUILD
#define AR_SUBSYS_DSP_0_BUILD 0xa00
#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD")

// User extension aux register SUBSYS_DSP_0_CONFIG
#define AR_SUBSYS_DSP_0_CONFIG 0xa02
#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG")

// User extension aux register SUBSYS_IO_0_BUILD
#define AR_SUBSYS_IO_0_BUILD 0xa04
#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD")

// User extension aux register SUBSYS_IO_1_BUILD
#define AR_SUBSYS_IO_1_BUILD 0xa05
#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD")

// User extension aux register SUBSYS_IO_2_BUILD
#define AR_SUBSYS_IO_2_BUILD 0xa06
#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD")

// User extension aux register SUBSYS_UAUX_OFFSET
#define AR_SUBSYS_UAUX_OFFSET 0xa1e
#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET")

// User extension aux register SUBSYS_APEX_OFFSET
#define AR_SUBSYS_APEX_OFFSET 0xa1f
#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET")
#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_PRESENT	1

// User extension aux register fpu_build
#define AR_FPU_BUILD 0xc8
#pragma Aux_register(0xc8, name=>"fpu_build")

// User extension aux register fpu_ctrl
#define AR_FPU_CTRL 0x300
#pragma Aux_register(0x300, name=>"fpu_ctrl")

// User extension aux register fpu_status
#define AR_FPU_STATUS 0x301
#pragma Aux_register(0x301, name=>"fpu_status")

// User extension instruction fsmadd
extern int fsmadd(int,int);
#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fsmsub
extern int fsmsub(int,int);
#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fsmul
extern int fsmul(int,int);
#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fsadd
extern int fsadd(int,int);
#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fssub
extern int fssub(int,int);
#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fcvt32
extern int fcvt32(int,int);
#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fsdiv
extern int fsdiv(int,int);
#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fscmp
extern int fscmp(int,int);
#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fscmp
extern int fscmp_f(int,int);
#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fscmpf
extern int fscmpf(int,int);
#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fscmpf
extern int fscmpf_f(int,int);
#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")

// User extension instruction fssqrt
extern int fssqrt(int);
#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")


#endif


]]></string>
  </configuration>
  <configuration name="alb_mss_clkctrl_regmap.h" filename="alb_mss_clkctrl_regmap.h">
    <string><![CDATA[
/*************************************************************************/
/**                                                                     **/
/** Copyright (C) 2016-2017 Synopsys, Inc.                              **/
/** All Rights Reserved.                                                **/
/**                                                                     **/
/** This Synopsys software and all associated documentation are         **/
/** proprietary to Synopsys, Inc. and may only be used pursuant to the  **/
/** terms and conditions of a written license agreement with Synopsys,  **/
/** Inc. All other use, reproduction, modification, or distribution of  **/
/** this Synopsys software or the associated documentation is strictly  **/
/** prohibited.                                                         **/
/**                                                                     **/
/*************************************************************************/


/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
 *
 * Description: Header file declaring the compiler extensions for Clock control 
 */
#ifndef  _alb_mss_clkctrl_regmap_H_
#define  _alb_mss_clkctrl_regmap_H_
// Use -tcf_include= #include "alb_mss_fab_system_memmap.h"
// Clock control registers
#define MSS_CLKCTRL_CFG_CTRL_ADDR            (MSS_CLKCTRL_0_BASE+0x0)
// clock divider registers
#define MSS_CLKCTRL_CLK_DIV_ADDR      (MSS_CLKCTRL_0_BASE+0x4)
#define MSS_CLKCTRL_MSS_CLK_DIV_ADDR      (MSS_CLKCTRL_0_BASE+0x8)
// clock enable ratio and status registers
// mbus_clk_en: clk <-> mss_clk; design rule: none (clk freq vs. mss_clk freq)
#define MSS_CLKCTRL_MBUS_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0xc)
#define MSS_CLKCTRL_MBUS_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x10)
// lbus_clk_en: clk <-> mss_clk; design rule: none (clk freq vs. mss_clk freq)
#define MSS_CLKCTRL_LBUS_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x14)
#define MSS_CLKCTRL_LBUS_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x18)
// mss_fab_mst0_clk_en: mss_clk <-> clk; design rule: none (mss_clk freq vs. clk freq)
#define MSS_CLKCTRL_MSS_FAB_MST0_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x1c)
#define MSS_CLKCTRL_MSS_FAB_MST0_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x20)
// mss_fab_mst1_clk_en: mss_clk <-> clk; design rule: none (mss_clk freq vs. clk freq)
#define MSS_CLKCTRL_MSS_FAB_MST1_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x24)
#define MSS_CLKCTRL_MSS_FAB_MST1_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x28)
// mss_fab_mst2_clk_en: mss_clk <-> clk; design rule: none (mss_clk freq vs. clk freq)
#define MSS_CLKCTRL_MSS_FAB_MST2_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x2c)
#define MSS_CLKCTRL_MSS_FAB_MST2_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x30)
// mss_fab_mst3_clk_en: mss_clk <-> clk; design rule: none (mss_clk freq vs. clk freq)
#define MSS_CLKCTRL_MSS_FAB_MST3_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x34)
#define MSS_CLKCTRL_MSS_FAB_MST3_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x38)
// mss_fab_slv0_clk_en: mss_clk <-> mss_clk; design rule: none (mss_clk freq vs. mss_clk freq)
#define MSS_CLKCTRL_MSS_FAB_SLV0_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x3c)
#define MSS_CLKCTRL_MSS_FAB_SLV0_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x40)
// mss_fab_slv1_clk_en: mss_clk <-> mss_clk; design rule: none (mss_clk freq vs. mss_clk freq)
#define MSS_CLKCTRL_MSS_FAB_SLV1_CLK_EN_RATIO_ADDR     (MSS_CLKCTRL_0_BASE+0x44)
#define MSS_CLKCTRL_MSS_FAB_SLV1_CLK_EN_STAT_ADDR      (MSS_CLKCTRL_0_BASE+0x48)

#define MSS_CLKCTRL_NMI_COUNTER              (MSS_CLKCTRL_0_BASE+0x4c)
#endif
]]></string>
  </configuration>
  <configuration name="system_memmap" filename="alb_mss_fab_system_memmap.h">
    <string><![CDATA[
/*************************************************************************/
/**                                                                     **/
/** Copyright (C) 2016-2017 Synopsys, Inc.                              **/
/** All Rights Reserved.                                                **/
/**                                                                     **/
/** This Synopsys software and all associated documentation are         **/
/** proprietary to Synopsys, Inc. and may only be used pursuant to the  **/
/** terms and conditions of a written license agreement with Synopsys,  **/
/** Inc. All other use, reproduction, modification, or distribution of  **/
/** this Synopsys software or the associated documentation is strictly  **/
/** prohibited.                                                         **/
/**                                                                     **/
/*************************************************************************/


/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
 *
 * Description: Header file declaring the compiler extensions for System Memory
 */
#ifndef  _alb_mss_fab_system_memmap_H_
#define  _alb_mss_fab_system_memmap_H_
// System memory map
#define MSS_CLKCTRL_0_BASE 0xc00000
#define MSS_CLKCTRL_0_SIZE 0x1000
#define MSS_MEM_0_BASE 0x0000
#define MSS_MEM_0_SIZE 0x100000000

// CCM system address with the specific name

#define HAS_DEFAULT_SLAVE 1
#endif
]]></string>
  </configuration>
  <configuration name="apex_assembly" filename="apexextensions.s">
    <string><![CDATA[

; Assembler directives for eia extensions in this design
.set apex_com_arc_hardware_dfss_io_i2c_mst0_present,1
 .set apex_com_arc_hardware_dfss_io_i2c_mst1_present,1
 .set apex_com_arc_hardware_dfss_io_i2c_mst2_present,1
 .set apex_com_arc_hardware_dfss_io_i2c_slv0_present,1
 .set apex_com_arc_hardware_dfss_io_pdm_rx0_present,1
 .set apex_com_arc_hardware_dfss_io_spi_slv0_present,1
 .set apex_com_arc_hardware_dfss_io_uart0_present,1
 .set apex_com_arc_hardware_dfss_io_uart1_present,1
 .set apex_com_arc_hardware_dfss_subsys_bcr_present,1
.set apex_com_arc_hardware_dfss_io_i2c_mst0_present,1
.extAuxRegister io_i2c_mst0_clken,0x800120c0,r|w
.extAuxRegister io_i2c_mst0_con,0x80012000,r|w
.extAuxRegister io_i2c_mst0_tar,0x80012004,r|w
.extAuxRegister io_i2c_mst0_data_cmd,0x80012010,r|w
.extAuxRegister io_i2c_mst0_ss_scl_hcnt,0x80012014,r|w
.extAuxRegister io_i2c_mst0_ss_scl_lcnt,0x80012018,r|w
.extAuxRegister io_i2c_mst0_fs_scl_hcnt,0x8001201c,r|w
.extAuxRegister io_i2c_mst0_fs_scl_lcnt,0x80012020,r|w
.extAuxRegister io_i2c_mst0_intr_stat,0x8001202c,r
.extAuxRegister io_i2c_mst0_intr_mask,0x80012030,r|w
.extAuxRegister io_i2c_mst0_raw_intr_stat,0x80012034,r
.extAuxRegister io_i2c_mst0_rx_tl,0x80012038,r|w
.extAuxRegister io_i2c_mst0_tx_tl,0x8001203c,r|w
.extAuxRegister io_i2c_mst0_clr_intr,0x80012040,r
.extAuxRegister io_i2c_mst0_clr_rx_under,0x80012044,r
.extAuxRegister io_i2c_mst0_clr_rx_over,0x80012048,r
.extAuxRegister io_i2c_mst0_clr_tx_over,0x8001204c,r
.extAuxRegister io_i2c_mst0_clr_tx_abrt,0x80012054,r
.extAuxRegister io_i2c_mst0_clr_activity,0x8001205c,r
.extAuxRegister io_i2c_mst0_clr_stop_det,0x80012060,r
.extAuxRegister io_i2c_mst0_clr_start_det,0x80012064,r
.extAuxRegister io_i2c_mst0_enable,0x8001206c,r|w
.extAuxRegister io_i2c_mst0_status,0x80012070,r
.extAuxRegister io_i2c_mst0_txflr,0x80012074,r
.extAuxRegister io_i2c_mst0_rxflr,0x80012078,r
.extAuxRegister io_i2c_mst0_sda_hold,0x8001207c,r|w
.extAuxRegister io_i2c_mst0_tx_abrt_source,0x80012080,r
.extAuxRegister io_i2c_mst0_enable_status,0x8001209c,r
.extAuxRegister io_i2c_mst0_fs_spklen,0x800120a0,r|w
.set apex_com_arc_hardware_dfss_io_i2c_mst1_present,1
.extAuxRegister io_i2c_mst1_clken,0x800121c0,r|w
.extAuxRegister io_i2c_mst1_con,0x80012100,r|w
.extAuxRegister io_i2c_mst1_tar,0x80012104,r|w
.extAuxRegister io_i2c_mst1_data_cmd,0x80012110,r|w
.extAuxRegister io_i2c_mst1_ss_scl_hcnt,0x80012114,r|w
.extAuxRegister io_i2c_mst1_ss_scl_lcnt,0x80012118,r|w
.extAuxRegister io_i2c_mst1_fs_scl_hcnt,0x8001211c,r|w
.extAuxRegister io_i2c_mst1_fs_scl_lcnt,0x80012120,r|w
.extAuxRegister io_i2c_mst1_intr_stat,0x8001212c,r
.extAuxRegister io_i2c_mst1_intr_mask,0x80012130,r|w
.extAuxRegister io_i2c_mst1_raw_intr_stat,0x80012134,r
.extAuxRegister io_i2c_mst1_rx_tl,0x80012138,r|w
.extAuxRegister io_i2c_mst1_tx_tl,0x8001213c,r|w
.extAuxRegister io_i2c_mst1_clr_intr,0x80012140,r
.extAuxRegister io_i2c_mst1_clr_rx_under,0x80012144,r
.extAuxRegister io_i2c_mst1_clr_rx_over,0x80012148,r
.extAuxRegister io_i2c_mst1_clr_tx_over,0x8001214c,r
.extAuxRegister io_i2c_mst1_clr_tx_abrt,0x80012154,r
.extAuxRegister io_i2c_mst1_clr_activity,0x8001215c,r
.extAuxRegister io_i2c_mst1_clr_stop_det,0x80012160,r
.extAuxRegister io_i2c_mst1_clr_start_det,0x80012164,r
.extAuxRegister io_i2c_mst1_enable,0x8001216c,r|w
.extAuxRegister io_i2c_mst1_status,0x80012170,r
.extAuxRegister io_i2c_mst1_txflr,0x80012174,r
.extAuxRegister io_i2c_mst1_rxflr,0x80012178,r
.extAuxRegister io_i2c_mst1_sda_hold,0x8001217c,r|w
.extAuxRegister io_i2c_mst1_tx_abrt_source,0x80012180,r
.extAuxRegister io_i2c_mst1_enable_status,0x8001219c,r
.extAuxRegister io_i2c_mst1_fs_spklen,0x800121a0,r|w
.set apex_com_arc_hardware_dfss_io_i2c_mst2_present,1
.extAuxRegister io_i2c_mst2_clken,0x800122c0,r|w
.extAuxRegister io_i2c_mst2_con,0x80012200,r|w
.extAuxRegister io_i2c_mst2_tar,0x80012204,r|w
.extAuxRegister io_i2c_mst2_data_cmd,0x80012210,r|w
.extAuxRegister io_i2c_mst2_ss_scl_hcnt,0x80012214,r|w
.extAuxRegister io_i2c_mst2_ss_scl_lcnt,0x80012218,r|w
.extAuxRegister io_i2c_mst2_fs_scl_hcnt,0x8001221c,r|w
.extAuxRegister io_i2c_mst2_fs_scl_lcnt,0x80012220,r|w
.extAuxRegister io_i2c_mst2_intr_stat,0x8001222c,r
.extAuxRegister io_i2c_mst2_intr_mask,0x80012230,r|w
.extAuxRegister io_i2c_mst2_raw_intr_stat,0x80012234,r
.extAuxRegister io_i2c_mst2_rx_tl,0x80012238,r|w
.extAuxRegister io_i2c_mst2_tx_tl,0x8001223c,r|w
.extAuxRegister io_i2c_mst2_clr_intr,0x80012240,r
.extAuxRegister io_i2c_mst2_clr_rx_under,0x80012244,r
.extAuxRegister io_i2c_mst2_clr_rx_over,0x80012248,r
.extAuxRegister io_i2c_mst2_clr_tx_over,0x8001224c,r
.extAuxRegister io_i2c_mst2_clr_tx_abrt,0x80012254,r
.extAuxRegister io_i2c_mst2_clr_activity,0x8001225c,r
.extAuxRegister io_i2c_mst2_clr_stop_det,0x80012260,r
.extAuxRegister io_i2c_mst2_clr_start_det,0x80012264,r
.extAuxRegister io_i2c_mst2_enable,0x8001226c,r|w
.extAuxRegister io_i2c_mst2_status,0x80012270,r
.extAuxRegister io_i2c_mst2_txflr,0x80012274,r
.extAuxRegister io_i2c_mst2_rxflr,0x80012278,r
.extAuxRegister io_i2c_mst2_sda_hold,0x8001227c,r|w
.extAuxRegister io_i2c_mst2_tx_abrt_source,0x80012280,r
.extAuxRegister io_i2c_mst2_enable_status,0x8001229c,r
.extAuxRegister io_i2c_mst2_fs_spklen,0x800122a0,r|w
.set apex_com_arc_hardware_dfss_io_i2c_slv0_present,1
.extAuxRegister io_i2c_slv0_clken,0x800130c0,r|w
.extAuxRegister io_i2c_slv0_con,0x80013000,r|w
.extAuxRegister io_i2c_slv0_sar,0x80013008,r|w
.extAuxRegister io_i2c_slv0_data_cmd,0x80013010,r|w
.extAuxRegister io_i2c_slv0_intr_stat,0x8001302c,r
.extAuxRegister io_i2c_slv0_intr_mask,0x80013030,r|w
.extAuxRegister io_i2c_slv0_raw_intr_stat,0x80013034,r
.extAuxRegister io_i2c_slv0_rx_tl,0x80013038,r|w
.extAuxRegister io_i2c_slv0_tx_tl,0x8001303c,r|w
.extAuxRegister io_i2c_slv0_clr_intr,0x80013040,r
.extAuxRegister io_i2c_slv0_clr_rx_under,0x80013044,r
.extAuxRegister io_i2c_slv0_clr_rx_over,0x80013048,r
.extAuxRegister io_i2c_slv0_clr_tx_over,0x8001304c,r
.extAuxRegister io_i2c_slv0_clr_rd_req,0x80013050,r
.extAuxRegister io_i2c_slv0_clr_tx_abrt,0x80013054,r
.extAuxRegister io_i2c_slv0_clr_rx_done,0x80013058,r
.extAuxRegister io_i2c_slv0_clr_activity,0x8001305c,r
.extAuxRegister io_i2c_slv0_clr_stop_det,0x80013060,r
.extAuxRegister io_i2c_slv0_clr_start_det,0x80013064,r
.extAuxRegister io_i2c_slv0_enable,0x8001306c,r|w
.extAuxRegister io_i2c_slv0_status,0x80013070,r
.extAuxRegister io_i2c_slv0_txflr,0x80013074,r
.extAuxRegister io_i2c_slv0_rxflr,0x80013078,r
.extAuxRegister io_i2c_slv0_sda_hold,0x8001307c,r|w
.extAuxRegister io_i2c_slv0_tx_abrt_source,0x80013080,r
.extAuxRegister io_i2c_slv0_sda_setup,0x80013094,r|w
.extAuxRegister io_i2c_slv0_enable_status,0x8001309c,r
.extAuxRegister io_i2c_slv0_fs_spklen,0x800130a0,r|w
.extAuxRegister io_i2c_slv0_clr_restart_det,0x800130a8,r
.set apex_com_arc_hardware_dfss_io_pdm_rx0_present,1
.extAuxRegister io_pdm_rx0_pdm_en,0x8001b000,r|w
.extAuxRegister io_pdm_rx0_pdm_ren,0x8001b004,r|w
.extAuxRegister io_pdm_rx0_cer,0x8001b00c,r|w
.extAuxRegister io_pdm_rx0_rxffr,0x8001b014,w
.extAuxRegister io_pdm_rx0_rer0,0x8001b028,r|w
.extAuxRegister io_pdm_rx0_isr,0x8001b038,r
.extAuxRegister io_pdm_rx0_imr,0x8001b03c,r|w
.extAuxRegister io_pdm_rx0_ror,0x8001b040,r
.extAuxRegister io_pdm_rx0_rfcr,0x8001b048,r|w
.extAuxRegister io_pdm_rx0_rxdma,0x8001b1c0,r
.extAuxRegister io_pdm_rx0_pdm_rr,0x8001b1d0,r|w
.extAuxRegister io_pdm_rx0_cic_n,0x8001b1d4,r|w
.extAuxRegister io_pdm_rx0_cic_d,0x8001b1d8,r|w
.extAuxRegister io_pdm_rx0_dcrc,0x8001b1dc,r|w
.extAuxRegister io_pdm_rx0_brc_b0,0x8001b1e0,r|w
.extAuxRegister io_pdm_rx0_brc_clp,0x8001b1f0,r|w
.set apex_com_arc_hardware_dfss_io_spi_slv0_present,1
.extAuxRegister io_spi_slv0_ctrlr0,0x80011000,r|w
.extAuxRegister io_spi_slv0_spien,0x80011002,r|w
.extAuxRegister io_spi_slv0_txftlr,0x80011006,r|w
.extAuxRegister io_spi_slv0_rxftlr,0x80011007,r|w
.extAuxRegister io_spi_slv0_txflr,0x80011008,r
.extAuxRegister io_spi_slv0_rxflr,0x80011009,r
.extAuxRegister io_spi_slv0_sr,0x8001100a,r
.extAuxRegister io_spi_slv0_imr,0x8001100b,r|w
.extAuxRegister io_spi_slv0_isr,0x8001100c,r
.extAuxRegister io_spi_slv0_risr,0x8001100d,r
.extAuxRegister io_spi_slv0_txoicr,0x8001100e,r
.extAuxRegister io_spi_slv0_rxoicr,0x8001100f,r
.extAuxRegister io_spi_slv0_rxuicr,0x80011010,r
.extAuxRegister io_spi_slv0_icr,0x80011012,r|w
.extAuxRegister io_spi_slv0_clken,0x80011016,r|w
.extAuxRegister io_spi_slv0_dr,0x80011018,r|w
.set apex_com_arc_hardware_dfss_io_uart0_present,1
.extAuxRegister io_uart0_clken,0x800140c0,r|w
.extAuxRegister io_uart0_rbr_thr_dll,0x80014000,r|w
.extAuxRegister io_uart0_ier_dlh,0x80014004,r|w
.extAuxRegister io_uart0_iir_fcr,0x80014008,r|w
.extAuxRegister io_uart0_lcr,0x8001400c,r|w
.extAuxRegister io_uart0_mcr,0x80014010,r|w
.extAuxRegister io_uart0_lsr,0x80014014,r
.extAuxRegister io_uart0_msr,0x80014018,r
.extAuxRegister io_uart0_usr,0x8001407c,r
.set apex_com_arc_hardware_dfss_io_uart1_present,1
.extAuxRegister io_uart1_clken,0x800141c0,r|w
.extAuxRegister io_uart1_rbr_thr_dll,0x80014100,r|w
.extAuxRegister io_uart1_ier_dlh,0x80014104,r|w
.extAuxRegister io_uart1_iir_fcr,0x80014108,r|w
.extAuxRegister io_uart1_lcr,0x8001410c,r|w
.extAuxRegister io_uart1_mcr,0x80014110,r|w
.extAuxRegister io_uart1_lsr,0x80014114,r
.extAuxRegister io_uart1_msr,0x80014118,r
.extAuxRegister io_uart1_usr,0x8001417c,r
.set apex_com_arc_hardware_dfss_subsys_bcr_present,1
.extAuxRegister SUBSYS_BUILD,0xf0,r
.extAuxRegister SUBSYS_DSP_0_BUILD,0xa00,r
.extAuxRegister SUBSYS_DSP_0_CONFIG,0xa02,r
.extAuxRegister SUBSYS_IO_0_BUILD,0xa04,r
.extAuxRegister SUBSYS_IO_1_BUILD,0xa05,r
.extAuxRegister SUBSYS_IO_2_BUILD,0xa06,r
.extAuxRegister SUBSYS_UAUX_OFFSET,0xa1e,r
.extAuxRegister SUBSYS_APEX_OFFSET,0xa1f,r
.set apex_com_arc_hardware_floating_point_unit_present,1
.extAuxRegister fpu_build,0xc8,r
.extAuxRegister fpu_ctrl,0x300,r|w
.extAuxRegister fpu_status,0x301,r|w
.extInstruction fsmadd,6,5,SUFFIX_COND,SYNTAX_3OP
.extInstruction fsmsub,6,6,SUFFIX_COND,SYNTAX_3OP
.extInstruction fsmul,6,0,SUFFIX_COND,SYNTAX_3OP
.extInstruction fsadd,6,1,SUFFIX_COND,SYNTAX_3OP
.extInstruction fssub,6,2,SUFFIX_COND,SYNTAX_3OP
.extInstruction fcvt32,6,8,SUFFIX_COND,SYNTAX_3OP
.extInstruction fsdiv,6,7,SUFFIX_COND,SYNTAX_3OP
.extInstruction fscmp,6,3,SUFFIX_COND|SUFFIX_FLAG,SYNTAX_3OP
.extInstruction fscmpf,6,4,SUFFIX_COND|SUFFIX_FLAG,SYNTAX_3OP
.extInstruction fssqrt,6,0,FLAGS_NONE,SYNTAX_2OP

]]></string>
  </configuration>
  <configuration name="alb_mss_fab_system_memmap.s" filename="alb_mss_fab_system_memmap.s">
    <string><![CDATA[
// System memory map

.equ MSS_CLKCTRL_0_BASE, 0xc00000
.equ MSS_CLKCTRL_0_SIZE, 0x1000
.equ MSS_MEM_0_BASE, 0x0000
.equ MSS_MEM_0_SIZE, 0x100000000



.equ UNALLOC_SPACE_NUM,       0

// CCM system address with the specific name

.equ HAS_DEFAULT_SLAVE, 1
]]></string>
  </configuration>
</config_list>