diff --git a/.gitignore b/.gitignore
index f770f0dc..46dd1c6f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,16 @@
 /.idea/
 /precheck_results/
 */tmp
-*/*/tmp
\ No newline at end of file
+*.hex*
+*.lst
+*.vcd
+*.gtkw
+/env
+/venv/
+/venv-cocotb/
+/caravel/
+runs/
+/dependencies/
+/mgmt_core_wrapper/
+/logs
+lvs_results/
diff --git a/Makefile b/Makefile
index cb1b2f9e..64761c3c 100644
--- a/Makefile
+++ b/Makefile
@@ -13,21 +13,58 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+MAKEFLAGS+=--warn-undefined-variables
 
-CARAVEL_ROOT?=$(PWD)/caravel
+export CARAVEL_ROOT?=$(PWD)/caravel
+export UPRJ_ROOT?=$(PWD)
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-SIM ?= RTL
-CUP_ROOT?=$(PWD)
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
 
-SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
-export OPEN_PDKS_COMMIT?=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
-export PDK?=sky130A
-export PDKPATH?=$(PDK_ROOT)/$(PDK)
 # Install lite version of caravel, (1): caravel-lite, (0): caravel
 CARAVEL_LITE?=1
 
-MPW_TAG ?= mpw-9k
+# PDK switch varient
+export PDK?=sky130A
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+PYTHON_BIN ?= python3
+
+ROOTLESS ?= 0
+USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
+ifeq ($(ROOTLESS), 1)
+	USER_ARGS =
+endif
+export OPENLANE_ROOT?=$(PWD)/dependencies/openlane_src
 export PDK_ROOT?=$(PWD)/dependencies/pdks
+export DISABLE_LVS?=0
+
+export ROOTLESS
+
+ifeq ($(PDK),sky130A)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0fe599b2afb6708d281543108caf8310912f54af
+	export OPENLANE_TAG?=2023.07.19-2
+	MPW_TAG ?= mpw-9k
+
+ifeq ($(CARAVEL_LITE),1)
+	CARAVEL_NAME := caravel-lite
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite
+	CARAVEL_TAG := $(MPW_TAG)
+else
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel
+	CARAVEL_TAG := $(MPW_TAG)
+endif
+
+endif
+
+ifeq ($(PDK),sky130B)
+	SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+	export OPEN_PDKS_COMMIT?=0fe599b2afb6708d281543108caf8310912f54af
+	export OPENLANE_TAG?=2023.07.19-2
+	MPW_TAG ?= mpw-9k
 
 ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
@@ -39,69 +76,150 @@ else
 	CARAVEL_TAG := $(MPW_TAG)
 endif
 
+endif
+
+ifeq ($(PDK),gf180mcuD)
+
+	MPW_TAG ?= gfmpw-1c
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
+	CARAVEL_TAG := $(MPW_TAG)
+	#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+	export OPEN_PDKS_COMMIT?=78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc
+	export OPENLANE_TAG?=2023.07.19
+
+endif
+
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
-%: 
-	export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+%:
+	export CARAVEL_ROOT=$(CARAVEL_ROOT) && export MPW_TAG=$(MPW_TAG) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
 
-# Verify Target for running simulations
-.PHONY: verify
-verify:
-	cd ./verilog/dv/ && \
-	export SIM=${SIM} && \
-		$(MAKE) -j$(THREADS)
+.PHONY: install
+install:
+	if [ -d "$(CARAVEL_ROOT)" ]; then\
+		echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+		rm -rf $(CARAVEL_ROOT) && sleep 2;\
+	fi
+	echo "Installing $(CARAVEL_NAME).."
+	git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
 
 # Install DV setup
 .PHONY: simenv
 simenv:
-	docker pull efabless/dv_setup:latest
+	docker pull efabless/dv:latest
 
-PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
-DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
-TARGET_PATH=$(shell pwd)
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
-$(DV_PATTERNS): verify-% : ./verilog/dv/% 
-	docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-                -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-                -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
-                -e CARAVEL_ROOT=${CARAVEL_ROOT} \
-                -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
-                sh -c $(VERIFY_COMMAND)
-				
-# Openlane Makefile Targets
-BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
-.PHONY: $(BLOCKS)
-$(BLOCKS): %:
-	cd openlane && $(MAKE) $*
+# Install cocotb docker
+.PHONY: simenv-cocotb
+simenv-cocotb:
+	docker pull efabless/dv:cocotb
 
 .PHONY: setup
-setup: check_dependencies install check-env install_mcw pdk-with-volare setup-timing-scripts setup-cocotb
+setup: check_dependencies install check-env install_mcw openlane pdk-with-volare setup-timing-scripts setup-cocotb precheck
 
-# Install caravel
-.PHONY: install
-install:
-	@echo "Installing $(CARAVEL_NAME).."
-	@git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
+# Openlane
+blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
+	$(MAKE) -C openlane $*
+
+dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c"  | sed -e 's|^.*/||' -e 's/.c//')
+dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+cocotb-dv-targets-rtl=$(cocotb-dv_patterns:%=cocotb-verify-%-rtl)
+dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+cocotb-dv-targets-gl=$(cocotb-dv_patterns:%=cocotb-verify-%-gl)
+dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+
+TARGET_PATH=$(shell pwd)
+verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+dv_base_dependencies=simenv
+docker_run_verify=\
+	docker run \
+		$(USER_ARGS) \
+		-v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+		-v ${MCW_ROOT}:${MCW_ROOT} \
+		-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
+		-e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \
+		-e DESIGNS=$(TARGET_PATH) \
+		-e USER_PROJECT_VERILOG=$(TARGET_PATH)/verilog \
+		-e PDK=$(PDK) \
+		-e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+		-e CARAVEL_VERILOG_PATH=$(TARGET_PATH)/caravel/verilog \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		efabless/dv:latest \
+		sh -c $(verify_command)
+
+.PHONY: harden
+harden: $(blocks)
+
+.PHONY: verify
+verify: $(dv-targets-rtl)
+
+.PHONY: verify-all-rtl
+verify-all-rtl: $(dv-targets-rtl)
+
+.PHONY: verify-all-gl
+verify-all-gl: $(dv-targets-gl)
+
+.PHONY: verify-all-gl-sdf
+verify-all-gl-sdf: $(dv-targets-gl-sdf)
+
+$(dv-targets-rtl): SIM=RTL
+$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl): SIM=GL
+$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl-sdf): SIM=GL_SDF
+$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+clean-targets=$(blocks:%=clean-%)
+.PHONY: $(clean-targets)
+$(clean-targets): clean-% :
+	rm -f ./verilog/gl/$*.v
+	rm -f ./spef/$*.spef
+	rm -f ./sdc/$*.sdc
+	rm -f ./sdf/$*.sdf
+	rm -f ./gds/$*.gds
+	rm -f ./mag/$*.mag
+	rm -f ./lef/$*.lef
+	rm -f ./maglef/*.maglef
+
+make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
+.PHONY: what
+what:
+	# $(make_what)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+	@if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\
+		echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \
+		echo "Please set it to a different directory"; \
+		exit 1; \
+	fi
+	cd openlane && $(MAKE) openlane
+
+#### Not sure if the targets following are of any use
 
 # Create symbolic links to caravel's main files
 .PHONY: simlink
 simlink: check-caravel
-### Symbolic links relative path to $CARAVEL_ROOT 
+### Symbolic links relative path to $CARAVEL_ROOT
 	$(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+	$(eval PIN_CFG_PATH  := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
 	mkdir -p openlane
+	mkdir -p openlane/user_project_wrapper
 	cd openlane &&\
 	ln -sf $(MAKEFILE_PATH) Makefile
-
-BLOCKS = $(shell cd lvs && find * -maxdepth 0 -type d)
-LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
-$(LVS_BLOCKS): lvs-% : ./lvs/%/lvs_config.json uncompress check-pdk check-precheck
-	@$(eval INPUT_DIRECTORY := $(shell pwd))
-	@cd $(PRECHECK_ROOT) && \
-	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
-	-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
-	-v $(PDK_ROOT):$(PDK_ROOT) \
-	-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
-	efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 checks/lvs_check/lvs.py --pdk_path $(PDK_ROOT)/$(PDK) --design_directory $(INPUT_DIRECTORY) --output_directory $(INPUT_DIRECTORY)/lvs --design_name $* --config_file $(INPUT_DIRECTORY)/lvs/$*/lvs_config.json"
+	cd openlane/user_project_wrapper &&\
+	ln -sf $(PIN_CFG_PATH) pin_order.cfg
 
 # Update Caravel
 .PHONY: update_caravel
@@ -110,18 +228,19 @@ update_caravel: check-caravel
 
 # Uninstall Caravel
 .PHONY: uninstall
-uninstall: 
+uninstall:
 	rm -rf $(CARAVEL_ROOT)
 
-# Install Openlane
-.PHONY: openlane
-openlane: 
-	cd openlane && $(MAKE) openlane
 
 # Install Pre-check
 # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
 .PHONY: precheck
 precheck:
+	if [ -d "$(PRECHECK_ROOT)" ]; then\
+		echo "Deleting exisiting $(PRECHECK_ROOT)" && \
+		rm -rf $(PRECHECK_ROOT) && sleep 2;\
+	fi
+	@echo "Installing Precheck.."
 	@git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
 	@docker pull efabless/mpw_precheck:latest
 
@@ -130,9 +249,10 @@ run-precheck: check-pdk check-precheck
 	@if [ "$$DISABLE_LVS" = "1" ]; then\
 		$(eval INPUT_DIRECTORY := $(shell pwd)) \
 		cd $(PRECHECK_ROOT) && \
-		docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		docker run -it -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
 		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
 		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(HOME)/.ipm:$(HOME)/.ipm \
 		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
 		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
 		-e PDK_ROOT=$(PDK_ROOT) \
@@ -142,9 +262,10 @@ run-precheck: check-pdk check-precheck
 	else \
 		$(eval INPUT_DIRECTORY := $(shell pwd)) \
 		cd $(PRECHECK_ROOT) && \
-		docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		docker run -it -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
 		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
 		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(HOME)/.ipm:$(HOME)/.ipm \
 		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
 		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
 		-e PDK_ROOT=$(PDK_ROOT) \
@@ -153,7 +274,17 @@ run-precheck: check-pdk check-precheck
 		efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"; \
 	fi
 
-# Clean 
+BLOCKS = $(shell cd lvs && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./lvs/%/lvs_config.json check-pdk check-precheck
+	@$(eval INPUT_DIRECTORY := $(shell pwd))
+	@cd $(PRECHECK_ROOT) && \
+	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+	-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+	-v $(PDK_ROOT):$(PDK_ROOT) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+	efabless/mpw_precheck:latest bash -c "export PYTHONPATH=$(PRECHECK_ROOT) ; cd $(PRECHECK_ROOT) ; python3 checks/lvs_check/lvs.py --pdk_path $(PDK_ROOT)/$(PDK) --design_directory $(INPUT_DIRECTORY) --output_directory $(INPUT_DIRECTORY)/lvs --design_name $* --config_file $(INPUT_DIRECTORY)/lvs/$*/lvs_config.json"
+
 .PHONY: clean
 clean:
 	cd ./verilog/dv/ && \
@@ -179,7 +310,7 @@ check-pdk:
 
 .PHONY: help
 help:
-	cd $(CARAVEL_ROOT) && $(MAKE) help 
+	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
 
 .PHONY: check_dependencies
@@ -188,14 +319,113 @@ check_dependencies:
 		mkdir $(PWD)/dependencies; \
 	fi
 
+
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/dependencies/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=https://github.com/efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+	@mkdir -p $(CUP_ROOT)/dependencies
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
 .PHONY: setup-timing-scripts
 setup-timing-scripts: $(TIMING_ROOT)
 	@( cd $(TIMING_ROOT) && git pull )
 	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
 
+.PHONY: install-caravel-cocotb
+install-caravel-cocotb:
+	rm -rf ./venv-cocotb
+	$(PYTHON_BIN) -m venv ./venv-cocotb
+	./venv-cocotb/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+	./venv-cocotb/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir caravel-cocotb
+
+.PHONY: setup-cocotb-env
+setup-cocotb-env:
+	@(./venv-cocotb/bin/$(PYTHON_BIN) $(PROJECT_ROOT)/verilog/dv/setup-cocotb.py $(CARAVEL_ROOT) $(MCW_ROOT) $(PDK_ROOT) $(PDK) $(PROJECT_ROOT))
+
 .PHONY: setup-cocotb
-setup-cocotb: 
-	@pip install caravel-cocotb==1.0.0 
-	@(python3 $(PROJECT_ROOT)/verilog/dv/setup-cocotb.py $(CARAVEL_ROOT) $(MCW_ROOT) $(PDK_ROOT) $(PDK) $(PROJECT_ROOT))
-	@docker pull efabless/dv:latest
-	@docker pull efabless/dv:cocotb
+setup-cocotb: install-caravel-cocotb setup-cocotb-env simenv-cocotb
+
+.PHONY: cocotb-verify-all-rtl
+cocotb-verify-all-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml )
+	
+.PHONY: cocotb-verify-all-gl
+cocotb-verify-all-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -tl user_proj_tests/user_proj_tests_gl.yaml -verbosity quiet)
+
+$(cocotb-dv-targets-rtl): cocotb-verify-%-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -t $*  )
+	
+$(cocotb-dv-targets-gl): cocotb-verify-%-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -t $* -verbosity quiet)
+
+./verilog/gl/user_project_wrapper.v:
+	$(error you don't have $@)
+
+./env/spef-mapping.tcl: 
+	@echo "run the following:"
+	@echo "make extract-parasitics"
+	@echo "make create-spef-mapping"
+	exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+	docker run \
+		--rm \
+		$(USER_ARGS) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(CUP_ROOT):$(CUP_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(TIMING_ROOT):$(TIMING_ROOT) \
+		-w $(shell pwd) \
+		efabless/timing-scripts:latest \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--macro-parent chip_core/mprj \
+			--project-root "$(CUP_ROOT)"
+
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+	docker run \
+		--rm \
+		$(USER_ARGS) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(CUP_ROOT):$(CUP_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(TIMING_ROOT):$(TIMING_ROOT) \
+		-w $(shell pwd) \
+		efabless/timing-scripts:latest \
+		python3 $(TIMING_ROOT)/scripts/get_macros.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./tmp-macros-list \
+			--project-root "$(CUP_ROOT)" \
+			--pdk-path $(PDK_ROOT)/$(PDK)
+	@cat ./tmp-macros-list | cut -d " " -f2 \
+		| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+			-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+	@cat ./tmp-macros-list
+	@rm ./tmp-macros-list
+	
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ -j3
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast -j3
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow -j3
+	@echo =============================================Summary=============================================
+	@find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff/timing/*/ -name "summary.log" | head -n1 \
+		| xargs head -n5 | tail -n1
+	@find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff/timing/*/ -name "summary.log" \
+		| xargs -I {} bash -c "head -n7 {} | tail -n1"
+	@echo =================================================================================================
+	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
+	@echo "Check summary.log of a specific corner to point to reports with reg2reg violations" 
+	@echo "Cap and slew violations are inside summary.log file itself"
diff --git a/lvs/user_analog_project_wrapper/lvs_config.json b/lvs/user_analog_project_wrapper/lvs_config.json
index 3548e373..e0abbc6d 100644
--- a/lvs/user_analog_project_wrapper/lvs_config.json
+++ b/lvs/user_analog_project_wrapper/lvs_config.json
@@ -11,6 +11,9 @@
 	"EXTRACT_ABSTRACT": [
 		""
 	],
+	"EXTRACT_CREATE_SUBCUT": [
+		""
+	],
 	"LVS_FLATTEN": [
 		""
 	],
@@ -20,14 +23,11 @@
 	"LVS_IGNORE": [
 		""
 	],
-	"LVS_SPICE_FILES_TO_FIX": [
-		"$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice"
-	],
 	"LVS_SPICE_FILES": [
-		""
+		"$UPRJ_ROOT/xschem/$TOP_SOURCE.spice"
 	],
 	"LVS_VERILOG_FILES": [
 		""
 	],
-	"LAYOUT_FILE": "$UPRJ_ROOT/gds/user_analog_project_wrapper.gds"
+	"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
 }
diff --git a/openlane/Makefile b/openlane/Makefile
deleted file mode 120000
index 48e5b4a5..00000000
--- a/openlane/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 00000000..25646a8b
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,103 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SHELL := /bin/bash
+MAKEFLAGS+=--warn-undefined-variables
+
+export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
+OPENLANE_TAG ?= 2023.07.19-2
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+designs=$(shell find * -maxdepth 0 -type d)
+
+ROOTLESS ?= 0
+USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
+ifeq ($(ROOTLESS), 1)
+	USER_ARGS =
+endif
+
+openlane_cmd = \
+	"flow.tcl \
+	-design $$(realpath ./$*) \
+	-save_path $$(realpath ..) \
+	-save \
+	-tag $(OPENLANE_RUN_TAG) \
+	-overwrite \
+	-ignore_mismatches"
+openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
+
+docker_mounts = \
+	-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
+	-v $(PDK_ROOT):$(PDK_ROOT) \
+	-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+	-v $(HOME)/.ipm:$(HOME)/.ipm \
+	-v $(OPENLANE_ROOT):/openlane
+
+docker_env = \
+	-e PDK_ROOT=$(PDK_ROOT) \
+	-e PDK=$(PDK) \
+	-e MISMATCHES_OK=1 \
+	-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+	-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG)
+
+ifneq ($(MCW_ROOT),)
+docker_env += -e MCW_ROOT=$(MCW_ROOT)
+docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
+endif
+
+docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
+docker_run = \
+	docker run $(docker_startup_mode) \
+	$(USER_ARGS) \
+	$(docker_mounts) \
+	$(docker_env) \
+
+list:
+	@echo $(designs)
+
+.PHONY: $(designs)
+$(designs) : % :
+	mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG)
+	rm -rf ./$*/runs/$*
+	ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
+	if [[ -f ./$@/interactive.tcl ]]; then \
+		$(docker_run) \
+			$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive); \
+	else \
+		$(docker_run) \
+			$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd); \
+	fi
+	@mkdir -p ../signoff/$*/
+	@cp ./$*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+	@cp ./$*/runs/$*/PDK_SOURCES ../signoff/$*/
+	@cp ./$*/runs/$*/reports/*.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane: check-openlane-env
+	if [ -d "$(OPENLANE_ROOT)" ]; then\
+		echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+		rm -rf $(OPENLANE_ROOT) && sleep 2; \
+		fi
+	git clone https://github.com/The-OpenROAD-Project/OpenLane -b $(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		$(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif
diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore
new file mode 100644
index 00000000..fe104e16
--- /dev/null
+++ b/verilog/dv/cocotb/.gitignore
@@ -0,0 +1,4 @@
+sim/ 
+*.log
+*.vcd 
+*.pyc
\ No newline at end of file
diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md
new file mode 100644
index 00000000..340e85d5
--- /dev/null
+++ b/verilog/dv/cocotb/README.md
@@ -0,0 +1,43 @@
+Overview
+======== 
+This directory contain tests to verify the example user project 16 bit counter and 2 other simple tests as examples. 
+
+directory hierarchy
+=====================
+
+# counter_tests 
+ 
+contain tests for 16 bit counter for more info refer to [counter_tests](counter_tests/README.md)
+ 
+ # hello_world 
+ 
+ Example test with empty firmware that only power and reset caravel the print "Hello World" 
+ 
+ # hello_world_uart 
+ 
+ Example test That uses the firmware to send "Hello World" using UART TX 
+ 
+# cocotb_tests.py 
+
+Module that should import all the tests used to be seen for cocotb as a test
+
+ 
+Run tests 
+===========
+# run hello_world_uart
+    ```bash
+    caravel_cocotb -t hello_world_uart -tag hello_world 
+    ```
+# run all counter testlist
+    ```bash
+    caravel_cocotb -tl counter_tests/counter_tests.yaml -tag counter_tests 
+    ```
+# run from different directory
+    ```bash
+    caravel_cocotb -t hello_world_uart -tag hello_world -design_info <path to design_info.yaml>
+    ```      
+# run with changing the results directory
+    ```bash
+    caravel_cocotb -t hello_world_uart -tag hello_world -sim  <path to results directory>
+    ```  
+
diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py
new file mode 100644
index 00000000..bb220ecb
--- /dev/null
+++ b/verilog/dv/cocotb/cocotb_tests.py
@@ -0,0 +1,7 @@
+from hello_world.hello_world import hello_world
+from hello_world_uart.hello_world_uart import hello_world_uart
+from user_proj_tests.counter_wb.counter_wb import counter_wb
+from user_proj_tests.counter_la.counter_la import counter_la
+from user_proj_tests.counter_la_reset.counter_la_reset import counter_la_reset
+from user_proj_tests.counter_la_clk.counter_la_clk import counter_la_clk
+from gpio_test.gpio_test import gpio_test
diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml
new file mode 100644
index 00000000..64f29369
--- /dev/null
+++ b/verilog/dv/cocotb/design_info.yaml
@@ -0,0 +1,9 @@
+CARAVEL_ROOT: /home/kanobailey/2409/caravel
+MCW_ROOT: /home/kanobailey/2409/mgmt_project_root
+PDK: sky130B
+PDK_ROOT: /home/kanobailey/2409/pdks
+USER_PROJECT_ROOT: /home/kanobailey/2409/caravel_user_project
+caravan: false
+clk: 25
+emailto:
+- null
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.c b/verilog/dv/cocotb/gpio_test/gpio_test.c
new file mode 100644
index 00000000..530c45ee
--- /dev/null
+++ b/verilog/dv/cocotb/gpio_test/gpio_test.c
@@ -0,0 +1,30 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h> // include required APIs
+void main(){
+   // Enable managment gpio as output to use as indicator for finishing configuration 
+   ManagmentGpio_outputEnable();
+   ManagmentGpio_write(0);
+   enableHkSpi(0); // disable housekeeping spi
+   //GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUT);
+   GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUTPUT);
+   GPIOs_loadConfigs();
+   GPIOs_writeLow(0x8F);
+   ManagmentGpio_write(1); // configuration finished 
+
+   
+   return;
+}
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.py b/verilog/dv/cocotb/gpio_test/gpio_test.py
new file mode 100644
index 00000000..17323fbe
--- /dev/null
+++ b/verilog/dv/cocotb/gpio_test/gpio_test.py
@@ -0,0 +1,36 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+from caravel_cocotb.caravel_interfaces import * # import python APIs
+import cocotb
+
+@cocotb.test() # cocotb test marker
+@report_test # wrapper for configure test reporting files
+async def gpio_test(dut):
+   caravelEnv = await test_configure(dut) #configure, start up and reset caravel
+   #await caravelEnv.release_csb()
+   await caravelEnv.wait_mgmt_gpio(1)
+   gpios_value_str = caravelEnv.monitor_gpio(37, 0).binstr
+   cocotb.log.info (f"All gpios '{gpios_value_str}'")
+   gpio_value_int = caravelEnv.monitor_gpio(37, 0).integer
+   #expected_gpio_value = 0xF8
+   expected_gpio_value = 0x8F
+   if (gpio_value_int == expected_gpio_value):
+      cocotb.log.info (f"[TEST] Pass the gpio value is '{hex(gpio_value_int)}'")
+   else:
+      cocotb.log.error (f"[TEST] Fail the gpio value is :'{hex(gpio_value_int)}' expected {hex(expected_gpio_value)}")
+   
+
diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c
new file mode 100644
index 00000000..f5825dd2
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world/hello_world.c
@@ -0,0 +1,19 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+void main(){
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py
new file mode 100644
index 00000000..6ea67c75
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world/hello_world.py
@@ -0,0 +1,25 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+
+@cocotb.test()
+@report_test
+async def hello_world(dut):
+    caravelEnv = await test_configure(dut,timeout_cycles=9373)
+    cocotb.log.info("Hello World")
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml
new file mode 100644
index 00000000..f3a98149
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world/hello_world.yaml
@@ -0,0 +1,27 @@
+---
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+# example 
+## tests: [debug,clock_redirect]
+## sim: [RTL,RTL]
+Tests: 
+    - {name: hello_world, sim: RTL}
+
+
+
+
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c
new file mode 100644
index 00000000..6acd8a74
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c
@@ -0,0 +1,28 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+
+void main(){
+    ManagmentGpio_write(0);
+    ManagmentGpio_outputEnable();
+    GPIOs_configure(6,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_loadConfigs();
+    UART_enableTX(1);
+    ManagmentGpio_write(1); // configuration finished 
+
+    print("Hello World\n");
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py
new file mode 100644
index 00000000..4ab26621
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py
@@ -0,0 +1,38 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+from caravel_cocotb.caravel_interfaces import UART
+
+@cocotb.test()
+@report_test
+async def hello_world_uart(dut):
+    caravelEnv = await test_configure(dut,timeout_cycles=3346140)
+
+    cocotb.log.info(f"[TEST] Start uart test")  
+    expected_msg = "Hello World"
+    uart = UART(caravelEnv)
+    # wait for start of sending
+    await caravelEnv.wait_mgmt_gpio(1)
+    # read the msg sent
+    msg = await uart.get_line()
+    if msg in expected_msg :
+        cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{msg}'")
+    else: 
+        cocotb.log.error (f"[TEST] recieved wrong msg from uart msg recieved:'{msg}' expected '{expected_msg}'")
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml
new file mode 100644
index 00000000..b231d9b4
--- /dev/null
+++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+
+Tests: 
+    - {name: hello_world_uart, sim: RTL}
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/README.md b/verilog/dv/cocotb/user_proj_tests/README.md
new file mode 100644
index 00000000..94f7006c
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/README.md
@@ -0,0 +1,26 @@
+
+Tests hierarchy
+=====================
+
+# counter_wb 
+ 
+Test that overwrite the counter value using wishbone interface 
+ 
+ # counter_la 
+ 
+Test that overwrite the counter value using logic analyzer interface 
+ 
+ # counter_la_clk 
+ 
+Counter can work by 2 different clocks wishbone clock or clock provided through logic analyzers.
+By default the wishbone clock is the used one. This test uses the logic analyzers clock
+
+
+ # counter_la_reset
+ 
+Counter reset also provided through wishbone or logic analyzers. this test uses the logic analyzers reset  
+ 
+# counter_tests.yaml
+
+Testlist contain all counter tests
+ 
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c
new file mode 100644
index 00000000..c83cf3db
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c
@@ -0,0 +1,39 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+
+void main(){
+    // Enable managment gpio as output to use as indicator for finishing configuration  
+    ManagmentGpio_outputEnable();
+    ManagmentGpio_write(0);
+    enableHkSpi(0); // disable housekeeping spi
+    // configure all gpios as  user out then chenge gpios from 32 to 37 before loading this configurations
+    GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(32,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(33,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(34,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(35,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(36,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(37,GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_loadConfigs(); // load the configuration 
+    ManagmentGpio_write(1); // configuration finished 
+    // configure la [63:32] as output from cpu
+    LogicAnalyzer_write(1,7<<16);
+    LogicAnalyzer_outputEnable(1,0);
+    ManagmentGpio_write(0); // configuration finished 
+    LogicAnalyzer_outputEnable(1,0xFFFFFFFF);
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py
new file mode 100644
index 00000000..b4424ae9
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py
@@ -0,0 +1,53 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb 
+
+@cocotb.test()
+@report_test
+async def counter_la(dut):
+    caravelEnv = await test_configure(dut, timeout_cycles=59844)
+
+    cocotb.log.info(f"[TEST] Start counter_la test")  
+    # wait for start of sending
+    await caravelEnv.release_csb()
+    await caravelEnv.wait_mgmt_gpio(1)
+    cocotb.log.info(f"[TEST] finish configuration") 
+    overwrite_val = 7 # value will be written to the counter by la 
+    # expect value bigger than 7 
+    await caravelEnv.wait_mgmt_gpio(0) # wait until writing 7 through la 
+    received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) 
+    counter = overwrite_val
+
+    if received_val != counter :
+        cocotb.log.fatal(f"LA writing is incorrect: {overwrite_val} receieved: {received_val}")
+    await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+
+    # wait until the LA writing is disabled 
+    while (received_val == counter): 
+        await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+        received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) 
+
+    counter = received_val
+    for i in range(100):
+        if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) :
+            cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }")
+        await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+        counter +=1
+    
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml
new file mode 100644
index 00000000..c0f1fdeb
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml
@@ -0,0 +1,21 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+
+Tests: 
+    - {name: counter_la, sim: RTL}
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c
new file mode 100644
index 00000000..da071c14
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c
@@ -0,0 +1,54 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+
+void main(){
+    // Enable managment gpio as output to use as indicator for finishing configuration  
+    ManagmentGpio_outputEnable();
+    ManagmentGpio_write(0);
+    enableHkSpi(0); // disable housekeeping spi
+    // configure all gpios as  user out then chenge gpios from 32 to 37 before loading this configurations
+    GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(32,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(33,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(34,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(35,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(36,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_loadConfigs(); // load the configuration 
+    // configure la 64 (clk enable by la) as output from cpu
+    // writing 1 in bit 64(first bit in reg 2) to reset 
+    LogicAnalyzer_write(2,0);
+    // LogicAnalyzer_inputEnable(2,0x1);
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFC);
+    // reset counter 
+    // reset 1
+    LogicAnalyzer_write(2,3); // clk pose edge
+    LogicAnalyzer_write(2,2);// clk pose edge
+    // reset 0
+    LogicAnalyzer_write(2,1); // clk pose edge
+    LogicAnalyzer_write(2,0);// clk pose edge
+
+    ManagmentGpio_write(1); // configuration finished 
+
+    for (int i = 0; i < 7; i++){
+        LogicAnalyzer_write(2,1); // clk pose edge
+        ManagmentGpio_write(0); 
+        LogicAnalyzer_write(2,0);// clk pose edge
+        ManagmentGpio_write(1); 
+        }
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py
new file mode 100644
index 00000000..93f70df6
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py
@@ -0,0 +1,47 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+
+@cocotb.test()
+@report_test
+async def counter_la_clk(dut):
+    caravelEnv = await test_configure(dut,timeout_cycles=61011)
+
+    cocotb.log.info(f"[TEST] Start counter_wb test")  
+    # wait for start of sending
+    await caravelEnv.release_csb()
+    await caravelEnv.wait_mgmt_gpio(1)
+    cocotb.log.info(f"[TEST] finish configuration") 
+    overwrite_val = 0 # because of the reset 
+    # expect value bigger than 7 
+    received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)  
+    counter = received_val
+
+    for i in range(5):
+        if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) :
+            cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }")
+        await wait_la_clock_cycle(caravelEnv)
+        counter +=1
+
+    
+async def wait_la_clock_cycle(caravelEnv): 
+    # clock is synced with mgmt_gpio
+    await caravelEnv.wait_mgmt_gpio(0)
+    await caravelEnv.wait_mgmt_gpio(1)
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml
new file mode 100644
index 00000000..758e3469
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml
@@ -0,0 +1,21 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+Tests: 
+    - {name: counter_la_clk, sim: RTL}
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c
new file mode 100644
index 00000000..a37ccaa1
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c
@@ -0,0 +1,49 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+
+void main(){
+    // Enable managment gpio as output to use as indicator for finishing configuration  
+    ManagmentGpio_outputEnable();
+    ManagmentGpio_write(0);
+    enableHkSpi(0); // disable housekeeping spi
+    // configure all gpios as  user out then chenge gpios from 32 to 37 before loading this configurations
+    GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED);
+    GPIOs_configure(32,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(33,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(34,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(35,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(36,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT);
+    GPIOs_loadConfigs(); // load the configuration 
+    // reset counter
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFD);
+    LogicAnalyzer_write(2,2);
+    LogicAnalyzer_write(2,0);
+
+    ManagmentGpio_write(1); // configuration finished 
+    // configure la 65 (reset enable by la) as output from cpu
+    // writing 1 in bit 65(second bit in reg 2) to reset 
+    // asset reset
+    LogicAnalyzer_write(2,2);
+    LogicAnalyzer_inputEnable(2,0x2);
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFD);
+    // deassert reset
+    LogicAnalyzer_inputEnable(2,0);
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFF);
+
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py
new file mode 100644
index 00000000..cfe8a583
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py
@@ -0,0 +1,58 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+
+@cocotb.test()
+@report_test
+async def counter_la_reset(dut):
+    caravelEnv = await test_configure(dut,timeout_cycles=1346140)
+
+    cocotb.log.info(f"[TEST] Start counter_wb test")  
+    # wait for start of sending
+    await caravelEnv.release_csb()
+    await caravelEnv.wait_mgmt_gpio(1)
+    cocotb.log.info(f"[TEST] finish configuration") 
+    overwrite_val = 0 # because of the reset 
+    # expect value bigger than 7 
+    received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) 
+    counter = received_val
+    if received_val <= overwrite_val :
+        cocotb.log.error(f"counter started late and value captured after configuration is smaller than overwrite value: {overwrite_val} receieved: {received_val}")
+    await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+
+    while True: # wait until reset asserted
+        if await get_reset_val(caravelEnv) == 1: 
+            cocotb.log.info(f"[TEST] Reset asserted by la")  
+            break
+    while True: # wait until reset deasserted
+        if await get_reset_val(caravelEnv) == 0: 
+            cocotb.log.info(f"[TEST] Reset deasserted by la")  
+            break
+    counter =0
+
+    for i in range(100):
+        if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) :
+            cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }")
+        await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+        counter +=1
+    
+async def get_reset_val(caravelEnv): 
+    """ get the counter reset value"""
+    await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+    return caravelEnv.user_hdl.mprj.counter.reset.value
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml
new file mode 100644
index 00000000..38110352
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml
@@ -0,0 +1,21 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+Tests: 
+    - {name: counter_la_reset, sim: RTL}
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c
new file mode 100644
index 00000000..c9f021c6
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c
@@ -0,0 +1,39 @@
+// SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//      http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <firmware_apis.h>
+
+void main(){
+    // Enable managment gpio as output to use as indicator for finishing configuration  
+    ManagmentGpio_outputEnable();
+    ManagmentGpio_write(0);
+    enableHkSpi(0); // disable housekeeping spi
+    // configure all gpios as  user out then chenge gpios from 32 to 37 before loading this configurations
+    GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED);
+    
+    GPIOs_loadConfigs(); // load the configuration 
+    User_enableIF(); // this necessary when reading or writing between wishbone and user project if interface isn't enabled no ack would be recieve and the command will be stuck
+    // user la reset and wb clk
+    LogicAnalyzer_outputEnable(2,1);
+    // reset counter 
+    LogicAnalyzer_write(2,2);
+    LogicAnalyzer_write(2,0);
+    ManagmentGpio_write(1); // configuration finished 
+    // writing to any address inside user project address space would reload the counter value
+    USER_writeWord(0x7,0x88);
+    ManagmentGpio_write(0); // start counting from 0
+
+    return;
+}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py
new file mode 100644
index 00000000..f4539fe2
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py
@@ -0,0 +1,63 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+
+from caravel_cocotb.caravel_interfaces import test_configure
+from caravel_cocotb.caravel_interfaces import report_test
+import cocotb
+
+@cocotb.test()
+@report_test
+async def counter_wb(dut):
+    caravelEnv = await test_configure(dut,timeout_cycles=22620)
+
+    cocotb.log.info(f"[TEST] Start counter_wb test")  
+    # wait for start of sending
+    await caravelEnv.release_csb()
+    await caravelEnv.wait_mgmt_gpio(1)
+    cocotb.log.info(f"[TEST] finish configuration") 
+    overwrite_val = 7 # value will be written to the counter by wishbone 
+    # expect value bigger than 7 
+    received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)  
+    counter = received_val
+    await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+
+    while True: # wait until the value 1 start counting after the initial
+        received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)  
+        if counter == 0xFFFF: # rollover 
+            counter = 0
+        else: 
+            counter +=1
+        if received_val != counter: 
+            if received_val == overwrite_val: 
+                counter = received_val +1
+                cocotb.log.info(f"Counter value has been overwritten by wishbone to be {received_val}")
+                while True: #wait until the wishbone writing finished and the counter start running again
+                    received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)  
+                    if counter == received_val: 
+                        break
+                    await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+                cocotb.log.info(f"Counter value has been overwritten by wishbone to be {received_val}")
+                break
+            else: 
+                cocotb.log.error(f"Counter has wrong value before overwrite happened expected: {counter} received: {received_val}")
+        await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+
+    for i in range(100):
+        if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) :
+            cocotb.log.error(f"Counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }")
+        await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
+        counter +=1
\ No newline at end of file
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml
new file mode 100644
index 00000000..8436c321
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml
@@ -0,0 +1,21 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+# Yalm file contain general design information that would mostly need to be updated in the first run only 
+Tests: 
+    - {name: counter_wb, sim: RTL}
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml
new file mode 100644
index 00000000..0d3a7fd5
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+
+# yaml file contain general design information that would mostly need to be updated in the first run only 
+includes: 
+    - counter_la/counter_la.yaml
+    - counter_wb/counter_wb.yaml
+    - counter_la_reset/counter_la_reset.yaml
+    - counter_la_clk/counter_la_clk.yaml
+
+
diff --git a/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml
new file mode 100644
index 00000000..4019756d
--- /dev/null
+++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml
@@ -0,0 +1,8 @@
+---
+# yaml file contain general design information that would mostly need to be updated in the first run only 
+Tests: 
+    - {name: counter_wb, sim: GL}
+    - {name: counter_la, sim: GL}
+    - {name: counter_la_reset, sim: GL}
+    - {name: counter_la_clk, sim: GL}
+
diff --git a/verilog/dv/setup-cocotb.py b/verilog/dv/setup-cocotb.py
new file mode 100644
index 00000000..4471ee64
--- /dev/null
+++ b/verilog/dv/setup-cocotb.py
@@ -0,0 +1,50 @@
+# SPDX-FileCopyrightText: 2023 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+#      http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# SPDX-License-Identifier: Apache-2.0
+import click
+import yaml
+
+
+@click.command()
+@click.argument('caravel_root', type=click.Path(exists=True))
+@click.argument('mcw_root', type=click.Path(exists=True))
+@click.argument('pdk_root', type=click.Path(exists=True))
+@click.argument('pdk')
+@click.argument('user_project_root', type=click.Path(exists=True))
+def update_design_info(caravel_root, mcw_root, pdk_root, pdk, user_project_root):
+    data = {
+        'CARAVEL_ROOT': caravel_root,
+        'MCW_ROOT': mcw_root,
+        'USER_PROJECT_ROOT': user_project_root,
+        'PDK_ROOT': pdk_root,
+        'PDK': pdk,
+        'clk': 25,
+        'caravan': False,
+        'emailto': [None]
+    }
+
+    with open(f'{user_project_root}/verilog/dv/cocotb/design_info.yaml', 'w') as file:
+        yaml.dump(data, file)
+
+
+if __name__ == "__main__":
+    update_design_info()
+
+# paths = EnvironmentPaths("/home/rady/caravel/caravel_orginal/caravel/",
+# "/home/rady/caravel/caravel_orginal/caravel_mgmt_soc_litex/",
+# "/home/rady/caravel/files4vcs/pdk","sky130A",
+# "/home/rady/caravel/swift/caravel_user_project/")
+
+# WriteDesignInfo("/home/Marwan/caravel/swift/caravel-dynamic-sims/cocotb/",paths,Emailto=["mostafa.rady@efabless.com"])