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SCH and PCB review - CRYO ASIC test adapter #2

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5 tasks done
filipswit opened this issue Mar 24, 2024 · 2 comments
Open
5 tasks done

SCH and PCB review - CRYO ASIC test adapter #2

filipswit opened this issue Mar 24, 2024 · 2 comments

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@filipswit
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filipswit commented Mar 24, 2024 •
edited by tprzywoz
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  • It is probably bug in documentation but it says that, 4th pin is drain referenced to 3.3V instead of 1.8V, so it should be verified.
    image

  • consider higher voltage rate of C5, 50V is close to working voltage.

  • vias are unmasked, is it on purpose?

  • Unconnected via
    image

  • missing outjob file
@tprzywoz
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tprzywoz commented Apr 9, 2024

  • It is probably bug in documentation but it says that, 4th pin is drain referenced to 3.3V instead of 1.8V, so it should be verified.

Checked. It is a bug in documentation.

  • consider higher voltage rate of C5, 50V is close to working voltage.

Changed to CC0805_1UF_100V_10%_X7S

  • vias are unmasked, is it on purpose?

I was using vias parameters from a previous project: https://github.com/elhep/SIQCI_ASIC_test_adapter

  • Unconnected via

Fixed

  • missing outjob file

Added

@filipswit
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filipswit commented Apr 21, 2024 •
edited by tprzywoz
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  • add L1 and L2 in gerber files outputer

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@filipswit @tprzywoz