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Due to #128 I implemented a watchdog mechanism that will reset liteeth. But when liteeth is under reset it transmits out packets. Easiest way to observe it is to assert the reset after 30 seconds. Then start the FPGA and start pinging. Once liteeth enters reset you will see old ping responses coming in.
The text was updated successfully, but these errors were encountered:
I forget I had it enabled locally. I tested with the master of liteeth and it happens but MUCH less. You have to test for a pretty long time for it to happen.
Due to #128 I implemented a watchdog mechanism that will reset liteeth. But when liteeth is under reset it transmits out packets. Easiest way to observe it is to assert the reset after 30 seconds. Then start the FPGA and start pinging. Once liteeth enters reset you will see old ping responses coming in.
The text was updated successfully, but these errors were encountered: