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Spi flash quad read not working with the ulx3s #2064

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dwalton65 opened this issue Sep 11, 2024 · 2 comments
Open

Spi flash quad read not working with the ulx3s #2064

dwalton65 opened this issue Sep 11, 2024 · 2 comments

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@dwalton65
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If I build litex with the option --with-spi-flash, the flash returns all 0xff

I then uncommented the line #define SPIFLASH_DEBUG in spiflash.c and re-built.

On boot up I got the following:

$ litex_term /dev/ttyUSB0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 11 2024 16:45:19
 BIOS CRC passed (ae635425)

 LiteX git sha1: 6d0ae25d6

--=============== SoC ==================--
CPU:            VexRiscv_Lite @ 50MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
L2:             8.0KiB
FLASH:          16.0MiB
SDRAM:          32.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:       32.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 14.0MiB/s
   Read speed: 24.2MiB/s

Initializing is25lp128 SPI Flash @0x01000000...
[ID: ff 9d 60 18]Enabling Quad mode...
Testing against CRC32: fea8a821
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x1000000 (Sequential, 4.0KiB)...
   Read speed: 4.1MiB/s
Memspeed at 0x1000000 (Random, 4.0KiB)...
   Read speed: 611.0KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

The flash region was all 0xff

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000
SRAM      0x10000000 0x2000
MAIN_RAM  0x40000000 0x2000000
SPIFLASH  0x01000000 0x1000000
CSR       0xf0000000 0x10000

litex> mem_read 0x01000000 0x20
Memory dump:
0x01000000  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................
0x01000010  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff  ................

litex>

When I changed the line in test_ulx3s_target.py from

self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4))

to

self.add_spi_flash(mode="1x", module=IS25LP128(Codes.READ_1_1_1))

I got the following:

$ litex_term /dev/ttyUSB0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 11 2024 17:15:30
 BIOS CRC passed (8a7a12ca)

 LiteX git sha1: 6d0ae25d6

--=============== SoC ==================--
CPU:            VexRiscv_Lite @ 50MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
L2:             8.0KiB
FLASH:          16.0MiB
SDRAM:          32.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:       32.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 14.0MiB/s
   Read speed: 24.2MiB/s

Initializing is25lp128 SPI Flash @0x01000000...
[ID: ff 9d 60 18]Testing against CRC32: 9b21485d
[DIV: 0] 9b21485d
SPI Flash clk configured to 25 MHz
Memspeed at 0x1000000 (Sequential, 4.0KiB)...
   Read speed: 2.3MiB/s
Memspeed at 0x1000000 (Random, 4.0KiB)...
   Read speed: 807.2KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

The flash region was no longer all 0xff

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000
SRAM      0x10000000 0x2000
MAIN_RAM  0x40000000 0x2000000
SPIFLASH  0x01000000 0x1000000
CSR       0xf0000000 0x10000

litex> mem_read 0x01000000 0x20
Memory dump:
0x01000000  ff ff ff bd b3 ff ff ff ff 3b 00 00 00 e2 00 00  .........;......
0x01000010  00 41 11 30 43 02 00 00 00 05 a0 41 07 14 18 60  .A.0C......A...`

litex>

Is there something else that needs to be done to use spi quad mode to read the flash?

The test project is attached
test2.gz
@dwalton65
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Author

The line "spiflash_master_write(0x00014307, 3, 1, 0x1);" in spiflash.c is not successfully putting the IS25LP128 FLASH into quad mode.
I replaced this line with a call to:

static void spiflash_enable_quad_mode(void)
{
	w_buf[0] = 0x01;
	w_buf[1] = 0x43;
	transfer_cmd(w_buf, r_buf, 2);
}

Now I get the following:

litex_term /dev/ttyUSB0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 12 2024 10:51:42
 BIOS CRC passed (74a710de)

 LiteX git sha1: 6d0ae25d6

--=============== SoC ==================--
CPU:            VexRiscv_Lite @ 50MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
L2:             8.0KiB
FLASH:          16.0MiB
SDRAM:          32.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:       32.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 14.0MiB/s
   Read speed: 24.2MiB/s

Initializing is25lp128 SPI Flash @0x01000000...
[ID: ff 9d 60 18]Enabling Quad mode...
Testing against CRC32: 9b21485d
[DIV: 0] 9b21485d
SPI Flash clk configured to 25 MHz
Memspeed at 0x1000000 (Sequential, 4.0KiB)...
   Read speed: 7.3MiB/s
Memspeed at 0x1000000 (Random, 4.0KiB)...
   Read speed: 938.1KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_read 0x01000000 0x20
Memory dump:
0x01000000  ff ff ff bd b3 ff ff ff ff 3b 00 00 00 e2 00 00  .........;......
0x01000010  00 41 11 30 43 02 00 00 00 05 a0 41 07 14 18 60  .A.0C......A...`

litex>

@dwalton65
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Author

The full changes I made to spiflash.c are as follows:

$ git diff spiflash.c

diff --git a/litex/soc/software/liblitespi/spiflash.c b/litex/soc/software/liblitespi/spiflash.c
index a8f8bf866..0d7bdffd6 100644
--- a/litex/soc/software/liblitespi/spiflash.c
+++ b/litex/soc/software/liblitespi/spiflash.c
@@ -150,6 +150,8 @@ static uint32_t spiflash_read_id_register(void)
        volatile uint8_t buf[4];
        w_buf[0] = 0x9F;
        w_buf[1] = 0x00;
+       w_buf[2] = 0x00;
+       w_buf[3] = 0x00;
        transfer_cmd(w_buf, buf, 4);

 #ifdef SPIFLASH_DEBUG
@@ -167,6 +169,8 @@ static uint32_t spiflash_read_status_register(void)
        volatile uint8_t buf[4];
        w_buf[0] = 0x05;
        w_buf[1] = 0x00;
+       w_buf[2] = 0x00;
+       w_buf[3] = 0x00;
        transfer_cmd(w_buf, buf, 4);

 #ifdef SPIFLASH_DEBUG
@@ -205,6 +209,13 @@ static void spiflash_sector_erase(uint32_t addr)
        transfer_cmd(w_buf, r_buf, 4);
 }

+static void spiflash_enable_quad_mode(void)
+{
+       w_buf[0] = 0x01;
+       w_buf[1] = 0x43;
+       transfer_cmd(w_buf, r_buf, 2);
+}
+
 /* erase page size in bytes, check flash datasheet */
 #define SPI_FLASH_ERASE_SIZE (64*1024)

@@ -299,7 +310,8 @@ void spiflash_init(void)
 #ifdef SPIFLASH_MODULE_QUAD_CAPABLE
        printf("Enabling Quad mode...\n");
        spiflash_master_write(0x00000006, 1, 1, 0x1);
-       spiflash_master_write(0x00014307, 3, 1, 0x1);
+       //spiflash_master_write(0x00014307, 3, 1, 0x1);
+       spiflash_enable_quad_mode();

 #ifdef SPIFLASH_MODULE_QPI_CAPABLE
        printf("Switching to QPI mode...\n");

@dwalton65 dwalton65 mentioned this issue Sep 16, 2024
Open
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@dwalton65