diff --git a/elasticai/creator/nn/binary/mac/_mac_test.py b/elasticai/creator/nn/binary/mac/_mac_test.py deleted file mode 100644 index aabc20ab..00000000 --- a/elasticai/creator/nn/binary/mac/_mac_test.py +++ /dev/null @@ -1,43 +0,0 @@ -import pytest -import torch - -from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator - -from .layer import MacLayer - -sw_function_test_data = [ - ((1, 1, 1), (-1, 1, -1), -1), - ((1, -1, -1, 1, 1), (1, -1, 1, -1, 1), 1), -] - - -@pytest.mark.parametrize(["x1", "x2", "expected"], sw_function_test_data) -def test_sw_function(x1, x2, expected): - x1 = torch.tensor((1, 1, 1), dtype=torch.float32) - x2 = torch.tensor((-1, 1, -1), dtype=torch.float32) - mac = MacLayer(vector_width=x1.shape[0]) - expected = -1 - y = mac(x1, x2).item() - assert expected == y - - -test_data = [ - # 00010 * 00010 -> 00000 00100 -> 000(00 001)00 -> 00001 - ((1, 1, 1), (1, 1, 1)), - # 00010 * 01000 -> 00000 10000 -> 000(00 100)00 -> 00100 - ((-1, 1), (-1, -1)), - ((-1, -1, 1), (1, 1, 1)), -] - - -@pytest.mark.simulation -@pytest.mark.parametrize(["x1", "x2"], test_data) -def test_mac_hw_for_integers(tmp_path, x1, x2): - root_dir_path = str(tmp_path) - mac = MacLayer(vector_width=len(x1)) - sim = mac.create_simulation(GHDLSimulator, working_dir=root_dir_path) - actual = sim(x1, x2) - y = mac( - torch.tensor(x1, dtype=torch.float32), torch.tensor(x2, dtype=torch.float32) - ) - assert y == actual diff --git a/elasticai/creator/nn/binary/mac/mactestbench.py b/elasticai/creator/nn/binary/mac/mactestbench.py deleted file mode 100644 index f1c16b94..00000000 --- a/elasticai/creator/nn/binary/mac/mactestbench.py +++ /dev/null @@ -1,54 +0,0 @@ -from elasticai.creator.file_generation.savable import Path -from elasticai.creator.file_generation.template import InProjectTemplate - - -class MacTestBench: - def __init__(self, uut, name, uut_name): - self._uut = uut - self._uut_name = uut_name - self._inputs = None - self._destination = None - self.name = name - - def set_inputs(self, *inputs): - self._inputs = inputs - - def parse_reported_content(self, outputs: list[str]): - return 2 * int(outputs[0]) - 1 - - @property - def _width(self) -> str: - return str(len(self._inputs[0])) - - def save_to(self, destination: Path): - self._destination = destination - inputs = self._prepare_inputs_for_test_bench(self._inputs) - test_bench = InProjectTemplate( - package="elasticai.creator.nn.binary.mac", - file_name="testbench.tpl.vhd", - parameters=inputs - | { - "uut_name": self._uut_name, - "name": self.name, - "total_width": self._width, - }, - ) - self._uut.save_to(destination) - destination.create_subpath(self.name).as_file(".vhd").write(test_bench) - - def _prepare_inputs_for_test_bench(self, inputs): - x1, x2 = inputs - - def zero_one(xs): - return ["0" if x < 0 else "1" for x in xs] - - def to_string(xs): - return '"{}"'.format("".join(xs)) - - x1 = zero_one(x1) - x2 = zero_one(x2) - inputs = { - "x1": to_string(x1), - "x2": to_string(x2), - } - return inputs diff --git a/elasticai/creator/nn/binary/mac/testbench.tpl.vhd b/elasticai/creator/nn/binary/mac/testbench.tpl.vhd deleted file mode 100644 index 59b4ed0e..00000000 --- a/elasticai/creator/nn/binary/mac/testbench.tpl.vhd +++ /dev/null @@ -1,56 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; -use ieee.std_logic_textio.all; -use std.env.finish; - - -entity $name is - -end; - -architecture Behavioral of $name is - constant TOTAL_WIDTH : integer := $total_width; - constant total_clock_cycles: integer := 4; - signal clock_period : time := 2 ps; - signal clock : std_logic := '0'; - signal reset : std_logic := '0'; - subtype input_t is std_logic_vector(TOTAL_WIDTH-1 downto 0); - signal next_sample : std_logic; - signal x1 : input_t := (others => '0'); - signal x2 : input_t := (others => '0'); - signal sum : std_logic; - signal done : std_logic; - - signal x1_values : input_t := $x1; - signal x2_values : input_t := $x2; - - - -begin - UUT : entity work.${uut_name} - port map (reset => reset, next_sample => next_sample, x1 => x1, x2 => x2, sum => sum, done => done); - - next_sample <= clock; - clock <= not clock after clock_period/2; - - testbench_1 : process(clock, done) - variable iteration_id : integer := 0; - variable reset_performed : std_logic := '0'; - variable value_id : integer := 0; - constant max_iterations : integer := 5; - begin - if rising_edge(clock) then - if iteration_id = 0 then - x1 <= x1_values; - x2 <= x2_values; - else - report to_string(sum); - finish; - end if; - iteration_id := iteration_id + 1; - end if; - end process; - -end Behavioral; diff --git a/elasticai/creator/nn/fixed_point/conv1d/_testbench_test.py b/elasticai/creator/nn/fixed_point/conv1d/_testbench_test.py new file mode 100644 index 00000000..8691ccd0 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/_testbench_test.py @@ -0,0 +1,141 @@ +from typing import Any, Callable + +import pytest +import torch + +from elasticai.creator.vhdl.auto_wire_protocols.port_definitions import create_port +from elasticai.creator.vhdl.design.ports import Port + +from ..number_converter import FXPParams, NumberConverter +from .testbench import Conv1dTestbench +from .design import Conv1dDesign + + +class DummyConv1d: + def __init__(self, fxp_params: FXPParams, in_channels: int, out_channels: int): + self.name: str = "conv1d" + self.kernel_size: int = 1 + self.input_signal_length = 1 + self.in_channels = in_channels + self.out_channels = out_channels + self.port: Port = create_port( + y_width=fxp_params.total_bits, + x_width=fxp_params.total_bits, + x_count=1, + y_count=2, + ) + + +def parameters_for_reported_content_parsing(fxp_params, input_expected_pairs): + def add_expected_prefix_to_pairs(pairs): + _converter_for_batch = NumberConverter( + FXPParams(8, 0) + ) # max for 255 lines of inputs + pairs_with_prefix = list() + for i, (pairs_text, pairs_number) in enumerate(pairs): + pairs_with_prefix.append(list()) + pairs_with_prefix[i].append(list()) + pairs_with_prefix[i].append(pairs_number) + for batch_number, batch_channel_text in enumerate(pairs_text): + for out_channel_text in batch_channel_text: + for value_text in out_channel_text: + pairs_with_prefix[i][0].append( + f"result: {_converter_for_batch.integer_to_bits(batch_number)}," + f" {value_text}" + ) + return pairs_with_prefix + + pairs_with_prefix = [ + (fxp_params, a, b) + for a, b in add_expected_prefix_to_pairs(input_expected_pairs) + ] + return pairs_with_prefix + + +@pytest.fixture +def create_uut() -> Callable[[FXPParams, int, int], Conv1dDesign]: + def create(fxp_params, in_channels: int, out_channels: int) -> Conv1dDesign: + return DummyConv1d(fxp_params, in_channels=in_channels, out_channels=out_channels) + + return create + + +@pytest.mark.parametrize( + "fxp_params, reported, y", ( + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=3, frac_bits=0), + input_expected_pairs=[ + ([[["010"]]], [[[2.0]]]), + ([[["001", "010"]]], [[[1.0, 2.0]]]), + ([[["111", "001"]]], [[[-1.0, 1.0]]]), + ] + ) + + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=4, frac_bits=1), + input_expected_pairs=[ + ([[["0001", "1111"]]], [[[0.5, -0.5]]]), + ([[["0001", "0011"]], [["1000", "1111"]]], [[[0.5, 1.5]], [[-4.0, -0.5]]]), + ] + ) + ) +) +def test_parse_reported_content_one_out_channel(fxp_params, reported, y, create_uut): + in_channels = None + out_channels = 1 + bench = Conv1dTestbench( + name="conv1d_testbench", fxp_params=fxp_params, uut=create_uut(fxp_params, in_channels, out_channels) + ) + print(reported) + assert y == bench.parse_reported_content(reported) + + +@pytest.mark.parametrize( + "fxp_params, reported, y", ( + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=3, frac_bits=0), + input_expected_pairs=[ + ([[["010"],["010"]]], [[[2.0],[2.0]]]), + ([[["001", "010"], ["001", "010"]]], [[[1.0, 2.0], [1.0, 2.0]]]), + ([[["111", "001"], ["111", "001"]]], [[[-1.0, 1.0], [-1.0, 1.0]]]), + ] + ) + + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=4, frac_bits=1), + input_expected_pairs=[ + ([[["0001", "1111"], ["0001", "1111"]]], [[[0.5, -0.5], [0.5, -0.5]]]), + ([[["0001", "0011"], ["0001", "0011"]], [["1000", "1111"], ["1000", "1111"]]], + [[[0.5, 1.5], [0.5, 1.5]], [[-4.0, -0.5], [-4.0, -0.5]]]), + ] + ) + ) +) +def test_parse_reported_content_two_out_channel(fxp_params, reported, y, create_uut): + in_channels = None + out_channels = 2 + bench = Conv1dTestbench( + name="conv1d_testbench", fxp_params=fxp_params, uut=create_uut(fxp_params, in_channels, out_channels) + ) + print(reported) + assert y == bench.parse_reported_content(reported) + +def test_input_preparation_with_one_in_channel(create_uut): + fxp_params = FXPParams(total_bits=3, frac_bits=0) + in_channels = 1 + out_channels = None + bench = Conv1dTestbench( + name="bench_name", fxp_params=fxp_params, uut=create_uut(fxp_params, in_channels, out_channels), + ) + input = torch.Tensor([[[1.0, 1.0]]]) + expected = [{"x_0_0": "001", "x_0_1": "001"}] + assert expected == bench.prepare_inputs(input.tolist()) + +def test_input_preparation_with_two_in_channel(create_uut): + fxp_params = FXPParams(total_bits=3, frac_bits=0) + in_channels = 1 + out_channels = None + bench = Conv1dTestbench( + name="bench_name", fxp_params=fxp_params, uut=create_uut(fxp_params, in_channels, out_channels), + ) + input = torch.Tensor([[[1.0, 1.0], [1.0, 2.0]]]) + expected = [{"x_0_0": "001", "x_0_1": "001", "x_1_0": "001", "x_1_1": "010"}] + assert expected == bench.prepare_inputs(input.tolist()) diff --git a/elasticai/creator/nn/fixed_point/conv1d/conv1d.tpl.vhd b/elasticai/creator/nn/fixed_point/conv1d/conv1d.tpl.vhd index cd0f22fd..ffca8d87 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/conv1d.tpl.vhd +++ b/elasticai/creator/nn/fixed_point/conv1d/conv1d.tpl.vhd @@ -1,6 +1,55 @@ --- Dummy File for testing implementation of conv1d Design -${total_bits} -${frac_bits} -${in_channels} -${out_channels} -${kernel_size} +library ieee; +use ieee.std_logic_1164.all; + +entity ${name} is + port ( + enable : in std_logic; + clock : in std_logic; + x_address : out std_logic_vector(${x_address_width}-1 downto 0); + y_address : in std_logic_vector(${y_address_width}-1 downto 0); + + x : in std_logic_vector(${x_width}-1 downto 0); + y : out std_logic_vector(${y_width}-1 downto 0); + + done : out std_logic + ); +end; + +architecture rtl of ${name} is + constant TOTAL_WIDTH : natural := ${x_width}; + constant FRAC_WIDTH : natural := ${frac_width}; + constant VECTOR_WIDTH : natural := ${vector_width}; + constant KERNEL_SIZE : natural := ${kernel_size}; + constant IN_CHANNELS : natural := ${in_channels}; + constant OUT_CHANNELS : natural := ${out_channels}; + constant X_ADDRESS_WIDTH : natural := ${x_address_width}; + constant Y_ADDRESS_WIDTH : natural := ${y_address_width}; + + signal reset : std_logic; + +begin + + reset <= not enable; + + ${name}_conv1d : entity work.conv1d_fxp_MAC_RoundToZero + generic map( + TOTAL_WIDTH => TOTAL_WIDTH, + FRAC_WIDTH => FRAC_WIDTH, + VECTOR_WIDTH => VECTOR_WIDTH, + KERNEL_SIZE => KERNEL_SIZE, + IN_CHANNELS => IN_CHANNELS, + OUT_CHANNELS => OUT_CHANNELS, + X_ADDRESS_WIDTH => X_ADDRESS_WIDTH, + Y_ADDRESS_WIDTH => Y_ADDRESS_WIDTH + ) + port map ( + clock => clock, + enable => enable, + reset => reset, + x => x, + x_address => x_address, + y => y, + y_address => y_address, + done => done + ); +end rtl; diff --git a/elasticai/creator/nn/fixed_point/conv1d/conv1d_function.tpl.vhd b/elasticai/creator/nn/fixed_point/conv1d/conv1d_function.tpl.vhd new file mode 100644 index 00000000..5cbdbab8 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/conv1d_function.tpl.vhd @@ -0,0 +1,222 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use IEEE.math_real.ceil; +use IEEE.math_real.floor; +use IEEE.math_real.log2; + +entity conv1d_fxp_MAC_RoundToZero is + generic ( + TOTAL_WIDTH : natural; + FRAC_WIDTH : natural; + VECTOR_WIDTH : natural; + KERNEL_SIZE : natural; + IN_CHANNELS : natural; + OUT_CHANNELS : natural; + X_ADDRESS_WIDTH : natural; + Y_ADDRESS_WIDTH : natural + ); + port ( + clock : in std_logic; + enable : in std_logic; + reset : in std_logic; + x : in std_logic_vector(TOTAL_WIDTH-1 downto 0); + x_address : out std_logic_vector(X_ADDRESS_WIDTH-1 downto 0); + y : out std_logic_vector(TOTAL_WIDTH-1 downto 0); + y_address : in std_logic_vector(Y_ADDRESS_WIDTH-1 downto 0); + done : out std_logic := '0' + ); +end; + +architecture rtl of conv1d_fxp_MAC_RoundToZero is + function ceil_log2(value : in natural) return integer is + variable result : integer; + begin + if value = 1 then + return 1; + else + result := integer(ceil(log2(real(value)))); + return result; + end if; + end function; + + constant FXP_ONE : signed(TOTAL_WIDTH-1 downto 0) := to_signed(2**FRAC_WIDTH,TOTAL_WIDTH); + + signal mac_reset : std_logic; + signal next_sample : std_logic; + signal x1 : signed(TOTAL_WIDTH-1 downto 0); + signal x2 : signed(TOTAL_WIDTH-1 downto 0); + signal sum : signed(TOTAL_WIDTH-1 downto 0); + signal mac_done : std_logic; + type data is array (0 to OUT_CHANNELS*(VECTOR_WIDTH-KERNEL_SIZE+1)-1) of std_logic_vector(TOTAL_WIDTH-1 downto 0); + signal y_ram : data; + + signal n_clock : std_logic; + signal w : std_logic_vector(TOTAL_WIDTH-1 downto 0); + signal b : std_logic_vector(TOTAL_WIDTH-1 downto 0); + signal w_address : std_logic_vector(ceil_log2(OUT_CHANNELS*IN_CHANNELS*KERNEL_SIZE)-1 downto 0); + signal b_address : std_logic_vector(ceil_log2(OUT_CHANNELS)-1 downto 0); + + type t_state is (s_reset, s_data_transfer_MAC, s_MAC_mul_x_w, s_MAC_add_b, s_MAC_get_result, s_reset_mac, s_done); + signal state : t_state; +begin + -- connecting signals to ports + n_clock <= not clock; + + + conv1d_fxp_MAC : entity work.fxp_MAC_RoundToZero + generic map( + VECTOR_WIDTH => KERNEL_SIZE*IN_CHANNELS+1, -- +1 need for Bias + TOTAL_WIDTH => TOTAL_WIDTH, + FRAC_WIDTH => FRAC_WIDTH + ) + port map ( + reset => mac_reset, + next_sample => next_sample, + x1 => x1, + x2 => x2, + sum => sum, + done => mac_done + ); + + main : process (clock) + variable kernel_counter : unsigned(ceil_log2(KERNEL_SIZE+1) downto 0); -- too big integer(round(log2(var-1)) downto 0) + variable input_counter : unsigned(ceil_log2(VECTOR_WIDTH+1) downto 0); -- too big integer(round(log2(var-1)) downto 0) + variable input_channel_counter : unsigned(ceil_log2(IN_CHANNELS+1) downto 0); -- too big integer(round(log2(var-1)) downto 0) + variable output_channel_counter : unsigned(ceil_log2(OUT_CHANNELS+1) downto 0); -- too big integer(round(log2(var-1)) downto 0) + variable bias_added : std_logic; + begin + if reset = '1' then + -- reset such that MAC_enable triggers MAC_enable directly + x_address <= (others => '0'); + w_address <= (others => '0'); + b_address <= (others => '0'); + kernel_counter := (others => '0'); + input_counter := (others => '0'); + input_channel_counter := (others => '0'); + output_channel_counter := (others => '0'); + bias_added := '0'; + next_sample <= '0'; + done <= '0'; + mac_reset <= '0'; + state <= s_reset; + else + if rising_edge(clock) then + if enable = '1' then + if state = s_reset then + report("debug: conv1d_function: state = s_reset"); + mac_reset <= '0'; + -- start first MAC_Computation + next_sample <= '1'; + state <= s_data_transfer_MAC; + elsif state = s_data_transfer_MAC then + report("debug: conv1d_function: state = s_data_transfer_MAC"); + mac_reset <= '1'; + next_sample <= '0'; + if input_counter /= VECTOR_WIDTH-KERNEL_SIZE+1 then + if output_channel_counter /= OUT_CHANNELS then + if input_channel_counter /= IN_CHANNELS then + if kernel_counter /= KERNEL_SIZE then + report("debug: conv1d_function: Input output_c input_c kernel"); + report("debug: conv1d_function: " & to_bstring(input_counter) &" "& to_bstring(output_channel_counter) &" " & to_bstring(input_channel_counter) & " " & to_bstring(kernel_counter)); + x_address <= std_logic_vector(resize(input_channel_counter * VECTOR_WIDTH + kernel_counter + input_counter, x_address'length)); + w_address <= std_logic_vector(resize(input_channel_counter * VECTOR_WIDTH + kernel_counter, w_address'length)); + state <= s_MAC_mul_x_w; + kernel_counter := kernel_counter + 1; + else + kernel_counter := (others => '0'); + input_channel_counter := input_channel_counter + 1; + end if; + elsif bias_added = '0' then + report("debug: conv1d_function: add bias"); + bias_added := '1'; + state <= s_MAC_add_b; + elsif bias_added = '1' then + --read MAC output from last computation and write to y_ram + bias_added := '0'; + state <= s_MAC_get_result; + kernel_counter := (others => '0'); + input_channel_counter := (others => '0'); + output_channel_counter := output_channel_counter + 1; + end if; + else + kernel_counter := (others => '0'); + input_channel_counter := (others => '0'); + output_channel_counter := (others => '0'); + input_counter := input_counter + 1; + end if; + else + state <= s_done; + end if; + elsif state = s_MAC_mul_x_w or state = s_MAC_add_b then + report("debug: conv1d_function: state = mul_x or add_b" ); + next_sample <= '1'; + state <= s_data_transfer_MAC; + elsif state = s_MAC_get_result then + report("debug: conv1d_function: state = s_MAC_get_result"); + next_sample <= '1'; + if mac_done = '1' then + report("debug: conv1d_function: mac: done"); + next_sample <= '0'; + report("debug: conv1d_function: write sum to y_ram"); + report("debug: conv1d_function: sum=" & to_bstring(sum)); + y_ram(to_integer(resize((output_channel_counter-1)*(VECTOR_WIDTH-KERNEL_SIZE+1)+input_counter, y_ram'length))) <= std_logic_vector(sum); + state <= s_reset_MAC; + end if; + elsif state = s_reset_MAC then + report("debug: conv1d_function: state = s_reset_MAC"); + mac_reset <= '0'; + state <= s_data_transfer_MAC; + elsif state = s_done then + report("debug: conv1d_function: state = s_done"); + done <= '1'; + end if; + end if; + end if; + end if; + end process main; + + y_writing : process (clock, state) + begin + if (state = s_done) or (state = s_reset) then + if falling_edge(clock) then + -- After the layer in at idle mode, y is readable + -- but it only update at the falling edge of the clock + y <= y_ram(to_integer(unsigned(y_address))); + end if; + end if; + end process y_writing; + + write_MAC_inputs : process (clock, state) + begin + if rising_edge(clock) then + if state = s_MAC_mul_x_w then + x1 <= signed(x); + x2 <= signed(w); + elsif state = s_MAC_add_b then + x1 <= FXP_ONE; + x2 <= signed(b); + end if; + end if; + end process write_MAC_inputs; + + -- Weights + rom_w : entity work.${rom_name_weights}(rtl) + port map ( + clk => n_clock, + en => '1', + addr => w_address, + data => w + ); + + -- Bias + rom_b : entity work.${rom_name_bias}(rtl) + port map ( + clk => n_clock, + en => '1', + addr => b_address, + data => b + ); + +end; diff --git a/elasticai/creator/nn/fixed_point/conv1d/design.py b/elasticai/creator/nn/fixed_point/conv1d/design.py index 8c0f2b55..959acfbc 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/design.py +++ b/elasticai/creator/nn/fixed_point/conv1d/design.py @@ -10,8 +10,18 @@ from elasticai.creator.vhdl.design.ports import Port from elasticai.creator.vhdl.shared_designs.rom import Rom +from .testbench import Conv1dDesignProtocol -class Conv1d(Design): + +def generate_parameters_from_port(port: Port) -> dict[str, str]: + params = {} + for signal in port: + if signal.width > 0: + params[f"{signal.name}_width"] = str(signal.width) + return params + + +class Conv1dDesign(Design, Conv1dDesignProtocol): def __init__( self, name: str, @@ -33,19 +43,36 @@ def __init__( self._kernel_size = kernel_size self._weights = weights self._bias = bias - self._output_signal_length = math.floor( - self._input_signal_length - self._kernel_size + 1 + self.output_signal_length = math.floor( + self.input_signal_length - self.kernel_size + 1 ) - - @property - def port(self) -> Port: - return create_port( + self._port = create_port( x_width=self._total_bits, y_width=self._total_bits, - x_count=self._input_signal_length * self._in_channels, - y_count=self._output_signal_length * self._out_channels, + x_count=self.input_signal_length * self._in_channels, + y_count=self.output_signal_length * self._out_channels, ) + @property + def input_signal_length(self) -> int: + return self._input_signal_length + + @property + def kernel_size(self) -> int: + return self._kernel_size + + @property + def port(self) -> Port: + return self._port + + @property + def in_channels(self) -> int: + return self._in_channels + + @property + def out_channels(self) -> int: + return self._out_channels + @staticmethod def _flatten_params(params: list[list[list[int]]]) -> list[int]: result = [] @@ -55,20 +82,42 @@ def _flatten_params(params: list[list[list[int]]]) -> list[int]: return result def save_to(self, destination: Path) -> None: + print(self.name) rom_name = dict(weights=f"{self.name}_w_rom", bias=f"{self.name}_b_rom") template = InProjectTemplate( package=module_to_package(self.__module__), file_name="conv1d.tpl.vhd", parameters=dict( - total_bits=str(self._total_bits), - frac_bits=str(self._frac_bits), + frac_width=str(self._frac_bits), in_channels=str(self._in_channels), out_channels=str(self._out_channels), - kernel_size=str(self._kernel_size), - ), + kernel_size=str(self.kernel_size), + vector_width=str(self.input_signal_length), + name=self.name, + ) + | generate_parameters_from_port(self._port), ) destination.create_subpath(self.name).as_file(".vhd").write(template) + core_component = InProjectTemplate( + package=module_to_package(self.__module__), + file_name="conv1d_function.tpl.vhd", + parameters={ + "rom_name_weights": rom_name["weights"], + "rom_name_bias": rom_name["bias"], + }, + ) + destination.create_subpath(f"{self.name}_fxp_MAC_RoundToZero").as_file( + ".vhd" + ).write(core_component) + + mac = InProjectTemplate( + package="elasticai.creator.vhdl.shared_designs.mac.fixed_point", + file_name="fxp_mac.tpl.vhd", + parameters={}, + ) + destination.create_subpath("fxp_mac").as_file(".vhd").write(mac) + weights_rom = Rom( name=rom_name["weights"], data_width=self._total_bits, diff --git a/elasticai/creator/nn/fixed_point/conv1d/design_integration_test.py b/elasticai/creator/nn/fixed_point/conv1d/design_integration_test.py new file mode 100644 index 00000000..df31346c --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/design_integration_test.py @@ -0,0 +1,54 @@ +from elasticai.creator.file_generation.in_memory_path import InMemoryPath, InMemoryFile +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.nn.sequential import Sequential +from elasticai.creator.nn.fixed_point.conv1d import Conv1d +from typing import cast + +import pytest +from elasticai.creator.vhdl.design.design import Design +from elasticai.creator.file_generation.in_memory_path import InMemoryFile, InMemoryPath + +@pytest.fixture +def seq_conv1d_design() -> Design: + return Sequential(Conv1d( + total_bits=16, + frac_bits=8, + in_channels=1, + out_channels=2, + kernel_size=3, + signal_length=4, + )).create_design("network") + +def save_design(design: Design) -> dict[str, str]: + destination = InMemoryPath("network", parent=None) + design.save_to(destination) + files = recursive_children_extraction(destination.children.values()) + return files + +def recursive_children_extraction(destination: dict[str, InMemoryPath| InMemoryFile]) -> dict[str, str | dict]: + data = {} + for dest in destination: + if type(dest) == InMemoryFile: + data[dest.name] = "\n".join(dest.text) + elif type(dest == InMemoryPath): + data[dest.name] = recursive_children_extraction(dest.children.values()) + return data + + +def test_network_generation_1(seq_conv1d_design: Design): + saved_files = save_design(seq_conv1d_design) + print(saved_files) + expected_files = ["conv1d_0", "network.vhd"] + actual_files = list(saved_files.keys()) + assert expected_files == actual_files + +def test_network_generation_2(seq_conv1d_design: Design): + saved_files = save_design(seq_conv1d_design) + expected_files_in_conv1d_0 = ["conv1d_0_w_rom.vhd", "conv1d_0_b_rom.vhd", "conv1d_0.vhd", "conv1d_0_fxp_MAC_RoundToZero.vhd", "fxp_mac.vhd"] + actual_files_in_conv1d0 = list(saved_files['conv1d_0'].keys()) + print(expected_files_in_conv1d_0) + print(actual_files_in_conv1d0) + for item in actual_files_in_conv1d0: + assert item in expected_files_in_conv1d_0 + + diff --git a/elasticai/creator/nn/fixed_point/conv1d/design_test.py b/elasticai/creator/nn/fixed_point/conv1d/design_test.py index 80b1762d..7d9f4276 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/design_test.py +++ b/elasticai/creator/nn/fixed_point/conv1d/design_test.py @@ -4,12 +4,12 @@ from elasticai.creator.file_generation.in_memory_path import InMemoryFile, InMemoryPath -from .design import Conv1d +from .design import Conv1dDesign @pytest.fixture -def conv1d_design() -> Conv1d: - return Conv1d( +def conv1d_design() -> Conv1dDesign: + return Conv1dDesign( name="conv1d", total_bits=16, frac_bits=8, @@ -22,23 +22,23 @@ def conv1d_design() -> Conv1d: ) -def save_design(design: Conv1d) -> dict[str, str]: +def save_design(design: Conv1dDesign) -> dict[str, str]: destination = InMemoryPath("conv1d", parent=None) design.save_to(destination) files = cast(list[InMemoryFile], list(destination.children.values())) return {file.name: "\n".join(file.text) for file in files} -def test_saved_design_contains_needed_files(conv1d_design: Conv1d) -> None: +def test_saved_design_contains_needed_files(conv1d_design: Conv1dDesign) -> None: saved_files = save_design(conv1d_design) - expected_files = {"conv1d_w_rom.vhd", "conv1d_b_rom.vhd", "conv1d.vhd"} + expected_files = {"conv1d_w_rom.vhd", "conv1d_b_rom.vhd", "conv1d.vhd", "conv1d_fxp_MAC_RoundToZero.vhd", "fxp_mac.vhd"} actual_files = set(saved_files.keys()) assert expected_files == actual_files -def test_weight_rom_code_generated_correctly(conv1d_design: Conv1d) -> None: +def test_weight_rom_code_generated_correctly(conv1d_design: Conv1dDesign) -> None: expected_code = """library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; @@ -70,7 +70,7 @@ def test_weight_rom_code_generated_correctly(conv1d_design: Conv1d) -> None: assert expected_code == actual_code -def test_bias_rom_code_generated_correctly(conv1d_design: Conv1d) -> None: +def test_bias_rom_code_generated_correctly(conv1d_design: Conv1dDesign) -> None: expected_code = """library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; @@ -101,14 +101,3 @@ def test_bias_rom_code_generated_correctly(conv1d_design: Conv1d) -> None: actual_code = saved_files["conv1d_b_rom.vhd"] assert expected_code == actual_code - -def test_conv1d_code_generated_correctly(conv1d_design: Conv1d) -> None: - expected_code = """-- Dummy File for testing implementation of conv1d Design -16 -8 -1 -2 -3""" - saved_files = save_design(conv1d_design) - actual_code = saved_files["conv1d.vhd"] - assert expected_code == actual_code diff --git a/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d.py b/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d.py index bd27925d..d8450042 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d.py +++ b/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d.py @@ -8,7 +8,7 @@ from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( FixedPointConfig, ) -from elasticai.creator.nn.fixed_point.conv1d.design import Conv1d as Conv1dDesign +from elasticai.creator.nn.fixed_point.conv1d.design import Conv1dDesign class BatchNormedConv1d(DesignCreatorModule): @@ -68,20 +68,19 @@ def bn_bias(self) -> torch.Tensor: return self._batch_norm.bias def forward(self, x: torch.Tensor) -> torch.Tensor: - has_batches = x.dim() == 2 - input_shape = ( - (x.shape[0], self._conv1d.in_channels, -1) - if has_batches - else (1, self._conv1d.in_channels, -1) - ) - output_shape = (x.shape[0], -1) if has_batches else (-1,) + has_batches = x.dim() == 3 + + if not has_batches: + x = x.view(1, *x.shape) - x = x.view(*input_shape) x = self._conv1d(x) x = self._batch_norm(x) x = self._operations.quantize(x) - return x.view(*output_shape) + if not has_batches: + x = x.squeeze(dim=0) + + return x def create_design(self, name: str) -> Conv1dDesign: def float_to_signed_int(value: float | list) -> int | list: diff --git a/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d_test.py b/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d_test.py index 53df45cd..66f53816 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d_test.py +++ b/elasticai/creator/nn/fixed_point/conv1d/layer/batch_normed_conv1d_test.py @@ -1,4 +1,3 @@ -import pytest import torch from .batch_normed_conv1d import BatchNormedConv1d @@ -12,37 +11,25 @@ def conv1d(signal_length: int, bias: bool, affine: bool) -> BatchNormedConv1d: signal_length=signal_length, bias=bias, in_channels=1, - out_channels=1, + out_channels=2, bn_affine=affine, bn_momentum=1, ) -@pytest.fixture -def batched_input() -> torch.Tensor: - return torch.rand(3, 15) - - -def test_that_output_is_flat_for_unbatched_input() -> None: +def test_output_contains_correct_number_of_output_channels() -> None: conv = conv1d(signal_length=15, bias=False, affine=False) - input_data = torch.rand(15) + input_data = torch.rand(1, 15) prediction = conv(input_data) - tensor_rank = prediction.dim() - flat_tensor_rank = 1 - assert flat_tensor_rank == tensor_rank + num_channels, _ = prediction.shape + print(prediction) + assert num_channels == 2 -def test_that_batch_dimension_is_kept(batched_input: torch.Tensor) -> None: +def test_that_batch_dimension_is_kept() -> None: conv = conv1d(signal_length=15, bias=False, affine=False) - prediction = conv(batched_input) + input_data = torch.rand(3, 1, 15) + prediction = conv(input_data) + print(prediction.shape) batch_dimension = prediction.shape[0] - expected_batch_dimension = batched_input.shape[0] - assert expected_batch_dimension == batch_dimension - - -def test_that_batched_output_is_flat(batched_input: torch.Tensor) -> None: - conv = conv1d(signal_length=15, bias=False, affine=False) - prediction = conv(batched_input) - tensor_rank = prediction.dim() - expected_rank = 2 - assert expected_rank == tensor_rank + assert batch_dimension == 3 diff --git a/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d.py b/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d.py index 5d9e163c..cf4273b3 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d.py +++ b/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d.py @@ -8,7 +8,8 @@ from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( FixedPointConfig, ) -from elasticai.creator.nn.fixed_point.conv1d.design import Conv1d as Conv1dDesign +from elasticai.creator.nn.fixed_point.conv1d.design import Conv1dDesign +from elasticai.creator.nn.fixed_point.conv1d.testbench import Conv1dTestbench class Conv1d(DesignCreatorModule, Conv1dBase): @@ -34,20 +35,6 @@ def __init__( device=device, ) - def forward(self, x: torch.Tensor) -> torch.Tensor: - has_batches = x.dim() == 2 - - input_shape = ( - (x.shape[0], self.in_channels, -1) - if has_batches - else (self.in_channels, -1) - ) - output_shape = (x.shape[0], -1) if has_batches else (-1,) - - x = x.view(*input_shape) - outputs = super().forward(x) - return outputs.view(*output_shape) - def create_design(self, name: str) -> Conv1dDesign: def float_to_signed_int(value: float | list) -> int | list: if isinstance(value, list): @@ -74,3 +61,6 @@ def flatten_tuple(x: int | tuple[int, ...]) -> int: weights=signed_int_weights, bias=signed_int_bias, ) + + def create_testbench(self, name: str, uut: Conv1dDesign) -> Conv1dTestbench: + return Conv1dTestbench(name=name, uut=uut, fxp_params=self._config) diff --git a/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d_test.py b/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d_test.py index eaeb6430..4b80c26b 100644 --- a/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d_test.py +++ b/elasticai/creator/nn/fixed_point/conv1d/layer/conv1d_test.py @@ -1,10 +1,6 @@ -from typing import cast - import pytest import torch -from elasticai.creator.file_generation.in_memory_path import InMemoryFile, InMemoryPath - from .conv1d import Conv1d @@ -21,22 +17,46 @@ def conv1d() -> Conv1d: ) -def conv_with_one_weights(signal_length: int) -> Conv1d: - conv = Conv1d( - total_bits=16, - frac_bits=8, - in_channels=1, - out_channels=1, - bias=False, - signal_length=signal_length, - kernel_size=2, - ) - conv.weight.data = torch.ones_like(conv.weight) - return conv +@pytest.fixture +def build_5_total_1_frac_conv1d(): + def build(in_channels, out_channels, kernel_size, signal_length): + return Conv1d( + total_bits=5, + frac_bits=1, + in_channels=in_channels, + out_channels=out_channels, + kernel_size=kernel_size, + signal_length=signal_length, + ) + + return build + + +@pytest.fixture +def to_1d_input_tensor(): + def get_list_nesting_depth(l): + level = 0 + while isinstance(l, list): + level += 1 + if len(l) > 0: + l = l[0] + else: + break + return level + + def convert(data: list): + correctly_nested = data + actual_depth = get_list_nesting_depth(data) + required_depth = 3 + for _ in range(required_depth - actual_depth): + correctly_nested = [correctly_nested] + return torch.tensor(correctly_nested) + + return convert @pytest.fixture -def conv_with_limited_precision() -> Conv1d: +def conv_with_4_total_1_frac_and_kernel_size_2() -> Conv1d: return Conv1d( total_bits=4, frac_bits=1, @@ -49,25 +69,39 @@ def conv_with_limited_precision() -> Conv1d: @pytest.fixture -def batched_input() -> torch.Tensor: +def tensor_of_size_3_15() -> torch.Tensor: return torch.rand(3, 15) -def test_that_output_is_flat_for_unbatched_input(conv1d: Conv1d) -> None: - input_data = torch.rand(15) - prediction = conv1d(input_data) - tensor_rank = prediction.dim() - flat_tensor_rank = 1 - assert tensor_rank == flat_tensor_rank +@pytest.fixture +def batched_input(tensor_of_size_3_15): + return tensor_of_size_3_15 + + +@pytest.fixture +def tensor_of_size_3_5_7() -> torch.Tensor: + return torch.rand(3, 5, 7) def test_that_batch_dimension_is_kept( - conv1d: Conv1d, batched_input: torch.Tensor + build_5_total_1_frac_conv1d, batched_input: torch.Tensor ) -> None: - prediction = conv1d(batched_input) - batch_dimension = prediction.shape[0] - expected_batch_dimension = batched_input.shape[0] - assert batch_dimension == expected_batch_dimension + in_channels = 5 + signal_length = 7 + batch_size = 3 + kernel_size = 2 + out_channels = 9 + input_data = torch.rand(batch_size, in_channels, signal_length) + conv1d = build_5_total_1_frac_conv1d( + in_channels=in_channels, + out_channels=out_channels, + kernel_size=kernel_size, + signal_length=signal_length, + ) + prediction = conv1d(input_data) + expected_size = (batch_size, out_channels, signal_length - kernel_size + 1) + + assert expected_size == prediction.size() def test_that_batched_output_is_flat( @@ -87,27 +121,46 @@ def test_that_batched_output_is_flat( ], ) def test_ones_weight_kernel_convolution( - signal_length: int, inputs: list[float], expected: list[float] + signal_length: int, inputs: list[float], expected: list[float], to_1d_input_tensor ) -> None: - input_tensor = torch.tensor(inputs) - prediction = conv_with_one_weights(signal_length)(input_tensor) + input_tensor = to_1d_input_tensor(inputs) + conv = Conv1d( + total_bits=16, + frac_bits=8, + in_channels=1, + out_channels=1, + bias=False, + signal_length=signal_length, + kernel_size=2, + ) + conv.weight.data = torch.ones_like(conv.weight) + prediction = conv(input_tensor) + expected = to_1d_input_tensor(expected).tolist() assert expected == prediction.tolist() -def test_no_overflow_after_multiplication(conv_with_limited_precision: Conv1d) -> None: - conv = conv_with_limited_precision +def test_no_overflow_after_multiplication( + conv_with_4_total_1_frac_and_kernel_size_2, to_1d_input_tensor +) -> None: + conv = conv_with_4_total_1_frac_and_kernel_size_2 conv.weight.data = 3.5 * torch.ones_like(conv.weight) - prediction = conv(torch.tensor([3.5, -3])) - expected = 1.5 # quantize(3.5 * 3.5 - 3 * 3.5) == quantize(1.75) == 1.5 - assert [expected] == prediction.tolist() + prediction = conv(to_1d_input_tensor([3.5, -3])) + expected = to_1d_input_tensor( + 1.5 + ).tolist() # quantize(3.5 * 3.5 - 3 * 3.5) == quantize(1.75) == 1.5 + assert expected == prediction.tolist() -def test_no_underflow_after_multiplication(conv_with_limited_precision: Conv1d) -> None: - conv = conv_with_limited_precision +def test_no_underflow_after_multiplication( + conv_with_4_total_1_frac_and_kernel_size_2, to_1d_input_tensor +) -> None: + conv = conv_with_4_total_1_frac_and_kernel_size_2 conv.weight.data = 0.5 * torch.ones_like(conv.weight) - prediction = conv(torch.tensor([0.5, 0])) - expected = 0 # quantize(0.5 * 0.5 + 0.5 * 0) == quantize(0.25) == 0 - assert [expected] == prediction.tolist() + prediction = conv(to_1d_input_tensor([0.5, 0])) + expected = to_1d_input_tensor( + 0 + ).tolist() # quantize(0.5 * 0.5 + 0.5 * 0) == quantize(0.25) == 0 + assert expected == prediction.tolist() @pytest.mark.parametrize( @@ -115,16 +168,20 @@ def test_no_underflow_after_multiplication(conv_with_limited_precision: Conv1d) [([2.0, 2.0], [3.5]), ([-2.0, -3.0], [-4.0])], ) def test_fxp_operations_additive_over_and_underflow( - conv_with_limited_precision: Conv1d, inputs: list[float], expected: list[float] + conv_with_4_total_1_frac_and_kernel_size_2, + inputs: list[float], + expected: list[float], + to_1d_input_tensor, ) -> None: - conv = conv_with_limited_precision + conv = conv_with_4_total_1_frac_and_kernel_size_2 conv.weight.data = torch.ones_like(conv.weight) - input_tensor = torch.tensor(inputs) + input_tensor = torch.tensor(to_1d_input_tensor(inputs)) prediction = conv(input_tensor) + expected = to_1d_input_tensor(expected).tolist() assert expected == prediction.tolist() -def test_bias_addition() -> None: +def test_ensure_bias_is_0_5(to_1d_input_tensor) -> None: conv = Conv1d( total_bits=4, frac_bits=1, @@ -136,22 +193,7 @@ def test_bias_addition() -> None: ) conv.weight.data = torch.ones_like(conv.weight) conv.bias.data = 0.5 * torch.ones_like(conv.bias) # type: ignore - inputs = torch.tensor([0.0, 0.0]) - predictions = conv(inputs) - assert predictions.tolist() == [0.5] - - -def test_conv1d_layer_creates_correct_design(conv1d: Conv1d) -> None: - expected_conv1d_code = """-- Dummy File for testing implementation of conv1d Design -16 -8 -3 -4 -2""" - - design = conv1d.create_design("conv1d") - destination = InMemoryPath("conv1d", parent=None) - design.save_to(destination) - actual_conv1d_code = "\n".join(cast(InMemoryFile, destination["conv1d"]).text) - - assert expected_conv1d_code == actual_conv1d_code + inputs = to_1d_input_tensor([0.0, 0.0]) + predictions = conv(inputs).tolist() + expected = to_1d_input_tensor(0.5).tolist() + assert expected == predictions diff --git a/elasticai/creator/nn/fixed_point/conv1d/rom/design.py b/elasticai/creator/nn/fixed_point/conv1d/rom/design.py new file mode 100644 index 00000000..3fcb5086 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/rom/design.py @@ -0,0 +1,5 @@ +class Rom: + def __init__(self, name: str, data_width: int, + values: list[int]) -> None: + self._name = name + self._data_width = data_width \ No newline at end of file diff --git a/elasticai/creator/nn/fixed_point/conv1d/simulation_test.py b/elasticai/creator/nn/fixed_point/conv1d/simulation_test.py new file mode 100644 index 00000000..aa91f506 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/simulation_test.py @@ -0,0 +1,79 @@ +import csv +import pathlib +from typing import Any + +import pytest +import torch + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator +from elasticai.creator.vhdl.simulated_layer import SimulatedLayer + +from .layer import Conv1d + + +def create_ones_conv1d_input_list( + batch_size: int, in_channels: int, signal_length: int +): + return [[[1.0] * signal_length] * in_channels] * batch_size + + +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", ([[[0.0, 1.0, 1.0]]], [[[1.0, 1.0, 1.0]]], [[[2.0, 1.0, 0.0]]]) +) +def test_verify_hw_sw_equivalence_3_inputs(x): + input_data = torch.Tensor(x) + sw_conv = Conv1d( + total_bits=4, + frac_bits=1, + in_channels=1, + out_channels=1, + signal_length=3, + kernel_size=2, + bias=True, + ) + sw_conv.weight.data = torch.ones_like(sw_conv.weight) + sw_conv.bias.data = torch.ones_like(sw_conv.bias) + sw_output = sw_conv(input_data) + design = sw_conv.create_design("conv1d") + testbench = sw_conv.create_testbench("conv1d_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim_layer = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + sim_output = sim_layer(input_data) + assert sw_output.tolist() == sim_output + + +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", + ( + create_ones_conv1d_input_list(1, 2, 4), + [[[0.5, 0.25, -1.0, 1.0], [-1.0, 1.0, -1.0, 1.0]]], + [[[0.0, 1.0, 1.0, 0.0], [-1.0, 1.0, -1.0, 1.0]]], + ), +) +def test_verify_hw_sw_equivalence_4_inputs(x): + input_data = torch.Tensor(x) + sw_conv = Conv1d( + total_bits=5, + frac_bits=2, + in_channels=2, + out_channels=2, + signal_length=4, + kernel_size=2, + bias=True, + ) + sw_conv.weight.data = torch.ones_like(sw_conv.weight) + sw_conv.bias.data = torch.ones_like(sw_conv.bias) + sw_output = sw_conv(input_data) + design = sw_conv.create_design("conv1d") + testbench = sw_conv.create_testbench("conv1d_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim_layer = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + sim_output = sim_layer(input_data) + assert sw_output.tolist() == sim_output diff --git a/elasticai/creator/nn/fixed_point/conv1d/testbench.py b/elasticai/creator/nn/fixed_point/conv1d/testbench.py new file mode 100644 index 00000000..90e0838e --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/testbench.py @@ -0,0 +1,153 @@ +import math +from abc import abstractmethod +from collections import defaultdict +from typing import Protocol + +from elasticai.creator.file_generation.savable import Path +from elasticai.creator.file_generation.template import ( + InProjectTemplate, + module_to_package, +) +from elasticai.creator.nn.fixed_point.number_converter import FXPParams, NumberConverter +from elasticai.creator.vhdl.design.ports import Port +from elasticai.creator.vhdl.simulated_layer import Testbench + + +class Conv1dDesignProtocol(Protocol): + @property + @abstractmethod + def name(self) -> str: + ... + + @property + @abstractmethod + def input_signal_length(self) -> int: + ... + + @property + @abstractmethod + def port(self) -> Port: + ... + + @property + @abstractmethod + def kernel_size(self) -> int: + ... + + @property + @abstractmethod + def in_channels(self) -> int: + ... + + @property + @abstractmethod + def out_channels(self) -> int: + ... + + +class Conv1dTestbench(Testbench): + def __init__(self, name: str, uut: Conv1dDesignProtocol, fxp_params: FXPParams): + self._converter = NumberConverter(fxp_params) + self._converter_for_batch = NumberConverter( + FXPParams(8, 0) + ) # max for 255 lines of inputs + self._name = name + self._uut_name = uut.name + self._input_signal_length = uut.input_signal_length + self._in_channels = uut.in_channels + self._out_channels = uut.out_channels + self._x_address_width = uut.port["x_address"].width + self._fxp_params = fxp_params + self._converter = NumberConverter(self._fxp_params) + self._kernel_size = uut.kernel_size + self._output_signal_length = math.floor( + self._input_signal_length - self._kernel_size + 1 + ) + self._y_address_width = uut.port["y_address"].width + + def save_to(self, destination: Path): + template = InProjectTemplate( + package=module_to_package(self.__module__), + file_name="testbench.tpl.vhd", + parameters={ + "testbench_name": self.name, + "input_signal_length": str(self._input_signal_length), + "in_channels": str(self._in_channels), + "out_channels": str(self._out_channels), + "total_bits": str(self._fxp_params.total_bits), + "x_address_width": str(self._x_address_width), + "output_signal_length": str(self._output_signal_length), + "y_address_width": str(self._y_address_width), + "uut_name": self._uut_name, + }, + ) + destination.create_subpath(self.name).as_file(".vhd").write(template) + + @property + def name(self) -> str: + return self._name + + def prepare_inputs(self, *inputs) -> list[dict]: + batches = inputs[0] + prepared_inputs = [] + for batch in batches: + prepared_inputs.append({}) + for channel_id, channel in enumerate(batch): + for time_step_id, time_step_val in enumerate(channel): + prepared_inputs[-1][f"x_{channel_id}_{time_step_id}"] = ( + self._converter.rational_to_bits(time_step_val) + ) + + return prepared_inputs + + def parse_reported_content(self, content: list[str]) -> list[list[list[float]]]: + """ + This function parses the reported content, which is just a list of strings. + All lines starting with 'output_text:' are considered as a result of the testbench. + These results will be stacked for each batch. + So you get a list[list[list[float]]] which is similar to batch[out channels[output neurons[float]]]. + For each item reported it is checked if the string starts with 'result: '. + If so the remaining part will be split by ','. The first number gives the batch. The second the result. + The channels are greedy guessed. + We do so by taking the first X-values, where X is the number of values per channel. + After we have enough values for the channel, we increase the channel number. + If you report not enough values per channel, this will look like the last channel has not reported enough values. + """ + + def split_list(a_list): + print("len(a_list): ", len(a_list)) + print("self._out_channels: ", self._out_channels) + out_channel_length = len(a_list) // self._out_channels + new_list = list() + out_channel_counter = ( + -1 + ) # start with -1 because it will be increased in first iteration of loop + for i, value in enumerate(a_list): + if i % out_channel_length == 0: + new_list.append(list()) + out_channel_counter += 1 + new_list[out_channel_counter].append(value) + return new_list + + results_dict = defaultdict(list) + print() + for line in map(str.strip, content): + if line.startswith("result: "): + batch_text = line.split(":")[1].split(",")[0][1:] + output_text = line.split(":")[1].split(",")[1][0:] + print("output_text: ", output_text) + batch = int(self._converter_for_batch.bits_to_rational(batch_text)) + if "U" not in line.split(":")[1].split(",")[1][1:]: + output = self._converter.bits_to_rational(output_text) + else: + output = output_text + results_dict[batch].append(output) + else: + print(line) + results = list() + for x in results_dict.items(): + results.append(split_list(x[1])) + print("results: ", results) + if len(results) is 0: + raise Exception(content) + return list(results) diff --git a/elasticai/creator/nn/fixed_point/conv1d/testbench.tpl.vhd b/elasticai/creator/nn/fixed_point/conv1d/testbench.tpl.vhd new file mode 100644 index 00000000..7a24407a --- /dev/null +++ b/elasticai/creator/nn/fixed_point/conv1d/testbench.tpl.vhd @@ -0,0 +1,147 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use ieee.std_logic_textio.all; +use std.env.finish; + +entity ${testbench_name} is + generic ( + INPUTS_FILE_PATH: string + ); +end; + +architecture rtl of ${testbench_name} is + + --CLOCK + signal clock_period : time := 2 ns; + + --DATA INPUT + type data is array (0 to ${input_signal_length}*${in_channels}-1) of std_logic_vector(${total_bits}-1 downto 0); + signal data_in : data; + file input_file : text open read_mode is INPUTS_FILE_PATH; + + --UUT + signal clock : std_logic := '0'; + signal enable : std_logic := '0'; + signal x : std_logic_vector(${total_bits}-1 downto 0); + signal x_address : std_logic_vector(${x_address_width}-1 downto 0) := (others => '0'); + signal x_address_std : std_logic_vector(${x_address_width}-1 downto 0); + signal y : std_logic_vector(${total_bits}-1 downto 0); + signal y_address : std_logic_vector(${y_address_width}-1 downto 0) := (others => '0'); + signal y_address_std : std_logic_vector(${y_address_width}-1 downto 0); + signal done : std_logic; + +begin + x_address <= x_address_std; + y_address_std <= y_address; + + UUT : entity work.${uut_name} + port map (clock => clock, enable => enable, x => x, x_address => x_address_std, y => y, y_address => y_address_std, done => done); + + x_writing : process (clock) + begin + if falling_edge(clock) then + -- After the layer in at idle mode, x is readable + -- but it only update at the falling edge of the clock + --report("debug: testbench: x_address " & to_bstring(x_address)); + x <= data_in(to_integer(unsigned(x_address))); + end if; + end process x_writing; + + + + clk : process + begin + clock <= not clock; + wait for clock_period/2; + end process; + + start_test : process (clock) + variable v_ILINE : line; + variable v_in : std_logic_vector(${total_bits}-1 downto 0); + variable v_SPACE : character; + variable input_idx : integer range 0 to ${input_signal_length}*${in_channels} := 0; + type TYPE_STATE is (s_start_up, s_load_batch, s_reset, s_start_computation, s_wait_for_computation_done, s_write_uut_output_address, s_read_uut_output, s_finish_simulation); + variable test_state : TYPE_STATE := s_start_up; + variable input_cycles : signed(7 downto 0) := (others => '0'); --max for 255 lines of inputs + begin + if rising_edge(clock) then + if test_state = s_start_up then + report "status: reading file " & INPUTS_FILE_PATH; + --file_open(input_file, INPUTS_FILE_PATH, read_mode); + readline(input_file, v_ILINE); -- read header + test_state := s_load_batch; + elsif test_state = s_load_batch then + if endfile(input_file) and input_idx = ${input_signal_length}*${in_channels} then + test_state := s_finish_simulation; + else + if input_idx = 0 then + report "status: start reading batch"; + readline(input_file, v_ILINE); + end if; + read(v_ILINE, v_in); -- read value + data_in(input_idx) <= v_in; + report("status: reading " & to_bstring(v_in)); + if input_idx /= ${input_signal_length}*${in_channels}-1 then + read(v_ILINE, v_SPACE); + else + report "status: data for batch loaded!"; + test_state := s_reset; + end if; + input_idx := input_idx + 1; + end if; + elsif test_state = s_reset then + report "status: test_state = s_reset"; + enable <= '0'; + test_state := s_start_computation; + y_address <= (others => '0'); + elsif test_state = s_start_computation then + report "status: test_state = s_start_computation"; + enable <= '1'; + test_state := s_wait_for_computation_done; + elsif test_state = s_wait_for_computation_done then + --report "status: test_state = s_wait_for_computation_done"; + if done = '1' then + report "status: computation finished"; + test_state := s_read_uut_output; + y_address <= (others => '0'); + enable <= '0'; + end if; + elsif test_state = s_write_uut_output_address then + report("status: test_state = s_write_uut_output_address"); + y_address <= std_logic_vector(unsigned(y_address) + 1); + test_state := s_read_uut_output; + elsif test_state = s_read_uut_output then + report("status: test_state = s_read_uut_output"); + report("status: " & to_bstring(input_cycles) & "," & to_bstring(y)); + report("result: " & to_bstring(input_cycles) & "," & to_bstring(y)); + if unsigned(y_address) /= ${output_signal_length}*${out_channels}-1 then + test_state := s_write_uut_output_address; + else + input_cycles := input_cycles + 1; + test_state := s_load_batch; + end if; + elsif test_state = s_finish_simulation then + report "status: test_state = s_finish_simulation"; + report "status: simulation finished"; + finish; + end if; + end if; + end process; + + end_after_100cycles : process (clock) + variable i : integer range 0 to 10000; + begin + if rising_edge(clock) then + if i = 200 then + report("OUT of TIME"); + finish; + else + i := i + 1; + end if; + end if; + end process; + + +end; diff --git a/elasticai/creator/nn/fixed_point/linear/_testbench_test.py b/elasticai/creator/nn/fixed_point/linear/_testbench_test.py new file mode 100644 index 00000000..60e7de67 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/linear/_testbench_test.py @@ -0,0 +1,102 @@ +from typing import Any, Callable + +import pytest +import torch + +from elasticai.creator.vhdl.auto_wire_protocols.port_definitions import create_port +from elasticai.creator.vhdl.design.ports import Port + +from ..number_converter import FXPParams, NumberConverter +from .testbench import LinearTestbench +from .design import LinearDesign + + +class DummyLinear: + def __init__(self, fxp_params: FXPParams, in_signal_length: int, out_signal_length: int): + self.name: str = "linear0" + self.in_feature_num = in_signal_length + self.out_feature_num = out_signal_length + self.data_width = fxp_params.total_bits + self.frac_width = fxp_params.frac_bits + self.port: Port = create_port( + y_width=fxp_params.total_bits, + x_width=fxp_params.total_bits, + x_count=1, + y_count=2, + ) + + +def parameters_for_reported_content_parsing(fxp_params, input_expected_pairs): + def add_expected_prefix_to_pairs(pairs): + _converter_for_batch = NumberConverter( + FXPParams(8, 0) + ) # max for 255 lines of inputs + pairs_with_prefix = list() + for i, (pairs_text, pairs_number) in enumerate(pairs): + pairs_with_prefix.append(list()) + pairs_with_prefix[i].append(list()) + pairs_with_prefix[i].append(pairs_number) + for batch_number, batch_channel_text in enumerate(pairs_text): + for out_channel_text in batch_channel_text: + for value_text in out_channel_text: + pairs_with_prefix[i][0].append( + f"result: {_converter_for_batch.integer_to_bits(batch_number)}," + f" {value_text}" + ) + return pairs_with_prefix + + pairs_with_prefix = [ + (fxp_params, a, b) + for a, b in add_expected_prefix_to_pairs(input_expected_pairs) + ] + return pairs_with_prefix + + +@pytest.fixture +def create_uut() -> Callable[[FXPParams, int, int], LinearDesign]: + def create(fxp_params: FXPParams, in_signal_length: int, out_signal_length: int) -> LinearDesign: + return DummyLinear(fxp_params=fxp_params, in_signal_length=in_signal_length, out_signal_length=out_signal_length) + + return create + + +@pytest.mark.parametrize( + "fxp_params, reported, y", ( + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=3, frac_bits=0), + input_expected_pairs=[ + ([[["010"]]], [[[2.0]]]), + ([[["001", "010"]]], [[[1.0, 2.0]]]), + ([[["111", "001"]]], [[[-1.0, 1.0]]]), + ] + ) + + parameters_for_reported_content_parsing( + fxp_params=FXPParams(total_bits=4, frac_bits=1), + input_expected_pairs=[ + ([[["0001", "1111"]]], [[[0.5, -0.5]]]), + ([[["0001", "0011", "1000", "1111"]]], [[[0.5, 1.5, -4.0, -0.5]]]), + ] + ) + ) +) +def test_parse_reported_content_one_out_channel(fxp_params, reported, y, create_uut): + in_signal_length = None + out_signal_length = 1 + bench = LinearTestbench( + name="linear_testbench", uut=create_uut(fxp_params, in_signal_length, out_signal_length) + ) + print(f"{reported=}") + assert y == bench.parse_reported_content(reported) + + +def test_input_preparation_with_one_in_channel(create_uut): + fxp_params = FXPParams(total_bits=3, frac_bits=0) + in_signal_length = 1 + out_signal_length = None + bench = LinearTestbench( + name="linear_testbench", uut=create_uut(fxp_params, in_signal_length, out_signal_length) + ) + input = torch.Tensor([[[1.0, 1.0]]]) + expected = [{"x_0_0": "001", "x_0_1": "001"}] + assert expected == bench.prepare_inputs(input.tolist()) + diff --git a/elasticai/creator/nn/fixed_point/linear/design.py b/elasticai/creator/nn/fixed_point/linear/design.py index 54339106..80908265 100644 --- a/elasticai/creator/nn/fixed_point/linear/design.py +++ b/elasticai/creator/nn/fixed_point/linear/design.py @@ -10,8 +10,10 @@ from elasticai.creator.vhdl.design.ports import Port from elasticai.creator.vhdl.shared_designs.rom import Rom +from .testbench import LinearDesignProtocol -class Linear(Design): + +class LinearDesign(Design, LinearDesignProtocol): def __init__( self, *, @@ -26,17 +28,38 @@ def __init__( resource_option: str = "auto", ) -> None: super().__init__(name=name) + self._name = name self.weights = weights self.bias = bias - self.in_feature_num = in_feature_num - self.out_feature_num = out_feature_num + self._in_feature_num = in_feature_num + self._out_feature_num = out_feature_num self.work_library_name = work_library_name self.resource_option = resource_option - self.frac_width = frac_bits - self.data_width = total_bits + self._frac_width = frac_bits + self._data_width = total_bits self.x_addr_width = self.port["x_address"].width self.y_addr_width = self.port["y_address"].width + @property + def name(self): + return self._name + + @property + def in_feature_num(self) -> int: + return self._in_feature_num + + @property + def out_feature_num(self) -> int: + return self._out_feature_num + + @property + def frac_width(self) -> int: + return self._frac_width + + @property + def data_width(self) -> int: + return self._data_width + @property def port(self) -> Port: return create_port( @@ -75,6 +98,7 @@ def save_to(self, destination: Path): bias_rom_name=rom_name["bias"], work_library_name=self.work_library_name, resource_option=f'"{self.resource_option}"', + log2_max_value="31", **self._template_parameters(), ), ) diff --git a/elasticai/creator/nn/fixed_point/linear/design_test.py b/elasticai/creator/nn/fixed_point/linear/design_test.py index 58182829..59be3af3 100644 --- a/elasticai/creator/nn/fixed_point/linear/design_test.py +++ b/elasticai/creator/nn/fixed_point/linear/design_test.py @@ -4,12 +4,12 @@ from elasticai.creator.file_generation.in_memory_path import InMemoryFile, InMemoryPath -from .design import Linear +from .design import LinearDesign @pytest.fixture -def linear_design() -> Linear: - return Linear( +def linear_design() -> LinearDesign: + return LinearDesign( name="linear", in_feature_num=3, out_feature_num=2, @@ -20,14 +20,14 @@ def linear_design() -> Linear: ) -def save_design(design: Linear) -> dict[str, str]: +def save_design(design: LinearDesign) -> dict[str, str]: destination = InMemoryPath("linear", parent=None) design.save_to(destination) files = cast(list[InMemoryFile], list(destination.children.values())) return {file.name: "\n".join(file.text) for file in files} -def test_saved_design_contains_needed_files(linear_design: Linear) -> None: +def test_saved_design_contains_needed_files(linear_design: LinearDesign) -> None: saved_files = save_design(linear_design) expected_files = {"linear_w_rom.vhd", "linear_b_rom.vhd", "linear.vhd"} @@ -36,7 +36,7 @@ def test_saved_design_contains_needed_files(linear_design: Linear) -> None: assert expected_files == actual_files -def test_weight_rom_code_generated_correctly(linear_design: Linear) -> None: +def test_weight_rom_code_generated_correctly(linear_design: LinearDesign) -> None: expected_code = """library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; @@ -68,7 +68,7 @@ def test_weight_rom_code_generated_correctly(linear_design: Linear) -> None: assert expected_code == actual_code -def test_bias_rom_code_generated_correctly(linear_design: Linear) -> None: +def test_bias_rom_code_generated_correctly(linear_design: LinearDesign) -> None: expected_code = """library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; @@ -100,7 +100,7 @@ def test_bias_rom_code_generated_correctly(linear_design: Linear) -> None: assert expected_code == actual_code -def test_linear_code_generated_correctly(linear_design: Linear) -> None: +def test_linear_code_generated_correctly(linear_design: LinearDesign) -> None: expected_code = """library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- for type conversions @@ -169,12 +169,12 @@ def test_linear_code_generated_correctly(linear_design: Linear) -> None: return TEMP2; end function; - -- Log2 funtion is for calculating the bitwidth of the address lines + -- Log2 function is for calculating the bitwidth of the address lines -- for bias and weights rom function log2(val : INTEGER) return natural is variable res : natural; begin - for i in 0 to 31 loop + for i in 1 to 31 loop if (val <= (2 ** i)) then res := i; exit; @@ -207,9 +207,9 @@ def test_linear_code_generated_correctly(linear_design: Linear) -> None: -- simple solution for the output buffer type t_y_array is array (0 to OUT_FEATURE_NUM) of std_logic_vector(DATA_WIDTH-1 downto 0); - shared variable y_ram : t_y_array; + signal y_ram : t_y_array; attribute rom_style : string; - attribute rom_style of y_ram : variable is RESOURCE_OPTION; + attribute rom_style of y_ram : signal is RESOURCE_OPTION; begin @@ -223,7 +223,7 @@ def test_linear_code_generated_correctly(linear_design: Linear) -> None: -- connects ports reset <= not enable; - linear_main : process (clock, enable) + linear_main : process (clock, enable, reset) variable current_neuron_idx : integer range 0 to OUT_FEATURE_NUM-1 := 0; variable current_input_idx : integer range 0 to IN_FEATURE_NUM-1 := 0; variable var_addr_w : integer range 0 to OUT_FEATURE_NUM*IN_FEATURE_NUM-1 := 0; @@ -272,19 +272,17 @@ def test_linear_code_generated_correctly(linear_design: Linear) -> None: state <= s_stop; else state <= s_idle; - current_neuron_idx := 0; + done <= '1'; end if; end if; - else - done <= '1'; end if; var_sum := multiply_accumulate(var_w, var_x, var_y); macc_sum <= var_sum; if y_write_en='1'then - y_ram(var_y_write_idx) := std_logic_vector(cut_down(var_sum)); + y_ram(var_y_write_idx) <= std_logic_vector(cut_down(var_sum)); y_write_en := '0'; end if; @@ -297,7 +295,7 @@ def test_linear_code_generated_correctly(linear_design: Linear) -> None: y_reading : process (clock, state) begin - if state=s_idle then + if (state=s_idle) or (state=s_stop) then if falling_edge(clock) then -- After the layer in at idle mode, y is readable -- but it only update at the rising edge of the clock diff --git a/elasticai/creator/nn/fixed_point/linear/layer/batch_normed_linear.py b/elasticai/creator/nn/fixed_point/linear/layer/batch_normed_linear.py index f087fe2d..e6e45b3c 100644 --- a/elasticai/creator/nn/fixed_point/linear/layer/batch_normed_linear.py +++ b/elasticai/creator/nn/fixed_point/linear/layer/batch_normed_linear.py @@ -8,7 +8,7 @@ from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( FixedPointConfig, ) -from elasticai.creator.nn.fixed_point.linear.design import Linear as LinearDesign +from elasticai.creator.nn.fixed_point.linear.design import LinearDesign class BatchNormedLinear(DesignCreatorModule, torch.nn.Module): diff --git a/elasticai/creator/nn/fixed_point/linear/layer/linear.py b/elasticai/creator/nn/fixed_point/linear/layer/linear.py index dfc4e125..2aac78b7 100644 --- a/elasticai/creator/nn/fixed_point/linear/layer/linear.py +++ b/elasticai/creator/nn/fixed_point/linear/layer/linear.py @@ -6,7 +6,8 @@ from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( FixedPointConfig, ) -from elasticai.creator.nn.fixed_point.linear.design import Linear as LinearDesign +from elasticai.creator.nn.fixed_point.linear.design import LinearDesign +from elasticai.creator.nn.fixed_point.linear.testbench import LinearTestbench class Linear(DesignCreatorModule, LinearBase): @@ -49,3 +50,6 @@ def float_to_signed_int(value: float | list) -> int | list: bias=signed_int_bias, name=name, ) + + def create_testbench(self, name: str, uut: LinearDesign) -> LinearTestbench: + return LinearTestbench(name, uut) diff --git a/elasticai/creator/nn/fixed_point/linear/layer/linear_test.py b/elasticai/creator/nn/fixed_point/linear/layer/linear_test.py index 392a0259..6a2f5187 100644 --- a/elasticai/creator/nn/fixed_point/linear/layer/linear_test.py +++ b/elasticai/creator/nn/fixed_point/linear/layer/linear_test.py @@ -129,12 +129,12 @@ def test_linear_layer_creates_correct_design() -> None: return TEMP2; end function; - -- Log2 funtion is for calculating the bitwidth of the address lines + -- Log2 function is for calculating the bitwidth of the address lines -- for bias and weights rom function log2(val : INTEGER) return natural is variable res : natural; begin - for i in 0 to 31 loop + for i in 1 to 31 loop if (val <= (2 ** i)) then res := i; exit; @@ -167,9 +167,9 @@ def test_linear_layer_creates_correct_design() -> None: -- simple solution for the output buffer type t_y_array is array (0 to OUT_FEATURE_NUM) of std_logic_vector(DATA_WIDTH-1 downto 0); - shared variable y_ram : t_y_array; + signal y_ram : t_y_array; attribute rom_style : string; - attribute rom_style of y_ram : variable is RESOURCE_OPTION; + attribute rom_style of y_ram : signal is RESOURCE_OPTION; begin @@ -183,7 +183,7 @@ def test_linear_layer_creates_correct_design() -> None: -- connects ports reset <= not enable; - linear_main : process (clock, enable) + linear_main : process (clock, enable, reset) variable current_neuron_idx : integer range 0 to OUT_FEATURE_NUM-1 := 0; variable current_input_idx : integer range 0 to IN_FEATURE_NUM-1 := 0; variable var_addr_w : integer range 0 to OUT_FEATURE_NUM*IN_FEATURE_NUM-1 := 0; @@ -232,19 +232,17 @@ def test_linear_layer_creates_correct_design() -> None: state <= s_stop; else state <= s_idle; - current_neuron_idx := 0; + done <= '1'; end if; end if; - else - done <= '1'; end if; var_sum := multiply_accumulate(var_w, var_x, var_y); macc_sum <= var_sum; if y_write_en='1'then - y_ram(var_y_write_idx) := std_logic_vector(cut_down(var_sum)); + y_ram(var_y_write_idx) <= std_logic_vector(cut_down(var_sum)); y_write_en := '0'; end if; @@ -257,7 +255,7 @@ def test_linear_layer_creates_correct_design() -> None: y_reading : process (clock, state) begin - if state=s_idle then + if (state=s_idle) or (state=s_stop) then if falling_edge(clock) then -- After the layer in at idle mode, y is readable -- but it only update at the rising edge of the clock diff --git a/elasticai/creator/nn/fixed_point/linear/linear.tpl.vhd b/elasticai/creator/nn/fixed_point/linear/linear.tpl.vhd index 2943ddd3..a2262745 100644 --- a/elasticai/creator/nn/fixed_point/linear/linear.tpl.vhd +++ b/elasticai/creator/nn/fixed_point/linear/linear.tpl.vhd @@ -66,12 +66,12 @@ architecture rtl of ${layer_name} is return TEMP2; end function; - -- Log2 funtion is for calculating the bitwidth of the address lines + -- Log2 function is for calculating the bitwidth of the address lines -- for bias and weights rom function log2(val : INTEGER) return natural is variable res : natural; begin - for i in 0 to 31 loop + for i in 1 to ${log2_max_value} loop if (val <= (2 ** i)) then res := i; exit; @@ -104,9 +104,9 @@ architecture rtl of ${layer_name} is -- simple solution for the output buffer type t_y_array is array (0 to OUT_FEATURE_NUM) of std_logic_vector(DATA_WIDTH-1 downto 0); - shared variable y_ram : t_y_array; + signal y_ram : t_y_array; attribute rom_style : string; - attribute rom_style of y_ram : variable is RESOURCE_OPTION; + attribute rom_style of y_ram : signal is RESOURCE_OPTION; begin @@ -120,7 +120,7 @@ begin -- connects ports reset <= not enable; - linear_main : process (clock, enable) + linear_main : process (clock, enable, reset) variable current_neuron_idx : integer range 0 to OUT_FEATURE_NUM-1 := 0; variable current_input_idx : integer range 0 to IN_FEATURE_NUM-1 := 0; variable var_addr_w : integer range 0 to OUT_FEATURE_NUM*IN_FEATURE_NUM-1 := 0; @@ -169,19 +169,17 @@ begin state <= s_stop; else state <= s_idle; - current_neuron_idx := 0; + done <= '1'; end if; end if; - else - done <= '1'; end if; var_sum := multiply_accumulate(var_w, var_x, var_y); macc_sum <= var_sum; if y_write_en='1'then - y_ram(var_y_write_idx) := std_logic_vector(cut_down(var_sum)); + y_ram(var_y_write_idx) <= std_logic_vector(cut_down(var_sum)); y_write_en := '0'; end if; @@ -194,7 +192,7 @@ begin y_reading : process (clock, state) begin - if state=s_idle then + if (state=s_idle) or (state=s_stop) then if falling_edge(clock) then -- After the layer in at idle mode, y is readable -- but it only update at the rising edge of the clock diff --git a/elasticai/creator/nn/fixed_point/linear/simulation_test.py b/elasticai/creator/nn/fixed_point/linear/simulation_test.py new file mode 100644 index 00000000..359ebea4 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/linear/simulation_test.py @@ -0,0 +1,130 @@ +import csv +import pathlib +from typing import Any + +import pytest +import torch + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator +from elasticai.creator.vhdl.simulated_layer import SimulatedLayer + +from .layer import Linear + + +def create_ones_input_list(batch_size: int, in_feature_num: int): + return [[[1.0] * in_feature_num]] * batch_size + + +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", ([[[0.0, 1.0, 1.0]]], [[[1.0, 1.0, 1.0]]], [[[2.0, 1.0, 0.0]]]) +) +def test_verify_hw_sw_equivalence_3_inputs(x): + input_data = torch.Tensor(x) + sw_conv = Linear( + in_features=3, + out_features=2, + total_bits=4, + frac_bits=1, + bias=True, + ) + sw_conv.weight.data = torch.ones_like(sw_conv.weight) + sw_conv.bias.data = torch.ones_like(sw_conv.bias) + sw_output = sw_conv(input_data) + design = sw_conv.create_design("linear") + testbench = sw_conv.create_testbench("linear_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim_layer = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + sim_output = sim_layer(input_data) + assert sw_output.tolist() == sim_output + + +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", + ( + create_ones_input_list(2, 4), + [[[0.5, 0.25, -1.0, 1.0]], [[-1.0, 1.0, -1.0, 1.0]]], + [[[0.0, 1.0, 1.0, 0.0]], [[-1.0, 1.0, -1.0, 1.0]]], + ), +) +def test_verify_hw_sw_equivalence_4_inputs(x): + input_data = torch.Tensor(x) + sw_conv = Linear( + in_features=4, + out_features=10, + total_bits=4, + frac_bits=1, + bias=True, + ) + sw_conv.weight.data = torch.ones_like(sw_conv.weight) + sw_conv.bias.data = torch.ones_like(sw_conv.bias) + sw_output = sw_conv(input_data) + design = sw_conv.create_design("linear") + print(f"{design.in_feature_num=}") + print(f"{design.out_feature_num=}") + testbench = sw_conv.create_testbench("linear_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim_layer = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + sim_output = sim_layer(input_data) + assert sw_output.tolist() == sim_output + + +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", + ( + [ + [[0.0, 0.0, 0.0, 0.0]], + [[1.0, 0.0, 0.0, 0.0]], + [[0.0, 1.0, 0.0, 0.0]], + [[0.0, 0.0, 1.0, 0.0]], + [[0.0, 0.0, 0.0, 1.0]], + [[2.0, 0.0, 0.0, 0.0]], + [[1.0, 1.0, 0.0, 0.0]], + [[1.0, 0.0, 1.0, 0.0]], + [[1.0, 0.0, 0.0, 1.0]], + [[3.0, 0.0, 0.0, 0.0]], + [[1.0, 2.0, 0.0, 0.0]], + [[1.0, 0.0, 2.0, 0.0]], + [[1.0, 0.0, 0.0, 2.0]], + [[1.0, 1.0, 0.0, 0.0]], + [[0.0, 1.0, 1.0, 0.0]], + [[0.0, 0.0, 1.0, 1.0]], + [[1.0, 0.0, 0.0, 1.0]], + [[-1.0, 0.0, 0.0, 0.0]], + [[0.0, -1.0, 0.0, 0.0]], + [[0.0, 0.0, -1.0, 0.0]], + [[0.0, 0.0, 0.0, -1.0]], + [[2.0, 0.0, 0.0, 0.0]], + [[0.0, 2.0, 0.0, 0.0]], + [[0.0, 0.0, 2.0, 0.0]], + [[0.0, 0.0, 0.0, 2.0]], + ], + ), +) +def test_verify_hw_sw_equivalence_4_inputs_3_outputs(x): + input_data = torch.Tensor(x) + sw_conv = Linear( + in_features=4, + out_features=3, + total_bits=8, + frac_bits=2, + bias=True, + ) + sw_conv.weight.data = torch.ones_like(sw_conv.weight) * 2 + sw_conv.bias.data = torch.Tensor([1.0, 2.0, -1.0]) + sw_output = sw_conv(input_data) + design = sw_conv.create_design("linear") + testbench = sw_conv.create_testbench("linear_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim_layer = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + sim_output = sim_layer(input_data) + assert sw_output.tolist() == sim_output diff --git a/elasticai/creator/nn/fixed_point/linear/testbench.py b/elasticai/creator/nn/fixed_point/linear/testbench.py new file mode 100644 index 00000000..145fbb91 --- /dev/null +++ b/elasticai/creator/nn/fixed_point/linear/testbench.py @@ -0,0 +1,135 @@ +import math +from abc import abstractmethod +from collections import defaultdict +from typing import Protocol + +from elasticai.creator.file_generation.savable import Path +from elasticai.creator.file_generation.template import ( + InProjectTemplate, + module_to_package, +) +from elasticai.creator.nn.fixed_point.number_converter import FXPParams, NumberConverter +from elasticai.creator.vhdl.design.ports import Port +from elasticai.creator.vhdl.simulated_layer import Testbench + + +class LinearDesignProtocol(Protocol): + @property + @abstractmethod + def name(self) -> str: + ... + + @property + @abstractmethod + def port(self) -> Port: + ... + + @property + @abstractmethod + def in_feature_num(self) -> int: + ... + + @property + @abstractmethod + def out_feature_num(self) -> int: + ... + + @property + @abstractmethod + def frac_width(self) -> int: + ... + + @property + @abstractmethod + def data_width(self) -> int: + ... + + +class LinearTestbench(Testbench): + def __init__(self, name: str, uut: LinearDesignProtocol): + self._converter_for_batch = NumberConverter( + FXPParams(8, 0) + ) # max for 255 lines of inputs + self._name = name + self._uut_name = uut.name + self._input_signal_length = uut.in_feature_num + self._x_address_width = uut.port["x_address"].width + self._fxp_params = FXPParams(uut.data_width, uut.frac_width) + self._converter = NumberConverter(self._fxp_params) + self._output_signal_length = uut.out_feature_num + self._y_address_width = uut.port["y_address"].width + + def save_to(self, destination: Path): + template = InProjectTemplate( + package=module_to_package(self.__module__), + file_name="testbench.tpl.vhd", + parameters={ + "testbench_name": self.name, + "input_signal_length": str(self._input_signal_length), + "total_bits": str(self._fxp_params.total_bits), + "x_address_width": str(self._x_address_width), + "output_signal_length": str(self._output_signal_length), + "y_address_width": str(self._y_address_width), + "uut_name": self._uut_name, + }, + ) + destination.create_subpath(self.name).as_file(".vhd").write(template) + + @property + def name(self) -> str: + return self._name + + def prepare_inputs(self, *inputs) -> list[dict]: + batches = inputs[0] + prepared_inputs = [] + for batch in batches: + prepared_inputs.append({}) + for channel_id, channel in enumerate(batch): + for time_step_id, time_step_val in enumerate(channel): + prepared_inputs[-1][f"x_{channel_id}_{time_step_id}"] = ( + self._converter.rational_to_bits(time_step_val) + ) + return prepared_inputs + + def parse_reported_content(self, content: list[str]) -> list[list[list[float]]]: + """ + This function parses the reported content, which is just a list of strings. + All lines starting with 'output_text:' are considered as a result of the testbench. + These results will be stacked for each batch. + So you get a list[list[list[float]]] which is similar to batch[out channels[output neurons[float]]]. + For linear layer the output neurons is 1. + For each item reported it is checked if the string starts with 'result: '. + If so the remaining part will be split by ','. The first number gives the batch. The second the result. + """ + + def split_list(a_list): + print("len(a_list): ", len(a_list)) + new_list = list() + new_list.append(list()) + for i, value in enumerate(a_list): + new_list[0].append(value) + return new_list + + results_dict = defaultdict(list) + + print() + for line in map(str.strip, content): + if line.startswith("result: "): + batch_text = line.split(":")[1].split(",")[0][1:] + output_text = line.split(":")[1].split(",")[1][0:] + print("output_text: ", output_text) + batch = int(self._converter_for_batch.bits_to_rational(batch_text)) + if "U" not in line.split(":")[1].split(",")[1][1:]: + output = self._converter.bits_to_rational(output_text) + else: + output = output_text + results_dict[batch].append(output) + else: + print(line) + results = list() + for x in results_dict.items(): + results.append(split_list(x[1])) + print("results: ", results) + if len(results) is 0: + raise Exception(content) + return list(results) diff --git a/elasticai/creator/nn/fixed_point/linear/testbench.tpl.vhd b/elasticai/creator/nn/fixed_point/linear/testbench.tpl.vhd new file mode 100644 index 00000000..a63058be --- /dev/null +++ b/elasticai/creator/nn/fixed_point/linear/testbench.tpl.vhd @@ -0,0 +1,149 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use ieee.std_logic_textio.all; +use std.env.finish; + +entity ${testbench_name} is + generic ( + INPUTS_FILE_PATH: string + ); +end; + +architecture rtl of ${testbench_name} is + + --CLOCK + signal clock_period : time := 2 ns; + + --DATA INPUT + type data is array (0 to ${input_signal_length}-1) of std_logic_vector(${total_bits}-1 downto 0); + signal data_in : data; + file input_file : text open read_mode is INPUTS_FILE_PATH; + + --UUT + signal clock : std_logic := '0'; + signal enable : std_logic := '0'; + signal x : std_logic_vector(${total_bits}-1 downto 0); + signal x_address : std_logic_vector(${x_address_width}-1 downto 0) := (others => '0'); + signal x_address_std : std_logic_vector(${x_address_width}-1 downto 0); + signal y : std_logic_vector(${total_bits}-1 downto 0); + signal y_address : std_logic_vector(${y_address_width}-1 downto 0) := (others => '0'); + signal y_address_std : std_logic_vector(${y_address_width}-1 downto 0); + signal done : std_logic; + +begin + x_address <= x_address_std; + y_address_std <= y_address; + + UUT : entity work.${uut_name} + port map (clock => clock, enable => enable, x => x, x_address => x_address_std, y => y, y_address => y_address_std, done => done); + + x_writing : process (clock) + begin + if falling_edge(clock) then + -- After the layer in at idle mode, x is readable + -- but it only update at the falling edge of the clock + --report("debug: testbench: x_address " & to_bstring(x_address)); + x <= data_in(to_integer(unsigned(x_address))); + end if; + end process x_writing; + + + + clk : process + begin + clock <= not clock; + wait for clock_period/2; + end process; + + start_test : process (clock) + variable v_ILINE : line; + variable v_in : std_logic_vector(${total_bits}-1 downto 0); + variable v_SPACE : character; + variable input_idx : integer range 0 to ${input_signal_length} := 0; + variable output_idx : integer range 0 to ${output_signal_length} := 0; + type TYPE_STATE is (s_start_up, s_load_batch, s_reset, s_start_computation, s_wait_for_computation_done, s_write_uut_output_address, s_read_uut_output, s_finish_simulation); + variable test_state : TYPE_STATE := s_start_up; + variable input_cycles : signed(7 downto 0) := (others => '0'); --max for 255 lines of inputs + begin + if rising_edge(clock) then + if test_state = s_start_up then + report "status: reading file " & INPUTS_FILE_PATH; + readline(input_file, v_ILINE); -- read header + test_state := s_load_batch; + elsif test_state = s_load_batch then + if input_idx = 0 then + report "status: start reading batch"; + readline(input_file, v_ILINE); + end if; + read(v_ILINE, v_in); -- read value + report("debug: reading " & to_bstring(v_in)); + report("debug: testbench: input_idx = " & integer'image(input_idx)); + data_in(input_idx) <= v_in; + if input_idx /= ${input_signal_length}-1 then + read(v_ILINE, v_SPACE); + else + report "status: data for batch loaded!"; + test_state := s_reset; + end if; + input_idx := input_idx + 1; + elsif test_state = s_reset then + input_idx := 0; + report "status: test_state = s_reset"; + enable <= '0'; + test_state := s_start_computation; + y_address <= (others => '0'); + elsif test_state = s_start_computation then + report "status: test_state = s_start_computation"; + enable <= '1'; + test_state := s_wait_for_computation_done; + elsif test_state = s_wait_for_computation_done then + --report "status: test_state = s_wait_for_computation_done"; + if done = '1' then + report "status: computation finished"; + test_state := s_read_uut_output; + y_address <= (others => '0'); + enable <= '0'; + end if; + elsif test_state = s_write_uut_output_address then + report("status: test_state = s_write_uut_output_address"); + y_address <= std_logic_vector(unsigned(y_address) + 1); + test_state := s_read_uut_output; + elsif test_state = s_read_uut_output then + report("status: test_state = s_read_uut_output"); + report("status: " & to_bstring(input_cycles) & "," & to_bstring(y)); + report("result: " & to_bstring(input_cycles) & "," & to_bstring(y)); + if unsigned(y_address) /= ${output_signal_length}-1 then + test_state := s_write_uut_output_address; + else + input_cycles := input_cycles + 1; + if endfile(input_file) then + test_state := s_finish_simulation; + else + test_state := s_load_batch; + end if; + end if; + elsif test_state = s_finish_simulation then + report "status: test_state = s_finish_simulation"; + report "status: simulation finished"; + finish; + end if; + end if; + end process; + + end_after_X_cycles : process (clock) + variable i : integer range 0 to 10000; + begin + if rising_edge(clock) then + if i = 10000 then + report("OUT of TIME"); + finish; + else + i := i + 1; + end if; + end if; + end process; + + +end; diff --git a/elasticai/creator/nn/fixed_point/lstm/design/_common_imports.py b/elasticai/creator/nn/fixed_point/lstm/design/_common_imports.py index dc2fd9a1..4def3237 100644 --- a/elasticai/creator/nn/fixed_point/lstm/design/_common_imports.py +++ b/elasticai/creator/nn/fixed_point/lstm/design/_common_imports.py @@ -10,7 +10,7 @@ ) from elasticai.creator.nn.fixed_point.hard_sigmoid import HardSigmoid from elasticai.creator.nn.fixed_point.hard_tanh.design import HardTanh -from elasticai.creator.nn.fixed_point.linear.design import Linear as FPLinear1d +from elasticai.creator.nn.fixed_point.linear.design import LinearDesign as FPLinear1d from elasticai.creator.vhdl.code_generation.addressable import calculate_address_width from elasticai.creator.vhdl.design import std_signals from elasticai.creator.vhdl.design.design import Design diff --git a/elasticai/creator/vhdl/design/design.py b/elasticai/creator/vhdl/design/design.py index 85e2fa4c..4f3e1b62 100644 --- a/elasticai/creator/vhdl/design/design.py +++ b/elasticai/creator/vhdl/design/design.py @@ -6,7 +6,11 @@ class Design(Savable, ABC): def __init__(self, name: str): - self.name = name + self._name = name + + @property + def name(self) -> str: + return self._name @property @abstractmethod diff --git a/elasticai/creator/vhdl/ghdl_simulation.py b/elasticai/creator/vhdl/ghdl_simulation.py index f749a09b..6b39ec98 100644 --- a/elasticai/creator/vhdl/ghdl_simulation.py +++ b/elasticai/creator/vhdl/ghdl_simulation.py @@ -5,21 +5,34 @@ from ._ghdl_report_parsing import parse_report +class SimulationError(Exception): + pass + + class GHDLSimulator: """Run a simulation tool for a given `top_design` and save whatever is written to stdout for subsequent inspection. This runner uses the GHDL tool. The parsed content has the following keys: `("source", "line", "column", "time", "type", "content")' + + Will raise a `SimulationError` in case any of the calls to ghdl in the steps `initialize` or `run` fails. + Args: + workdir: typically the path to your build root, this is where we will look for vhd files """ - def __init__(self, workdir, top_design_name): + def __init__(self, workdir, top_design_name) -> None: self._root = workdir self._ghdl_dir = "ghdl_build" self._files = list(glob.glob(f"**/*.vhd", root_dir=self._root, recursive=True)) self._standard = "08" - self._result = {} self._test_bench_name = top_design_name + self._generics: dict[str, str] = {} + self._error_message = "" + self._completed_process: None | subprocess.CompletedProcess = None + + def add_generic(self, **kwargs): + self._generics.update(kwargs) def initialize(self): """Call this function once before calling `run()` and on every file change.""" @@ -30,10 +43,17 @@ def initialize(self): def run(self): """Runs the simulation and saves whatever the tool wrote to stdout. You're supposed to call `initialize` once, before calling `run`.""" - self._result = self._execute_command_and_return_stdout( - self._assemble_command("-r") + [self._test_bench_name] + generic_options = [f"-g{key}={value}" for key, value in self._generics.items()] + self._execute_command( + self._assemble_command(["-r"]) + + ["-fsynopsys", self._test_bench_name] + + generic_options ) + @property + def _result(self) -> str: + return self._stdout() + def getReportedContent(self) -> list[str]: """Strips any information that the simulation tool added automatically to the output to return only the information that was printed to stdout via VHDL/Verilog statements. @@ -60,15 +80,51 @@ def _compile(self): ) def _execute_command(self, command): - return subprocess.run(command, cwd=self._root) - - def _execute_command_and_return_stdout(self, command): - return subprocess.run( - command, cwd=self._root, capture_output=True - ).stdout.decode() - - def _assemble_command(self, command_flag): - return ["ghdl", command_flag, f"--std={self._standard}", self._workdir_flag] + try: + self._completed_process = subprocess.run( + command, cwd=self._root, capture_output=True, check=True + ) + except subprocess.CalledProcessError as e: + raise SimulationError( + f"ERROR:: executing {command}\n\tSTDERR::" + f" {e.stderr.decode()}\n\tSTDOUT:: {e.stdout.decode()}" + ) + + self._check_for_error() + + def _check_for_error(self): + try: + self._completed_process.check_returncode() + except subprocess.CalledProcessError as exception: + error_message = self._get_error_message() + sim_error = SimulationError(error_message) + raise sim_error from exception + + def _get_error_message(self) -> str: + # ghdl seems to pipe errors to stdout instead of stdin + error_message = self._stderr() + if error_message == "": + error_message = self._stdout() + return error_message + + def _stdout(self) -> str: + if self._completed_process is not None: + return self._completed_process.stdout.decode() + else: + return "" + + def _stderr(self) -> str: + if self._completed_process is not None: + return self._completed_process.stderr.decode() + else: + return "" + + def _assemble_command(self, command_flags): + if isinstance(command_flags, str): + command_flags = [command_flags] + return ( + ["ghdl"] + command_flags + [f"--std={self._standard}", self._workdir_flag] + ) @property def _workdir_flag(self): diff --git a/elasticai/creator/nn/fixed_point/mac/__init__.py b/elasticai/creator/vhdl/shared_designs/mac/__init__.py similarity index 100% rename from elasticai/creator/nn/fixed_point/mac/__init__.py rename to elasticai/creator/vhdl/shared_designs/mac/__init__.py diff --git a/elasticai/creator/vhdl/shared_designs/mac/binary/__init__.py b/elasticai/creator/vhdl/shared_designs/mac/binary/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/elasticai/creator/vhdl/shared_designs/mac/binary/_mac_test.py b/elasticai/creator/vhdl/shared_designs/mac/binary/_mac_test.py new file mode 100644 index 00000000..8062950d --- /dev/null +++ b/elasticai/creator/vhdl/shared_designs/mac/binary/_mac_test.py @@ -0,0 +1,70 @@ +import pytest +import torch + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator +from elasticai.creator.vhdl.simulated_layer import SimulatedLayer + +from .design import MacDesign +from .layer import MacLayer + +sw_function_test_data = [ + [[[1, 1, 1], [-1, 1, -1]], [[1, 1, 1], [-1, 1, 1]]], + [[[1, -1, -1, 1, 1], [1, -1, 1, -1, 1]]], +] + + +@pytest.mark.parametrize( + "data", + ( + ([[[1, 1, 1], [-1, 1, -1]], [[1, 1, 1], [-1, 1, 1]]], [-1, 1]), + ([[[1, -1, -1, 1, 1], [1, -1, 1, -1, 1]]], [1]), + ), +) +def test_sw_function(data): + x, expected = data + for i, (x1, x2) in enumerate(x): + x1 = torch.tensor(x1, dtype=torch.float32) + x2 = torch.tensor(x2, dtype=torch.float32) + mac = MacLayer(vector_width=x1.shape[0]) + y = mac(x1, x2).item() + assert y == expected[i] + + +@pytest.mark.skip( + reason=( + "Functionality could be fine, but testbenches is designed for input after input" + " like 'normal' mac operator" + ) +) +@pytest.mark.simulation +@pytest.mark.parametrize( + "x", + ( + # 00010 * 00010 -> 00000 00100 -> 000(00 001)00 -> 00001 + [ + [[1, 1, 1], [1, 1, 1]], + [[1, 1, 1], [1, 1, -1]], + ], + # 00010 * 01000 -> 00000 10000 -> 000(00 100)00 -> 00100 + [ + [[-1, 1], [-1, -1]], + ], + [[[-1, -1, 1], [1, 1, 1]]], + ), +) +def test_mac_hw_for_integers(x): + sw_mac = MacLayer(vector_width=1) + design: MacDesign = sw_mac.create_design("mac") + testbench = sw_mac.create_testbench("mac_testbench", design) + build_dir = OnDiskPath("build") + design.save_to(build_dir.create_subpath("srcs")) + testbench.save_to(build_dir.create_subpath("testbenches")) + sim = SimulatedLayer(testbench, GHDLSimulator, working_dir="build") + print(f"{x=}") + actual = sim(x) + for i, (x1, x2) in enumerate(x): + y = sw_mac( + torch.tensor(x1, dtype=torch.float32), torch.tensor(x2, dtype=torch.float32) + ) + assert y == actual[i] diff --git a/elasticai/creator/nn/binary/mac/bin_mac.vhd b/elasticai/creator/vhdl/shared_designs/mac/binary/bin_mac.vhd similarity index 100% rename from elasticai/creator/nn/binary/mac/bin_mac.vhd rename to elasticai/creator/vhdl/shared_designs/mac/binary/bin_mac.vhd diff --git a/elasticai/creator/nn/binary/mac/design.py b/elasticai/creator/vhdl/shared_designs/mac/binary/design.py similarity index 90% rename from elasticai/creator/nn/binary/mac/design.py rename to elasticai/creator/vhdl/shared_designs/mac/binary/design.py index d2537cd6..fa3c6cdd 100644 --- a/elasticai/creator/nn/binary/mac/design.py +++ b/elasticai/creator/vhdl/shared_designs/mac/binary/design.py @@ -9,7 +9,7 @@ def __init__(self, name: str, vector_width: int): def save_to(self, destination: Path) -> None: core_component = InProjectTemplate( - package="elasticai.creator.nn.binary.mac", + package="elasticai.creator.vhdl.shared_designs.mac.binary", file_name="bin_mac.vhd", parameters={ "total_width": str(self._vector_width), diff --git a/elasticai/creator/nn/binary/mac/layer.py b/elasticai/creator/vhdl/shared_designs/mac/binary/layer.py similarity index 58% rename from elasticai/creator/nn/binary/mac/layer.py rename to elasticai/creator/vhdl/shared_designs/mac/binary/layer.py index d2a2a3f4..8c1dd251 100644 --- a/elasticai/creator/nn/binary/mac/layer.py +++ b/elasticai/creator/vhdl/shared_designs/mac/binary/layer.py @@ -1,7 +1,6 @@ from elasticai.creator.file_generation.savable import Savable -from elasticai.creator.vhdl.simulated_layer import SimulatedLayer +from elasticai.creator.nn.binary._math_operations import MathOperations -from .._math_operations import MathOperations from .design import MacDesign from .mactestbench import MacTestBench @@ -18,12 +17,9 @@ def __call__(self, a, b): def create_design(self, name: str) -> Savable: return MacDesign(vector_width=self._vector_width, name=name) - def create_testbench(self, name: str) -> MacTestBench: + def create_testbench(self, name: str, design: MacDesign) -> MacTestBench: return MacTestBench( - uut=self.create_design("mac_wrapper_test"), - uut_name="mac_wrapper_test", + uut=design, + uut_name="mac", name=name, ) - - def create_simulation(self, simulator, working_dir): - return SimulatedLayer(self, simulator, working_dir=working_dir) diff --git a/elasticai/creator/vhdl/shared_designs/mac/binary/mactestbench.py b/elasticai/creator/vhdl/shared_designs/mac/binary/mactestbench.py new file mode 100644 index 00000000..0c0d6a2a --- /dev/null +++ b/elasticai/creator/vhdl/shared_designs/mac/binary/mactestbench.py @@ -0,0 +1,53 @@ +from collections import defaultdict + +from elasticai.creator.file_generation.savable import Path +from elasticai.creator.file_generation.template import InProjectTemplate +from elasticai.creator.vhdl.simulated_layer import Testbench + + +class MacTestBench(Testbench): + def __init__(self, uut, name, uut_name): + self._uut = uut + self._uut_name = uut_name + self._inputs = None + self._destination = None + self._name = name + + @property + def name(self) -> str: + return self._name + + def parse_reported_content(self, content: list[str]): + """ + Somehow there is no content... + """ + for line in content: + print(line) + + def save_to(self, destination: Path): + self._destination = destination + test_bench = InProjectTemplate( + package="elasticai.creator.vhdl.shared_designs.mac.binary", + file_name="testbench.tpl.vhd", + parameters={ + "uut_name": self._uut_name, + "name": self.name, + }, + ) + destination.create_subpath(self.name).as_file(".vhd").write(test_bench) + + def prepare_inputs(self, inputs) -> list[dict]: + def zero_one(x): + if x < 0: + return "0" + else: + return "1" + + prepared_inputs = [] + for batch in inputs: + prepared_inputs.append({}) + for i in range(0, len(batch[0])): + prepared_inputs[-1].update( + {f"x1_{i}": zero_one(batch[0][i]), f"x2_{i}": zero_one(batch[1][i])} + ) + return prepared_inputs diff --git a/elasticai/creator/vhdl/shared_designs/mac/binary/testbench.tpl.vhd b/elasticai/creator/vhdl/shared_designs/mac/binary/testbench.tpl.vhd new file mode 100644 index 00000000..b485cfdd --- /dev/null +++ b/elasticai/creator/vhdl/shared_designs/mac/binary/testbench.tpl.vhd @@ -0,0 +1,132 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; +use ieee.std_logic_textio.all; +use std.env.finish; + + +entity $name is + generic ( + INPUTS_FILE_PATH: string + ); +end; + +architecture Behavioral of $name is + signal clock_period : time := 2 ps; + signal clock : std_logic := '0'; + signal reset : std_logic := '0'; + signal next_sample : std_logic; + signal x1 : std_logic_vector(0 downto 0) := (others => '0'); + signal x2 : std_logic_vector(0 downto 0) := (others => '0'); + signal sum : std_logic; + signal done : std_logic; + + type data is array (0 to 100) of std_logic_vector(0 downto 0); + signal data_in_x1 : data; + signal data_in_x2 : data; + file input_file : text open read_mode is INPUTS_FILE_PATH; + + +begin + UUT : entity work.${uut_name} + port map (reset => reset, next_sample => next_sample, x1 => x1, x2 => x2, sum => sum, done => done); + + clk : process + begin + clock <= not clock; + wait for clock_period/2; + end process; + + + testbench_1 : process(clock, done) + + variable v_ILINE : line; + variable v_in : std_logic_vector(0 downto 0); + variable v_SPACE : character; + variable input_idx : integer range 0 to 100 := 0; + variable num_inputs : integer range 0 to 100:= 0; + type TYPE_STATE is (s_start_up, s_load_batch, s_reset, s_start_computation, s_wait_for_computation_done, s_read_uut_output, s_finish_simulation); + variable test_state : TYPE_STATE := s_start_up; + + begin + if rising_edge(clock) then + if test_state = s_start_up then + report "status: reading file " & INPUTS_FILE_PATH; + readline (input_file, v_ILINE); --read header + test_state := s_load_batch; + elsif test_state = s_load_batch then + if input_idx = 0 then + report "status: start reading batch"; + readline(input_file, v_ILINE); + end if; + if v_ILINE'length >= 3 then + read(v_ILINE, v_in); -- read value + report "debug: reading x1 " & to_bstring(v_in); + data_in_x1(input_idx) <= v_in; + read(v_ILINE, v_SPACE); + + read(v_ILINE, v_in); -- read value + report "debug: reading x2 " & to_bstring(v_in); + data_in_x2(input_idx) <= v_in; + if v_ILINE'length > 0 then + read(v_ILINE, v_SPACE); + end if; + else + report "status: data for batch loaded"; + test_state := s_reset; + num_inputs := input_idx; + end if; + input_idx := input_idx + 1; + elsif test_state = s_reset then + input_idx := 0; + reset <= '0'; + x1 <= (others => '0'); + x2 <= (others => '0'); + test_state := s_start_computation; + next_sample <= '0'; + elsif test_state = s_start_computation then + reset <= '1'; + x1 <= data_in_x1(input_idx); + x2 <= data_in_x2(input_idx); + next_sample <= '1'; + test_state := s_wait_for_computation_done; + elsif test_state = s_wait_for_computation_done then + next_sample <= '0'; + if done = '1' then + if input_idx = num_inputs then + input_idx := 0; + test_state := s_read_uut_output; + else + input_idx := input_idx +1; + test_state := s_start_computation; + end if; + end if; + elsif test_state = s_read_uut_output then + report "result: " & to_string(sum); + if endfile(input_file) then + test_state := s_finish_simulation; + else + test_state := s_load_batch; + end if; + elsif test_state = s_finish_simulation then + report "status: simulation finished"; + finish; + end if; + end if; + end process; + + end_after_X_cycles : process (clock) + variable i : integer range 0 to 10000; + begin + if rising_edge(clock) then + if i = 10000 then + report("OUT of TIME"); + finish; + else + i := i + 1; + end if; + end if; + end process; + +end Behavioral; diff --git a/elasticai/creator/vhdl/shared_designs/mac/fixed_point/__init__.py b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/elasticai/creator/nn/fixed_point/mac/_hw_test.py b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/_hw_test.py similarity index 94% rename from elasticai/creator/nn/fixed_point/mac/_hw_test.py rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/_hw_test.py index 603d586b..1a38254e 100644 --- a/elasticai/creator/nn/fixed_point/mac/_hw_test.py +++ b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/_hw_test.py @@ -3,9 +3,9 @@ import pytest import torch +from elasticai.creator.nn.fixed_point.number_converter import FXPParams from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator -from ..number_converter import FXPParams from .layer import MacLayer integer_test_data = [ @@ -38,6 +38,9 @@ ] +@pytest.mark.skip( + reason="Not changed for new SimulatedLayer. Needs to be implemented in the future" +) @pytest.mark.simulation @pytest.mark.parametrize( ["fxp_params", "x1", "x2"], integer_test_data + fractions_test_data diff --git a/elasticai/creator/nn/fixed_point/mac/design.py b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/design.py similarity index 100% rename from elasticai/creator/nn/fixed_point/mac/design.py rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/design.py diff --git a/elasticai/creator/nn/fixed_point/mac/fxp_mac.tpl.vhd b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/fxp_mac.tpl.vhd similarity index 64% rename from elasticai/creator/nn/fixed_point/mac/fxp_mac.tpl.vhd rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/fxp_mac.tpl.vhd index ec1a61f1..a7985779 100644 --- a/elasticai/creator/nn/fixed_point/mac/fxp_mac.tpl.vhd +++ b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/fxp_mac.tpl.vhd @@ -47,28 +47,36 @@ architecture rtl of fxp_Mac_RoundToZero is end function; begin - mac : process (next_sample) + mac : process (next_sample, reset) variable accumulator : signed(2*TOTAL_WIDTH-1 downto 0) := (others=>'0'); variable vector_idx : integer := 0; type t_state is (s_compute, s_finished); variable state : t_state := s_compute; begin - if rising_edge(next_sample) then - if reset = '0' then - accumulator := (others => '0'); - vector_idx := 0; - state := s_compute; - done <= '0'; - sum <= (others => '0'); - elsif state=s_compute then - accumulator := x1*x2 + accumulator; - vector_idx := vector_idx + 1; - if vector_idx = VECTOR_WIDTH then - sum <= cut_down(accumulator); - state := s_finished; + if reset = '0' then + --report("debug: fxpMAC: reset"); + accumulator := (others => '0'); + vector_idx := 0; + state := s_compute; + done <= '0'; + sum <= (others => '0'); + else + if rising_edge(next_sample) then + if state=s_compute then + --report("debug: fxpMAC: state = s_compute"); + --report("debug: fxpMAC: x1 = " & to_bstring(x1)); + --report("debug: fxpMAC: x2 = " & to_bstring(x2)); + accumulator := x1*x2 + accumulator; + vector_idx := vector_idx + 1; + if vector_idx = VECTOR_WIDTH then + --report("debug: fxpMAC: Vectorwidth reached"); + sum <= cut_down(accumulator); + state := s_finished; + end if; + elsif state = s_finished then + --report("debug: fxpMAC: state = s_finished"); + done <= '1'; end if; - elsif state = s_finished then - done <= '1'; end if; end if; end process mac; diff --git a/elasticai/creator/nn/fixed_point/mac/layer.py b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/layer.py similarity index 82% rename from elasticai/creator/nn/fixed_point/mac/layer.py rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/layer.py index 283611e7..ba64fc93 100644 --- a/elasticai/creator/nn/fixed_point/mac/layer.py +++ b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/layer.py @@ -1,9 +1,11 @@ from elasticai.creator.file_generation.savable import Savable +from elasticai.creator.nn.fixed_point._math_operations import MathOperations +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) +from elasticai.creator.nn.fixed_point.number_converter import FXPParams from elasticai.creator.vhdl.simulated_layer import SimulatedLayer -from .._math_operations import MathOperations -from .._two_complement_fixed_point_config import FixedPointConfig -from ..number_converter import FXPParams from .design import MacDesign from .mactestbench import MacTestBench diff --git a/elasticai/creator/nn/fixed_point/mac/mac_design.tpl.vhd b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/mac_design.tpl.vhd similarity index 100% rename from elasticai/creator/nn/fixed_point/mac/mac_design.tpl.vhd rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/mac_design.tpl.vhd diff --git a/elasticai/creator/nn/fixed_point/mac/mactestbench.py b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/mactestbench.py similarity index 96% rename from elasticai/creator/nn/fixed_point/mac/mactestbench.py rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/mactestbench.py index ccf868ac..963e54a1 100644 --- a/elasticai/creator/nn/fixed_point/mac/mactestbench.py +++ b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/mactestbench.py @@ -1,7 +1,6 @@ from elasticai.creator.file_generation.savable import Path from elasticai.creator.file_generation.template import InProjectTemplate - -from ..number_converter import NumberConverter +from elasticai.creator.nn.fixed_point.number_converter import NumberConverter class MacTestBench: diff --git a/elasticai/creator/nn/fixed_point/mac/testbench.tpl.vhd b/elasticai/creator/vhdl/shared_designs/mac/fixed_point/testbench.tpl.vhd similarity index 100% rename from elasticai/creator/nn/fixed_point/mac/testbench.tpl.vhd rename to elasticai/creator/vhdl/shared_designs/mac/fixed_point/testbench.tpl.vhd diff --git a/elasticai/creator/vhdl/simulated_layer.py b/elasticai/creator/vhdl/simulated_layer.py index 0a948ad5..3932999a 100644 --- a/elasticai/creator/vhdl/simulated_layer.py +++ b/elasticai/creator/vhdl/simulated_layer.py @@ -1,53 +1,56 @@ +import csv +import pathlib from typing import Any, Protocol -from elasticai.creator.file_generation.on_disk_path import OnDiskPath from elasticai.creator.file_generation.savable import Path -from elasticai.creator.vhdl.ghdl_simulation import GHDLSimulator -class Design(Protocol): - def save_to(self, destination: Path): ... - - -class Layer(Design, Protocol): +class Testbench: @property - def name(self) -> str: ... - - def create_testbench(self, name: str) -> "TestBench": ... - - -class TestBench(Design, Protocol): - def set_inputs(self, *inputs) -> None: ... + def name(self) -> str: + raise NotImplementedError - def parse_reported_content(self, content: Any) -> Any: ... + def save_to(self, destination: Path) -> None: + raise NotImplementedError + def prepare_inputs(self, *args: Any, **kwargs: Any) -> Any: + raise NotImplementedError -class SimulationConstructor(Protocol): - def __call__(self, workdir: str, top_design_name: str) -> GHDLSimulator: ... + def parse_reported_content(self, *args, **kwargs: Any) -> Any: + raise NotImplementedError class SimulatedLayer: - def __init__( - self, - layer_under_test: Layer, - simulation_constructor: SimulationConstructor, - working_dir: str, - ): - self._layer_under_test = layer_under_test - self._simulation_constructor = simulation_constructor + def __init__(self, testbench: Testbench, simulator_constructor, working_dir): + self._testbench = testbench + self._simulator_constructor = simulator_constructor self._working_dir = working_dir - self._inputs = None - - def __call__(self, *inputs): - root = OnDiskPath("main", parent=self._working_dir) - testbench_name = f"testbench_{self._layer_under_test.name}" - testbench = self._layer_under_test.create_testbench(testbench_name) - testbench.set_inputs(*inputs) - testbench.save_to(root) - runner = self._simulation_constructor( - workdir=f"{self._working_dir}", top_design_name=testbench.name + self._inputs_file_path = ( + f"{self._working_dir}/{self._testbench.name}_inputs.csv" + ) + + def __call__(self, inputs: Any) -> Any: + runner = self._simulator_constructor( + workdir=f"{self._working_dir}", top_design_name=self._testbench.name + ) + inputs = self._testbench.prepare_inputs(inputs) + self._write_csv(inputs) + runner.add_generic( + INPUTS_FILE_PATH=str(pathlib.Path(self._inputs_file_path).absolute()) ) runner.initialize() runner.run() - actual = testbench.parse_reported_content(runner.getReportedContent()) + actual = self._testbench.parse_reported_content(runner.getReportedContent()) return actual + + def _write_csv(self, inputs): + with open(self._inputs_file_path, "w") as f: + header = [x for x in inputs[0].keys()] + writer = csv.DictWriter( + f, + fieldnames=header, + lineterminator="\n", + delimiter=" ", + ) + writer.writeheader() + writer.writerows(inputs) diff --git a/elasticai/creator/vhdl/system_integrations/firmware_env5_test.py b/elasticai/creator/vhdl/system_integrations/firmware_env5_test.py index 40ee5897..04872a8c 100644 --- a/elasticai/creator/vhdl/system_integrations/firmware_env5_test.py +++ b/elasticai/creator/vhdl/system_integrations/firmware_env5_test.py @@ -234,40 +234,44 @@ def test_firmware_generates_correct_skeleton_v2() -> None: busy <= not done; wake_up <= done; - receive_data_from_middleware: process (clock, wr, address_in) - variable int_addr : integer range 0 to 20000; + receive_data_from_middleware: process (clock) + variable int_addr : integer range 0 to 18 + X_NUM_VALUES; begin if rising_edge(clock) then if reset = '1' then network_enable <= '0'; else - int_addr := to_integer(unsigned(address_in)); - if int_addr = 16 then - network_enable <= data_in(0); - elsif int_addr >= 18 and int_addr < 18 + X_NUM_VALUES then - data_buf_in(int_addr) <= data_in(DATA_WIDTH_IN-1 downto 0); + if wr = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr = 16 then + network_enable <= data_in(0); + elsif int_addr >= 18 and int_addr < 18 + X_NUM_VALUES then + data_buf_in(int_addr-18) <= data_in(DATA_WIDTH_IN-1 downto 0); + end if; end if; end if; end if; end process; - sendback_data_to_middleware: process (clock, rd, address_in) - variable int_addr : integer range 0 to 20000; + sendback_data_to_middleware: process (clock) + variable int_addr : integer range 0 to 18 + Y_NUM_VALUES; begin if rising_edge(clock) then - int_addr := to_integer(unsigned(address_in)); - if int_addr <= 15 then - data_out(7 downto 0) <= skeleton_id_str(int_addr); - elsif int_addr >= 18 and int_addr < 18 + Y_NUM_VALUES then - y_address <= std_logic_vector(unsigned(address_in(y_address'length-1 downto 0))-16); - data_out(7 downto 0) <= pad_output_to_middleware(y); + if rd = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr <= 15 then + data_out(7 downto 0) <= skeleton_id_str(int_addr); + elsif int_addr >= 18 and int_addr < 18 + Y_NUM_VALUES then + y_address <= std_logic_vector(unsigned(address_in(y_address'length-1 downto 0))-18); + data_out(7 downto 0) <= pad_output_to_middleware(y); + end if; end if; end if; end process; - send_buf_to_network: process (clock, x_address) + send_buf_to_network: process (clock) begin - if rising_edge(clock) then + if falling_edge(clock) then x <= data_buf_in(to_integer(unsigned(x_address))); end if; end process; diff --git a/elasticai/creator/vhdl/system_integrations/middleware/icapInterface.vhd b/elasticai/creator/vhdl/system_integrations/middleware/icapInterface.vhd index 150b6cf8..6358530e 100644 --- a/elasticai/creator/vhdl/system_integrations/middleware/icapInterface.vhd +++ b/elasticai/creator/vhdl/system_integrations/middleware/icapInterface.vhd @@ -36,8 +36,7 @@ end icapInterface; architecture Behavioral of icapInterface is -type state_type is - (IDLE, WAITING_FLASH,DUMMY,SYNC,CMD_0,CMD_1,CMD_2,CMD_3,WRITE_CMD,IPROG); +type state_type is (IDLE, WAITING_FLASH, DUMMY, SYNC, CMD_0, CMD_1, CMD_2, CMD_3, WRITE_CMD, IPROG); attribute enum_encoding : string; attribute enum_encoding of state_type : type is "sequential"; type state_type_vector is array (0 to 9) of state_type; diff --git a/elasticai/creator/vhdl/system_integrations/plug_and_play_solution_ENV5.py b/elasticai/creator/vhdl/system_integrations/plug_and_play_solution_ENV5.py index 1e27f5e5..bc16ef57 100644 --- a/elasticai/creator/vhdl/system_integrations/plug_and_play_solution_ENV5.py +++ b/elasticai/creator/vhdl/system_integrations/plug_and_play_solution_ENV5.py @@ -1,4 +1,5 @@ import warnings +from types import NoneType from typing import Protocol from elasticai.creator.file_generation.savable import Path @@ -7,7 +8,11 @@ ENV5Constraints, ) from elasticai.creator.vhdl.system_integrations.middleware.middleware import Middleware -from elasticai.creator.vhdl.system_integrations.skeleton.skeleton import LSTMSkeleton +from elasticai.creator.vhdl.system_integrations.skeleton.skeleton import ( + EchoSkeletonV2, + LSTMSkeleton, + Skeleton, +) from elasticai.creator.vhdl.system_integrations.top.env5_reconfig_top import ( ENV5ReconfigTop, ) @@ -30,7 +35,7 @@ def create_testbench(self, name: str, design: Design) -> Design: ... -class FirmwareENv5: +class FirmwareLSTMENv5: def __init__(self, model: _DesignAndTestbenchCreator): self._network = model.create_design("network") self._testbench = model.create_testbench("network_tb", self._network) @@ -60,3 +65,32 @@ def save_constraints(destination: Path): constraints = destination.create_subpath("constraints") save_constraints(constraints) save_srcs(srcs) + + +class FirmwareEchoServerSkeletonV2: + def __init__(self, num_inputs: int, bitwidth: int): + self._num_inputs = num_inputs + self._bitwidth = bitwidth + self.skeleton_id: list[int] = list() + + def save_to(self, destination: Path): + def save_srcs(destination: Path): + skeleton = EchoSkeletonV2(self._num_inputs, bitwidth=self._bitwidth) + self.skeleton_id = skeleton._id + skeleton.save_to(destination.create_subpath("skeleton")) + + + middleware = Middleware() + middleware.save_to(destination.create_subpath("middleware")) + + env5_reconfig_top = ENV5ReconfigTop() + env5_reconfig_top.save_to(destination.create_subpath("env5_reconfig_top")) + + def save_constraints(destination: Path): + env5_config = ENV5Constraints() + env5_config.save_to(destination.create_subpath("env5_config")) + + srcs = destination.create_subpath("srcs") + constraints = destination.create_subpath("constraints") + save_constraints(constraints) + save_srcs(srcs) diff --git a/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2.tpl.vhd b/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2.tpl.vhd index 1e103afe..1efbef7c 100644 --- a/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2.tpl.vhd +++ b/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2.tpl.vhd @@ -74,40 +74,44 @@ begin busy <= not done; wake_up <= done; - receive_data_from_middleware: process (clock, wr, address_in) - variable int_addr : integer range 0 to 20000; + receive_data_from_middleware: process (clock) + variable int_addr : integer range 0 to 18 + X_NUM_VALUES; begin if rising_edge(clock) then if reset = '1' then network_enable <= '0'; else - int_addr := to_integer(unsigned(address_in)); - if int_addr = 16 then - network_enable <= data_in(0); - elsif int_addr >= 18 and int_addr < 18 + X_NUM_VALUES then - data_buf_in(int_addr) <= data_in(DATA_WIDTH_IN-1 downto 0); + if wr = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr = 16 then + network_enable <= data_in(0); + elsif int_addr >= 18 and int_addr < 18 + X_NUM_VALUES then + data_buf_in(int_addr-18) <= data_in(DATA_WIDTH_IN-1 downto 0); + end if; end if; end if; end if; end process; - sendback_data_to_middleware: process (clock, rd, address_in) - variable int_addr : integer range 0 to 20000; + sendback_data_to_middleware: process (clock) + variable int_addr : integer range 0 to 18 + Y_NUM_VALUES; begin if rising_edge(clock) then - int_addr := to_integer(unsigned(address_in)); - if int_addr <= 15 then - data_out(7 downto 0) <= skeleton_id_str(int_addr); - elsif int_addr >= 18 and int_addr < 18 + Y_NUM_VALUES then - y_address <= std_logic_vector(unsigned(address_in(y_address'length-1 downto 0))-16); - data_out(7 downto 0) <= pad_output_to_middleware(y); + if rd = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr <= 15 then + data_out(7 downto 0) <= skeleton_id_str(int_addr); + elsif int_addr >= 18 and int_addr < 18 + Y_NUM_VALUES then + y_address <= std_logic_vector(unsigned(address_in(y_address'length-1 downto 0))-18); + data_out(7 downto 0) <= pad_output_to_middleware(y); + end if; end if; end if; end process; - send_buf_to_network: process (clock, x_address) + send_buf_to_network: process (clock) begin - if rising_edge(clock) then + if falling_edge(clock) then x <= data_buf_in(to_integer(unsigned(x_address))); end if; end process; diff --git a/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2_echo.tpl.vhd b/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2_echo.tpl.vhd new file mode 100644 index 00000000..7335cf57 --- /dev/null +++ b/elasticai/creator/vhdl/system_integrations/skeleton/network_skeleton_v2_echo.tpl.vhd @@ -0,0 +1,81 @@ +library ieee; +USE ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity $name is + port ( + -- control interface + clock : in std_logic; + clk_hadamard : in std_logic; + reset : in std_logic; -- controls functionality (sleep) + busy : out std_logic; -- done with entire calculation + wake_up : out std_logic; + -- indicate new data or request + rd : in std_logic; -- request a variable + wr : in std_logic; -- request changing a variable + + -- data interface + data_in : in std_logic_vector(7 downto 0); + address_in : in std_logic_vector(15 downto 0); + data_out : out std_logic_vector(7 downto 0); + + debug : out std_logic_vector(7 downto 0); + + led_ctrl : out std_logic_vector(3 DOWNTO 0) + ); +end; + +architecture rtl of $name is + constant DATA_WIDTH_IN : integer := ${data_width}; + constant NUM_VALUES : integer := ${num_values}; + signal network_enable : std_logic; + + signal wake_up_write: std_logic := '0'; + signal wake_up_read : std_logic := '0'; + + type buf_data_in_t is array (0 to NUM_VALUES) of std_logic_vector(DATA_WIDTH_IN-1 downto 0); + signal data_buf_in : buf_data_in_t; + type skeleton_id_data_t is array (0 to 15) of std_logic_vector(7 downto 0); + signal skeleton_id_str : skeleton_id_data_t := (${id}); +begin + + busy <= '0'; + wake_up <= wake_up_write; + wake_up <= wake_up_read; + + receive_data_from_middleware: process (clock) + variable int_addr : integer range 0 to 18 + NUM_VALUES; + begin + if rising_edge(clock) then + if reset = '1' then + network_enable <= '0'; + else + if wr = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr = 16 then + network_enable <= data_in(0); + wake_up_write <= '1'; + elsif int_addr >= 18 and int_addr < 18 + NUM_VALUES then + data_buf_in(int_addr-18) <= data_in(DATA_WIDTH_IN-1 downto 0); + end if; + end if; + end if; + end if; + end process; + + sendback_data_to_middleware: process (clock) + variable int_addr : integer range 0 to 18 + NUM_VALUES; + begin + if rising_edge(clock) then + if rd = '1' then + int_addr := to_integer(unsigned(address_in)); + if int_addr <= 15 then + data_out(7 downto 0) <= skeleton_id_str(int_addr); + elsif int_addr >= 18 and int_addr < 18 + NUM_VALUES then + data_out(7 downto 0) <= std_logic_vector(signed(data_buf_in(int_addr-18))+1); + wake_up_read <= '0'; + end if; + end if; + end if; + end process; +end rtl; diff --git a/elasticai/creator/vhdl/system_integrations/skeleton/skeleton.py b/elasticai/creator/vhdl/system_integrations/skeleton/skeleton.py index ef52c770..eec55057 100644 --- a/elasticai/creator/vhdl/system_integrations/skeleton/skeleton.py +++ b/elasticai/creator/vhdl/system_integrations/skeleton/skeleton.py @@ -117,3 +117,33 @@ def save_to(self, destination: Path): ) file = destination.as_file(".vhd") file.write(template) + + +class EchoSkeletonV2: + def __init__(self, num_values: int, bitwidth: int): + self._num_values = num_values + self._bitwidth = bitwidth + self._name = "skeleton" + if bitwidth > 8: + raise Exception( + "Not more than 8 bit supported by middleware. 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b/tests/system_tests/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/tests/system_tests/conv1d/__init__.py b/tests/system_tests/conv1d/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/tests/system_tests/conv1d/conv1d.py b/tests/system_tests/conv1d/conv1d.py new file mode 100644 index 00000000..ccafd023 --- /dev/null +++ b/tests/system_tests/conv1d/conv1d.py @@ -0,0 +1,191 @@ +import atexit +import subprocess +import time +import tomllib +from pathlib import Path + +import serial +import torch +from elasticai.runtime.env5.usb import UserRemoteControl, get_env5_port + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.nn import Sequential +from elasticai.creator.nn.fixed_point import Conv1d +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) +from elasticai.creator.vhdl.system_integrations.firmware_env5 import FirmwareENv5 +from tests.system_tests.helper.parse_tensors_to_bytearray import ( + parse_bytearray_to_fxp_tensor, + parse_fxp_tensor_to_bytearray, +) + + +def create_vhd_files( + output_dir: str, + num_inputs: int, + num_outputs: int, + num_in_channels: int, + num_out_channels: int, + kernel_size: int, + total_bits: int, + frac_bits: int, + skeleton_id: list[int], +) -> Sequential: + nn = Sequential( + Conv1d( + total_bits=total_bits, + frac_bits=frac_bits, + in_channels=num_in_channels, + out_channels=num_out_channels, + signal_length=num_inputs, + kernel_size=kernel_size, + ) + ) + nn[0].weight.data = torch.ones_like(nn[0].weight) * 2 + nn[0].bias.data = torch.ones_like(nn[0].bias) * -1 + destination = OnDiskPath(output_dir) + my_design = nn.create_design("nn") + my_design.save_to(destination.create_subpath("srcs")) + + firmware = FirmwareENv5( + network=my_design, + x_num_values=num_inputs, + y_num_values=num_outputs, + id=skeleton_id, + skeleton_version="v2", + ) + firmware.save_to(destination) + return nn + + +def vivado_build_binfile(input_dir: str, binfile_dir: str): + print(f"Building binfile in {binfile_dir}") + with open("./tests/system_tests/vivado_build_server_conf.toml", "rb") as f: + config = tomllib.load(f) + out = subprocess.run( + [ + "bash", + "./utils/autobuild_binfile_vivado2021.1.sh", + config["username"], + config["ip"], + input_dir, + binfile_dir, + ], + capture_output=True, + ) + print(f"{out.stdout=}") + + +if __name__ == "__main__": + # dev_address = "COM8" + dev_address = get_env5_port() + vhdl_dir = "./tests/system_tests/conv1d/build_dir" + binfile_dir = "./tests/system_tests/conv1d/build_dir_output" + binfile_path = Path(binfile_dir + "/output/env5_top_reconfig.bin") + skeleton_id = list(range(15, -1, -1)) + skeleton_id_as_bytearray = bytearray() + for x in skeleton_id: + skeleton_id_as_bytearray.extend( + x.to_bytes(length=1, byteorder="little", signed=False) + ) + + total_bits = 8 + frac_bits = 2 + num_inputs = 5 + kernel_size = 3 + num_in_channels = 1 + num_out_channels = 1 + # batches = 2 + num_outputs = num_inputs - kernel_size + 1 + nn = create_vhd_files( + output_dir=vhdl_dir, + num_inputs=num_inputs, + num_outputs=num_outputs, + num_in_channels=num_in_channels, + num_out_channels=num_out_channels, + kernel_size=kernel_size, + total_bits=total_bits, + frac_bits=frac_bits, + skeleton_id=skeleton_id, + ) + + fxp_conf = FixedPointConfig(total_bits, frac_bits) + + # inputs = fxp_conf.as_rational(fxp_conf.as_integer(torch.rand(batches, num_in_channels, num_inputs))) + inputs = fxp_conf.as_rational( + fxp_conf.as_integer( + torch.Tensor( + [ + [[0.0, 0.0, 0.0, 0.0, 0.0]], + [[1.0, 0.0, 0.0, 0.0, 0.0]], + [[0.0, 1.0, 0.0, 0.0, 0.0]], + [[0.0, 0.0, 1.0, 0.0, 0.0]], + [[0.0, 0.0, 0.0, 1.0, 0.0]], + [[0.0, 0.0, 0.0, 0.0, 1.0]], + [[2.0, 0.0, 0.0, 0.0, 0.0]], + [[1.0, 1.0, 0.0, 0.0, 0.0]], + [[1.0, 0.0, 1.0, 0.0, 0.0]], + [[1.0, 0.0, 0.0, 1.0, 0.0]], + [[1.0, 0.0, 0.0, 0.0, 1.0]], + [[3.0, 0.0, 0.0, 0.0, 0.0]], + [[1.0, 2.0, 0.0, 0.0, 0.0]], + [[1.0, 0.0, 2.0, 0.0, 0.0]], + [[1.0, 0.0, 0.0, 2.0, 0.0]], + [[1.0, 0.0, 0.0, 0.0, 2.0]], + [[1.0, 1.0, 0.0, 0.0, 0.0]], + [[0.0, 1.0, 1.0, 0.0, 0.0]], + [[0.0, 0.0, 1.0, 1.0, 0.0]], + [[0.0, 0.0, 0.0, 1.0, 1.0]], + [[-1.0, 0.0, 0.0, 0.0, 0.0]], + [[0.0, -1.0, 0.0, 0.0, 0.0]], + [[0.0, 0.0, -1.0, 0.0, 0.0]], + [[0.0, 0.0, 0.0, -1.0, 0.0]], + [[0.0, 0.0, 0.0, 0.0, -1.0]], + [[2.0, 0.0, 0.0, 0.0, 0.0]], + [[0.0, 2.0, 0.0, 0.0, 0.0]], + [[0.0, 0.0, 2.0, 0.0, 0.0]], + [[0.0, 0.0, 0.0, 2.0, 0.0]], + [[0.0, 0.0, 0.0, 0.0, 2.0]], + ] + ) + ) + ) + batches = inputs.shape[0] + + expected_outputs = nn(inputs) + + vivado_build_binfile(vhdl_dir, binfile_dir) + + with serial.Serial(dev_address) as serial_con: + flash_start_address = 0 + + urc = UserRemoteControl(device=serial_con) + urc.send_and_deploy_model( + binfile_path, flash_start_address, skeleton_id_as_bytearray + ) + # urc.deploy_model(flash_start_address, skeleton_id_as_bytearray) + + batch_data = parse_fxp_tensor_to_bytearray(inputs, total_bits, frac_bits) + inference_result = list() + for i, sample in enumerate(batch_data): + batch_result = urc.inference_with_data( + sample, num_outputs * num_out_channels + ) + my_result = parse_bytearray_to_fxp_tensor( + [batch_result], + total_bits, + frac_bits, + (1, num_out_channels, num_outputs), + ) + print( + f"Batch {i}: {my_result} == {expected_outputs[i]}, for input" + f" {inputs[i]}" + ) + + inference_result.append(batch_result) + actual_result = parse_bytearray_to_fxp_tensor( + inference_result, total_bits, frac_bits, expected_outputs.shape + ) + + assert torch.equal(actual_result, expected_outputs) diff --git a/tests/system_tests/echo_server/__init__.py b/tests/system_tests/echo_server/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/tests/system_tests/echo_server/echo_server.py b/tests/system_tests/echo_server/echo_server.py new file mode 100644 index 00000000..3dd58c30 --- /dev/null +++ b/tests/system_tests/echo_server/echo_server.py @@ -0,0 +1,114 @@ +import atexit +import pathlib +import subprocess +import time +import tomllib + +import serial # type: ignore +import torch +from elasticai.runtime.env5.usb import UserRemoteControl, get_env5_port # type: ignore + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) +from elasticai.creator.vhdl.system_integrations.plug_and_play_solution_ENV5 import ( + FirmwareEchoServerSkeletonV2, +) +from tests.system_tests.helper.parse_tensors_to_bytearray import ( + parse_bytearray_to_fxp_tensor, + parse_fxp_tensor_to_bytearray, +) + + +def build_vhdl_source(output_dir: str, num_inputs: int) -> bytearray: + f = FirmwareEchoServerSkeletonV2(num_inputs=num_inputs, bitwidth=8) + f.save_to(OnDiskPath(output_dir)) + skeleton_id_as_bytearray = bytearray() + for x in f.skeleton_id: + skeleton_id_as_bytearray.extend( + x.to_bytes(length=1, byteorder="little", signed=False) + ) + return skeleton_id_as_bytearray + + +def vivado_build_binfile(input_dir: str, binfile_dir: str): + print(f"Building binfile in {binfile_dir}") + with open("./tests/system_tests/vivado_build_server_conf.toml", "rb") as f: + config = tomllib.load(f) + out = subprocess.run( + [ + "bash", + "./utils/autobuild_binfile_vivado2021.1.sh", + config["username"], + config["ip"], + input_dir, + binfile_dir, + ], + capture_output=True, + ) + print(out.stdout) + + +def send_binfile( + local_urc: UserRemoteControl, binfile_address: int, file_dir: str +) -> bool: + print(f"Sending binfile to {binfile_address=}") + with open(file_dir + "output/env5_top_reconfig.bin", "rb") as file: + binfile: bytes = file.read() + print(f"Sending binfile to {binfile_address=}: {finished=}") + return finished + + +def exit_handler(cdc_port: serial.Serial): + cdc_port.close() + print(f"closed {cdc_port.port=}") + + +if __name__ == "__main__": + output_dir = vhdl_dir = "./tests/system_tests/echo_server/build_dir" + binfile_dir = "./tests/system_tests/echo_server/build_dir_output/" + binfile_path = pathlib.Path(binfile_dir + "output/env5_top_reconfig.bin") + + total_bits = 8 + frac_bits = 2 + batches = 3 + num_inputs = 4 + num_outputs = num_inputs + + skeleton_id_as_bytearray = build_vhdl_source(output_dir, num_inputs) + + vivado_build_binfile(output_dir, binfile_dir) + + # serial_con = serial.Serial(get_env5_port()) + serial_con = serial.Serial("/dev/tty.usbmodem101") + atexit.register(exit_handler, serial_con) + binfile_address = 0 + + urc = UserRemoteControl(device=serial_con) + + print("Send and deploy model") + successful = urc.send_and_deploy_model( + binfile_path, binfile_address, skeleton_id_as_bytearray + ) + successful = urc.deploy_model(binfile_address, skeleton_id_as_bytearray) + print(f"Model deployed {successful=}") + + fxp_conf = FixedPointConfig(total_bits, frac_bits) + x = torch.randn(batches, 1, num_inputs) + inputs = fxp_conf.as_rational(fxp_conf.as_integer(x)) + inference_data = parse_fxp_tensor_to_bytearray(inputs, total_bits, frac_bits) + + print(f"Start inference") + inference_result = list() + for batch_data in inference_data: + batch_result = urc.inference_with_data(batch_data, num_outputs) + inference_result.append(batch_result) + + actual_result = parse_bytearray_to_fxp_tensor( + inference_result, total_bits, frac_bits, inputs.shape + ) + print(f"{actual_result=}") + print(f"{inputs + 1/(2**frac_bits)=}") + assert torch.equal(actual_result, inputs + 1 / (2**frac_bits)) + print("Test successful") diff --git a/tests/system_tests/example_vivado_build_server_conf.toml b/tests/system_tests/example_vivado_build_server_conf.toml new file mode 100644 index 00000000..f882b25e --- /dev/null +++ b/tests/system_tests/example_vivado_build_server_conf.toml @@ -0,0 +1,4 @@ +# Rename this file to vivado_build_server_conf.toml +# Change ip and username accordingly +ip = "xxx.xxx.xxx.xxx" # serverip +username = "my_username_on_server" diff --git a/tests/system_tests/helper/__init__.py b/tests/system_tests/helper/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/tests/system_tests/helper/parse_tensors_to_bytearray.py b/tests/system_tests/helper/parse_tensors_to_bytearray.py new file mode 100644 index 00000000..b9bc3103 --- /dev/null +++ b/tests/system_tests/helper/parse_tensors_to_bytearray.py @@ -0,0 +1,39 @@ +from torch import Tensor, flatten + +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) + + +def parse_fxp_tensor_to_bytearray( + tensor: Tensor, total_bits: int, frac_bits: int +) -> list[bytearray]: + tensor = flatten(tensor.permute([0, 2, 1]), start_dim=1) + fxp_config = FixedPointConfig(total_bits=total_bits, frac_bits=frac_bits) + ints = fxp_config.as_integer(tensor).tolist() + data = list() + for i, batch in enumerate(ints): + data.append(bytearray()) + for item in batch: + item_as_bytes = int(item).to_bytes(1, byteorder="big", signed=True) + data[i].extend(item_as_bytes) + return data + + +def parse_bytearray_to_fxp_tensor( + data: list[bytearray], total_bits: int, frac_bits: int, dimensions: tuple +) -> Tensor: + fxp_config = FixedPointConfig(total_bits=total_bits, frac_bits=frac_bits) + rationals = list() + for i, batch in enumerate(data): + rationals.append(list()) + my_batch = batch.hex(sep=" ", bytes_per_sep=1).split(" ") + for item in my_batch: + item_as_bytes = bytes.fromhex(item) + item_as_int = int.from_bytes(item_as_bytes, byteorder="big", signed=True) + item_as_rational = fxp_config.as_rational(item_as_int) + rationals[i].append(item_as_rational) + tensor = Tensor(rationals) + tensor = tensor.unflatten(1, (dimensions[2], dimensions[1])) + tensor = tensor.transpose(1, 2) + return tensor diff --git a/tests/system_tests/helper/test_parse_tensors_to_bytearray.py b/tests/system_tests/helper/test_parse_tensors_to_bytearray.py new file mode 100644 index 00000000..df7589e5 --- /dev/null +++ b/tests/system_tests/helper/test_parse_tensors_to_bytearray.py @@ -0,0 +1,40 @@ +import torch +from torch import Tensor + +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) +from tests.system_tests.helper.parse_tensors_to_bytearray import ( + parse_bytearray_to_fxp_tensor, + parse_fxp_tensor_to_bytearray, +) + + +def test_tensors_to_bytearray(): + torch.manual_seed(0) + total_bits = 8 + frac_bits = 2 + fxp_conf = FixedPointConfig(total_bits=total_bits, frac_bits=frac_bits) + tensor = fxp_conf.as_rational(fxp_conf.as_integer(torch.randn(2, 3, 4))) + result = parse_fxp_tensor_to_bytearray(tensor, total_bits, frac_bits) + expected = [ + bytearray(b"\xfc\x03\x01\xfc\x02\x00\xff\xff\x05\xff\xf8\x01"), + bytearray(b"\x00\x03\x02\x03\x05\xff\x00\x08\xfd\x00\x00\xf7"), + ] + assert result == expected + + +def test_bytearray_to_tensor(): + input = [ + bytearray(b"\xfc\x03\x01\xfc\x02\x00\xff\xff\x05\xff\xf8\x01"), + bytearray(b"\x00\x03\x02\x03\x05\xff\x00\x08\xfd\x00\x00\xf7"), + ] + total_bits = 8 + frac_bits = 2 + torch.manual_seed(0) + fxp_conf = FixedPointConfig(total_bits=total_bits, frac_bits=frac_bits) + dimensions = (2, 3, 4) + expected = fxp_conf.as_rational(fxp_conf.as_integer(torch.randn(dimensions))) + print(f"{expected=}") + result = parse_bytearray_to_fxp_tensor(input, total_bits, frac_bits, dimensions) + assert torch.equal(result, expected) diff --git a/tests/system_tests/linear_layer/__init__.py b/tests/system_tests/linear_layer/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/tests/system_tests/linear_layer/linear_layer.py b/tests/system_tests/linear_layer/linear_layer.py new file mode 100644 index 00000000..83e1fbc0 --- /dev/null +++ b/tests/system_tests/linear_layer/linear_layer.py @@ -0,0 +1,165 @@ +import subprocess +import time +import tomllib +from pathlib import Path + +import numpy as np +import serial # type: ignore +import torch +from elasticai.runtime.env5.usb import UserRemoteControl, get_env5_port # type: ignore + +from elasticai.creator.file_generation.on_disk_path import OnDiskPath +from elasticai.creator.nn import Sequential +from elasticai.creator.nn.fixed_point._two_complement_fixed_point_config import ( + FixedPointConfig, +) +from elasticai.creator.nn.fixed_point.linear import Linear +from elasticai.creator.vhdl.system_integrations.firmware_env5 import FirmwareENv5 +from tests.system_tests.helper.parse_tensors_to_bytearray import ( + parse_bytearray_to_fxp_tensor, + parse_fxp_tensor_to_bytearray, +) + + +def create_vhd_files( + output_dir: str, + num_inputs: int, + num_outputs: int, + total_bits: int, + frac_bits: int, + skeleton_id: list[int], +) -> Sequential: + nn = Sequential( + Linear( + in_features=num_inputs, + out_features=num_outputs, + bias=True, + total_bits=total_bits, + frac_bits=frac_bits, + ) + ) + nn[0].weight.data = torch.ones_like(nn[0].weight) * 2 + nn[0].bias.data = torch.Tensor([1.0, 2.0, -1.0]) + destination = OnDiskPath(output_dir) + my_design = nn.create_design("nn") + my_design.save_to(destination.create_subpath("srcs")) + + firmware = FirmwareENv5( + network=my_design, + x_num_values=num_inputs, + y_num_values=num_outputs, + id=skeleton_id, + skeleton_version="v2", + ) + firmware.save_to(destination) + return nn + + +def vivado_build_binfile(input_dir: str, binfile_dir: str) -> None: + print(f"Building binfile in {binfile_dir}") + time.sleep(5) + with open("./tests/system_tests/vivado_build_server_conf.toml", "rb") as f: + config = tomllib.load(f) + out = subprocess.run( + [ + "bash", + "./utils/autobuild_binfile_vivado2021.1.sh", + config["username"], + config["ip"], + input_dir, + binfile_dir, + ], + capture_output=True, + ) + # print(f"{out.stdout=}") + + +if __name__ == "__main__": + # --- Settings + # dev_address = "COM8" + dev_address = get_env5_port() + vivado_build = True + + # torch.manual_seed(1) + total_bits = 8 + frac_bits = 2 + num_inputs = 5 + num_outputs = 3 + skeleton_id = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + + # --- Processing + # --- Creating the dummy + input_tensor = torch.Tensor([[[0.0, 0.0, 0.0, 0.0, 0.0]]]) + for idx_array in range(0, num_inputs): + for value in np.arange(-2, 2, 0.5): + list_zeros = [0.0 for idx in range(0, num_inputs)] + list_zeros[idx_array] = value + input_tensor = torch.cat( + (input_tensor, torch.Tensor([[list_zeros]])), dim=0 + ) + + skeleton_id_as_bytearray = bytearray() + for x in skeleton_id: + skeleton_id_as_bytearray.extend( + x.to_bytes(length=1, byteorder="little", signed=False) + ) + + # --- Preparing the VHDL code generation + vhdl_dir = "./tests/system_tests/linear_layer/build_dir" + binfile_dir = "./tests/system_tests/linear_layer/build_dir_output" + binfile_path = Path(binfile_dir + "/output/env5_top_reconfig.bin") + nn = create_vhd_files( + vhdl_dir, num_inputs, num_outputs, total_bits, frac_bits, skeleton_id + ) + + fxp_conf = FixedPointConfig(total_bits, frac_bits) + # inputs = fxp_conf.as_rational(fxp_conf.as_integer(torch.rand(batches, 1, num_inputs))) + inputs = fxp_conf.as_rational(fxp_conf.as_integer(input_tensor)) + batches = inputs.shape[0] + expected_outputs = nn(inputs) + + # --- Building the code + if vivado_build: + vivado_build_binfile(vhdl_dir, binfile_dir) + + # --- Open Serial Communication to Device + with serial.Serial(dev_address) as serial_con: + flash_start_address = 0 + urc = UserRemoteControl(device=serial_con) + urc.send_and_deploy_model( + binfile_path, flash_start_address, skeleton_id_as_bytearray + ) + # urc.deploy_model(flash_start_address, skeleton_id_as_bytearray) + + # --- Doing the test + batch_data = parse_fxp_tensor_to_bytearray(inputs, total_bits, frac_bits) + inference_result = list() + state = False + urc.fpga_leds(True, False, False, False) + for i, sample in enumerate(batch_data): + urc.fpga_leds(True, False, False, state) + state = False if state else True + + batch_result = urc.inference_with_data(sample, num_outputs) + my_result = parse_bytearray_to_fxp_tensor( + [batch_result], total_bits, frac_bits, (1, 1, 3) + ) + + dev_inp = my_result + dev_out = expected_outputs.data[i].view((1, 1, 3)) + if not torch.equal(dev_inp, dev_out): + print( + f"Batch #{i:02d}: \t{dev_inp} == {dev_out}, (Delta =" + f" {dev_inp - dev_out}) \t\t\t\tfor input {inputs[i]}" + ) + if i % 4 == 3: + print("\n") + + inference_result.append(batch_result) + + urc.fpga_leds(False, False, False, False) + actual_result = parse_bytearray_to_fxp_tensor( + inference_result, total_bits, frac_bits, expected_outputs.shape + ) + + assert torch.equal(actual_result, expected_outputs)