add a system-test(end-to-end ) for the existing linear layer

[LeoBuron]

As a developer for vhdl-code I want to be able to test my code on different levels. An end-to-end system-test is what would allow direct verification.

The generated code should be implemented with the vivado-build pipeline. The generated binfile should be flashed via usb automatically with the new usb-protocol. The FPGA should be started and load the binfile. The file should be verified. Data should be sent over PC to RP2040 to FPGA for inference. The result should be sent back.

• Integrate dominiks vivado-build pipeline #362
• Integrate the usb-protocol from the runtime #363
• Implement a script to combine vivado-build pipeline and usb-protocol #364
• Implement inference execution with pytest #365