diff --git a/core-v-mini-mcu-fpga.core b/core-v-mini-mcu-fpga.core new file mode 100644 index 000000000..38663aea9 --- /dev/null +++ b/core-v-mini-mcu-fpga.core @@ -0,0 +1,72 @@ +CAPI=2: + +# Copyright 2024 EPFL +# Solderpad Hardware License, Version 2.1, see LICENSE.md for details. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +name: openhwgroup.org:systems:core-v-mini-mcu-fpga +description: CORE-V MINI-MCU FPGA related files. + +filesets: + rtl-fpga: + depend: + - x-heep::packages + files: + - hw/fpga/sram_wrapper.sv + file_type: systemVerilogSource + + ip-fpga: + files: + - hw/fpga/scripts/generate_sram.tcl: { file_type: tclSource } + - hw/fpga/prim_xilinx_clk.sv: { file_type: systemVerilogSource } + - hw/fpga/cv32e40p_xilinx_clock_gate.sv: { file_type: systemVerilogSource } + - hw/fpga/cv32e40x_xilinx_clock_gate.sv: { file_type: systemVerilogSource } + - hw/fpga/cve2_xilinx_clock_gate.sv: { file_type: systemVerilogSource } + - hw/fpga/cv32e40px_xilinx_clock_gate.sv: { file_type: systemVerilogSource } + - hw/fpga/pad_cell_input_xilinx.sv: { file_type: systemVerilogSource } + - hw/fpga/pad_cell_output_xilinx.sv: { file_type: systemVerilogSource } + - hw/fpga/pad_cell_inout_xilinx.sv: { file_type: systemVerilogSource } + - hw/fpga/pad_cell_bypass_input_xilinx.sv: { file_type: systemVerilogSource } + - hw/fpga/pad_cell_bypass_output_xilinx.sv: { file_type: systemVerilogSource } + + ip-fpga-pynq-z2: + files: + - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } + + ip-fpga-nexys: + files: + - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } + + ip-fpga-zcu104: + files: + - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } + + xdc-fpga-nexys: + files: + - hw/fpga/constraints/nexys/pin_assign.xdc + - hw/fpga/constraints/nexys/constraints.xdc + file_type: xdc + + xdc-fpga-pynq-z2: + files: + - hw/fpga/constraints/pynq-z2/pin_assign.xdc + - hw/fpga/constraints/pynq-z2/constraints.xdc + file_type: xdc + + xdc-fpga-zcu104: + files: + - hw/fpga/constraints/zcu104/pin_assign.xdc + file_type: xdc + + +targets: + default: &default_target + filesets: + - rtl-fpga + - ip-fpga + - target_pynq-z2 ? (ip-fpga-pynq-z2) + - target_pynq-z2 ? (xdc-fpga-pynq-z2) + - target_nexys-a7-100t ? (ip-fpga-nexys) + - target_nexys-a7-100t ? (xdc-fpga-nexys) + - target_zcu104 ? (ip-fpga-zcu104) + - target_zcu104 ? (xdc-fpga-zcu104) diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core index d923e930f..8dac12332 100644 --- a/core-v-mini-mcu.core +++ b/core-v-mini-mcu.core @@ -95,37 +95,12 @@ filesets: file_type: vlt rtl-fpga: + depend: + - openhwgroup.org:systems:core-v-mini-mcu-fpga files: - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv - - hw/fpga/sram_wrapper.sv file_type: systemVerilogSource - ip-fpga: - files: - - hw/fpga/scripts/generate_sram.tcl: { file_type: tclSource } - - hw/fpga/prim_xilinx_clk.sv: { file_type: systemVerilogSource } - - hw/fpga/cv32e40p_xilinx_clock_gate.sv: { file_type: systemVerilogSource } - - hw/fpga/cv32e40x_xilinx_clock_gate.sv: { file_type: systemVerilogSource } - - hw/fpga/cve2_xilinx_clock_gate.sv: { file_type: systemVerilogSource } - - hw/fpga/cv32e40px_xilinx_clock_gate.sv: { file_type: systemVerilogSource } - - hw/fpga/pad_cell_input_xilinx.sv: { file_type: systemVerilogSource } - - hw/fpga/pad_cell_output_xilinx.sv: { file_type: systemVerilogSource } - - hw/fpga/pad_cell_inout_xilinx.sv: { file_type: systemVerilogSource } - - hw/fpga/pad_cell_bypass_input_xilinx.sv: { file_type: systemVerilogSource } - - hw/fpga/pad_cell_bypass_output_xilinx.sv: { file_type: systemVerilogSource } - - ip-fpga-pynq-z2: - files: - - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } - - ip-fpga-nexys: - files: - - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } - - ip-fpga-zcu104: - files: - - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl: { file_type: tclSource } - ip-asic: depend: - technology::prim_mytech @@ -144,28 +119,6 @@ filesets: files: - hw/asic/sky130/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib : { copyto: lib/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib } - xdc-fpga-nexys: - files: - - hw/fpga/constraints/nexys/pin_assign.xdc - - hw/fpga/constraints/nexys/constraints.xdc - file_type: xdc - - xdc-fpga-pynq-z2: - files: - - hw/fpga/constraints/pynq-z2/pin_assign.xdc - - hw/fpga/constraints/pynq-z2/constraints.xdc - file_type: xdc - - xdc-fpga-zcu104: - files: - - hw/fpga/constraints/zcu104/pin_assign.xdc - file_type: xdc - - netlist-fpga: - files: - - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v - file_type: verilogSource - # Scripts for hooks post_build_modelsim_scripts: files: @@ -460,9 +413,6 @@ targets: filesets_append: - x_heep_system - rtl-fpga - - ip-fpga-nexys - - ip-fpga - - xdc-fpga-nexys parameters: - COREV_PULP - FPU @@ -484,9 +434,6 @@ targets: filesets_append: - x_heep_system - rtl-fpga - - ip-fpga-pynq-z2 - - ip-fpga - - xdc-fpga-pynq-z2 parameters: - COREV_PULP - FPU @@ -507,9 +454,6 @@ targets: filesets_append: - x_heep_system - rtl-fpga - - ip-fpga-zcu104 - - ip-fpga - - xdc-fpga-zcu104 parameters: - COREV_PULP - FPU diff --git a/hw/fpga/constraints/nexys/pin_assign.xdc b/hw/fpga/constraints/nexys/pin_assign.xdc index be6203565..d3723fef9 100644 --- a/hw/fpga/constraints/nexys/pin_assign.xdc +++ b/hw/fpga/constraints/nexys/pin_assign.xdc @@ -13,9 +13,8 @@ set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {rst_led_o}] set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {clk_led_o}]; set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {exit_valid_o}]; set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {exit_value_o}]; -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_out_OBUF] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_OBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_o_OBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_o_OBUF] ##Switches set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {execute_from_flash_i}]; #Sch=sw[1] @@ -79,5 +78,24 @@ set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]} set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]; #IO_L10N_T1_D15_14 Sch=btnr set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +##7 segment display +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports { gpio_io[11] }]; +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports { gpio_io[12] }]; +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports { gpio_io[13] }]; +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { gpio_io[14] }]; +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports { pdm2pcm_clk_io }]; +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports { pdm2pcm_pdm_io }]; +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports { i2s_sck_io }]; +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports { i2s_ws_io }]; +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports { i2s_sd_io }]; +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io[15] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { gpio_io[16] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { gpio_io[17] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { spi2_csb_o[0] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { spi2_csb_o[1] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { spi2_sck_o }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { spi2_sd_io[0] }]; #IO_L23P_T3_35 Sch=an[6] + + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]