diff --git a/hw/fpga/prim_xilinx_clk.sv b/hw/fpga/prim_xilinx_clk.sv
index 35165b880..a01324482 100644
--- a/hw/fpga/prim_xilinx_clk.sv
+++ b/hw/fpga/prim_xilinx_clk.sv
@@ -9,16 +9,13 @@ module xilinx_clk_gating (
     output logic clk_o
 );
 
-  logic clk_en;
-
-  // Use a latch based clock gate instead of BUFGCE. Otherwise we quickly run out of BUFGCTRL cells on the FPGAs.
-  always_latch begin
-    if (clk_i == 1'b0) clk_en <= en_i | test_en_i;
-  end
-
-  assign clk_o = clk_i & clk_en;
-
-
+  // In Zynq7000, just bypass the clock gating because there are not enough BUFGs that can be 
+  // cascaded with the BUFG of the MMCM.
+  // In the Zynq UltraScale+, it can be implemented as BUFGCE without trouble, since there
+  // are > 500 BUFGCEs and the rules for cascading are more relaxed.
+  // NOTE: This **cannot** be substituted by a latch+and
+ assign clk_o = clk_i;
+ 
 endmodule
 
 module xilinx_clk_inverter (
@@ -158,12 +155,3 @@ module tc_clk_xor2 (
   assign clk_o = clk0_i ^ clk1_i;
 
 endmodule
-
-module tc_clk_inverter (
-    input  logic clk_i,
-    output logic clk_o
-);
-
-  xilinx_clk_inverter clk_inv_i (.*);
-
-endmodule