diff --git a/.gitignore b/.gitignore
index 822378eac..d369ddf84 100644
--- a/.gitignore
+++ b/.gitignore
@@ -41,6 +41,7 @@ hw/fpga/scripts/generate_sram.tcl
 # same for the C header file and linker scripts and assembly files
 sw/device/lib/crt/crt0.S
 sw/device/lib/runtime/core_v_mini_mcu.h
+sw/device/lib/runtime/core_v_mini_mcu_memory.h
 sw/linker/link.ld
 sw/linker/link_flash_exec.ld
 sw/linker/link_flash_load.ld
diff --git a/Makefile b/Makefile
index 905b2c6b3..ca1a02b0c 100644
--- a/Makefile
+++ b/Makefile
@@ -33,6 +33,8 @@ endif
 # Project options are based on the app to be build (default - hello_world)
 PROJECT  ?= hello_world
 
+LINK_FOLDER ?= $(mkfile_path)/sw/linker
+
 # Linker options are 'on_chip' (default),'flash_load','flash_exec','freertos'
 LINKER   ?= on_chip
 
@@ -111,7 +113,8 @@ mcu-gen:
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
-	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link.ld.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.upf.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.dc.upf.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.sv.tpl
@@ -121,8 +124,8 @@ mcu-gen:
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/data/pad_control.hjson.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/rtl/pad_control.sv.tpl
 	bash -c "cd hw/system/pad_control; source pad_control_gen.sh; cd ../../../"
-	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_exec.ld.tpl
-	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_load.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link_flash_exec.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link_flash_load.ld.tpl
 	$(PYTHON) ./util/structs_periph_gen.py
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/sram_wrapper.sv.tpl
 	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/scripts/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/scripts/generate_sram.tcl.tpl
@@ -147,7 +150,7 @@ verible:
 ## @param COMPILER_PREFIX=riscv32-unknown-(default)
 ## @param ARCH=rv32imc(default), <any RISC-V ISA string supported by the CPU>
 app: clean-app
-	$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE) \
+	$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) LINK_FOLDER=$(LINK_FOLDER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE) \
 	|| { \
 	echo "\033[0;31mHmmm... seems like the compilation failed...\033[0m"; \
 	echo "\033[0;31mIf you do not understand why, it is likely that you either:\033[0m"; \
diff --git a/sw/Makefile b/sw/Makefile
index a36f5ead2..e327138b5 100644
--- a/sw/Makefile
+++ b/sw/Makefile
@@ -59,7 +59,7 @@ $(info $$You are fetching sources from $(source_path) )
 SOURCE_PATH   		       = $(source_path)/
 ROOT_PROJECT               = $(mkfile_path)/
 INC_FOLDERS                = $(mkfile_path)/device/target/$(TARGET)/
-LINK_FOLDER                = $(mkfile_path)/linker
+LINK_FOLDER                ?= $(mkfile_path)/linker
 
 # CMake keyword
 CMAKE_DIR=cmake
diff --git a/sw/device/lib/crt/vectors.S b/sw/device/lib/crt/vectors.S
index f6a805c65..8e573eefd 100644
--- a/sw/device/lib/crt/vectors.S
+++ b/sw/device/lib/crt/vectors.S
@@ -126,39 +126,13 @@ new vector table (which is at mtvec) */
 
 .section .text.vecs
 /* exception handling */
+.globl __no_irq_handler
 __no_irq_handler:
 	la a0, no_exception_handler_msg
 	jal ra, puts
 	j __no_irq_handler
 
-
-sw_irq_handler:
-	csrr t0, mcause
-	slli t0, t0, 1  /* shift off the high bit */
-	srli t0, t0, 1
-	li t1, 2
-	beq t0, t1, handle_illegal_insn
-	li t1, 11
-	beq t0, t1, handle_ecall
-	li t1, 3
-	beq t0, t1, handle_ebreak
-	j handle_unknown
-
-handle_ecall:
-	la a0, ecall_msg
-	jal ra, puts
-	j end_handler
-
-handle_ebreak:
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler
-
-handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler
-
+.globl handle_unknown
 handle_unknown:
 	la a0, unknown_msg
 	jal ra, puts
diff --git a/sw/device/lib/crt/vectors_freertos.S b/sw/device/lib/crt/vectors_freertos.S
index 3596dc186..c4586b300 100644
--- a/sw/device/lib/crt/vectors_freertos.S
+++ b/sw/device/lib/crt/vectors_freertos.S
@@ -132,33 +132,6 @@ __no_irq_handler:
 	jal ra, puts
 	j __no_irq_handler
 
-sw_irq_handler:
-	csrr t0, mcause
-	slli t0, t0, 1  /* shift off the high bit */
-	srli t0, t0, 1
-	li t1, 2
-	beq t0, t1, handle_illegal_insn
-	li t1, 11
-	beq t0, t1, handle_ecall
-	li t1, 3
-	beq t0, t1, handle_ebreak
-	j handle_unknown
-
-handle_ecall:
-	la a0, ecall_msg
-	jal ra, puts
-	j end_handler
-
-handle_ebreak:
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler
-
-handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler
-
 handle_unknown:
 	la a0, unknown_msg
 	jal ra, puts
diff --git a/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl b/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
new file mode 100644
index 000000000..02a99da59
--- /dev/null
+++ b/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
@@ -0,0 +1,29 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#ifndef COREV_MINI_MCU_MEMORY_H_
+#define COREV_MINI_MCU_MEMORY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+#include "core_v_mini_mcu.h"
+
+typedef struct memory_address {
+    unsigned int start;
+    unsigned int end;
+} xheep_memory_address_t;
+
+xheep_memory_address_t xheep_memory_regions[MEMORY_BANKS] = {
+% for bank in xheep.iter_ram_banks():
+    {.start = RAM${bank.name()}_START_ADDRESS, .end = RAM${bank.name()}_END_ADDRESS},
+% endfor
+};
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif  // __cplusplus
+
+#endif  // COREV_MINI_MCU_MEMORY_H_