From 38e212b2afd230acc2951d53c19cdca25183d111 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Mon, 16 Oct 2023 20:17:45 +0200 Subject: [PATCH 1/5] update cv32e40p verilator waiver --- hw/vendor/waiver/lint/cv32e40p.vlt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/vendor/waiver/lint/cv32e40p.vlt b/hw/vendor/waiver/lint/cv32e40p.vlt index 5f55d4577..65542b42f 100644 --- a/hw/vendor/waiver/lint/cv32e40p.vlt +++ b/hw/vendor/waiver/lint/cv32e40p.vlt @@ -111,3 +111,6 @@ lint_off -rule WIDTH -file "*/rtl/cv32e40p_controller.sv" -match "Logical operat lint_off -rule WIDTH -file "*/rtl/cv32e40p_controller.sv" -match "Logical operator IF expects 1 bit on the If, but If's VARREF 'COREV_PULP' generates 32 bits." lint_off -rule WIDTH -file "*/rtl/cv32e40p_cs_registers.sv" -match "Logical operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'COREV_PULP' generates 32 bits." lint_off -rule WIDTH -file "*/rtl/cv32e40p_decoder.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits*" +lint_off -rule WIDTH -file "*/rtl/cv32e40p_controller.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*" +lint_off -rule WIDTH -file "*/rtl/cv32e40p_cs_registers.sv" -match "Logical operator LOGOR expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*" +lint_off -rule LATCH -file "*/rtl/cv32e40p_id_stage.sv" -match "Latch inferred for signal*apu_read_regs*" From a1a938bb694fa6dfbee2e9029c3987acb864714f Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Mon, 16 Oct 2023 20:19:53 +0200 Subject: [PATCH 2/5] update cv32e40px verilator waiver --- hw/vendor/waiver/lint/cv32e40px.vlt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/vendor/waiver/lint/cv32e40px.vlt b/hw/vendor/waiver/lint/cv32e40px.vlt index 480681037..a6665860b 100644 --- a/hw/vendor/waiver/lint/cv32e40px.vlt +++ b/hw/vendor/waiver/lint/cv32e40px.vlt @@ -111,3 +111,6 @@ lint_off -rule WIDTH -file "*/rtl/cv32e40px_controller.sv" -match "Logical opera lint_off -rule WIDTH -file "*/rtl/cv32e40px_controller.sv" -match "Logical operator IF expects 1 bit on the If, but If's VARREF 'COREV_PULP' generates 32 bits." lint_off -rule WIDTH -file "*/rtl/cv32e40px_cs_registers.sv" -match "Logical operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'COREV_PULP' generates 32 bits." lint_off -rule WIDTH -file "*/rtl/cv32e40px_decoder.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits*" +lint_off -rule WIDTH -file "*/rtl/cv32e40px_controller.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*" +lint_off -rule WIDTH -file "*/rtl/cv32e40px_cs_registers.sv" -match "Logical operator LOGOR expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*" +lint_off -rule LATCH -file "*/rtl/cv32e40px_id_stage.sv" -match "Latch inferred for signal*apu_read_regs*" From 1a014239f684e4771fa74abb12bb944cefc5c380 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Mon, 16 Oct 2023 21:39:30 +0200 Subject: [PATCH 3/5] reduce FPGA frequency to 15MHz to accomodate FPU --- hw/fpga/scripts/xilinx_generate_clk_wizard.tcl | 4 ++-- sw/device/target/pynq-z2/x-heep.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl b/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl index 6a01c149f..1c2a41a09 100644 --- a/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl +++ b/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl @@ -5,7 +5,7 @@ set design_name xilinx_clk_wizard set in_clk_freq_MHz 125 -set out_clk_freq_MHz 20 +set out_clk_freq_MHz 15 # Select board set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project] @@ -25,7 +25,7 @@ set_property -dict [ list \ CONFIG.CLKIN1_JITTER_PS {80.0} \ CONFIG.CLKOUT1_JITTER {172.798} \ CONFIG.CLKOUT1_PHASE_ERROR {96.948} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \ CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \ CONFIG.MMCM_CLKIN1_PERIOD {8.000} \ CONFIG.MMCM_CLKOUT0_DIVIDE_F {50.000} \ diff --git a/sw/device/target/pynq-z2/x-heep.h b/sw/device/target/pynq-z2/x-heep.h index 844aed03c..768b4cbb1 100644 --- a/sw/device/target/pynq-z2/x-heep.h +++ b/sw/device/target/pynq-z2/x-heep.h @@ -12,7 +12,7 @@ extern "C" { #endif // __cplusplus -#define REFERENCE_CLOCK_Hz 20*1000*1000 +#define REFERENCE_CLOCK_Hz 15*1000*1000 #define UART_BAUDRATE 115200 #define TARGET_PYNQ_Z2 1 From 2d5d84d0a2cfe400a035584776d174cb9442bed5 Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Tue, 17 Oct 2023 09:22:39 +0200 Subject: [PATCH 4/5] reduced baudrate uart fpga --- sw/device/target/pynq-z2/x-heep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/device/target/pynq-z2/x-heep.h b/sw/device/target/pynq-z2/x-heep.h index 768b4cbb1..43cef0d47 100644 --- a/sw/device/target/pynq-z2/x-heep.h +++ b/sw/device/target/pynq-z2/x-heep.h @@ -13,7 +13,7 @@ extern "C" { #define REFERENCE_CLOCK_Hz 15*1000*1000 -#define UART_BAUDRATE 115200 +#define UART_BAUDRATE 9600 #define TARGET_PYNQ_Z2 1 /** From 394489500b0d0a451a2fc5e7e48fe5177a054a3e Mon Sep 17 00:00:00 2001 From: davide schiavone Date: Tue, 17 Oct 2023 11:55:35 +0200 Subject: [PATCH 5/5] update README --- README.md | 13 ++++++++++++- docs/source/How_to/ExecuteFromFlash.md | 2 ++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e63003cfc..0e0130b7c 100644 --- a/README.md +++ b/README.md @@ -514,9 +514,20 @@ to load the binaries with the HS2 cable over JTAG, or follow the [ExecuteFromFlash](./ExecuteFromFlash.md) guide if you have a FLASH attached to the FPGA. - Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running. +For example, if you want to run your application using flash_exec, do as follow: + +compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec` + +and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly. + +To look at the output of your printf, run in another terminal: + +`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2` + +Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example). + ### Linux-FEMU (Linux Fpga EMUlation) diff --git a/docs/source/How_to/ExecuteFromFlash.md b/docs/source/How_to/ExecuteFromFlash.md index a168a5b01..8413a1299 100644 --- a/docs/source/How_to/ExecuteFromFlash.md +++ b/docs/source/How_to/ExecuteFromFlash.md @@ -19,6 +19,8 @@ These three modes are mainly controlled by the two inputs pins | 1 | 1 | SPI Flash Execution | | 1 | 0 | SPI Flash Loading | + +On the FPGA, such inputs are mapped to two switch buttons. Below, a description of the three modes is provided. ### JTAG Boot Procedure