diff --git a/.github/workflows/simulate.yml b/.github/workflows/simulate.yml index 8e11e0851..7626d9ef7 100644 --- a/.github/workflows/simulate.yml +++ b/.github/workflows/simulate.yml @@ -17,6 +17,6 @@ jobs: conda activate core-v-mini-mcu make clean-all sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson - sed 's/num_channels: 0x1,/num_channels: 0x4,/' -i mcu_cfg.hjson + sed 's/num_channels: 0x1$/num_channels: 0x4/' -i mcu_cfg.hjson make mcu-gen MEMORY_BANKS=6 python3 .github/workflows/sim-apps-job/test_apps.py \ No newline at end of file diff --git a/configs/ci.hjson b/configs/ci.hjson index 51a278b7f..c788643fd 100644 --- a/configs/ci.hjson +++ b/configs/ci.hjson @@ -1,5 +1,5 @@ { - bus_type: "onetoM", + bus_type: "onetoM" ram_banks: { code_and_data: { num: 6 @@ -14,7 +14,7 @@ start: 0 #minimum size for freeRTOS and clang size: 0x00000D800 - }, + } { name: data start: 0x00000D800 diff --git a/configs/example_interleaved.hjson b/configs/example_interleaved.hjson index e831d7978..81f46cda6 100644 --- a/configs/example_interleaved.hjson +++ b/configs/example_interleaved.hjson @@ -1,5 +1,5 @@ { - bus_type: "NtoM", + bus_type: "NtoM" ram_banks: { code_and_data: { sizes: 64 @@ -31,7 +31,7 @@ start: 0 // minimum size for freeRTOS and clang size: 0x00000C800 - }, + } { name: data start: 0x00000C800 diff --git a/configs/general.hjson b/configs/general.hjson index d3465c500..d74ad88e3 100644 --- a/configs/general.hjson +++ b/configs/general.hjson @@ -1,6 +1,6 @@ { ram_address: 0 - bus_type: "onetoM", + bus_type: "onetoM" ram_banks: { code_and_data: { num: 2 @@ -15,7 +15,7 @@ start: 0 #minimum size for freeRTOS and clang size: 0x00000C800 - }, + } { name: data start: 0x00000C800 diff --git a/configs/testall.hjson b/configs/testall.hjson index 36828dc81..97ba92b81 100644 --- a/configs/testall.hjson +++ b/configs/testall.hjson @@ -1,5 +1,5 @@ { - bus_type: "onetoM", + bus_type: "onetoM" ram_banks: { code_and_data: { num: 3 @@ -14,7 +14,7 @@ start: 0 #minimum size for freeRTOS and clang size: 0x00000D800 - }, + } { name: data start: 0x00000D800 diff --git a/docs/source/Configuration/Configuration.rst b/docs/source/Configuration/Configuration.rst index c18a4e26b..d1bad2bbd 100644 --- a/docs/source/Configuration/Configuration.rst +++ b/docs/source/Configuration/Configuration.rst @@ -92,7 +92,7 @@ The other name can be used in code with a `.xheep_` prefix, like in `example_mat { ram_address: 0 - bus_type: "onetoM", + bus_type: "onetoM" ram_banks: { code_and_data: { num: 2 diff --git a/docs/source/How_to/IntegratePeripheral.md b/docs/source/How_to/IntegratePeripheral.md index f39bdbd19..ea3dafaf0 100644 --- a/docs/source/How_to/IntegratePeripheral.md +++ b/docs/source/How_to/IntegratePeripheral.md @@ -85,17 +85,17 @@ b. The module `xilinx_core_v_mini_mcu_wrapper` should be modified as follows: + inout logic [X-1:0] gpio_io, ``` -c. The pads configuration (pad_cfg.json) must be adapted as well: +c. The pads configuration (pad_cfg.hjson) must be adapted as well: ```diff gpio: { -- num: , -+ num: , - num_offset: 0, #first gpio is gpio0 +- num: ++ num: + num_offset: 0 # first gpio is gpio0 type: inout }, + pdm2pcm_pdm: { -+ num: 1, ++ num: 1 + type: inout + mux: { + : { @@ -153,14 +153,14 @@ II. The module must be instantiated in the peripheral subsystem: - hw/ip//.vlt ``` -8. The MCU configuration (mcu_cfg.json) must be adapted: +8. The MCU configuration (mcu_cfg.hjson) must be adapted: ```diff peripherals: { <...> + : { -+ offset: 0x00060000, -+ length: 0x00010000, ++ offset: 0x00060000 ++ length: 0x00010000 + }, }, ``` @@ -237,9 +237,9 @@ reg2hw.register.q // Data to be read from a register ``` { window: { - name: "RX_WINDOW_NAME", - items: "1", - validbits: "32", + name: "RX_WINDOW_NAME" + items: "1" + validbits: "32" desc: '''Window purpose description''' swaccess: "ro" } @@ -314,10 +314,10 @@ If the GPIOs usage has changed, the testbench must be adapted as follows: ``` ## Add an interrupt -You must register the interrupt in the MCU configuration `mcu_cfg.json`. +You must register the interrupt in the MCU configuration `mcu_cfg.hjson`. ```diff interrupts: { - number: 64, // Do not change this number! + number: 64 // Do not change this number! list: { ... + : diff --git a/docs/source/How_to/eXtendingHEEP.md b/docs/source/How_to/eXtendingHEEP.md index 0f875a5f1..6094f88be 100644 --- a/docs/source/How_to/eXtendingHEEP.md +++ b/docs/source/How_to/eXtendingHEEP.md @@ -38,15 +38,15 @@ In order to vendorize `X-HEEP` create inside your repository's base directory (` // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 { - name: "esl_epfl_x_heep", - target_dir: "esl_epfl_x_heep", + name: "esl_epfl_x_heep" + target_dir: "esl_epfl_x_heep" upstream: { - url: "https://github.com/esl-epfl/x-heep.git", - rev: "main", + url: "https://github.com/esl-epfl/x-heep.git" + rev: "main" }, - patch_dir: "patches/esl_epfl_x_heep", + patch_dir: "patches/esl_epfl_x_heep" exclude_from_upstream: [ ".github", diff --git a/hw/ip/dma/data/dma.hjson b/hw/ip/dma/data/dma.hjson index 58f6d3a03..11043984f 100644 --- a/hw/ip/dma/data/dma.hjson +++ b/hw/ip/dma/data/dma.hjson @@ -2,306 +2,306 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "dma", - clock_primary: "clk_i", +{ name: "dma" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" registers: [ - { name: "SRC_PTR", - desc: "Input data pointer (word aligned)", - swaccess: "rw", - hwaccess: "hro", + { name: "SRC_PTR" + desc: "Input data pointer (word aligned)" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "31:0", name: "PTR_IN", desc: "Input data pointer (word aligned)" } ] - }, - { name: "DST_PTR", - desc: "Output data pointer (word aligned)", - swaccess: "rw", - hwaccess: "hro", + } + { name: "DST_PTR" + desc: "Output data pointer (word aligned)" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" } ] - }, - { name: "ADDR_PTR", - desc: "Addess data pointer (word aligned)", - swaccess: "rw", - hwaccess: "hro", + } + { name: "ADDR_PTR" + desc: "Addess data pointer (word aligned)" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "31:0", name: "PTR_ADDR", desc: "Address data pointer (word aligned) - used only in Address mode" } ] - }, - { name: "SIZE_D1", - desc: "Number of bytes to copy from, defined with respect to the first dimension - Once a value is written, the copy starts", - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse + } + { name: "SIZE_D1" + desc: "Number of bytes to copy from, defined with respect to the first dimension - Once a value is written, the copy starts" + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse // Dimensioned to 16 bits to allow for 64kB transfers on 1D fields: [ { bits: "15:0", name: "SIZE", desc: "DMA counter D1 and start" } ] - }, - { name: "SIZE_D2", - desc: "Number of bytes to copy from, defined with respect to the second dimension", - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse + } + { name: "SIZE_D2" + desc: "Number of bytes to copy from, defined with respect to the second dimension" + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse // Dimensioned to 16 bits to allow for 64kB transfers on 2D fields: [ { bits: "15:0", name: "SIZE", desc: "DMA counter D2" } ] - }, - { name: "STATUS", - desc: '''Status bits are set to one if a given event occurred''', - swaccess: "ro", - hwaccess: "hrw", - hwext: "true", - hwre: "true", // enable `re` latched signal of software read pulse - resval: 1, + } + { name: "STATUS" + desc: '''Status bits are set to one if a given event occurred''' + swaccess: "ro" + hwaccess: "hrw" + hwext: "true" + hwre: "true" // enable `re` latched signal of software read pulse + resval: 1 fields: [ - { bits: "0", name: "READY", desc: "Transaction is done"}, - { bits: "1", name: "WINDOW_DONE", desc: "set if DMA is copying second half"}, + { bits: "0", name: "READY", desc: "Transaction is done"} + { bits: "1", name: "WINDOW_DONE", desc: "set if DMA is copying second half"} ] - }, - { name: "SRC_PTR_INC_D1", - desc: "Increment the D1 source pointer every time a word is copied", - swaccess: "rw", - hwaccess: "hro", + } + { name: "SRC_PTR_INC_D1" + desc: "Increment the D1 source pointer every time a word is copied" + swaccess: "rw" + hwaccess: "hro" // Dimensioned to allow a maximum of a 15 element stride for a data_type_word case fields: [ - { bits: "5:0", - name: "INC", - desc: "Source pointer d1 increment", + { bits: "5:0" + name: "INC" + desc: "Source pointer d1 increment" resval:4 } ] - }, - { name: "SRC_PTR_INC_D2", - desc: "Increment the D2 source pointer every time a word is copied", - swaccess: "rw", - hwaccess: "hro", + } + { name: "SRC_PTR_INC_D2" + desc: "Increment the D2 source pointer every time a word is copied" + swaccess: "rw" + hwaccess: "hro" // Dimensioned to allow a maximum of 15 element stride for a data_type_word fields: [ - { bits: "22:0", - name: "INC", - desc: "Source pointer d2 increment", + { bits: "22:0" + name: "INC" + desc: "Source pointer d2 increment" resval:4 } ] - }, - { name: "DST_PTR_INC_D1", - desc: "Increment the D1 destination pointer every time a word is copied", - swaccess: "rw", - hwaccess: "hro", + } + { name: "DST_PTR_INC_D1" + desc: "Increment the D1 destination pointer every time a word is copied" + swaccess: "rw" + hwaccess: "hro" fields: [ - { bits: "5:0", - name: "INC", - desc: "Destination pointer d1 increment", + { bits: "5:0" + name: "INC" + desc: "Destination pointer d1 increment" resval:4 } ] - }, - { name: "DST_PTR_INC_D2", - desc: "Increment the D2 destination pointer every time a word is copied", - swaccess: "rw", - hwaccess: "hro", + } + { name: "DST_PTR_INC_D2" + desc: "Increment the D2 destination pointer every time a word is copied" + swaccess: "rw" + hwaccess: "hro" fields: [ - { bits: "22:0", - name: "INC", - desc: "Destination pointer d2 increment", + { bits: "22:0" + name: "INC" + desc: "Destination pointer d2 increment" resval:4 } ] - }, - { name: "SLOT", + } + { name: "SLOT" desc: '''The DMA will wait for the signal connected to the selected trigger_slots to be high - on the read and write side respectivly''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + on the read and write side respectivly''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ - { bits: "15:0", name: "RX_TRIGGER_SLOT", + { bits: "15:0", name: "RX_TRIGGER_SLOT" desc: "Slot selection mask" - }, - { bits: "31:16", name: "TX_TRIGGER_SLOT", + } + { bits: "31:16", name: "TX_TRIGGER_SLOT" desc: "Slot selection mask" } ] - }, - { name: "SRC_DATA_TYPE", - desc: '''Width/type of the source data to transfer''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + } + { name: "SRC_DATA_TYPE" + desc: '''Width/type of the source data to transfer''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ - { bits: "1:0", name: "DATA_TYPE", - desc: "Data type", + { bits: "1:0", name: "DATA_TYPE" + desc: "Data type" enum: [ - { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"}, - { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"}, - { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers 8 bits"}, - { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers 8 bits"}, + { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"} + { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"} + { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers 8 bits"} + { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers 8 bits"} ] } ] - }, - { name: "DST_DATA_TYPE", - desc: '''Width/type of the destination data to transfer''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + } + { name: "DST_DATA_TYPE" + desc: '''Width/type of the destination data to transfer''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ - { bits: "1:0", name: "DATA_TYPE", - desc: "Data type", + { bits: "1:0", name: "DATA_TYPE" + desc: "Data type" enum: [ - { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"}, - { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"}, - { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers 8 bits"}, - { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers 8 bits"}, + { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"} + { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"} + { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers 8 bits"} + { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers 8 bits"} ] } ] - }, + } { - name: "SIGN_EXT", - desc: '''Is the data to be sign extended? (Checked only if the dst data type is wider than the src data type)''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + name: "SIGN_EXT" + desc: '''Is the data to be sign extended? (Checked only if the dst data type is wider than the src data type)''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ - { bits: "0", name: "SIGNED", - desc: "Extend the sign to the destination data", + { bits: "0", name: "SIGNED" + desc: "Extend the sign to the destination data" enum: [ - { value: "0", name: "NO_EXTEND", desc: "Does not extend the sign"}, - { value: "1", name: "EXTEND", desc: "Extends the sign"}, + { value: "0", name: "NO_EXTEND", desc: "Does not extend the sign"} + { value: "1", name: "EXTEND", desc: "Extends the sign"} ] } ] - }, - { name: "MODE", - desc: '''Set the operational mode of the DMA''', - swaccess: "rw", - hwaccess: "hro", + } + { name: "MODE" + desc: '''Set the operational mode of the DMA''' + swaccess: "rw" + hwaccess: "hro" fields: [ - { bits: "1:0", name: "MODE", - desc: "DMA operation mode", + { bits: "1:0", name: "MODE" + desc: "DMA operation mode" enum: [ - { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"}, - { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"}, - { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"}, + { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"} + { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"} + { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"} ] } ] - }, - { name: "DIM_CONFIG", - desc: '''Set the dimensionality of the DMA''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + } + { name: "DIM_CONFIG" + desc: '''Set the dimensionality of the DMA''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ { bits: "0", name: "DMA_DIM", desc: "DMA transfer dimensionality"} ] - }, - { name: "DIM_INV", - desc: '''DMA dimensionality inversion selector''', - swaccess: "rw", - hwaccess: "hro", - resval: 0, + } + { name: "DIM_INV" + desc: '''DMA dimensionality inversion selector''' + swaccess: "rw" + hwaccess: "hro" + resval: 0 fields: [ { bits: "0", name: "SEL", desc: "DMA dimensionality inversion, used to perform transposition"} ] - }, - { name: "PAD_TOP", - desc: '''Set the top padding''', - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse: used to trigger the padding - resval: 0, + } + { name: "PAD_TOP" + desc: '''Set the top padding''' + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse: used to trigger the padding + resval: 0 fields: [ { bits: "5:0", name: "PAD", desc: "Top margin padding (2D)"} ] - }, - { name: "PAD_BOTTOM", - desc: '''Set the bottom padding''', - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse: used to trigger the padding - resval: 0, + } + { name: "PAD_BOTTOM" + desc: '''Set the bottom padding''' + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse: used to trigger the padding + resval: 0 fields: [ { bits: "5:0", name: "PAD", desc: "Bottom margin padding (2D)"} ] - }, - { name: "PAD_RIGHT", - desc: '''Set the right padding''', - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse: used to trigger the padding - resval: 0, + } + { name: "PAD_RIGHT" + desc: '''Set the right padding''' + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse: used to trigger the padding + resval: 0 fields: [ { bits: "5:0", name: "PAD", desc: "Right margin padding (1D/2D)"} ] - }, - { name: "PAD_LEFT", - desc: '''Set the left padding''', - swaccess: "rw", - hwaccess: "hro", - hwqe: "true", // enable `qe` latched signal of software write pulse: used to trigger the padding - resval: 0, + } + { name: "PAD_LEFT" + desc: '''Set the left padding''' + swaccess: "rw" + hwaccess: "hro" + hwqe: "true" // enable `qe` latched signal of software write pulse: used to trigger the padding + resval: 0 fields: [ { bits: "5:0", name: "PAD", desc: "Left margin padding (1D/2D)"} ] - }, - { name: "WINDOW_SIZE", + } + { name: "WINDOW_SIZE" desc: '''Will trigger a every "WINDOW_SIZE" writes - Set to 0 to disable.''', - swaccess: "rw", - hwaccess: "hro", + Set to 0 to disable.''' + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "12:0", name: "WINDOW_SIZE", desc: ""} ] - }, - { name: "WINDOW_COUNT", + } + { name: "WINDOW_COUNT" desc: '''Number of times the end of the window was reached since the beginning. - Reset at start''', - swaccess: "ro", - // hwext: "true", - hwaccess: "hrw", - resval: 0, + Reset at start''' + swaccess: "ro" + //hwext: "true" + hwaccess: "hrw" + resval: 0 fields: [ { bits: "7:0", name: "WINDOW_COUNT", desc: "Number of windows transferred in the transaction" } ] - }, - { name: "INTERRUPT_EN", + } + { name: "INTERRUPT_EN" desc: '''Interrupt Enable Register - (Only the interrupt with the lowest id will be triggered)''', - swaccess: "rw", - hwaccess: "hro", + (Only the interrupt with the lowest id will be triggered)''' + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "0", name: "TRANSACTION_DONE", desc: "Enables transaction done interrupt" } { bits: "1", name: "WINDOW_DONE", desc: "Enables window done interrupt" } ] - }, - { name: "TRANSACTION_IFR", - desc: '''Interrupt Flag Register for transactions''', - swaccess: "ro", - hwaccess: "hrw", - hwext: "true", - hwre: "true", // latched signal of software write pulse - resval: 0, + } + { name: "TRANSACTION_IFR" + desc: '''Interrupt Flag Register for transactions''' + swaccess: "ro" + hwaccess: "hrw" + hwext: "true" + hwre: "true" // latched signal of software write pulse + resval: 0 fields: [ { bits: "0", name: "FLAG", desc: "Set for transaction done interrupt" } ] - }, - { name: "WINDOW_IFR", - desc: '''Interrupt Flag Register for windows''', - swaccess: "ro", - hwaccess: "hrw", - hwext: "true", - hwre: "true", // latched signal of software write pulse - resval: 0, + } + { name: "WINDOW_IFR" + desc: '''Interrupt Flag Register for windows''' + swaccess: "ro" + hwaccess: "hrw" + hwext: "true" + hwre: "true" // latched signal of software write pulse + resval: 0 fields: [ { bits: "0", name: "FLAG", desc: "Set for window done interrupt" } ] diff --git a/hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson b/hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson index 1bb0642b2..0b961fb75 100644 --- a/hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson +++ b/hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson @@ -1,38 +1,38 @@ // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "fast_intr_ctrl", - clock_primary: "clk_i", +{ name: "fast_intr_ctrl" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" registers: [ - { name: "FAST_INTR_PENDING", - desc: "Pending fast interrupt", + { name: "FAST_INTR_PENDING" + desc: "Pending fast interrupt" resval: "0x00000000" - swaccess: "ro", - hwaccess: "hrw", + swaccess: "ro" + hwaccess: "hrw" fields: [ { bits: "14:0", name: "FAST_INTR_PENDING", desc: "Pending Fast Interrupt Reg" } ] } - { name: "FAST_INTR_CLEAR", - desc: "Clear fast interrupt", + { name: "FAST_INTR_CLEAR" + desc: "Clear fast interrupt" resval: "0x00000000" - swaccess: "rw", - hwaccess: "hrw", + swaccess: "rw" + hwaccess: "hrw" fields: [ { bits: "14:0", name: "FAST_INTR_CLEAR", desc: "Clear Fast Interrupt" } ] } - { name: "FAST_INTR_ENABLE", - desc: "Enable fast interrupt", + { name: "FAST_INTR_ENABLE" + desc: "Enable fast interrupt" resval: "0x7fff" - swaccess: "rw", - hwaccess: "hro", + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "14:0", name: "FAST_INTR_ENABLE", desc: "Enable fast interrupt" } ] diff --git a/hw/ip/i2s/data/i2s.hjson b/hw/ip/i2s/data/i2s.hjson index 95b1e3be4..dabba7fb3 100644 --- a/hw/ip/i2s/data/i2s.hjson +++ b/hw/ip/i2s/data/i2s.hjson @@ -2,35 +2,35 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "i2s", - clock_primary: "clk_i", +{ name: "i2s" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" param_list: [ - { name: "MaxWordWidth", - desc: '''Defines the maximal word width''', - type: "int", + { name: "MaxWordWidth" + desc: '''Defines the maximal word width''' + type: "int" default: "32" } - { name: "ClkDividerWidth", - desc: '''Bits available for the clock divider''', - type: "int", + { name: "ClkDividerWidth" + desc: '''Bits available for the clock divider''' + type: "int" default: "16" } - { name: "WatermarkWidth", - desc: '''Bits available for the watermark''', - type: "int", + { name: "WatermarkWidth" + desc: '''Bits available for the watermark''' + type: "int" default: "16" } ] interrupt_list: [ - { name: "i2s_event", + { name: "i2s_event" desc: '''Event-related interrupts.''' } - ], - no_auto_intr_regs: "true", + ] + no_auto_intr_regs: "true" registers: [ @@ -45,34 +45,34 @@ { bits: "0", name: "EN", desc: "Enable I2s - CLK Domain" } { bits: "1", name: "EN_WS", desc: "Enable word select generation" } { bits: "3:2", name: "EN_RX", desc: "Enable rx channels" - resval: "0", + resval: "0" enum: [ - { value: "0", name: "DISABLED", desc: "Disable I2s" }, - { value: "1", name: "ONLY_LEFT", desc: "Enable left channel" }, - { value: "2", name: "ONLY_RIGHT", desc: "Enable right channel" }, - { value: "3", name: "BOTH_CHANNELS", desc: "Enable both channels" }, + { value: "0", name: "DISABLED", desc: "Disable I2s" } + { value: "1", name: "ONLY_LEFT", desc: "Enable left channel" } + { value: "2", name: "ONLY_RIGHT", desc: "Enable right channel" } + { value: "3", name: "BOTH_CHANNELS", desc: "Enable both channels" } ] } { bits: "4", name: "INTR_EN", desc: "enable watermark interrupt" } { bits: "5", name: "EN_WATERMARK", desc: "en watermark counter" } { bits: "6", name: "RESET_WATERMARK", desc: "reset watermark counter", hwaccess: "hrw"} { bits: "7", name: "EN_IO", desc: "connects the peripheral to the IOs" } - { bits: "9:8", name: "DATA_WIDTH", - desc: "Bytes per sample", - resval: "3", + { bits: "9:8", name: "DATA_WIDTH" + desc: "Bytes per sample" + resval: "3" enum: [ - { value: "0", name: "8_BITS", desc: "8 bits" }, - { value: "1", name: "16_BITS", desc: "16 bits" }, - { value: "2", name: "24_BITS", desc: "24 bits" }, + { value: "0", name: "8_BITS", desc: "8 bits" } + { value: "1", name: "16_BITS", desc: "16 bits" } + { value: "2", name: "24_BITS", desc: "24 bits" } { value: "3", name: "32_BITS", desc: "32 bits" } ] } - { bits: "10", name: "RX_START_CHANNEL", - desc: "Channel (left/right) of first sample - alternating afterwards.", - resval: "0", + { bits: "10", name: "RX_START_CHANNEL" + desc: "Channel (left/right) of first sample - alternating afterwards." + resval: "0" enum: [ - { value: "0", name: "LEFT_FIRST", desc: "Start left channel first (default for WAVE)"}, - { value: "1", name: "RIGHT_FIRST", desc: "Start right channel first"}, + { value: "0", name: "LEFT_FIRST", desc: "Start left channel first (default for WAVE)"} + { value: "1", name: "RIGHT_FIRST", desc: "Start right channel first"} ] } { bits: "11", name: "RESET_RX_OVERFLOW", desc: "reset rx overflow", hwaccess: "hrw"} @@ -96,13 +96,13 @@ desc: "Control register" swaccess: "rw" hwaccess: "hro" - resval: 4, + resval: 4 fields: [ { bits: "15:0", name: "COUNT", desc: "Index at which clock divide." } ] } // RX DATA - { name: "RXDATA", + { name: "RXDATA" desc: "I2s Receive data" swaccess: "ro" hwaccess: "hrw" diff --git a/hw/ip/obi_spimemio/data/obi_spimemio.hjson b/hw/ip/obi_spimemio/data/obi_spimemio.hjson index c4c0424f1..8ea6e0740 100644 --- a/hw/ip/obi_spimemio/data/obi_spimemio.hjson +++ b/hw/ip/obi_spimemio/data/obi_spimemio.hjson @@ -1,26 +1,26 @@ // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "obi_spimemio", - clock_primary: "clk_i", +{ name: "obi_spimemio" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" registers: [ - { name: "START_SPIMEM", - desc: "Start SPIMEM", - swaccess: "rw", - hwaccess: "hro", + { name: "START_SPIMEM" + desc: "Start SPIMEM" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "0", name: "START_SPIMEM", desc: "Start YosysHQ SPIMEM Reg" } ] } - { name: "CFG_SPIMEM", - desc: "Cfg SPIMEM", + { name: "CFG_SPIMEM" + desc: "Cfg SPIMEM" //none as we use it only to generate the SW - swaccess: "none", - hwaccess: "none", + swaccess: "none" + hwaccess: "none" fields: [ { bits: "31:0", name: "CFG_SPIMEM", desc: "Cfg YosysHQ SPIMEM Reg" } ] diff --git a/hw/ip/pdm2pcm/data/pdm2pcm.hjson b/hw/ip/pdm2pcm/data/pdm2pcm.hjson index 0aa97ab20..ae1c0d972 100644 --- a/hw/ip/pdm2pcm/data/pdm2pcm.hjson +++ b/hw/ip/pdm2pcm/data/pdm2pcm.hjson @@ -297,9 +297,9 @@ ] } { window: { - name: "RXDATA", - items: "1", - validbits: "32", + name: "RXDATA" + items: "1" + validbits: "32" desc: '''PCM Receive data ''' swaccess: "ro" diff --git a/hw/ip/soc_ctrl/data/soc_ctrl.hjson b/hw/ip/soc_ctrl/data/soc_ctrl.hjson index 827514b65..4f9b1e8c1 100644 --- a/hw/ip/soc_ctrl/data/soc_ctrl.hjson +++ b/hw/ip/soc_ctrl/data/soc_ctrl.hjson @@ -1,77 +1,77 @@ // Copyright lowRISC contributors. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "soc_ctrl", - clock_primary: "clk_i", +{ name: "soc_ctrl" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" registers: [ - { name: "EXIT_VALID", - desc: "Exit Valid - Used to write exit valid bit", - swaccess: "rw", - hwaccess: "hro", + { name: "EXIT_VALID" + desc: "Exit Valid - Used to write exit valid bit" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "0", name: "EXIT_VALID", desc: "Exit Valid Reg" } ] - }, - { name: "EXIT_VALUE", - desc: "Exit Value - Used to write exit value register", - swaccess: "rw", - hwaccess: "hro", + } + { name: "EXIT_VALUE" + desc: "Exit Value - Used to write exit value register" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "31:0", name: "EXIT_VALUE", desc: "Exit Value Reg" } ] } - { name: "BOOT_SELECT", - desc: "Boot Select Value - Used to decide whether to boot from JTAG or FLASH", - swaccess: "ro", - hwaccess: "hrw", + { name: "BOOT_SELECT" + desc: "Boot Select Value - Used to decide whether to boot from JTAG or FLASH" + swaccess: "ro" + hwaccess: "hrw" fields: [ { bits: "0", name: "BOOT_SELECT", desc: "Boot Select Reg" } ] } - { name: "BOOT_EXIT_LOOP", - desc: "Boot Exit Loop Value - Set externally (e.g. JTAG, TESTBENCH, or another MASTER) to make the CPU jump to the main function entry", - swaccess: "rw", - hwaccess: "hrw", + { name: "BOOT_EXIT_LOOP" + desc: "Boot Exit Loop Value - Set externally (e.g. JTAG, TESTBENCH, or another MASTER) to make the CPU jump to the main function entry" + swaccess: "rw" + hwaccess: "hrw" fields: [ { bits: "0", name: "BOOT_EXIT_LOOP", desc: "Boot Exit Reg" } ] } - { name: "BOOT_ADDRESS", - desc: "Boot Address Value - Used in the boot rom or power-on-reset functions", + { name: "BOOT_ADDRESS" + desc: "Boot Address Value - Used in the boot rom or power-on-reset functions" resval: "0x00000180" - swaccess: "rw", - hwaccess: "hro", + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "31:0", name: "BOOT_ADDRESS", desc: "Boot Address Reg" } ] } - { name: "USE_SPIMEMIO", - desc: "Spi Module Select Value - Used to decide whether to use the SPI from Yosys or OpenTitan", + { name: "USE_SPIMEMIO" + desc: "Spi Module Select Value - Used to decide whether to use the SPI from Yosys or OpenTitan" resval: "0x1" - swaccess: "rw", - hwaccess: "hrw", + swaccess: "rw" + hwaccess: "hrw" fields: [ { bits: "0", name: "USE_SPIMEMIO", desc: "Spi Select Reg" } ] } - { name: "ENABLE_SPI_SEL", - desc: "Enable Spi module selection from software", + { name: "ENABLE_SPI_SEL" + desc: "Enable Spi module selection from software" resval: "0x0" - swaccess: "rw", - hwaccess: "hro", + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "0", name: "ENABLE_SPI_SEL", desc: "Enable Spi Select Reg" } ] } - { name: "SYSTEM_FREQUENCY_HZ", - desc: "System Frequency Value - Used to know and set at which frequency the system is running (in Hz)", + { name: "SYSTEM_FREQUENCY_HZ" + desc: "System Frequency Value - Used to know and set at which frequency the system is running (in Hz)" resval: "0x1" - swaccess: "rw", - hwaccess: "none", + swaccess: "rw" + hwaccess: "none" fields: [ { bits: "31:0", name: "SYSTEM_FREQUENCY_HZ", desc: "Contains the value in Hz of the frequency the system is running" } ] diff --git a/hw/ip_examples/ams/data/ams.hjson b/hw/ip_examples/ams/data/ams.hjson index 38dad9dcb..20c1294e0 100644 --- a/hw/ip_examples/ams/data/ams.hjson +++ b/hw/ip_examples/ams/data/ams.hjson @@ -2,29 +2,29 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "ams", - clock_primary: "clk_i", +{ name: "ams" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], - regwidth: "32", + ] + regwidth: "32" registers: [ - { name: "SEL", - desc: "Select the ADC threshold value (20%, 40%, 60%, 80% of VDD)", - swaccess: "rw", - hwaccess: "hro", + { name: "SEL" + desc: "Select the ADC threshold value (20%, 40%, 60%, 80% of VDD)" + swaccess: "rw" + hwaccess: "hro" fields: [ { bits: "1:0", name:"VALUE", desc: "Set the ADC threshold value" } ] - }, - { name: "GET", - desc: "Get the ADC output", - swaccess: "ro", - hwaccess: "hrw", + } + { name: "GET" + desc: "Get the ADC output" + swaccess: "ro" + hwaccess: "hrw" fields: [ { bits: "0", name:"VALUE", desc: "Get the ADC output" } ] - }, + } ] } diff --git a/hw/ip_examples/iffifo/data/iffifo.hjson b/hw/ip_examples/iffifo/data/iffifo.hjson index 919cceaf6..9090e6ea4 100644 --- a/hw/ip_examples/iffifo/data/iffifo.hjson +++ b/hw/ip_examples/iffifo/data/iffifo.hjson @@ -6,7 +6,7 @@ clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } - ], + ] regwidth: 32 registers: [ diff --git a/mcu_cfg.hjson b/mcu_cfg.hjson index df55d1609..a5c148897 100644 --- a/mcu_cfg.hjson +++ b/mcu_cfg.hjson @@ -8,194 +8,194 @@ cpu_type: cv32e20 linker_script: { - stack_size: 0x800, - heap_size: 0x800, + stack_size: 0x800 + heap_size: 0x800 } debug: { - address: 0x10000000, - length: 0x00100000, - }, + address: 0x10000000 + length: 0x00100000 + } ao_peripherals: { - address: 0x20000000, - length: 0x00100000, + address: 0x20000000 + length: 0x00100000 soc_ctrl: { - offset: 0x00000000, - length: 0x00010000, + offset: 0x00000000 + length: 0x00010000 path: "./hw/ip/soc_ctrl/data/soc_ctrl.hjson" - }, + } bootrom: { - offset: 0x00010000, - length: 0x00010000, - }, + offset: 0x00010000 + length: 0x00010000 + } spi_flash: { - offset: 0x00020000, - length: 0x00008000, - }, + offset: 0x00020000 + length: 0x00008000 + } spi_memio: { - offset: 0x00028000, - length: 0x00008000, - }, + offset: 0x00028000 + length: 0x00008000 + } dma: { - offset: 0x00030000, - length: 0x00010000, - ch_length: 0x100, - num_channels: 0x1, + offset: 0x00030000 + length: 0x00010000 + ch_length: 0x100 + num_channels: 0x1 path: "./hw/ip/dma/data/dma.hjson" - }, + } power_manager: { - offset: 0x00040000, - length: 0x00010000, + offset: 0x00040000 + length: 0x00010000 path: "./hw/ip/power_manager/data/power_manager.hjson" - }, + } rv_timer_ao: { - offset: 0x00050000, - length: 0x00010000, - }, + offset: 0x00050000 + length: 0x00010000 + } fast_intr_ctrl: { - offset: 0x00060000, - length: 0x00010000, + offset: 0x00060000 + length: 0x00010000 path: "./hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson" - }, + } ext_peripheral: { - offset: 0x00070000, - length: 0x00010000, - }, + offset: 0x00070000 + length: 0x00010000 + } pad_control: { - offset: 0x00080000, - length: 0x00010000, - }, + offset: 0x00080000 + length: 0x00010000 + } gpio_ao: { - offset: 0x00090000, - length: 0x00010000, - }, + offset: 0x00090000 + length: 0x00010000 + } uart: { - offset: 0x000A0000, - length: 0x00010000, + offset: 0x000A0000 + length: 0x00010000 path: "./hw/vendor/lowrisc_opentitan/hw/ip/uart/data/uart.hjson" - }, - }, + } + } peripherals: { - address: 0x30000000, - length: 0x00100000, + address: 0x30000000 + length: 0x00100000 rv_plic: { - offset: 0x00000000, - length: 0x00010000, - is_included: "yes", + offset: 0x00000000 + length: 0x00010000 + is_included: "yes" path: "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson" - }, + } spi_host: { - offset: 0x00010000, - length: 0x00010000, - is_included: "yes", + offset: 0x00010000 + length: 0x00010000 + is_included: "yes" path: "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson" - }, + } gpio: { - offset: 0x00020000, - length: 0x00010000, - is_included: "yes", + offset: 0x00020000 + length: 0x00010000 + is_included: "yes" path: "./hw/vendor/pulp_platform_gpio/gpio_regs.hjson" - }, + } i2c: { - offset: 0x00030000, - length: 0x00010000, - is_included: "yes", + offset: 0x00030000 + length: 0x00010000 + is_included: "yes" path: "./hw/vendor/lowrisc_opentitan/hw/ip/i2c/data/i2c.hjson" - }, + } rv_timer: { - offset: 0x00040000, - length: 0x00010000, - is_included: "yes", + offset: 0x00040000 + length: 0x00010000 + is_included: "yes" path: "./hw/vendor/lowrisc_opentitan/hw/ip/rv_timer/data/rv_timer.hjson" - }, + } spi2: { - offset: 0x00050000, - length: 0x00010000, - is_included: "yes", - }, + offset: 0x00050000 + length: 0x00010000 + is_included: "yes" + } pdm2pcm: { - offset: 0x00060000, - length: 0x00010000, - is_included: "no", + offset: 0x00060000 + length: 0x00010000 + is_included: "no" path: "./hw/ip/pdm2pcm/data/pdm2pcm.hjson" - }, + } i2s: { - offset: 0x00070000, - length: 0x00010000, - is_included: "yes", + offset: 0x00070000 + length: 0x00010000 + is_included: "yes" path: "./hw/ip/i2s/data/i2s.hjson" - }, + } - }, + } flash_mem: { - address: 0x40000000, - length: 0x01000000, - }, + address: 0x40000000 + length: 0x01000000 + } ext_slaves: { - address: 0xF0000000, - length: 0x01000000, - }, + address: 0xF0000000 + length: 0x01000000 + } interrupts: { - number: 64, // Do not change this number! + number: 64 // Do not change this number! list: { // First one is always zero - null_intr: 0, - uart_intr_tx_watermark: 1, - uart_intr_rx_watermark: 2, - uart_intr_tx_empty: 3, - uart_intr_rx_overflow: 4, - uart_intr_rx_frame_err: 5, - uart_intr_rx_break_err: 6, - uart_intr_rx_timeout: 7, - uart_intr_rx_parity_err: 8, - gpio_intr_8: 9, - gpio_intr_9: 10, - gpio_intr_10: 11, - gpio_intr_11: 12, - gpio_intr_12: 13, - gpio_intr_13: 14, - gpio_intr_14: 15, - gpio_intr_15: 16, - gpio_intr_16: 17, - gpio_intr_17: 18, - gpio_intr_18: 19, - gpio_intr_19: 20, - gpio_intr_20: 21, - gpio_intr_21: 22, - gpio_intr_22: 23, - gpio_intr_23: 24, - gpio_intr_24: 25, - gpio_intr_25: 26, - gpio_intr_26: 27, - gpio_intr_27: 28, - gpio_intr_28: 29, - gpio_intr_29: 30, - gpio_intr_30: 31, - gpio_intr_31: 32, - intr_fmt_watermark: 33, - intr_rx_watermark: 34, - intr_fmt_overflow: 35, - intr_rx_overflow: 36, - intr_nak: 37, - intr_scl_interference: 38, - intr_sda_interference: 39, - intr_stretch_timeout: 40, - intr_sda_unstable: 41, - intr_trans_complete: 42, - intr_tx_empty: 43, - intr_tx_nonempty: 44, - intr_tx_overflow: 45, - intr_acq_overflow: 46, - intr_ack_stop: 47, - intr_host_timeout: 48, - spi2_intr_event: 49, - i2s_intr_event: 50, - dma_window_intr: 51, + null_intr: 0 + uart_intr_tx_watermark: 1 + uart_intr_rx_watermark: 2 + uart_intr_tx_empty: 3 + uart_intr_rx_overflow: 4 + uart_intr_rx_frame_err: 5 + uart_intr_rx_break_err: 6 + uart_intr_rx_timeout: 7 + uart_intr_rx_parity_err: 8 + gpio_intr_8: 9 + gpio_intr_9: 10 + gpio_intr_10: 11 + gpio_intr_11: 12 + gpio_intr_12: 13 + gpio_intr_13: 14 + gpio_intr_14: 15 + gpio_intr_15: 16 + gpio_intr_16: 17 + gpio_intr_17: 18 + gpio_intr_18: 19 + gpio_intr_19: 20 + gpio_intr_20: 21 + gpio_intr_21: 22 + gpio_intr_22: 23 + gpio_intr_23: 24 + gpio_intr_24: 25 + gpio_intr_25: 26 + gpio_intr_26: 27 + gpio_intr_27: 28 + gpio_intr_28: 29 + gpio_intr_29: 30 + gpio_intr_30: 31 + gpio_intr_31: 32 + intr_fmt_watermark: 33 + intr_rx_watermark: 34 + intr_fmt_overflow: 35 + intr_rx_overflow: 36 + intr_nak: 37 + intr_scl_interference: 38 + intr_sda_interference: 39 + intr_stretch_timeout: 40 + intr_sda_unstable: 41 + intr_trans_complete: 42 + intr_tx_empty: 43 + intr_tx_nonempty: 44 + intr_tx_overflow: 45 + intr_acq_overflow: 46 + intr_ack_stop: 47 + intr_host_timeout: 48 + spi2_intr_event: 49 + i2s_intr_event: 50 + dma_window_intr: 51 } } } diff --git a/mcu_cfg_minimal.hjson b/mcu_cfg_minimal.hjson index 0be257d7b..938f349ba 100644 --- a/mcu_cfg_minimal.hjson +++ b/mcu_cfg_minimal.hjson @@ -8,193 +8,193 @@ cpu_type: cv32e20 linker_script: { - stack_size: 0x800, - heap_size: 0x800, + stack_size: 0x800 + heap_size: 0x800 } debug: { - address: 0x10000000, - length: 0x00100000, - }, + address: 0x10000000 + length: 0x00100000 + } ao_peripherals: { - address: 0x20000000, - length: 0x00100000, + address: 0x20000000 + length: 0x00100000 soc_ctrl: { - offset: 0x00000000, - length: 0x00010000, + offset: 0x00000000 + length: 0x00010000 path: "./hw/ip/soc_ctrl/data/soc_ctrl.hjson" - }, + } bootrom: { - offset: 0x00010000, - length: 0x00010000, - }, + offset: 0x00010000 + length: 0x00010000 + } spi_flash: { - offset: 0x00020000, - length: 0x00008000, - }, + offset: 0x00020000 + length: 0x00008000 + } spi_memio: { - offset: 0x00028000, - length: 0x00008000, - }, + offset: 0x00028000 + length: 0x00008000 + } dma: { - offset: 0x00030000, - length: 0x00010000, - ch_length: 0x100, - num_channels: 0x1, + offset: 0x00030000 + length: 0x00010000 + ch_length: 0x100 + num_channels: 0x1 path: "./hw/ip/dma/data/dma.hjson" - }, + } power_manager: { - offset: 0x00040000, - length: 0x00010000, + offset: 0x00040000 + length: 0x00010000 path: "./hw/ip/power_manager/data/power_manager.hjson" - }, + } rv_timer_ao: { - offset: 0x00050000, - length: 0x00010000, - }, + offset: 0x00050000 + length: 0x00010000 + } fast_intr_ctrl: { - offset: 0x00060000, - length: 0x00010000, + offset: 0x00060000 + length: 0x00010000 path: "./hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson" - }, + } ext_peripheral: { - offset: 0x00070000, - length: 0x00010000, - }, + offset: 0x00070000 + length: 0x00010000 + } pad_control: { - offset: 0x00080000, - length: 0x00010000, - }, + offset: 0x00080000 + length: 0x00010000 + } gpio_ao: { - offset: 0x00090000, - length: 0x00010000, - }, + offset: 0x00090000 + length: 0x00010000 + } uart: { - offset: 0x000A0000, - length: 0x00010000, + offset: 0x000A0000 + length: 0x00010000 path: "./hw/vendor/lowrisc_opentitan/hw/ip/uart/data/uart.hjson" - }, - }, + } + } peripherals: { - address: 0x30000000, - length: 0x00100000, + address: 0x30000000 + length: 0x00100000 rv_plic: { - offset: 0x00000000, - length: 0x00010000, - is_included: "no", + offset: 0x00000000 + length: 0x00010000 + is_included: "no" path: "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson" - }, + } spi_host: { - offset: 0x00010000, - length: 0x00010000, - is_included: "no", + offset: 0x00010000 + length: 0x00010000 + is_included: "no" path: "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson" - }, + } gpio: { - offset: 0x00020000, - length: 0x00010000, - is_included: "no", + offset: 0x00020000 + length: 0x00010000 + is_included: "no" path: "./hw/vendor/pulp_platform_gpio/gpio_regs.hjson" - }, + } i2c: { - offset: 0x00030000, - length: 0x00010000, - is_included: "no", + offset: 0x00030000 + length: 0x00010000 + is_included: "no" path: "./hw/vendor/lowrisc_opentitan/hw/ip/i2c/data/i2c.hjson" - }, + } rv_timer: { - offset: 0x00040000, - length: 0x00010000, - is_included: "no", + offset: 0x00040000 + length: 0x00010000 + is_included: "no" path: "./hw/vendor/lowrisc_opentitan/hw/ip/rv_timer/data/rv_timer.hjson" - }, + } spi2: { - offset: 0x00050000, - length: 0x00010000, - is_included: "no", - }, + offset: 0x00050000 + length: 0x00010000 + is_included: "no" + } pdm2pcm: { - offset: 0x00060000, - length: 0x00010000, - is_included: "no", + offset: 0x00060000 + length: 0x00010000 + is_included: "no" path: "./hw/ip/pdm2pcm/data/pdm2pcm.hjson" - }, + } i2s: { - offset: 0x00070000, - length: 0x00010000, - is_included: "no", + offset: 0x00070000 + length: 0x00010000 + is_included: "no" path: "./hw/ip/i2s/data/i2s.hjson" - }, - }, + } + } flash_mem: { - address: 0x40000000, - length: 0x01000000, - }, + address: 0x40000000 + length: 0x01000000 + } ext_slaves: { - address: 0xF0000000, - length: 0x01000000, - }, + address: 0xF0000000 + length: 0x01000000 + } interrupts: { - number: 64, // Do not change this number! + number: 64 // Do not change this number! list: { // First one is always zero - null_intr: 0, - uart_intr_tx_watermark: 1, - uart_intr_rx_watermark: 2, - uart_intr_tx_empty: 3, - uart_intr_rx_overflow: 4, - uart_intr_rx_frame_err: 5, - uart_intr_rx_break_err: 6, - uart_intr_rx_timeout: 7, - uart_intr_rx_parity_err: 8, - gpio_intr_8: 9, - gpio_intr_9: 10, - gpio_intr_10: 11, - gpio_intr_11: 12, - gpio_intr_12: 13, - gpio_intr_13: 14, - gpio_intr_14: 15, - gpio_intr_15: 16, - gpio_intr_16: 17, - gpio_intr_17: 18, - gpio_intr_18: 19, - gpio_intr_19: 20, - gpio_intr_20: 21, - gpio_intr_21: 22, - gpio_intr_22: 23, - gpio_intr_23: 24, - gpio_intr_24: 25, - gpio_intr_25: 26, - gpio_intr_26: 27, - gpio_intr_27: 28, - gpio_intr_28: 29, - gpio_intr_29: 30, - gpio_intr_30: 31, - gpio_intr_31: 32, - intr_fmt_watermark: 33, - intr_rx_watermark: 34, - intr_fmt_overflow: 35, - intr_rx_overflow: 36, - intr_nak: 37, - intr_scl_interference: 38, - intr_sda_interference: 39, - intr_stretch_timeout: 40, - intr_sda_unstable: 41, - intr_trans_complete: 42, - intr_tx_empty: 43, - intr_tx_nonempty: 44, - intr_tx_overflow: 45, - intr_acq_overflow: 46, - intr_ack_stop: 47, - intr_host_timeout: 48, - spi2_intr_event: 49, - i2s_intr_event: 50, - dma_window_intr: 51, + null_intr: 0 + uart_intr_tx_watermark: 1 + uart_intr_rx_watermark: 2 + uart_intr_tx_empty: 3 + uart_intr_rx_overflow: 4 + uart_intr_rx_frame_err: 5 + uart_intr_rx_break_err: 6 + uart_intr_rx_timeout: 7 + uart_intr_rx_parity_err: 8 + gpio_intr_8: 9 + gpio_intr_9: 10 + gpio_intr_10: 11 + gpio_intr_11: 12 + gpio_intr_12: 13 + gpio_intr_13: 14 + gpio_intr_14: 15 + gpio_intr_15: 16 + gpio_intr_16: 17 + gpio_intr_17: 18 + gpio_intr_18: 19 + gpio_intr_19: 20 + gpio_intr_20: 21 + gpio_intr_21: 22 + gpio_intr_22: 23 + gpio_intr_23: 24 + gpio_intr_24: 25 + gpio_intr_25: 26 + gpio_intr_26: 27 + gpio_intr_27: 28 + gpio_intr_28: 29 + gpio_intr_29: 30 + gpio_intr_30: 31 + gpio_intr_31: 32 + intr_fmt_watermark: 33 + intr_rx_watermark: 34 + intr_fmt_overflow: 35 + intr_rx_overflow: 36 + intr_nak: 37 + intr_scl_interference: 38 + intr_sda_interference: 39 + intr_stretch_timeout: 40 + intr_sda_unstable: 41 + intr_trans_complete: 42 + intr_tx_empty: 43 + intr_tx_nonempty: 44 + intr_tx_overflow: 45 + intr_acq_overflow: 46 + intr_ack_stop: 47 + intr_host_timeout: 48 + spi2_intr_event: 49 + i2s_intr_event: 50 + dma_window_intr: 51 } } } diff --git a/pad_cfg.hjson b/pad_cfg.hjson index 1cfa8c798..65da702b8 100644 --- a/pad_cfg.hjson +++ b/pad_cfg.hjson @@ -21,259 +21,259 @@ // attributes: { // bits: 7:0 // resval: 0x3 -// }, +// } { pads: { clk: { - num: 1, + num: 1 type: input - }, + } rst: { - num: 1, - active: low, + num: 1 + active: low driven_manually: True type: input - }, + } boot_select: { - num: 1, + num: 1 type: input - }, + } execute_from_flash: { - num: 1, + num: 1 type: input - }, + } jtag_tck: { - num: 1, + num: 1 type: input - }, + } jtag_tms: { - num: 1, + num: 1 type: input - }, + } jtag_trst: { - num: 1, - active: low, + num: 1 + active: low type: input - }, + } jtag_tdi: { - num: 1, + num: 1 type: input - }, + } jtag_tdo: { - num: 1, + num: 1 type: output - }, + } uart_rx: { - num: 1, + num: 1 type: input - }, + } uart_tx: { - num: 1, + num: 1 type: output - }, + } exit_valid: { - num: 1, + num: 1 type: output - }, + } gpio: { - num: 18, - num_offset: 0, #first gpio is gpio0 + num: 18 + num_offset: 0 # first gpio is gpio0 type: inout - }, + } spi_flash_sck: { - num: 1, + num: 1 type: inout - }, + } spi_flash_cs: { - num: 2, #carefull, the x-heep uses the CS from the spi pkg, change it + num: 2 # careful, the x-heep uses the CS from the spi pkg, change it type: inout - }, + } spi_flash_sd: { - num: 4, + num: 4 type: inout - }, + } spi_sck: { - num: 1, + num: 1 type: inout - }, + } spi_cs: { - num: 2, + num: 2 type: inout - }, + } spi_sd: { - num: 4, + num: 4 type: inout - }, + } pdm2pcm_pdm: { - num: 1, + num: 1 type: inout mux: { pdm2pcm_pdm: { type: inout - }, + } gpio_18: { type: inout } } - }, + } pdm2pcm_clk: { - num: 1, + num: 1 type: inout mux: { pdm2pcm_clk: { type: inout - }, + } gpio_19: { type: inout } } - }, + } i2s_sck: { - num: 1, + num: 1 type: inout mux: { i2s_sck: { type: inout - }, + } gpio_20: { type: inout } } - }, + } i2s_ws: { - num: 1, + num: 1 type: inout mux: { i2s_ws: { type: inout - }, + } gpio_21: { type: inout } } - }, + } i2s_sd: { - num: 1, + num: 1 type: inout mux: { i2s_sd: { type: inout - }, + } gpio_22: { type: inout } } - }, + } spi2_cs_0: { - num: 1, + num: 1 type: inout mux: { spi2_cs_0: { type: inout - }, + } gpio_23: { type: inout - }, + } } - }, + } spi2_cs_1: { - num: 1, + num: 1 type: inout mux: { spi2_cs_1: { type: inout - }, + } gpio_24: { type: inout - }, - }, - }, + } + } + } spi2_sck: { - num: 1, + num: 1 type: inout mux: { spi2_sck: { type: inout - }, + } gpio_25: { type: inout - }, + } } - }, + } spi2_sd_0: { - num: 1, + num: 1 type: inout mux: { spi2_sd_0: { type: inout - }, + } gpio_26: { type: inout - }, + } } - }, + } spi2_sd_1: { - num: 1, + num: 1 type: inout mux: { spi2_sd_1: { type: inout - }, + } gpio_27: { type: inout - }, + } } - }, + } spi2_sd_2: { - num: 1, + num: 1 type: inout mux: { spi2_sd_2: { type: inout - }, + } gpio_28: { type: inout - }, + } } - }, + } spi2_sd_3: { - num: 1, + num: 1 type: inout mux: { spi2_sd_3: { type: inout - }, + } gpio_29: { type: inout - }, + } } - }, + } i2c_scl: { - num: 1, + num: 1 type: inout mux: { i2c_scl: { type: inout - }, + } gpio_31: { type: inout - }, + } } - }, + } i2c_sda: { - num: 1, + num: 1 type: inout mux: { i2c_sda: { type: inout - }, + } gpio_30: { type: inout - }, + } } } }