diff --git a/hw/ip_examples/ams/ams.core b/hw/ip_examples/ams/ams.core
index c6eb491fa..51ae7498f 100644
--- a/hw/ip_examples/ams/ams.core
+++ b/hw/ip_examples/ams/ams.core
@@ -15,7 +15,7 @@ filesets:
     - rtl/ams_reg_pkg.sv
     - rtl/ams_reg_top.sv
     - rtl/ams.sv
-    - "!ams_sim? (rtl/dummy_adc.sv)"
+    - "!ams_sim? (rtl/dummy_myinverter.sv)"
     file_type: systemVerilogSource
 
 targets:
diff --git a/hw/ip_examples/ams/analog/adc.sp b/hw/ip_examples/ams/analog/adc.sp
deleted file mode 100644
index 5ce63745b..000000000
--- a/hw/ip_examples/ams/analog/adc.sp
+++ /dev/null
@@ -1,94 +0,0 @@
-** Copyright EPFL contributors.
-** Licensed under the Apache License, Version 2.0, see LICENSE for details.
-** SPDX-License-Identifier: Apache-2.0
-
-** Uses the 65nm_bulk PTM Bulk CMOS model, February 22, 2006 release
-** (obtained from https://ptm.asu.edu)
-
-.include "../../../hw/ip_examples/ams/analog/65nm_bulk.pm"
-
-v_vdd VDD 0 1.2
-v_gnd GND 0 0
-.global VDD GND
-
-.subckt INVERTER GND IN OUT VDD
-MN0 OUT IN GND GND nmos L=60n W=400n
-MN1 OUT IN VDD VDD pmos L=60n W=400n
-.ends INVERTER
-
-.subckt DEMUX A B C D GND SEL_0 SEL_1 VDD
-MN20 B SEL_0_not GND GND  nmos L=60n W=200n
-MN18 B SEL_1 GND GND nmos L=60n W=200n
-MN17 C SEL_1_not GND GND nmos L=60n W=200n
-MN15 C SEL_0 GND GND nmos L=60n W=200n
-MN9 A SEL_1 GND GND nmos L=60n W=200n
-MN7 A SEL_0 GND GND nmos L=60n W=200n
-MN13 D SEL_1_not GND GND nmos L=60n W=200n
-MN11 D SEL_0_not GND GND nmos L=60n W=200n
-XI4 GND SEL_1 SEL_1_not VDD INVERTER
-XI3 GND SEL_0 SEL_0_not VDD INVERTER
-MN21 B SEL_0_not net25 VDD pmos L=60n W=800n
-MN19 net25 SEL_1 VDD VDD pmos L=60n W=800n
-MN16 net26 SEL_1_not VDD VDD pmos L=60n W=800n
-MN14 C SEL_0 net26 VDD pmos L=60n W=800n
-MN8 net28 SEL_1 VDD VDD pmos L=60n W=800n
-MN6 A SEL_0 net28 VDD pmos L=60n W=800n
-MN10 D SEL_0_not net27 VDD pmos L=60n W=800n
-MN12 net27 SEL_1_not VDD VDD pmos L=60n W=800n
-.ends DEMUX
-
-.subckt ANALOG_MUX A B C D GND OUT SEL_0 SEL_1 VDD
-XI0 SEL_A SEL_B SEL_C SEL_D GND SEL_0 SEL_1 VDD DEMUX
-XI4 GND SEL_C SEL_C_not VDD INVERTER
-XI3 GND SEL_D SEL_D_not VDD INVERTER
-XI1 GND SEL_A SEL_A_not VDD INVERTER
-XI2 GND SEL_B SEL_B_not VDD INVERTER
-MN4 OUT SEL_D_not D VDD pmos L=60n W=2u
-MN2 OUT SEL_B_not B VDD pmos L=60n W=2u
-MN0 OUT SEL_A_not A VDD pmos L=60n W=2u
-MN21 OUT SEL_C_not C VDD pmos L=60n W=2u
-MN5 D SEL_D OUT GND nmos L=60n W=1u
-MN3 B SEL_B OUT GND nmos L=60n W=1u
-MN1 A SEL_A OUT GND nmos L=60n W=1u
-MN20 C SEL_C OUT GND nmos L=60n W=1u
-.ends ANALOG_MUX
-
-.subckt COMPARATOR GND IN_N IN_P OUT VDD
-MN52 OUT net54 VDD VDD pmos L=60n W=1.2u
-MN49 net52 net29 net31 VDD pmos L=60n W=1.2u
-MN48 net54 net24 net31 VDD pmos L=60n W=1.2u
-MN34 net15 net15 VDD VDD pmos L=60n W=1.2u
-MN39 net29 net51 VDD VDD pmos L=60n W=1.2u
-MN38 net51 net51 VDD VDD pmos L=60n W=1.2u
-MN37 net21 IN_N net19 VDD pmos L=60n W=1.2u
-MN36 net24 net15 VDD VDD pmos L=60n W=1.2u
-MN35 net13 IN_P net19 VDD pmos L=60n W=1.2u
-MN53 OUT net54 GND GND nmos L=60n W=600n
-MN51 net54 net52 GND GND nmos L=60n W=600n
-MN50 net52 net52 GND GND nmos L=60n W=600n
-MN47 net29 net29 GND GND nmos L=60n W=600n
-MN46 net24 net24 GND GND nmos L=60n W=600n
-MN45 net29 net24 GND GND nmos L=60n W=600n
-MN41 net21 net21 GND GND nmos L=60n W=600n
-MN40 net13 net13 GND GND nmos L=60n W=600n
-MN44 net24 net29 GND GND nmos L=60n W=600n
-MN33 net51 IN_N net18 GND nmos L=60n W=600n
-MN32 net15 IN_P net18 GND nmos L=60n W=600n
-MN43 net15 net21 GND GND nmos L=60n W=600n
-MN42 net51 net13 GND GND nmos L=60n W=600n
-I2 VDD net31 DC=200u
-I1 net18 GND DC=100u
-I0 VDD net19 DC=200u
-.ends COMPARATOR
-
-.subckt AMS_ADC_1b GND OUT SEL<1> SEL<0> VDD
-XI0 net010 net7 net8 net02 GND Vmux_out SEL<0> SEL<1> VDD ANALOG_MUX
-XI1 GND Vmux_out Vin OUT VDD COMPARATOR
-R4 net010 GND 100k
-R3 net7 net010 100k
-R2 net8 net7 100k
-R1 net02 net8 100k
-R0 VDD net02 100k
-V2 Vin GND SIN 600m 600m 1e6 250e-9
-.ends AMS_ADC_1b
-
diff --git a/hw/ip_examples/ams/analog/control.init b/hw/ip_examples/ams/analog/control.init
index dc54dd518..06343bed7 100644
--- a/hw/ip_examples/ams/analog/control.init
+++ b/hw/ip_examples/ams/analog/control.init
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-choose xa ../../../hw/ip_examples/ams/analog/adc.sp;
-port_connect -cell ams_adc_1b ( vdd => vdd , gnd => gnd );
-port_dir -cell ams_adc_1b (input sel; output out);
+choose xa ../../../hw/ip_examples/ams/analog/myinverter.sp;
+port_connect -cell myinverter ( vdd => vdd , gnd => gnd );
+port_dir -cell myinverter (input a; output z);
 bus_format <%d>;
diff --git a/hw/ip_examples/ams/analog/myinverter.sp b/hw/ip_examples/ams/analog/myinverter.sp
new file mode 100644
index 000000000..bfb7ae54c
--- /dev/null
+++ b/hw/ip_examples/ams/analog/myinverter.sp
@@ -0,0 +1,22 @@
+** Copyright EPFL contributors.
+** Licensed under the Apache License, Version 2.0, see LICENSE for details.
+** SPDX-License-Identifier: Apache-2.0
+
+** Uses the 65nm_bulk PTM Bulk CMOS model, February 22, 2006 release
+** (obtained from https://ptm.asu.edu)
+
+v_vdd VDD 0 1.8
+v_gnd VSS 0 0
+.global VDD VSS
+
+*Model Description
+.param temp=27
+
+*Include model file
+.lib "/scrap/users/schiavon/gitdir/skywater-pdk/libraries/sky130_fd_pr/latest/models/sky130.lib.spice" tt
+
+*d g s b
+.SUBCKT myinverter a z VDD VSS
+X1 z a VDD VDD sky130_fd_pr__pfet_01v8 w =0.84 l = 0.15
+X2 z a VSS VSS sky130_fd_pr__nfet_01v8 w =0.36 l = 0.15
+.ENDS myinverter
diff --git a/hw/ip_examples/ams/data/ams.hjson b/hw/ip_examples/ams/data/ams.hjson
index 38dad9dcb..76f3fe0a4 100644
--- a/hw/ip_examples/ams/data/ams.hjson
+++ b/hw/ip_examples/ams/data/ams.hjson
@@ -14,7 +14,7 @@
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "1:0", name:"VALUE", desc: "Set the ADC threshold value" }
+        { bits: "0", name:"VALUE", desc: "Set the ADC threshold value" }
       ]
     },
     { name:     "GET",
diff --git a/hw/ip_examples/ams/rtl/ams.sv b/hw/ip_examples/ams/rtl/ams.sv
index b72dd7189..f46f9449a 100644
--- a/hw/ip_examples/ams/rtl/ams.sv
+++ b/hw/ip_examples/ams/rtl/ams.sv
@@ -19,9 +19,9 @@ module ams #(
 
   assign hw2reg.get.de = 1;
 
-  ams_adc_1b ams_adc_1b_i (
-      .sel(reg2hw.sel.q),
-      .out(hw2reg.get.d)
+  myinverter myinverter_i (
+      .a(reg2hw.sel.q),
+      .z(hw2reg.get.d)
   );
 
   ams_reg_top #(
diff --git a/hw/ip_examples/ams/rtl/ams_reg_pkg.sv b/hw/ip_examples/ams/rtl/ams_reg_pkg.sv
index 0475c8dec..96c632230 100644
--- a/hw/ip_examples/ams/rtl/ams_reg_pkg.sv
+++ b/hw/ip_examples/ams/rtl/ams_reg_pkg.sv
@@ -13,7 +13,7 @@ package ams_reg_pkg;
   // Typedefs for registers //
   ////////////////////////////
 
-  typedef struct packed {logic [1:0] q;} ams_reg2hw_sel_reg_t;
+  typedef struct packed {logic q;} ams_reg2hw_sel_reg_t;
 
   typedef struct packed {logic q;} ams_reg2hw_get_reg_t;
 
@@ -24,7 +24,7 @@ package ams_reg_pkg;
 
   // Register -> HW type
   typedef struct packed {
-    ams_reg2hw_sel_reg_t sel;  // [2:1]
+    ams_reg2hw_sel_reg_t sel;  // [1:1]
     ams_reg2hw_get_reg_t get;  // [0:0]
   } ams_reg2hw_t;
 
diff --git a/hw/ip_examples/ams/rtl/ams_reg_top.sv b/hw/ip_examples/ams/rtl/ams_reg_top.sv
index 3d55ff01a..0105499de 100644
--- a/hw/ip_examples/ams/rtl/ams_reg_top.sv
+++ b/hw/ip_examples/ams/rtl/ams_reg_top.sv
@@ -68,8 +68,8 @@ module ams_reg_top #(
   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic [1:0] sel_qs;
-  logic [1:0] sel_wd;
+  logic sel_qs;
+  logic sel_wd;
   logic sel_we;
   logic get_qs;
 
@@ -77,9 +77,9 @@ module ams_reg_top #(
   // R[sel]: V(False)
 
   prim_subreg #(
-      .DW      (2),
+      .DW      (1),
       .SWACCESS("RW"),
-      .RESVAL  (2'h0)
+      .RESVAL  (1'h0)
   ) u_sel (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -146,14 +146,14 @@ module ams_reg_top #(
   end
 
   assign sel_we = addr_hit[0] & reg_we & !reg_error;
-  assign sel_wd = reg_wdata[1:0];
+  assign sel_wd = reg_wdata[0];
 
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
-        reg_rdata_next[1:0] = sel_qs;
+        reg_rdata_next[0] = sel_qs;
       end
 
       addr_hit[1]: begin
diff --git a/hw/ip_examples/ams/rtl/dummy_adc.sv b/hw/ip_examples/ams/rtl/dummy_myinverter.sv
similarity index 62%
rename from hw/ip_examples/ams/rtl/dummy_adc.sv
rename to hw/ip_examples/ams/rtl/dummy_myinverter.sv
index e44fa89bc..334fd848c 100644
--- a/hw/ip_examples/ams/rtl/dummy_adc.sv
+++ b/hw/ip_examples/ams/rtl/dummy_myinverter.sv
@@ -2,10 +2,10 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module ams_adc_1b (
-    input logic [1:0] sel,
-    output logic out
+module myinverter (
+    input  logic a,
+    output logic z
 );
 
-endmodule : ams_adc_1b
+endmodule : myinverter