From cb24aef4960708fbc7ee7bed7c13f193fc8a843f Mon Sep 17 00:00:00 2001 From: Luigi2898 Date: Thu, 19 Sep 2024 11:02:57 +0200 Subject: [PATCH 1/9] Don't disable global interrupts with DMA interrupt --- sw/device/lib/drivers/dma/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/device/lib/drivers/dma/dma.c b/sw/device/lib/drivers/dma/dma.c index 520977702..4eb8d0895 100644 --- a/sw/device/lib/drivers/dma/dma.c +++ b/sw/device/lib/drivers/dma/dma.c @@ -60,7 +60,7 @@ extern "C" /** * Returns the mask to enable/disable DMA interrupts. */ -#define DMA_CSR_REG_MIE_MASK (( 1 << 19 ) | (1 << 11 ) ) // @ToDo Add definitions for this 19 and 11 +#define DMA_CSR_REG_MIE_MASK (( 1 << 19 )) // 19 is DMA fast interrupt bit in MIE CSR /** * Mask to determine if an address is multiple of 4 (Word aligned). From 0b9442dff23dda3e249ea51c3d923f7f578b8e5f Mon Sep 17 00:00:00 2001 From: alessionaclerio22 Date: Thu, 24 Oct 2024 13:56:36 +0200 Subject: [PATCH 2/9] Add vsim option --- core-v-mini-mcu.core | 1 + 1 file changed, 1 insertion(+) diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core index aef1f20e2..e07824be3 100644 --- a/core-v-mini-mcu.core +++ b/core-v-mini-mcu.core @@ -339,6 +339,7 @@ targets: vsim_options: - -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi - -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs + - -voptargs=+acc=npr vcs: vcs_options: - -override_timescale=1ns/1ps From a82c2a254888dce4beea8e903f6e2a01ac92fa1c Mon Sep 17 00:00:00 2001 From: alessionaclerio22 Date: Thu, 24 Oct 2024 14:10:20 +0200 Subject: [PATCH 3/9] Add DMA functionality for SPI subaddressing --- hw/ip/dma/data/dma.hjson | 3 +- hw/ip/dma/rtl/dma.sv | 305 +++++++- hw/ip/dma/rtl/dma_reg_pkg.sv | 312 +++++---- hw/ip/dma/rtl/dma_reg_top.sv | 999 ++++++++++++++------------- sw/device/lib/drivers/dma/dma.h | 2 +- sw/device/lib/drivers/dma/dma_regs.h | 3 +- 6 files changed, 975 insertions(+), 649 deletions(-) diff --git a/hw/ip/dma/data/dma.hjson b/hw/ip/dma/data/dma.hjson index 4f144c612..cad7588e8 100644 --- a/hw/ip/dma/data/dma.hjson +++ b/hw/ip/dma/data/dma.hjson @@ -186,12 +186,13 @@ hwaccess: "hro", resval: 0, fields: [ - { bits: "1:0", name: "MODE", + { bits: "2:0", name: "MODE", desc: "DMA operation mode", enum: [ { value: "0", name: "LINEAR_MODE", desc: "Transfers data linearly"}, { value: "1", name: "CIRCULAR_MODE", desc: "Transfers data in circular mode"}, { value: "2", name: "ADDRESS_MODE" , desc: "Transfers data using as destination address the data from ADD_PTR"}, + { value: "3", name: "SUBADDRESS_MODE" , desc: "Implements transferrin of data when SRC_PTR is fixed and related to a peripheral"}, ] } ] diff --git a/hw/ip/dma/rtl/dma.sv b/hw/ip/dma/rtl/dma.sv index 923b5a1fa..6464fa50b 100644 --- a/hw/ip/dma/rtl/dma.sv +++ b/hw/ip/dma/rtl/dma.sv @@ -105,15 +105,18 @@ module dma #( logic dma_window_intr_n; /* FIFO signals */ - logic [Addr_Fifo_Depth-1:0] read_fifo_usage; + logic [3:0][Addr_Fifo_Depth-1:0] read_fifo_usage; logic [Addr_Fifo_Depth-1:0] read_addr_fifo_usage; logic [Addr_Fifo_Depth-1:0] write_fifo_usage; logic fifo_flush; - logic read_fifo_full; - logic read_fifo_empty; + logic [3:0] read_fifo_full; + logic [3:0] read_fifo_empty; logic read_fifo_alm_full; - logic read_fifo_pop; + logic read_fifo_pop_pad; + //logic read_fifo_pop_pad_d; + logic [3:0] read_fifo_pop; + logic [3:0] read_fifo_pop_act; logic [31:0] read_fifo_input; logic [31:0] read_fifo_output; @@ -126,9 +129,12 @@ module dma #( logic write_fifo_empty; logic write_fifo_alm_full; logic write_fifo_push; + logic write_fifo_push_act; logic write_fifo_pop; logic [31:0] write_fifo_input; logic [31:0] write_fifo_output; + //logic [31:0] write_fifo_input_d; + logic [31:0] write_fifo_input_act; /* Trigger signals */ logic wait_for_rx; @@ -151,8 +157,11 @@ module dma #( } dma_state_q, dma_state_d; + dma_data_type_t src_data_type; + logic circular_mode; logic address_mode; + logic subaddressing_mode; logic dma_start_pending; @@ -183,25 +192,109 @@ module dma #( - /* Read FIFO */ + /* Read FIFOs */ + // fifo_v3 #( + // .DEPTH(FIFO_DEPTH), + // .FALL_THROUGH(1'b1) + // ) dma_read_fifo_i ( + // .clk_i(clk_cg), + // .rst_ni, + // .flush_i(fifo_flush), + // .testmode_i(1'b0), + // // status flags + // .full_o(read_fifo_full), + // .empty_o(read_fifo_empty), + // .usage_o(read_fifo_usage), + // // as long as the queue is not full we can push new data + // .data_i(read_fifo_input), + // .push_i(data_in_rvalid), + // // as long as the queue is not empty we can pop new elements + // .data_o(read_fifo_output), + // .pop_i(read_fifo_pop) + // ); + fifo_v3 #( .DEPTH(FIFO_DEPTH), - .FALL_THROUGH(1'b1) - ) dma_read_fifo_i ( + .FALL_THROUGH(1'b1), + .DATA_WIDTH(8) + ) dma_read_fifo_0_i ( .clk_i(clk_cg), .rst_ni, .flush_i(fifo_flush), .testmode_i(1'b0), // status flags - .full_o(read_fifo_full), - .empty_o(read_fifo_empty), - .usage_o(read_fifo_usage), + .full_o(read_fifo_full[0]), + .empty_o(read_fifo_empty[0]), + .usage_o(read_fifo_usage[0]), // as long as the queue is not full we can push new data - .data_i(read_fifo_input), + .data_i(read_fifo_input[7:0]), .push_i(data_in_rvalid), // as long as the queue is not empty we can pop new elements - .data_o(read_fifo_output), - .pop_i(read_fifo_pop) + .data_o(read_fifo_output[7:0]), + .pop_i(read_fifo_pop_act[0]) + ); + + fifo_v3 #( + .DEPTH(FIFO_DEPTH), + .FALL_THROUGH(1'b1), + .DATA_WIDTH(8) + ) dma_read_fifo_1_i ( + .clk_i(clk_cg), + .rst_ni, + .flush_i(fifo_flush), + .testmode_i(1'b0), + // status flags + .full_o(read_fifo_full[1]), + .empty_o(read_fifo_empty[1]), + .usage_o(read_fifo_usage[1]), + // as long as the queue is not full we can push new data + .data_i(read_fifo_input[15:8]), + .push_i(data_in_rvalid), + // as long as the queue is not empty we can pop new elements + .data_o(read_fifo_output[15:8]), + .pop_i(read_fifo_pop_act[1]) + ); + + fifo_v3 #( + .DEPTH(FIFO_DEPTH), + .FALL_THROUGH(1'b1), + .DATA_WIDTH(8) + ) dma_read_fifo_2_i ( + .clk_i(clk_cg), + .rst_ni, + .flush_i(fifo_flush), + .testmode_i(1'b0), + // status flags + .full_o(read_fifo_full[2]), + .empty_o(read_fifo_empty[2]), + .usage_o(read_fifo_usage[2]), + // as long as the queue is not full we can push new data + .data_i(read_fifo_input[23:16]), + .push_i(data_in_rvalid), + // as long as the queue is not empty we can pop new elements + .data_o(read_fifo_output[23:16]), + .pop_i(read_fifo_pop_act[2]) + ); + + fifo_v3 #( + .DEPTH(FIFO_DEPTH), + .FALL_THROUGH(1'b1), + .DATA_WIDTH(8) + ) dma_read_fifo_3_i ( + .clk_i(clk_cg), + .rst_ni, + .flush_i(fifo_flush), + .testmode_i(1'b0), + // status flags + .full_o(read_fifo_full[3]), + .empty_o(read_fifo_empty[3]), + .usage_o(read_fifo_usage[3]), + // as long as the queue is not full we can push new data + .data_i(read_fifo_input[31:24]), + .push_i(data_in_rvalid), + // as long as the queue is not empty we can pop new elements + .data_o(read_fifo_output[31:24]), + .pop_i(read_fifo_pop_act[3]) ); /* Read address mode FIFO */ @@ -239,8 +332,8 @@ module dma #( .empty_o(write_fifo_empty), .usage_o(write_fifo_usage), // as long as the queue is not full we can push new data - .data_i(write_fifo_input), - .push_i(write_fifo_push), + .data_i(write_fifo_input_act), + .push_i(write_fifo_push_act), // as long as the queue is not empty we can pop new elements .data_o(write_fifo_output), .pop_i(write_fifo_pop) @@ -267,7 +360,7 @@ module dma #( .dma_start_i(dma_start), .dma_done_i(dma_done), .ext_dma_stop_i, - .read_fifo_full_i(read_fifo_full), + .read_fifo_full_i(|read_fifo_full), .read_fifo_alm_full_i(read_fifo_alm_full), .wait_for_rx_i(wait_for_rx), .data_in_gnt_i(data_in_gnt), @@ -305,13 +398,14 @@ module dma #( .reg2hw_i(reg2hw), .dma_padding_fsm_on_i(dma_padding_fsm_on), .dma_start_i(dma_start), - .read_fifo_empty_i(read_fifo_empty), + .read_fifo_empty_i(&(read_fifo_empty)), + .subaddressing_mode_i(subaddressing_mode), .write_fifo_full_i(write_fifo_full), .write_fifo_alm_full_i(write_fifo_alm_full), .data_read_i(read_fifo_output), .padding_fsm_done_o(padding_fsm_done), .write_fifo_push_o(write_fifo_push), - .read_fifo_pop_o(read_fifo_pop), + .read_fifo_pop_o(read_fifo_pop_pad), .data_write_o(write_fifo_input) ); @@ -495,6 +589,172 @@ module dma #( end end + // Subaddressing mode controlling logic + + always_ff @(posedge clk_cg, negedge rst_ni) begin + if (~rst_ni) begin + read_fifo_pop = 4'b0000; + end else begin + if (subaddressing_mode == 1'b1) begin + case (src_data_type) + DMA_DATA_TYPE_HALF_WORD: begin + + read_fifo_pop = 4'b0011; + + if (read_fifo_pop_pad == 1'b1) begin + if (read_fifo_pop == 4'b1100) begin + read_fifo_pop = 4'b0011; + end else begin + read_fifo_pop = read_fifo_pop << 2; + end + end else begin + read_fifo_pop = read_fifo_pop; + end + + end + + DMA_DATA_TYPE_BYTE: begin + + read_fifo_pop = 4'b0001; + + if (read_fifo_pop_pad == 1'b1) begin + if (read_fifo_pop == 4'b1000) begin + read_fifo_pop = 4'b0001; + end else begin + read_fifo_pop = read_fifo_pop << 1; + end + end else begin + read_fifo_pop = read_fifo_pop; + end + + end + + default: read_fifo_pop = 4'b1111; + + endcase + end else begin + read_fifo_pop = 4'b1111; + end + end + end + + always_comb begin + if (subaddressing_mode == 1'b1) begin + if (read_fifo_pop_pad == 1'b1) begin + case (src_data_type) + DMA_DATA_TYPE_HALF_WORD: + + if (read_fifo_pop == 4'b0000) begin + write_fifo_input_act = '0; + write_fifo_push_act = 1'b0; + end else if (read_fifo_pop == 4'b1100) begin + write_fifo_input_act = {{16{1'b0}}, write_fifo_input[31:16]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0011) begin + write_fifo_input_act = {{16{1'b0}}, write_fifo_input[15:0]}; + write_fifo_push_act = 1'b1; + end else begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + + DMA_DATA_TYPE_BYTE: + + if (read_fifo_pop == 4'b0000) begin + write_fifo_input_act = '0; + write_fifo_push_act = 1'b0; + end else if (read_fifo_pop == 4'b1000) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[31:24]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0100) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[23:16]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0010) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[15:8]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0001) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[7:0]}; + write_fifo_push_act = 1'b1; + end else begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + + default: begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + + endcase + end else begin + write_fifo_input_act = '0; + write_fifo_push_act = 1'b0; + end + end else begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + end + + always_comb begin + if (read_fifo_pop_pad == 1'b1) begin + read_fifo_pop_act = read_fifo_pop; + end else begin + read_fifo_pop_act = 4'b0000; + end + end + + + /* always_ff @(posedge clk_cg, negedge rst_ni) begin + if (~rst_ni) begin + read_fifo_pop = 4'b0000; + end else begin + if(subaddressing_mode == 1'b1) begin + case(src_data_type) + DMA_DATA_TYPE_HALF_WORD: + + if(read_fifo_pop_pad == 1'b1) begin + if(read_fifo_pop == 4'b1111) begin + read_fifo_pop = 4'b0011; + end else if (read_fifo_pop == 4'b1100) begin + read_fifo_pop = 4'b0011; + end else if (read_fifo_pop == 4'b1100) begin + read_fifo_pop = 4'b0011; + end else begin + read_fifo_pop = 4'b1111; + end + end else begin + read_fifo_pop = 4'b1111; + end + + DMA_DATA_TYPE_BYTE: + + if(read_fifo_pop_pad == 1'b1) begin + if(read_fifo_pop == 4'b1111) begin + read_fifo_pop = 4'b0001; + end else if (read_fifo_pop == 4'b0001) begin + read_fifo_pop = 4'b0010; + end else if (read_fifo_pop == 4'b0010) begin + read_fifo_pop = 4'b0100; + end else if (read_fifo_pop == 4'b0100) begin + read_fifo_pop = 4'b1000; + end else if (read_fifo_pop == 4'b0001) begin + read_fifo_pop = 4'b0001; + end else begin + read_fifo_pop = 4'1111; + end + end else begin + read_fifo_pop = 4'b1111; + end + + default: + read_fifo_pop <= 4'b1111; + endcase + end else begin + read_fifo_pop <= 4'b1111; + end + end + end */ /*_________________________________________________________________________________________________________________________________ */ @@ -550,11 +810,15 @@ module dma #( assign circular_mode = reg2hw.mode.q == 1; assign address_mode = reg2hw.mode.q == 2; + assign subaddressing_mode = reg2hw.mode.q == 4; assign wait_for_rx = |(reg2hw.slot.rx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i)); assign wait_for_tx = |(reg2hw.slot.tx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i)); - assign read_fifo_alm_full = (read_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]); + assign read_fifo_alm_full = (read_fifo_usage[0] == LastFifoUsage[Addr_Fifo_Depth-1:0]) & + (read_fifo_usage[1] == LastFifoUsage[Addr_Fifo_Depth-1:0]) & + (read_fifo_usage[2] == LastFifoUsage[Addr_Fifo_Depth-1:0]) & + (read_fifo_usage[3] == LastFifoUsage[Addr_Fifo_Depth-1:0]); assign read_addr_fifo_alm_full = (read_addr_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]); assign write_fifo_alm_full = (write_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]); @@ -563,4 +827,7 @@ module dma #( // Count gnt write transaction and generate event pulse if WINDOW_SIZE is reached assign dma_window_event = |reg2hw.window_size.q & data_out_gnt & (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q}); + + assign src_data_type = dma_data_type_t'(reg2hw.src_data_type.q); + endmodule : dma diff --git a/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/ip/dma/rtl/dma_reg_pkg.sv index 4e98968c2..701e5540a 100644 --- a/hw/ip/dma/rtl/dma_reg_pkg.sv +++ b/hw/ip/dma/rtl/dma_reg_pkg.sv @@ -13,170 +13,226 @@ package dma_reg_pkg; // Typedefs for registers // //////////////////////////// - typedef struct packed {logic [31:0] q;} dma_reg2hw_src_ptr_reg_t; + typedef struct packed { + logic [31:0] q; + } dma_reg2hw_src_ptr_reg_t; - typedef struct packed {logic [31:0] q;} dma_reg2hw_dst_ptr_reg_t; + typedef struct packed { + logic [31:0] q; + } dma_reg2hw_dst_ptr_reg_t; - typedef struct packed {logic [31:0] q;} dma_reg2hw_addr_ptr_reg_t; + typedef struct packed { + logic [31:0] q; + } dma_reg2hw_addr_ptr_reg_t; typedef struct packed { logic [15:0] q; logic qe; } dma_reg2hw_size_d1_reg_t; - typedef struct packed {logic [15:0] q;} dma_reg2hw_size_d2_reg_t; + typedef struct packed { + logic [15:0] q; + } dma_reg2hw_size_d2_reg_t; typedef struct packed { struct packed { - logic q; - logic re; + logic q; + logic re; } ready; struct packed { - logic q; - logic re; + logic q; + logic re; } window_done; } dma_reg2hw_status_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_src_ptr_inc_d1_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_src_ptr_inc_d1_reg_t; - typedef struct packed {logic [22:0] q;} dma_reg2hw_src_ptr_inc_d2_reg_t; + typedef struct packed { + logic [22:0] q; + } dma_reg2hw_src_ptr_inc_d2_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_dst_ptr_inc_d1_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_dst_ptr_inc_d1_reg_t; - typedef struct packed {logic [22:0] q;} dma_reg2hw_dst_ptr_inc_d2_reg_t; + typedef struct packed { + logic [22:0] q; + } dma_reg2hw_dst_ptr_inc_d2_reg_t; typedef struct packed { - struct packed {logic [15:0] q;} rx_trigger_slot; - struct packed {logic [15:0] q;} tx_trigger_slot; + struct packed { + logic [15:0] q; + } rx_trigger_slot; + struct packed { + logic [15:0] q; + } tx_trigger_slot; } dma_reg2hw_slot_reg_t; - typedef struct packed {logic [1:0] q;} dma_reg2hw_src_data_type_reg_t; + typedef struct packed { + logic [1:0] q; + } dma_reg2hw_src_data_type_reg_t; - typedef struct packed {logic [1:0] q;} dma_reg2hw_dst_data_type_reg_t; + typedef struct packed { + logic [1:0] q; + } dma_reg2hw_dst_data_type_reg_t; - typedef struct packed {logic q;} dma_reg2hw_sign_ext_reg_t; + typedef struct packed { + logic q; + } dma_reg2hw_sign_ext_reg_t; - typedef struct packed {logic [1:0] q;} dma_reg2hw_mode_reg_t; + typedef struct packed { + logic [2:0] q; + } dma_reg2hw_mode_reg_t; - typedef struct packed {logic q;} dma_reg2hw_dim_config_reg_t; + typedef struct packed { + logic q; + } dma_reg2hw_dim_config_reg_t; - typedef struct packed {logic q;} dma_reg2hw_dim_inv_reg_t; + typedef struct packed { + logic q; + } dma_reg2hw_dim_inv_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_top_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_pad_top_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_bottom_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_pad_bottom_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_right_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_pad_right_reg_t; - typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_left_reg_t; + typedef struct packed { + logic [5:0] q; + } dma_reg2hw_pad_left_reg_t; - typedef struct packed {logic [12:0] q;} dma_reg2hw_window_size_reg_t; + typedef struct packed { + logic [12:0] q; + } dma_reg2hw_window_size_reg_t; - typedef struct packed {logic [7:0] q;} dma_reg2hw_window_count_reg_t; + typedef struct packed { + logic [7:0] q; + } dma_reg2hw_window_count_reg_t; typedef struct packed { - struct packed {logic q;} transaction_done; - struct packed {logic q;} window_done; + struct packed { + logic q; + } transaction_done; + struct packed { + logic q; + } window_done; } dma_reg2hw_interrupt_en_reg_t; typedef struct packed { - logic q; - logic re; + logic q; + logic re; } dma_reg2hw_transaction_ifr_reg_t; typedef struct packed { - logic q; - logic re; + logic q; + logic re; } dma_reg2hw_window_ifr_reg_t; typedef struct packed { - struct packed {logic d;} ready; - struct packed {logic d;} window_done; + struct packed { + logic d; + } ready; + struct packed { + logic d; + } window_done; } dma_hw2reg_status_reg_t; typedef struct packed { - logic [7:0] d; - logic de; + logic [7:0] d; + logic de; } dma_hw2reg_window_count_reg_t; - typedef struct packed {logic d;} dma_hw2reg_transaction_ifr_reg_t; + typedef struct packed { + logic d; + } dma_hw2reg_transaction_ifr_reg_t; - typedef struct packed {logic d;} dma_hw2reg_window_ifr_reg_t; + typedef struct packed { + logic d; + } dma_hw2reg_window_ifr_reg_t; // Register -> HW type typedef struct packed { - dma_reg2hw_src_ptr_reg_t src_ptr; // [282:251] - dma_reg2hw_dst_ptr_reg_t dst_ptr; // [250:219] - dma_reg2hw_addr_ptr_reg_t addr_ptr; // [218:187] - dma_reg2hw_size_d1_reg_t size_d1; // [186:170] - dma_reg2hw_size_d2_reg_t size_d2; // [169:154] - dma_reg2hw_status_reg_t status; // [153:150] - dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1; // [149:144] - dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2; // [143:121] - dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1; // [120:115] - dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2; // [114:92] - dma_reg2hw_slot_reg_t slot; // [91:60] - dma_reg2hw_src_data_type_reg_t src_data_type; // [59:58] - dma_reg2hw_dst_data_type_reg_t dst_data_type; // [57:56] - dma_reg2hw_sign_ext_reg_t sign_ext; // [55:55] - dma_reg2hw_mode_reg_t mode; // [54:53] - dma_reg2hw_dim_config_reg_t dim_config; // [52:52] - dma_reg2hw_dim_inv_reg_t dim_inv; // [51:51] - dma_reg2hw_pad_top_reg_t pad_top; // [50:45] - dma_reg2hw_pad_bottom_reg_t pad_bottom; // [44:39] - dma_reg2hw_pad_right_reg_t pad_right; // [38:33] - dma_reg2hw_pad_left_reg_t pad_left; // [32:27] - dma_reg2hw_window_size_reg_t window_size; // [26:14] - dma_reg2hw_window_count_reg_t window_count; // [13:6] - dma_reg2hw_interrupt_en_reg_t interrupt_en; // [5:4] - dma_reg2hw_transaction_ifr_reg_t transaction_ifr; // [3:2] - dma_reg2hw_window_ifr_reg_t window_ifr; // [1:0] + dma_reg2hw_src_ptr_reg_t src_ptr; // [283:252] + dma_reg2hw_dst_ptr_reg_t dst_ptr; // [251:220] + dma_reg2hw_addr_ptr_reg_t addr_ptr; // [219:188] + dma_reg2hw_size_d1_reg_t size_d1; // [187:171] + dma_reg2hw_size_d2_reg_t size_d2; // [170:155] + dma_reg2hw_status_reg_t status; // [154:151] + dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1; // [150:145] + dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2; // [144:122] + dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1; // [121:116] + dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2; // [115:93] + dma_reg2hw_slot_reg_t slot; // [92:61] + dma_reg2hw_src_data_type_reg_t src_data_type; // [60:59] + dma_reg2hw_dst_data_type_reg_t dst_data_type; // [58:57] + dma_reg2hw_sign_ext_reg_t sign_ext; // [56:56] + dma_reg2hw_mode_reg_t mode; // [55:53] + dma_reg2hw_dim_config_reg_t dim_config; // [52:52] + dma_reg2hw_dim_inv_reg_t dim_inv; // [51:51] + dma_reg2hw_pad_top_reg_t pad_top; // [50:45] + dma_reg2hw_pad_bottom_reg_t pad_bottom; // [44:39] + dma_reg2hw_pad_right_reg_t pad_right; // [38:33] + dma_reg2hw_pad_left_reg_t pad_left; // [32:27] + dma_reg2hw_window_size_reg_t window_size; // [26:14] + dma_reg2hw_window_count_reg_t window_count; // [13:6] + dma_reg2hw_interrupt_en_reg_t interrupt_en; // [5:4] + dma_reg2hw_transaction_ifr_reg_t transaction_ifr; // [3:2] + dma_reg2hw_window_ifr_reg_t window_ifr; // [1:0] } dma_reg2hw_t; // HW -> register type typedef struct packed { - dma_hw2reg_status_reg_t status; // [12:11] - dma_hw2reg_window_count_reg_t window_count; // [10:2] - dma_hw2reg_transaction_ifr_reg_t transaction_ifr; // [1:1] - dma_hw2reg_window_ifr_reg_t window_ifr; // [0:0] + dma_hw2reg_status_reg_t status; // [12:11] + dma_hw2reg_window_count_reg_t window_count; // [10:2] + dma_hw2reg_transaction_ifr_reg_t transaction_ifr; // [1:1] + dma_hw2reg_window_ifr_reg_t window_ifr; // [0:0] } dma_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h0; - parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h4; - parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h8; - parameter logic [BlockAw-1:0] DMA_SIZE_D1_OFFSET = 7'hc; - parameter logic [BlockAw-1:0] DMA_SIZE_D2_OFFSET = 7'h10; - parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h14; - parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D1_OFFSET = 7'h18; - parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D2_OFFSET = 7'h1c; - parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D1_OFFSET = 7'h20; - parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D2_OFFSET = 7'h24; - parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h28; - parameter logic [BlockAw-1:0] DMA_SRC_DATA_TYPE_OFFSET = 7'h2c; - parameter logic [BlockAw-1:0] DMA_DST_DATA_TYPE_OFFSET = 7'h30; - parameter logic [BlockAw-1:0] DMA_SIGN_EXT_OFFSET = 7'h34; - parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h38; - parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h3c; - parameter logic [BlockAw-1:0] DMA_DIM_INV_OFFSET = 7'h40; - parameter logic [BlockAw-1:0] DMA_PAD_TOP_OFFSET = 7'h44; - parameter logic [BlockAw-1:0] DMA_PAD_BOTTOM_OFFSET = 7'h48; - parameter logic [BlockAw-1:0] DMA_PAD_RIGHT_OFFSET = 7'h4c; - parameter logic [BlockAw-1:0] DMA_PAD_LEFT_OFFSET = 7'h50; - parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h54; - parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h58; - parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h5c; - parameter logic [BlockAw-1:0] DMA_TRANSACTION_IFR_OFFSET = 7'h60; - parameter logic [BlockAw-1:0] DMA_WINDOW_IFR_OFFSET = 7'h64; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] DMA_SIZE_D1_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] DMA_SIZE_D2_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D1_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D2_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D1_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D2_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] DMA_SRC_DATA_TYPE_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] DMA_DST_DATA_TYPE_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] DMA_SIGN_EXT_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] DMA_DIM_INV_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] DMA_PAD_TOP_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] DMA_PAD_BOTTOM_OFFSET = 7'h 48; + parameter logic [BlockAw-1:0] DMA_PAD_RIGHT_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] DMA_PAD_LEFT_OFFSET = 7'h 50; + parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h 54; + parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h 58; + parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h 5c; + parameter logic [BlockAw-1:0] DMA_TRANSACTION_IFR_OFFSET = 7'h 60; + parameter logic [BlockAw-1:0] DMA_WINDOW_IFR_OFFSET = 7'h 64; // Reset values for hwext registers and their fields - parameter logic [1:0] DMA_STATUS_RESVAL = 2'h1; - parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h1; - parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h0; - parameter logic [0:0] DMA_TRANSACTION_IFR_RESVAL = 1'h0; - parameter logic [0:0] DMA_TRANSACTION_IFR_FLAG_RESVAL = 1'h0; - parameter logic [0:0] DMA_WINDOW_IFR_RESVAL = 1'h0; - parameter logic [0:0] DMA_WINDOW_IFR_FLAG_RESVAL = 1'h0; + parameter logic [1:0] DMA_STATUS_RESVAL = 2'h 1; + parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h 1; + parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h 0; + parameter logic [0:0] DMA_TRANSACTION_IFR_RESVAL = 1'h 0; + parameter logic [0:0] DMA_TRANSACTION_IFR_FLAG_RESVAL = 1'h 0; + parameter logic [0:0] DMA_WINDOW_IFR_RESVAL = 1'h 0; + parameter logic [0:0] DMA_WINDOW_IFR_FLAG_RESVAL = 1'h 0; // Register index typedef enum int { @@ -209,33 +265,33 @@ package dma_reg_pkg; } dma_id_e; // Register width information to check illegal writes - parameter logic [3:0] DMA_PERMIT[26] = '{ - 4'b1111, // index[ 0] DMA_SRC_PTR - 4'b1111, // index[ 1] DMA_DST_PTR - 4'b1111, // index[ 2] DMA_ADDR_PTR - 4'b0011, // index[ 3] DMA_SIZE_D1 - 4'b0011, // index[ 4] DMA_SIZE_D2 - 4'b0001, // index[ 5] DMA_STATUS - 4'b0001, // index[ 6] DMA_SRC_PTR_INC_D1 - 4'b0111, // index[ 7] DMA_SRC_PTR_INC_D2 - 4'b0001, // index[ 8] DMA_DST_PTR_INC_D1 - 4'b0111, // index[ 9] DMA_DST_PTR_INC_D2 - 4'b1111, // index[10] DMA_SLOT - 4'b0001, // index[11] DMA_SRC_DATA_TYPE - 4'b0001, // index[12] DMA_DST_DATA_TYPE - 4'b0001, // index[13] DMA_SIGN_EXT - 4'b0001, // index[14] DMA_MODE - 4'b0001, // index[15] DMA_DIM_CONFIG - 4'b0001, // index[16] DMA_DIM_INV - 4'b0001, // index[17] DMA_PAD_TOP - 4'b0001, // index[18] DMA_PAD_BOTTOM - 4'b0001, // index[19] DMA_PAD_RIGHT - 4'b0001, // index[20] DMA_PAD_LEFT - 4'b0011, // index[21] DMA_WINDOW_SIZE - 4'b0001, // index[22] DMA_WINDOW_COUNT - 4'b0001, // index[23] DMA_INTERRUPT_EN - 4'b0001, // index[24] DMA_TRANSACTION_IFR - 4'b0001 // index[25] DMA_WINDOW_IFR + parameter logic [3:0] DMA_PERMIT [26] = '{ + 4'b 1111, // index[ 0] DMA_SRC_PTR + 4'b 1111, // index[ 1] DMA_DST_PTR + 4'b 1111, // index[ 2] DMA_ADDR_PTR + 4'b 0011, // index[ 3] DMA_SIZE_D1 + 4'b 0011, // index[ 4] DMA_SIZE_D2 + 4'b 0001, // index[ 5] DMA_STATUS + 4'b 0001, // index[ 6] DMA_SRC_PTR_INC_D1 + 4'b 0111, // index[ 7] DMA_SRC_PTR_INC_D2 + 4'b 0001, // index[ 8] DMA_DST_PTR_INC_D1 + 4'b 0111, // index[ 9] DMA_DST_PTR_INC_D2 + 4'b 1111, // index[10] DMA_SLOT + 4'b 0001, // index[11] DMA_SRC_DATA_TYPE + 4'b 0001, // index[12] DMA_DST_DATA_TYPE + 4'b 0001, // index[13] DMA_SIGN_EXT + 4'b 0001, // index[14] DMA_MODE + 4'b 0001, // index[15] DMA_DIM_CONFIG + 4'b 0001, // index[16] DMA_DIM_INV + 4'b 0001, // index[17] DMA_PAD_TOP + 4'b 0001, // index[18] DMA_PAD_BOTTOM + 4'b 0001, // index[19] DMA_PAD_RIGHT + 4'b 0001, // index[20] DMA_PAD_LEFT + 4'b 0011, // index[21] DMA_WINDOW_SIZE + 4'b 0001, // index[22] DMA_WINDOW_COUNT + 4'b 0001, // index[23] DMA_INTERRUPT_EN + 4'b 0001, // index[24] DMA_TRANSACTION_IFR + 4'b 0001 // index[25] DMA_WINDOW_IFR }; endpackage diff --git a/hw/ip/dma/rtl/dma_reg_top.sv b/hw/ip/dma/rtl/dma_reg_top.sv index ea7897c00..57c732e0e 100644 --- a/hw/ip/dma/rtl/dma_reg_top.sv +++ b/hw/ip/dma/rtl/dma_reg_top.sv @@ -8,44 +8,44 @@ `include "common_cells/assertions.svh" module dma_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 7 + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 ) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write - input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write + input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access + // Config + input devmode_i // If 1, explicit error return for unmapped register access ); - import dma_reg_pkg::*; + import dma_reg_pkg::* ; localparam int DW = 32; - localparam int DBW = DW / 8; // Byte Width + localparam int DBW = DW/8; // Byte Width // register signals logic reg_we; logic reg_re; - logic [ AW-1:0] reg_addr; - logic [ DW-1:0] reg_wdata; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; logic [DBW-1:0] reg_be; - logic [ DW-1:0] reg_rdata; + logic [DW-1:0] reg_rdata; logic reg_error; - logic addrmiss, wr_err; + logic addrmiss, wr_err; logic [DW-1:0] reg_rdata_next; // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; assign reg_intf_req = reg_req_i; @@ -61,7 +61,7 @@ module dma_reg_top #( assign reg_intf_rsp.error = reg_error; assign reg_intf_rsp.ready = 1'b1; - assign reg_rdata = reg_rdata_next; + assign reg_rdata = reg_rdata_next ; assign reg_error = (devmode_i & addrmiss) | wr_err; @@ -114,8 +114,8 @@ module dma_reg_top #( logic sign_ext_qs; logic sign_ext_wd; logic sign_ext_we; - logic [1:0] mode_qs; - logic [1:0] mode_wd; + logic [2:0] mode_qs; + logic [2:0] mode_wd; logic mode_we; logic dim_config_qs; logic dim_config_wd; @@ -154,135 +154,135 @@ module dma_reg_top #( // R[src_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_src_ptr ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(src_ptr_we), - .wd(src_ptr_wd), + // from register interface + .we (src_ptr_we), + .wd (src_ptr_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.src_ptr.q), + // to internal hardware + .qe (), + .q (reg2hw.src_ptr.q ), - // to register interface (read) - .qs(src_ptr_qs) + // to register interface (read) + .qs (src_ptr_qs) ); // R[dst_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_dst_ptr ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dst_ptr_we), - .wd(dst_ptr_wd), + // from register interface + .we (dst_ptr_we), + .wd (dst_ptr_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dst_ptr.q), + // to internal hardware + .qe (), + .q (reg2hw.dst_ptr.q ), - // to register interface (read) - .qs(dst_ptr_qs) + // to register interface (read) + .qs (dst_ptr_qs) ); // R[addr_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_addr_ptr ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(addr_ptr_we), - .wd(addr_ptr_wd), + // from register interface + .we (addr_ptr_we), + .wd (addr_ptr_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.addr_ptr.q), + // to internal hardware + .qe (), + .q (reg2hw.addr_ptr.q ), - // to register interface (read) - .qs(addr_ptr_qs) + // to register interface (read) + .qs (addr_ptr_qs) ); // R[size_d1]: V(False) prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_size_d1 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(size_d1_we), - .wd(size_d1_wd), + // from register interface + .we (size_d1_we), + .wd (size_d1_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(reg2hw.size_d1.qe), - .q (reg2hw.size_d1.q), + // to internal hardware + .qe (reg2hw.size_d1.qe), + .q (reg2hw.size_d1.q ), - // to register interface (read) - .qs(size_d1_qs) + // to register interface (read) + .qs (size_d1_qs) ); // R[size_d2]: V(False) prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_size_d2 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(size_d2_we), - .wd(size_d2_wd), + // from register interface + .we (size_d2_we), + .wd (size_d2_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.size_d2.q), + // to internal hardware + .qe (), + .q (reg2hw.size_d2.q ), - // to register interface (read) - .qs(size_d2_qs) + // to register interface (read) + .qs (size_d2_qs) ); @@ -290,139 +290,139 @@ module dma_reg_top #( // F[ready]: 0:0 prim_subreg_ext #( - .DW(1) + .DW (1) ) u_status_ready ( - .re (status_ready_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.ready.d), - .qre(reg2hw.status.ready.re), - .qe (), - .q (reg2hw.status.ready.q), - .qs (status_ready_qs) + .re (status_ready_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ready.d), + .qre (reg2hw.status.ready.re), + .qe (), + .q (reg2hw.status.ready.q ), + .qs (status_ready_qs) ); // F[window_done]: 1:1 prim_subreg_ext #( - .DW(1) + .DW (1) ) u_status_window_done ( - .re (status_window_done_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.window_done.d), - .qre(reg2hw.status.window_done.re), - .qe (), - .q (reg2hw.status.window_done.q), - .qs (status_window_done_qs) + .re (status_window_done_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.window_done.d), + .qre (reg2hw.status.window_done.re), + .qe (), + .q (reg2hw.status.window_done.q ), + .qs (status_window_done_qs) ); // R[src_ptr_inc_d1]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h4) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h4) ) u_src_ptr_inc_d1 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(src_ptr_inc_d1_we), - .wd(src_ptr_inc_d1_wd), + // from register interface + .we (src_ptr_inc_d1_we), + .wd (src_ptr_inc_d1_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.src_ptr_inc_d1.q), + // to internal hardware + .qe (), + .q (reg2hw.src_ptr_inc_d1.q ), - // to register interface (read) - .qs(src_ptr_inc_d1_qs) + // to register interface (read) + .qs (src_ptr_inc_d1_qs) ); // R[src_ptr_inc_d2]: V(False) prim_subreg #( - .DW (23), - .SWACCESS("RW"), - .RESVAL (23'h4) + .DW (23), + .SWACCESS("RW"), + .RESVAL (23'h4) ) u_src_ptr_inc_d2 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(src_ptr_inc_d2_we), - .wd(src_ptr_inc_d2_wd), + // from register interface + .we (src_ptr_inc_d2_we), + .wd (src_ptr_inc_d2_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.src_ptr_inc_d2.q), + // to internal hardware + .qe (), + .q (reg2hw.src_ptr_inc_d2.q ), - // to register interface (read) - .qs(src_ptr_inc_d2_qs) + // to register interface (read) + .qs (src_ptr_inc_d2_qs) ); // R[dst_ptr_inc_d1]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h4) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h4) ) u_dst_ptr_inc_d1 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dst_ptr_inc_d1_we), - .wd(dst_ptr_inc_d1_wd), + // from register interface + .we (dst_ptr_inc_d1_we), + .wd (dst_ptr_inc_d1_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dst_ptr_inc_d1.q), + // to internal hardware + .qe (), + .q (reg2hw.dst_ptr_inc_d1.q ), - // to register interface (read) - .qs(dst_ptr_inc_d1_qs) + // to register interface (read) + .qs (dst_ptr_inc_d1_qs) ); // R[dst_ptr_inc_d2]: V(False) prim_subreg #( - .DW (23), - .SWACCESS("RW"), - .RESVAL (23'h4) + .DW (23), + .SWACCESS("RW"), + .RESVAL (23'h4) ) u_dst_ptr_inc_d2 ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dst_ptr_inc_d2_we), - .wd(dst_ptr_inc_d2_wd), + // from register interface + .we (dst_ptr_inc_d2_we), + .wd (dst_ptr_inc_d2_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dst_ptr_inc_d2.q), + // to internal hardware + .qe (), + .q (reg2hw.dst_ptr_inc_d2.q ), - // to register interface (read) - .qs(dst_ptr_inc_d2_qs) + // to register interface (read) + .qs (dst_ptr_inc_d2_qs) ); @@ -430,376 +430,376 @@ module dma_reg_top #( // F[rx_trigger_slot]: 15:0 prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_slot_rx_trigger_slot ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(slot_rx_trigger_slot_we), - .wd(slot_rx_trigger_slot_wd), + // from register interface + .we (slot_rx_trigger_slot_we), + .wd (slot_rx_trigger_slot_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.slot.rx_trigger_slot.q), + // to internal hardware + .qe (), + .q (reg2hw.slot.rx_trigger_slot.q ), - // to register interface (read) - .qs(slot_rx_trigger_slot_qs) + // to register interface (read) + .qs (slot_rx_trigger_slot_qs) ); // F[tx_trigger_slot]: 31:16 prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_slot_tx_trigger_slot ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(slot_tx_trigger_slot_we), - .wd(slot_tx_trigger_slot_wd), + // from register interface + .we (slot_tx_trigger_slot_we), + .wd (slot_tx_trigger_slot_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.slot.tx_trigger_slot.q), + // to internal hardware + .qe (), + .q (reg2hw.slot.tx_trigger_slot.q ), - // to register interface (read) - .qs(slot_tx_trigger_slot_qs) + // to register interface (read) + .qs (slot_tx_trigger_slot_qs) ); // R[src_data_type]: V(False) prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) ) u_src_data_type ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(src_data_type_we), - .wd(src_data_type_wd), + // from register interface + .we (src_data_type_we), + .wd (src_data_type_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.src_data_type.q), + // to internal hardware + .qe (), + .q (reg2hw.src_data_type.q ), - // to register interface (read) - .qs(src_data_type_qs) + // to register interface (read) + .qs (src_data_type_qs) ); // R[dst_data_type]: V(False) prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) ) u_dst_data_type ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dst_data_type_we), - .wd(dst_data_type_wd), + // from register interface + .we (dst_data_type_we), + .wd (dst_data_type_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dst_data_type.q), + // to internal hardware + .qe (), + .q (reg2hw.dst_data_type.q ), - // to register interface (read) - .qs(dst_data_type_qs) + // to register interface (read) + .qs (dst_data_type_qs) ); // R[sign_ext]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_sign_ext ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(sign_ext_we), - .wd(sign_ext_wd), + // from register interface + .we (sign_ext_we), + .wd (sign_ext_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.sign_ext.q), + // to internal hardware + .qe (), + .q (reg2hw.sign_ext.q ), - // to register interface (read) - .qs(sign_ext_qs) + // to register interface (read) + .qs (sign_ext_qs) ); // R[mode]: V(False) prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) ) u_mode ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(mode_we), - .wd(mode_wd), + // from register interface + .we (mode_we), + .wd (mode_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.mode.q), + // to internal hardware + .qe (), + .q (reg2hw.mode.q ), - // to register interface (read) - .qs(mode_qs) + // to register interface (read) + .qs (mode_qs) ); // R[dim_config]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_dim_config ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dim_config_we), - .wd(dim_config_wd), + // from register interface + .we (dim_config_we), + .wd (dim_config_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dim_config.q), + // to internal hardware + .qe (), + .q (reg2hw.dim_config.q ), - // to register interface (read) - .qs(dim_config_qs) + // to register interface (read) + .qs (dim_config_qs) ); // R[dim_inv]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_dim_inv ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(dim_inv_we), - .wd(dim_inv_wd), + // from register interface + .we (dim_inv_we), + .wd (dim_inv_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.dim_inv.q), + // to internal hardware + .qe (), + .q (reg2hw.dim_inv.q ), - // to register interface (read) - .qs(dim_inv_qs) + // to register interface (read) + .qs (dim_inv_qs) ); // R[pad_top]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_top ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(pad_top_we), - .wd(pad_top_wd), + // from register interface + .we (pad_top_we), + .wd (pad_top_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.pad_top.q), + // to internal hardware + .qe (), + .q (reg2hw.pad_top.q ), - // to register interface (read) - .qs(pad_top_qs) + // to register interface (read) + .qs (pad_top_qs) ); // R[pad_bottom]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_bottom ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(pad_bottom_we), - .wd(pad_bottom_wd), + // from register interface + .we (pad_bottom_we), + .wd (pad_bottom_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.pad_bottom.q), + // to internal hardware + .qe (), + .q (reg2hw.pad_bottom.q ), - // to register interface (read) - .qs(pad_bottom_qs) + // to register interface (read) + .qs (pad_bottom_qs) ); // R[pad_right]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_right ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(pad_right_we), - .wd(pad_right_wd), + // from register interface + .we (pad_right_we), + .wd (pad_right_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.pad_right.q), + // to internal hardware + .qe (), + .q (reg2hw.pad_right.q ), - // to register interface (read) - .qs(pad_right_qs) + // to register interface (read) + .qs (pad_right_qs) ); // R[pad_left]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_left ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(pad_left_we), - .wd(pad_left_wd), + // from register interface + .we (pad_left_we), + .wd (pad_left_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.pad_left.q), + // to internal hardware + .qe (), + .q (reg2hw.pad_left.q ), - // to register interface (read) - .qs(pad_left_qs) + // to register interface (read) + .qs (pad_left_qs) ); // R[window_size]: V(False) prim_subreg #( - .DW (13), - .SWACCESS("RW"), - .RESVAL (13'h0) + .DW (13), + .SWACCESS("RW"), + .RESVAL (13'h0) ) u_window_size ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(window_size_we), - .wd(window_size_wd), + // from register interface + .we (window_size_we), + .wd (window_size_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.window_size.q), + // to internal hardware + .qe (), + .q (reg2hw.window_size.q ), - // to register interface (read) - .qs(window_size_qs) + // to register interface (read) + .qs (window_size_qs) ); // R[window_count]: V(False) prim_subreg #( - .DW (8), - .SWACCESS("RO"), - .RESVAL (8'h0) + .DW (8), + .SWACCESS("RO"), + .RESVAL (8'h0) ) u_window_count ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - .we(1'b0), - .wd('0), + .we (1'b0), + .wd ('0 ), - // from internal hardware - .de(hw2reg.window_count.de), - .d (hw2reg.window_count.d), + // from internal hardware + .de (hw2reg.window_count.de), + .d (hw2reg.window_count.d ), - // to internal hardware - .qe(), - .q (reg2hw.window_count.q), + // to internal hardware + .qe (), + .q (reg2hw.window_count.q ), - // to register interface (read) - .qs(window_count_qs) + // to register interface (read) + .qs (window_count_qs) ); @@ -807,85 +807,85 @@ module dma_reg_top #( // F[transaction_done]: 0:0 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_interrupt_en_transaction_done ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(interrupt_en_transaction_done_we), - .wd(interrupt_en_transaction_done_wd), + // from register interface + .we (interrupt_en_transaction_done_we), + .wd (interrupt_en_transaction_done_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.interrupt_en.transaction_done.q), + // to internal hardware + .qe (), + .q (reg2hw.interrupt_en.transaction_done.q ), - // to register interface (read) - .qs(interrupt_en_transaction_done_qs) + // to register interface (read) + .qs (interrupt_en_transaction_done_qs) ); // F[window_done]: 1:1 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_interrupt_en_window_done ( - .clk_i (clk_i), - .rst_ni(rst_ni), + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // from register interface - .we(interrupt_en_window_done_we), - .wd(interrupt_en_window_done_wd), + // from register interface + .we (interrupt_en_window_done_we), + .wd (interrupt_en_window_done_wd), - // from internal hardware - .de(1'b0), - .d ('0), + // from internal hardware + .de (1'b0), + .d ('0 ), - // to internal hardware - .qe(), - .q (reg2hw.interrupt_en.window_done.q), + // to internal hardware + .qe (), + .q (reg2hw.interrupt_en.window_done.q ), - // to register interface (read) - .qs(interrupt_en_window_done_qs) + // to register interface (read) + .qs (interrupt_en_window_done_qs) ); // R[transaction_ifr]: V(True) prim_subreg_ext #( - .DW(1) + .DW (1) ) u_transaction_ifr ( - .re (transaction_ifr_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.transaction_ifr.d), - .qre(reg2hw.transaction_ifr.re), - .qe (), - .q (reg2hw.transaction_ifr.q), - .qs (transaction_ifr_qs) + .re (transaction_ifr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.transaction_ifr.d), + .qre (reg2hw.transaction_ifr.re), + .qe (), + .q (reg2hw.transaction_ifr.q ), + .qs (transaction_ifr_qs) ); // R[window_ifr]: V(True) prim_subreg_ext #( - .DW(1) + .DW (1) ) u_window_ifr ( - .re (window_ifr_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.window_ifr.d), - .qre(reg2hw.window_ifr.re), - .qe (), - .q (reg2hw.window_ifr.q), - .qs (window_ifr_qs) + .re (window_ifr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.window_ifr.d), + .qre (reg2hw.window_ifr.re), + .qe (), + .q (reg2hw.window_ifr.q ), + .qs (window_ifr_qs) ); @@ -894,16 +894,16 @@ module dma_reg_top #( logic [25:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[0] = (reg_addr == DMA_SRC_PTR_OFFSET); - addr_hit[1] = (reg_addr == DMA_DST_PTR_OFFSET); - addr_hit[2] = (reg_addr == DMA_ADDR_PTR_OFFSET); - addr_hit[3] = (reg_addr == DMA_SIZE_D1_OFFSET); - addr_hit[4] = (reg_addr == DMA_SIZE_D2_OFFSET); - addr_hit[5] = (reg_addr == DMA_STATUS_OFFSET); - addr_hit[6] = (reg_addr == DMA_SRC_PTR_INC_D1_OFFSET); - addr_hit[7] = (reg_addr == DMA_SRC_PTR_INC_D2_OFFSET); - addr_hit[8] = (reg_addr == DMA_DST_PTR_INC_D1_OFFSET); - addr_hit[9] = (reg_addr == DMA_DST_PTR_INC_D2_OFFSET); + addr_hit[ 0] = (reg_addr == DMA_SRC_PTR_OFFSET); + addr_hit[ 1] = (reg_addr == DMA_DST_PTR_OFFSET); + addr_hit[ 2] = (reg_addr == DMA_ADDR_PTR_OFFSET); + addr_hit[ 3] = (reg_addr == DMA_SIZE_D1_OFFSET); + addr_hit[ 4] = (reg_addr == DMA_SIZE_D2_OFFSET); + addr_hit[ 5] = (reg_addr == DMA_STATUS_OFFSET); + addr_hit[ 6] = (reg_addr == DMA_SRC_PTR_INC_D1_OFFSET); + addr_hit[ 7] = (reg_addr == DMA_SRC_PTR_INC_D2_OFFSET); + addr_hit[ 8] = (reg_addr == DMA_DST_PTR_INC_D1_OFFSET); + addr_hit[ 9] = (reg_addr == DMA_DST_PTR_INC_D2_OFFSET); addr_hit[10] = (reg_addr == DMA_SLOT_OFFSET); addr_hit[11] = (reg_addr == DMA_SRC_DATA_TYPE_OFFSET); addr_hit[12] = (reg_addr == DMA_DST_DATA_TYPE_OFFSET); @@ -922,7 +922,7 @@ module dma_reg_top #( addr_hit[25] = (reg_addr == DMA_WINDOW_IFR_OFFSET); end - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0; + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; // Check sub-word write is permitted always_comb begin @@ -1002,7 +1002,7 @@ module dma_reg_top #( assign sign_ext_wd = reg_wdata[0]; assign mode_we = addr_hit[14] & reg_we & !reg_error; - assign mode_wd = reg_wdata[1:0]; + assign mode_wd = reg_wdata[2:0]; assign dim_config_we = addr_hit[15] & reg_we & !reg_error; assign dim_config_wd = reg_wdata[0]; @@ -1081,7 +1081,7 @@ module dma_reg_top #( end addr_hit[10]: begin - reg_rdata_next[15:0] = slot_rx_trigger_slot_qs; + reg_rdata_next[15:0] = slot_rx_trigger_slot_qs; reg_rdata_next[31:16] = slot_tx_trigger_slot_qs; end @@ -1098,7 +1098,7 @@ module dma_reg_top #( end addr_hit[14]: begin - reg_rdata_next[1:0] = mode_qs; + reg_rdata_next[2:0] = mode_qs; end addr_hit[15]: begin @@ -1166,23 +1166,24 @@ module dma_reg_top #( endmodule -module dma_reg_top_intf #( - parameter int AW = 7, - localparam int DW = 32 +module dma_reg_top_intf +#( + parameter int AW = 7, + localparam int DW = 32 ) ( - input logic clk_i, - input logic rst_ni, - REG_BUS.in regbus_slave, - // To HW - output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write - input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write + input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access ); - localparam int unsigned STRB_WIDTH = DW / 8; + localparam int unsigned STRB_WIDTH = DW/8; - `include "register_interface/typedef.svh" - `include "register_interface/assign.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" // Define structs for reg_bus typedef logic [AW-1:0] addr_t; @@ -1192,27 +1193,27 @@ module dma_reg_top_intf #( reg_bus_req_t s_reg_req; reg_bus_rsp_t s_reg_rsp; - + // Assign SV interface to structs `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - + dma_reg_top #( - .reg_req_t(reg_bus_req_t), - .reg_rsp_t(reg_bus_rsp_t), - .AW(AW) + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) ) i_regs ( - .clk_i, - .rst_ni, - .reg_req_i(s_reg_req), - .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write - .hw2reg, // Read - .devmode_i + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i ); - + endmodule diff --git a/sw/device/lib/drivers/dma/dma.h b/sw/device/lib/drivers/dma/dma.h index 98a4f0f4b..d4b996200 100644 --- a/sw/device/lib/drivers/dma/dma.h +++ b/sw/device/lib/drivers/dma/dma.h @@ -227,7 +227,7 @@ typedef enum parameters. This generates a circular mode in the source and/or destination pointing to memory. */ DMA_TRANS_MODE_ADDRESS = DMA_MODE_MODE_VALUE_ADDRESS_MODE, /*!< In this mode, the destination address is read from the address port! */ - + DMA_TRANS_MODE_SUBADDRESS = 4, DMA_TRANS_MODE__size, /*!< Not used, only for sanity checks. */ } dma_trans_mode_t; diff --git a/sw/device/lib/drivers/dma/dma_regs.h b/sw/device/lib/drivers/dma/dma_regs.h index c0ef3797a..6500f3bd3 100644 --- a/sw/device/lib/drivers/dma/dma_regs.h +++ b/sw/device/lib/drivers/dma/dma_regs.h @@ -114,13 +114,14 @@ extern "C" { // Set the operational mode of the DMA #define DMA_MODE_REG_OFFSET 0x38 -#define DMA_MODE_MODE_MASK 0x3 +#define DMA_MODE_MODE_MASK 0x7 #define DMA_MODE_MODE_OFFSET 0 #define DMA_MODE_MODE_FIELD \ ((bitfield_field32_t) { .mask = DMA_MODE_MODE_MASK, .index = DMA_MODE_MODE_OFFSET }) #define DMA_MODE_MODE_VALUE_LINEAR_MODE 0x0 #define DMA_MODE_MODE_VALUE_CIRCULAR_MODE 0x1 #define DMA_MODE_MODE_VALUE_ADDRESS_MODE 0x2 +#define DMA_MODE_MODE_VALUE_SUBADDRESS_MODE 0x3 // Set the dimensionality of the DMA #define DMA_DIM_CONFIG_REG_OFFSET 0x3c From e6b2a477cc4e74116cafc9f01b8572396ea2ff24 Mon Sep 17 00:00:00 2001 From: Luigi2898 Date: Thu, 24 Oct 2024 16:31:16 +0200 Subject: [PATCH 4/9] Add setup functions to bsp --- sw/device/bsp/w25q/w25q.c | 111 ++++++++++++++++++++++++++++++++- sw/device/bsp/w25q/w25q128jw.h | 20 ++++++ 2 files changed, 130 insertions(+), 1 deletion(-) diff --git a/sw/device/bsp/w25q/w25q.c b/sw/device/bsp/w25q/w25q.c index f6a3ac990..eb5a5b623 100644 --- a/sw/device/bsp/w25q/w25q.c +++ b/sw/device/bsp/w25q/w25q.c @@ -319,6 +319,54 @@ w25q_error_codes_t w25q128jw_write(uint32_t addr, void *data, uint32_t length, u return status; } +uint32_t* w25q128jw_read_standard_setup(uint32_t addr, void *data, uint32_t length) { + + // Sanity checks + if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return NULL; + + // Take into account the extra bytes (if any) + if (length % 4 != 0) { + //only multiple of 4 bytes are supported in this function + return NULL; + } + + /* + * SET UP DMA + */ + // SPI and SPI_FLASH are the same IP so same register map + uint32_t *fifo_ptr_rx = (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET); + + // Address + Read command + uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD); + // Load command to TX FIFO + spi_write_word(spi, read_byte_cmd); + spi_wait_for_ready(spi); + + // Set up segment parameters -> send command and address + const uint32_t cmd_read_1 = spi_create_command((spi_command_t){ + .len = 3, // 4 Bytes + .csaat = true, // Command not finished + .speed = SPI_SPEED_STANDARD, // Single speed + .direction = SPI_DIR_TX_ONLY // Write only + }); + // Load segment parameters to COMMAND register + spi_set_command(spi, cmd_read_1); + spi_wait_for_ready(spi); + + // Set up segment parameters -> read length bytes + const uint32_t cmd_read_2 = spi_create_command((spi_command_t){ + .len = length-1, // len bytes + .csaat = false, // End command + .speed = SPI_SPEED_STANDARD, // Single speed + .direction = SPI_DIR_RX_ONLY // Read only + }); + spi_set_command(spi, cmd_read_2); + spi_wait_for_ready(spi); + + + return fifo_ptr_rx; +} + w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t length) { // Sanity checks if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR; @@ -440,7 +488,6 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data, } - w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_init_dma, uint8_t no_sanity_checks) { // Sanity checks @@ -540,6 +587,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32 return FLASH_OK; } + w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data, uint32_t length) { // Sanity checks @@ -679,6 +727,67 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard_dma(uint32_t addr, void* d } +uint32_t* w25q128jw_read_quad_setup(uint32_t addr, void *data, uint32_t length) { + // Sanity checks + if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return NULL; + + // Send quad read command at standard speed + uint32_t cmd_read_quadIO = FC_RDQIO; + spi_write_word(spi, cmd_read_quadIO); + const uint32_t cmd_read = spi_create_command((spi_command_t){ + .len = 0, // 1 Byte + .csaat = true, // Command not finished + .speed = SPI_SPEED_STANDARD, // Single speed + .direction = SPI_DIR_TX_ONLY // Write only + }); + spi_set_command(spi, cmd_read); + spi_wait_for_ready(spi); + + /* + * Send address at quad speed. + * Last byte is Fxh (here FFh) required by W25Q128JW + */ + uint32_t read_byte_cmd = (REVERT_24b_ADDR(addr) | (0xFF << 24)); + spi_write_word(spi, read_byte_cmd); + const uint32_t cmd_address = spi_create_command((spi_command_t){ + .len = 3, // 3 Byte + .csaat = true, // Command not finished + .speed = SPI_SPEED_QUAD, // Quad speed + .direction = SPI_DIR_TX_ONLY // Write only + }); + spi_set_command(spi, cmd_address); + spi_wait_for_ready(spi); + + // Quad read requires dummy clocks + const uint32_t dummy_clocks_cmd = spi_create_command((spi_command_t){ + #ifndef TARGET_SIM + .len = DUMMY_CLOCKS_FAST_READ_QUAD_IO-1, // W25Q128JW flash needs 4 dummy cycles + #else + .len = DUMMY_CLOCKS_SIM-1, // SPI flash simulation model needs 8 dummy cycles + #endif + .csaat = true, // Command not finished + .speed = SPI_SPEED_QUAD, // Quad speed + .direction = SPI_DIR_DUMMY // Dummy + }); + spi_set_command(spi, dummy_clocks_cmd); + spi_wait_for_ready(spi); + + // Read back the requested data at quad speed + const uint32_t cmd_read_rx = spi_create_command((spi_command_t){ + .len = length-1, // length bytes + .csaat = false, // End command + .speed = SPI_SPEED_QUAD, // Quad speed + .direction = SPI_DIR_RX_ONLY // Read only + }); + spi_set_command(spi, cmd_read_rx); + spi_wait_for_ready(spi); + + /* COMMAND FINISHED */ + + // SPI and SPI_FLASH are the same IP so same register map + return (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET); + +} w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void *data, uint32_t length) { // Sanity checks diff --git a/sw/device/bsp/w25q/w25q128jw.h b/sw/device/bsp/w25q/w25q128jw.h index 501f69c60..21449455d 100644 --- a/sw/device/bsp/w25q/w25q128jw.h +++ b/sw/device/bsp/w25q/w25q128jw.h @@ -224,6 +224,16 @@ w25q_error_codes_t w25q128jw_read(uint32_t addr, void* data, uint32_t length); */ w25q_error_codes_t w25q128jw_write(uint32_t addr, void* data, uint32_t length, uint8_t erase_before_write); +/** + * @brief Setup SPI to read from flash at standard speed. (NEEDS TO BE FOLLOWED BY MANUAL SETUP OF THE DMA) + * + * @param addr 24-bit flash address to read from. + * @param data pointer to the data buffer. + * @param length number of bytes to write. + * @return ptr to SPI data register. +*/ +uint32_t* w25q128jw_read_standard_setup(uint32_t addr, void *data, uint32_t length); + /** * @brief Read from flash at standard speed. * @@ -309,6 +319,16 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard_dma(uint32_t addr, void* d */ w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void* data, uint32_t length); +/** + * @brief Setup SPI to read from flash at quad speed. (NEEDS TO BE FOLLOWED BY MANUAL SETUP OF THE DMA) + * + * @param addr 24-bit flash address to read from. + * @param data pointer to the data buffer. + * @param length number of bytes to write. + * @return ptr to SPI data register. +*/ +uint32_t* w25q128jw_read_quad_setup(uint32_t addr, void *data, uint32_t length); + /** * @brief Write to flash at quad speed. Use this function only to write to unitialized data * From c8799b768d7a1c6f022b92c11c67458288f77631 Mon Sep 17 00:00:00 2001 From: alessionaclerio22 Date: Fri, 25 Oct 2024 18:39:27 +0200 Subject: [PATCH 5/9] Fix DMA subaddressing mode. --- hw/ip/dma/rtl/dma.sv | 180 ++++++++++++++++--------------------------- 1 file changed, 67 insertions(+), 113 deletions(-) diff --git a/hw/ip/dma/rtl/dma.sv b/hw/ip/dma/rtl/dma.sv index 6464fa50b..62ddcb72a 100644 --- a/hw/ip/dma/rtl/dma.sv +++ b/hw/ip/dma/rtl/dma.sv @@ -114,7 +114,6 @@ module dma #( logic [3:0] read_fifo_empty; logic read_fifo_alm_full; logic read_fifo_pop_pad; - //logic read_fifo_pop_pad_d; logic [3:0] read_fifo_pop; logic [3:0] read_fifo_pop_act; logic [31:0] read_fifo_input; @@ -133,7 +132,6 @@ module dma #( logic write_fifo_pop; logic [31:0] write_fifo_input; logic [31:0] write_fifo_output; - //logic [31:0] write_fifo_input_d; logic [31:0] write_fifo_input_act; /* Trigger signals */ @@ -399,7 +397,6 @@ module dma #( .dma_padding_fsm_on_i(dma_padding_fsm_on), .dma_start_i(dma_start), .read_fifo_empty_i(&(read_fifo_empty)), - .subaddressing_mode_i(subaddressing_mode), .write_fifo_full_i(write_fifo_full), .write_fifo_alm_full_i(write_fifo_alm_full), .data_read_i(read_fifo_output), @@ -593,47 +590,41 @@ module dma #( always_ff @(posedge clk_cg, negedge rst_ni) begin if (~rst_ni) begin - read_fifo_pop = 4'b0000; + read_fifo_pop <= 4'b0000; end else begin if (subaddressing_mode == 1'b1) begin case (src_data_type) DMA_DATA_TYPE_HALF_WORD: begin - read_fifo_pop = 4'b0011; - - if (read_fifo_pop_pad == 1'b1) begin + if (dma_start == 1'b1) begin + read_fifo_pop <= 4'b0011; + end else if (read_fifo_pop_pad == 1'b1) begin if (read_fifo_pop == 4'b1100) begin - read_fifo_pop = 4'b0011; + read_fifo_pop <= 4'b0011; end else begin - read_fifo_pop = read_fifo_pop << 2; + read_fifo_pop <= read_fifo_pop << 2; end - end else begin - read_fifo_pop = read_fifo_pop; end - end DMA_DATA_TYPE_BYTE: begin - read_fifo_pop = 4'b0001; - - if (read_fifo_pop_pad == 1'b1) begin + if (dma_start == 1'b1) begin + read_fifo_pop <= 4'b0001; + end else if (read_fifo_pop_pad == 1'b1) begin if (read_fifo_pop == 4'b1000) begin - read_fifo_pop = 4'b0001; + read_fifo_pop <= 4'b0001; end else begin - read_fifo_pop = read_fifo_pop << 1; - end - end else begin - read_fifo_pop = read_fifo_pop; + read_fifo_pop <= read_fifo_pop << 1; + end end - end - default: read_fifo_pop = 4'b1111; + default: read_fifo_pop <= {4{read_fifo_pop_pad}}; endcase end else begin - read_fifo_pop = 4'b1111; + read_fifo_pop <= {4{read_fifo_pop_pad}}; end end end @@ -642,119 +633,82 @@ module dma #( if (subaddressing_mode == 1'b1) begin if (read_fifo_pop_pad == 1'b1) begin case (src_data_type) - DMA_DATA_TYPE_HALF_WORD: - - if (read_fifo_pop == 4'b0000) begin - write_fifo_input_act = '0; - write_fifo_push_act = 1'b0; - end else if (read_fifo_pop == 4'b1100) begin - write_fifo_input_act = {{16{1'b0}}, write_fifo_input[31:16]}; - write_fifo_push_act = 1'b1; - end else if (read_fifo_pop == 4'b0011) begin - write_fifo_input_act = {{16{1'b0}}, write_fifo_input[15:0]}; - write_fifo_push_act = 1'b1; - end else begin - write_fifo_input_act = write_fifo_input; - write_fifo_push_act = write_fifo_push; + DMA_DATA_TYPE_HALF_WORD: begin + + read_fifo_pop_act = read_fifo_pop; + + if (read_fifo_pop == 4'b0000) begin + write_fifo_input_act = '0; + write_fifo_push_act = 1'b0; + end else if (read_fifo_pop == 4'b1100) begin + write_fifo_input_act = {{16{1'b0}}, write_fifo_input[31:16]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0011) begin + write_fifo_input_act = {{16{1'b0}}, write_fifo_input[15:0]}; + write_fifo_push_act = 1'b1; + end else begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + end - DMA_DATA_TYPE_BYTE: - - if (read_fifo_pop == 4'b0000) begin - write_fifo_input_act = '0; - write_fifo_push_act = 1'b0; - end else if (read_fifo_pop == 4'b1000) begin - write_fifo_input_act = {{24{1'b0}}, write_fifo_input[31:24]}; - write_fifo_push_act = 1'b1; - end else if (read_fifo_pop == 4'b0100) begin - write_fifo_input_act = {{24{1'b0}}, write_fifo_input[23:16]}; - write_fifo_push_act = 1'b1; - end else if (read_fifo_pop == 4'b0010) begin - write_fifo_input_act = {{24{1'b0}}, write_fifo_input[15:8]}; - write_fifo_push_act = 1'b1; - end else if (read_fifo_pop == 4'b0001) begin - write_fifo_input_act = {{24{1'b0}}, write_fifo_input[7:0]}; - write_fifo_push_act = 1'b1; - end else begin - write_fifo_input_act = write_fifo_input; - write_fifo_push_act = write_fifo_push; + DMA_DATA_TYPE_BYTE: begin + + read_fifo_pop_act = read_fifo_pop; + + if (read_fifo_pop == 4'b0000) begin + write_fifo_input_act = '0; + write_fifo_push_act = 1'b0; + end else if (read_fifo_pop == 4'b1000) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[31:24]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0100) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[23:16]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0010) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[15:8]}; + write_fifo_push_act = 1'b1; + end else if (read_fifo_pop == 4'b0001) begin + write_fifo_input_act = {{24{1'b0}}, write_fifo_input[7:0]}; + write_fifo_push_act = 1'b1; + end else begin + write_fifo_input_act = write_fifo_input; + write_fifo_push_act = write_fifo_push; + end + end default: begin write_fifo_input_act = write_fifo_input; write_fifo_push_act = write_fifo_push; + read_fifo_pop_act = {4{read_fifo_pop_pad}}; end endcase end else begin write_fifo_input_act = '0; write_fifo_push_act = 1'b0; + read_fifo_pop_act = {4{read_fifo_pop_pad}}; end end else begin write_fifo_input_act = write_fifo_input; write_fifo_push_act = write_fifo_push; + read_fifo_pop_act = {4{read_fifo_pop_pad}}; end end - always_comb begin - if (read_fifo_pop_pad == 1'b1) begin - read_fifo_pop_act = read_fifo_pop; - end else begin - read_fifo_pop_act = 4'b0000; - end - end - - - /* always_ff @(posedge clk_cg, negedge rst_ni) begin - if (~rst_ni) begin - read_fifo_pop = 4'b0000; - end else begin - if(subaddressing_mode == 1'b1) begin - case(src_data_type) - DMA_DATA_TYPE_HALF_WORD: - - if(read_fifo_pop_pad == 1'b1) begin - if(read_fifo_pop == 4'b1111) begin - read_fifo_pop = 4'b0011; - end else if (read_fifo_pop == 4'b1100) begin - read_fifo_pop = 4'b0011; - end else if (read_fifo_pop == 4'b1100) begin - read_fifo_pop = 4'b0011; - end else begin - read_fifo_pop = 4'b1111; - end - end else begin - read_fifo_pop = 4'b1111; - end - - DMA_DATA_TYPE_BYTE: - - if(read_fifo_pop_pad == 1'b1) begin - if(read_fifo_pop == 4'b1111) begin - read_fifo_pop = 4'b0001; - end else if (read_fifo_pop == 4'b0001) begin - read_fifo_pop = 4'b0010; - end else if (read_fifo_pop == 4'b0010) begin - read_fifo_pop = 4'b0100; - end else if (read_fifo_pop == 4'b0100) begin - read_fifo_pop = 4'b1000; - end else if (read_fifo_pop == 4'b0001) begin - read_fifo_pop = 4'b0001; - end else begin - read_fifo_pop = 4'1111; - end - end else begin - read_fifo_pop = 4'b1111; - end - - default: - read_fifo_pop <= 4'b1111; - endcase + /*always_comb begin + if(subaddressing_mode == 1'b1) begin + if (read_fifo_pop_pad == 1'b1) begin + read_fifo_pop_act = read_fifo_pop; end else begin - read_fifo_pop <= 4'b1111; + read_fifo_pop_act = 4'b0000; end + end else begin + end - end */ + end*/ /*_________________________________________________________________________________________________________________________________ */ From 54c58556d410201ab127dbc95a18f9a94b545f9b Mon Sep 17 00:00:00 2001 From: alessionaclerio22 Date: Fri, 25 Oct 2024 18:42:00 +0200 Subject: [PATCH 6/9] Add tests for DMA subaddressing mode. --- .../example_dma_subaddressing/buffer.h | 67 ++++ .../example_dma_subaddressing/main.c | 296 ++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 sw/applications/example_dma_subaddressing/buffer.h create mode 100644 sw/applications/example_dma_subaddressing/main.c diff --git a/sw/applications/example_dma_subaddressing/buffer.h b/sw/applications/example_dma_subaddressing/buffer.h new file mode 100644 index 000000000..66d8b1734 --- /dev/null +++ b/sw/applications/example_dma_subaddressing/buffer.h @@ -0,0 +1,67 @@ + uint32_t flash_original_128B[32] = { + 0x76543211, 0xfedcba99, 0x579a6f91, 0x657d5bef, 0x758ee420, 0x01234568, 0xfedbca97, 0x89abde00, + 0x76543212, 0xfedcba9a, 0x579a6f92, 0x657d5bf0, 0x758ee421, 0x01234569, 0xfedbca98, 0x89abde01, + 0x76543213, 0xfedcba9b, 0x579a6f93, 0x657d5bf1, 0x758ee422, 0x0123456a, 0xfedbca99, 0x89abde02, + 0x76543214, 0xfedcba9c, 0x579a6f94, 0x657d5bf2, 0x758ee423, 0x0123456b, 0xfedbca9a, 0x89abde03 +}; + +uint32_t test_flash_se_half_words[64] = { + 0x00003211, 0x00007654, 0xffffba99, 0xfffffedc, 0x00006f91, 0x0000579a, 0x00005bef, 0x0000657d, + 0xffffe420, 0x0000758e, 0x00004568, 0x00000123, 0xffffca97, 0xfffffedb, 0xffffde00, 0xffff89ab, + 0x00003212, 0x00007654, 0xffffba9a, 0xfffffedc, 0x00006f92, 0x0000579a, 0x00005bf0, 0x0000657d, + 0xffffe421, 0x0000758e, 0x00004569, 0x00000123, 0xffffca98, 0xfffffedb, 0xffffde01, 0xffff89ab, + 0x00003213, 0x00007654, 0xffffba9b, 0xfffffedc, 0x00006f93, 0x0000579a, 0x00005bf1, 0x0000657d, + 0xffffe422, 0x0000758e, 0x0000456a, 0x00000123, 0xffffca99, 0xfffffedb, 0xffffde02, 0xffff89ab, + 0x00003214, 0x00007654, 0xffffba9c, 0xfffffedc, 0x00006f94, 0x0000579a, 0x00005bf2, 0x0000657d, + 0xffffe423, 0x0000758e, 0x0000456b, 0x00000123, 0xffffca9a, 0xfffffedb, 0xffffde03, 0xffff89ab +}; + +uint32_t test_flash_half_words[64] = { + 0x00003211, 0x00007654, 0x0000ba99, 0x0000fedc, 0x00006f91, 0x0000579a, 0x00005bef, 0x0000657d, + 0x0000e420, 0x0000758e, 0x00004568, 0x00000123, 0x0000ca97, 0x0000fedb, 0x0000de00, 0x000089ab, + 0x00003212, 0x00007654, 0x0000ba9a, 0x0000fedc, 0x00006f92, 0x0000579a, 0x00005bf0, 0x0000657d, + 0x0000e421, 0x0000758e, 0x00004569, 0x00000123, 0x0000ca98, 0x0000fedb, 0x0000de01, 0x000089ab, + 0x00003213, 0x00007654, 0x0000ba9b, 0x0000fedc, 0x00006f93, 0x0000579a, 0x00005bf1, 0x0000657d, + 0x0000e422, 0x0000758e, 0x0000456a, 0x00000123, 0x0000ca99, 0x0000fedb, 0x0000de02, 0x000089ab, + 0x00003214, 0x00007654, 0x0000ba9c, 0x0000fedc, 0x00006f94, 0x0000579a, 0x00005bf2, 0x0000657d, + 0x0000e423, 0x0000758e, 0x0000456b, 0x00000123, 0x0000ca9a, 0x0000fedb, 0x0000de03, 0x000089ab +}; + +uint32_t test_flash_se_bytes[128] = { + 0x00000011, 0x00000032, 0x00000054, 0x00000076, 0xffffff99, 0xffffffba, 0xffffffdc, 0xfffffffe, + 0xffffff91, 0x0000006f, 0xffffff9a, 0x00000057, 0xffffffef, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000020, 0xffffffe4, 0xffffff8e, 0x00000075, 0x00000068, 0x00000045, 0x00000023, 0x00000001, + 0xffffff97, 0xffffffca, 0xffffffdb, 0xfffffffe, 0x00000000, 0xffffffde, 0xffffffab, 0xffffff89, + 0x00000012, 0x00000032, 0x00000054, 0x00000076, 0xffffff9a, 0xffffffba, 0xffffffdc, 0xfffffffe, + 0xffffff92, 0x0000006f, 0xffffff9a, 0x00000057, 0xfffffff0, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000021, 0xffffffe4, 0xffffff8e, 0x00000075, 0x00000069, 0x00000045, 0x00000023, 0x00000001, + 0xffffff98, 0xffffffca, 0xffffffdb, 0xfffffffe, 0x00000001, 0xffffffde, 0xffffffab, 0xffffff89, + 0x00000013, 0x00000032, 0x00000054, 0x00000076, 0xffffff9b, 0xffffffba, 0xffffffdc, 0xfffffffe, + 0xffffff93, 0x0000006f, 0xffffff9a, 0x00000057, 0xfffffff1, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000022, 0xffffffe4, 0xffffff8e, 0x00000075, 0x0000006a, 0x00000045, 0x00000023, 0x00000001, + 0xffffff99, 0xffffffca, 0xffffffdb, 0xfffffffe, 0x00000002, 0xffffffde, 0xffffffab, 0xffffff89, + 0x00000014, 0x00000032, 0x00000054, 0x00000076, 0xffffff9c, 0xffffffba, 0xffffffdc, 0xfffffffe, + 0xffffff94, 0x0000006f, 0xffffff9a, 0x00000057, 0xfffffff2, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000023, 0xffffffe4, 0xffffff8e, 0x00000075, 0x0000006b, 0x00000045, 0x00000023, 0x00000001, + 0xffffff9a, 0xffffffca, 0xffffffdb, 0xfffffffe, 0x00000003, 0xffffffde, 0xffffffab, 0xffffff89 +}; + +uint32_t test_flash_bytes[128] = { + 0x00000011, 0x00000032, 0x00000054, 0x00000076, 0x00000099, 0x000000ba, 0x000000dc, 0x000000fe, + 0x00000091, 0x0000006f, 0x0000009a, 0x00000057, 0x000000ef, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000020, 0x000000e4, 0x0000008e, 0x00000075, 0x00000068, 0x00000045, 0x00000023, 0x00000001, + 0x00000097, 0x000000ca, 0x000000db, 0x000000fe, 0x00000000, 0x000000de, 0x000000ab, 0x00000089, + 0x00000012, 0x00000032, 0x00000054, 0x00000076, 0x0000009a, 0x000000ba, 0x000000dc, 0x000000fe, + 0x00000092, 0x0000006f, 0x0000009a, 0x00000057, 0x000000f0, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000021, 0x000000e4, 0x0000008e, 0x00000075, 0x00000069, 0x00000045, 0x00000023, 0x00000001, + 0x00000098, 0x000000ca, 0x000000db, 0x000000fe, 0x00000001, 0x000000de, 0x000000ab, 0x00000089, + 0x00000013, 0x00000032, 0x00000054, 0x00000076, 0x0000009b, 0x000000ba, 0x000000dc, 0x000000fe, + 0x00000093, 0x0000006f, 0x0000009a, 0x00000057, 0x000000f1, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000022, 0x000000e4, 0x0000008e, 0x00000075, 0x0000006a, 0x00000045, 0x00000023, 0x00000001, + 0x00000099, 0x000000ca, 0x000000db, 0x000000fe, 0x00000002, 0x000000de, 0x000000ab, 0x00000089, + 0x00000014, 0x00000032, 0x00000054, 0x00000076, 0x0000009c, 0x000000ba, 0x000000dc, 0x000000fe, + 0x00000094, 0x0000006f, 0x0000009a, 0x00000057, 0x000000f2, 0x0000005b, 0x0000007d, 0x00000065, + 0x00000023, 0x000000e4, 0x0000008e, 0x00000075, 0x0000006b, 0x00000045, 0x00000023, 0x00000001, + 0x0000009a, 0x000000ca, 0x000000db, 0x000000fe, 0x00000003, 0x000000de, 0x000000ab, 0x00000089 +}; + diff --git a/sw/applications/example_dma_subaddressing/main.c b/sw/applications/example_dma_subaddressing/main.c new file mode 100644 index 000000000..c2704d0ec --- /dev/null +++ b/sw/applications/example_dma_subaddressing/main.c @@ -0,0 +1,296 @@ +/** + * @file main.c + * @brief Simple spi write example using BSP + * + * Simple example that writes a 1kB buffer to flash memory at a specific address + * and then read it back to check if the data was written correctly. + * +*/ + +#include +#include +#include + +/* To get TX and RX FIFO depth */ +#include "spi_host_regs.h" +/* To get SPI functions */ +#include "spi_host.h" + +#include "x-heep.h" +#include "w25q128jw.h" +#include "dma.h" + +/* By default, PRINTFs are activated for FPGA and disabled for simulation. */ +#define PRINTF_IN_FPGA 0 +#define PRINTF_IN_SIM 1 + +#if TARGET_SIM && PRINTF_IN_SIM + #define PRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) +#elif PRINTF_IN_FPGA && !TARGET_SIM + #define PRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) +#else + #define PRINTF(...) +#endif + +#if defined(TARGET_PYNQ_Z2) || defined(TARGET_ZCU104) || defined(TARGET_NEXYS_A7_100T) + #define USE_SPI_FLASH +#endif + +#ifndef TARGET_SIM +#define USE_SPI_FLASH +#endif + +// Start buffers (the original data) +#include "buffer.h" +// End buffer (where what is read is stored) +uint32_t flash_data[256]; + +#define TEST_BUFFER_WORDS flash_original_128B +#define TEST_BUFFER_SE_HALF_WORDS test_flash_se_half_words +#define TEST_BUFFER_SE_BYTES test_flash_se_bytes +#define TEST_BUFFER_HALF_WORDS test_flash_half_words +#define TEST_BUFFER_BYTES test_flash_bytes +#define LENGTH 128 + +typedef enum { + TYPE_WORD = 2, + TYPE_HALF_WORD = 1, + TYPE_BYTE = 0 +} dma_trans_data_t; + +// Test functions +uint32_t test_read_dma(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint8_t sign_extend); +uint32_t test_read_quad_dma(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint8_t sign_extend); + +// Check function +uint32_t check_result(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint32_t sign_extend); + +// Define global status variable +w25q_error_codes_t global_status; + +int main(int argc, char *argv[]) { + soc_ctrl_t soc_ctrl; + soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS); + + if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) { + PRINTF("This application cannot work with the memory mapped SPI FLASH" + "module - do not use the FLASH_EXEC linker script for this application\n"); + return EXIT_SUCCESS; + } + + // Pick the correct spi device based on simulation type + spi_host_t* spi; + #ifndef USE_SPI_FLASH + spi = spi_host1; + #else + spi = spi_flash; + #endif + + // Define status variable + int32_t errors = 0; + + // Init SPI host and SPI<->Flash bridge parameters + if (w25q128jw_init(spi) != FLASH_OK) return EXIT_FAILURE; + + // DMA transaction data type + dma_trans_data_t dma_data_type; + + // Test simple read with DMA + PRINTF("Testing read with DMA in SUBADDRESS mode...\n"); +/* + dma_data_type = TYPE_WORD; + errors += test_read_dma(TEST_BUFFER_WORDS, LENGTH, dma_data_type, 0); + dma_data_type = TYPE_HALF_WORD; + errors += test_read_dma(TEST_BUFFER_HALF_WORDS, LENGTH, dma_data_type, 0); + errors += test_read_dma(TEST_BUFFER_SE_HALF_WORDS, LENGTH, dma_data_type, 1); + dma_data_type = TYPE_BYTE; + errors += test_read_dma(TEST_BUFFER_BYTES, LENGTH, dma_data_type, 0); + errors += test_read_dma(TEST_BUFFER_SE_BYTES, LENGTH, dma_data_type, 1); */ + + // Test quad read with DMA + dma_data_type = TYPE_WORD; + errors += test_read_quad_dma(TEST_BUFFER_WORDS, LENGTH, dma_data_type, 0); + dma_data_type = TYPE_HALF_WORD; + errors += test_read_quad_dma(TEST_BUFFER_HALF_WORDS, LENGTH, dma_data_type, 0); + errors += test_read_quad_dma(TEST_BUFFER_SE_HALF_WORDS, LENGTH, dma_data_type, 1); + dma_data_type = TYPE_BYTE; + errors += test_read_quad_dma(TEST_BUFFER_BYTES, LENGTH, dma_data_type, 0); + errors += test_read_quad_dma(TEST_BUFFER_SE_BYTES, LENGTH, dma_data_type, 1); + + PRINTF("\n--------TEST FINISHED--------\n"); + if (errors == 0) { + PRINTF("All tests passed!\n"); + return EXIT_SUCCESS; + } else { + PRINTF("Some tests failed!\n"); + return EXIT_FAILURE; + } + +} + +uint32_t test_read_dma(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint8_t sign_extend) { + + dma_data_type_t dma_trans_data_type; + + switch (dma_data_type) { + case TYPE_WORD: + dma_trans_data_type = DMA_DATA_TYPE_WORD; + break; + case TYPE_HALF_WORD: + dma_trans_data_type = DMA_DATA_TYPE_HALF_WORD; + break; + case TYPE_BYTE: + dma_trans_data_type = DMA_DATA_TYPE_BYTE; + break; + default: + break; + } + + dma_init(NULL); + + // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal + #ifndef USE_SPI_FLASH + uint8_t slot = DMA_TRIG_SLOT_SPI_RX; + #else + uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX; + #endif + + // Set up DMA source target + dma_target_t tgt_src = { + .inc_d1_du = 0, // Target is peripheral, no increment + .type = dma_trans_data_type, + }; + // Target is SPI RX FIFO + tgt_src.ptr = (uint8_t*) (w25q128jw_read_standard_setup((uint32_t*)(TEST_BUFFER_WORDS), flash_data, len)); + // Trigger to control the data flow + tgt_src.trig = slot; + + // Set up DMA destination target + dma_target_t tgt_dst = { + .inc_d1_du = 1, // Increment by 1 data unit (word) + .type = DMA_DATA_TYPE_WORD, + .trig = DMA_TRIG_MEMORY, // Read-write operation to memory + }; + tgt_dst.ptr = (uint8_t*)flash_data; // Target is the data buffer + + // Set up DMA transaction + dma_trans_t trans = { + .src = &tgt_src, + .dst = &tgt_dst, + .end = DMA_TRANS_END_POLLING, + .mode = DMA_TRANS_MODE_SUBADDRESS, + .sign_ext = sign_extend, + }; + + // Size is in data units (words in this case) + trans.size_d1_du = len >> (dma_data_type); + + // Validate, load and launch DMA transaction + dma_config_flags_t res; + res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY ); + res = dma_load_transaction(&trans); + res = dma_launch(&trans); + + // Wait for DMA to finish transaction + while(!dma_is_ready(0)); + + uint32_t result = check_result(test_buffer, len, dma_data_type, sign_extend); + + // Reset the flash data buffer + memset(flash_data, 0, len * sizeof(uint8_t)); + + return result; +} + +uint32_t test_read_quad_dma(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint8_t sign_extend) { + + dma_data_type_t dma_trans_data_type; + + switch (dma_data_type) { + case TYPE_WORD: + dma_trans_data_type = DMA_DATA_TYPE_WORD; + break; + case TYPE_HALF_WORD: + dma_trans_data_type = DMA_DATA_TYPE_HALF_WORD; + break; + case TYPE_BYTE: + dma_trans_data_type = DMA_DATA_TYPE_BYTE; + break; + default: + break; + } + + dma_init(NULL); + + // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal + #ifndef USE_SPI_FLASH + uint8_t slot = DMA_TRIG_SLOT_SPI_RX; + #else + uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX; + #endif + + // Set up DMA source target + dma_target_t tgt_src = { + .inc_d1_du = 0, // Target is peripheral, no increment + .type = dma_trans_data_type, + }; + // Target is SPI RX FIFO + tgt_src.ptr = (uint8_t*) (w25q128jw_read_quad_setup((uint32_t*)(TEST_BUFFER_WORDS), flash_data, len)); + // Trigger to control the data flow + tgt_src.trig = slot; + + // Set up DMA destination target + dma_target_t tgt_dst = { + .inc_d1_du = 1, // Increment by 1 data unit (word) + .type = DMA_DATA_TYPE_WORD, + .trig = DMA_TRIG_MEMORY, // Read-write operation to memory + }; + tgt_dst.ptr = (uint8_t*)flash_data; // Target is the data buffer + + // Set up DMA transaction + dma_trans_t trans = { + .src = &tgt_src, + .dst = &tgt_dst, + .end = DMA_TRANS_END_POLLING, + .mode = DMA_TRANS_MODE_SUBADDRESS, + .sign_ext = sign_extend, + }; + + // Size is in data units (words in this case) + trans.size_d1_du = len >> (dma_data_type); + + // Validate, load and launch DMA transaction + dma_config_flags_t res; + res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY ); + res = dma_load_transaction(&trans); + res = dma_launch(&trans); + + // Wait for DMA to finish transaction + while(!dma_is_ready(0)); + + uint32_t result = check_result(test_buffer, len, dma_data_type, sign_extend); + + // Reset the flash data buffer + memset(flash_data, 0, len * sizeof(uint8_t)); + + return result; +} + +uint32_t check_result(uint32_t *test_buffer, uint32_t len, dma_trans_data_t dma_data_type, uint32_t sign_extend) { + uint32_t errors = 0; + + for (uint32_t i = 0; i < len>>dma_data_type; i += 1) { + if (test_buffer[i] != flash_data[i]) { + PRINTF("Error in transfer %d %d at position %d: expected %x, got %x\n", dma_data_type, sign_extend, i, test_buffer[i], flash_data[i]); + errors++; + } + } + + if (errors == 0) { + PRINTF("success!\n"); + } else { + PRINTF("failure, %d errors!\n", errors); + } + + return errors; +} From b29300c733084be4f96abe374e020c016558aef3 Mon Sep 17 00:00:00 2001 From: Luigi2898 Date: Mon, 28 Oct 2024 13:53:04 +0100 Subject: [PATCH 7/9] Fix verible --- hw/ip/dma/rtl/dma_reg_pkg.sv | 312 +++++------ hw/ip/dma/rtl/dma_reg_top.sv | 991 +++++++++++++++++------------------ 2 files changed, 623 insertions(+), 680 deletions(-) diff --git a/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/ip/dma/rtl/dma_reg_pkg.sv index 701e5540a..36fb3cc24 100644 --- a/hw/ip/dma/rtl/dma_reg_pkg.sv +++ b/hw/ip/dma/rtl/dma_reg_pkg.sv @@ -13,226 +13,170 @@ package dma_reg_pkg; // Typedefs for registers // //////////////////////////// - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_src_ptr_reg_t; + typedef struct packed {logic [31:0] q;} dma_reg2hw_src_ptr_reg_t; - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_dst_ptr_reg_t; + typedef struct packed {logic [31:0] q;} dma_reg2hw_dst_ptr_reg_t; - typedef struct packed { - logic [31:0] q; - } dma_reg2hw_addr_ptr_reg_t; + typedef struct packed {logic [31:0] q;} dma_reg2hw_addr_ptr_reg_t; typedef struct packed { logic [15:0] q; logic qe; } dma_reg2hw_size_d1_reg_t; - typedef struct packed { - logic [15:0] q; - } dma_reg2hw_size_d2_reg_t; + typedef struct packed {logic [15:0] q;} dma_reg2hw_size_d2_reg_t; typedef struct packed { struct packed { - logic q; - logic re; + logic q; + logic re; } ready; struct packed { - logic q; - logic re; + logic q; + logic re; } window_done; } dma_reg2hw_status_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_src_ptr_inc_d1_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_src_ptr_inc_d1_reg_t; - typedef struct packed { - logic [22:0] q; - } dma_reg2hw_src_ptr_inc_d2_reg_t; + typedef struct packed {logic [22:0] q;} dma_reg2hw_src_ptr_inc_d2_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_dst_ptr_inc_d1_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_dst_ptr_inc_d1_reg_t; - typedef struct packed { - logic [22:0] q; - } dma_reg2hw_dst_ptr_inc_d2_reg_t; + typedef struct packed {logic [22:0] q;} dma_reg2hw_dst_ptr_inc_d2_reg_t; typedef struct packed { - struct packed { - logic [15:0] q; - } rx_trigger_slot; - struct packed { - logic [15:0] q; - } tx_trigger_slot; + struct packed {logic [15:0] q;} rx_trigger_slot; + struct packed {logic [15:0] q;} tx_trigger_slot; } dma_reg2hw_slot_reg_t; - typedef struct packed { - logic [1:0] q; - } dma_reg2hw_src_data_type_reg_t; + typedef struct packed {logic [1:0] q;} dma_reg2hw_src_data_type_reg_t; - typedef struct packed { - logic [1:0] q; - } dma_reg2hw_dst_data_type_reg_t; + typedef struct packed {logic [1:0] q;} dma_reg2hw_dst_data_type_reg_t; - typedef struct packed { - logic q; - } dma_reg2hw_sign_ext_reg_t; + typedef struct packed {logic q;} dma_reg2hw_sign_ext_reg_t; - typedef struct packed { - logic [2:0] q; - } dma_reg2hw_mode_reg_t; + typedef struct packed {logic [2:0] q;} dma_reg2hw_mode_reg_t; - typedef struct packed { - logic q; - } dma_reg2hw_dim_config_reg_t; + typedef struct packed {logic q;} dma_reg2hw_dim_config_reg_t; - typedef struct packed { - logic q; - } dma_reg2hw_dim_inv_reg_t; + typedef struct packed {logic q;} dma_reg2hw_dim_inv_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_pad_top_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_top_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_pad_bottom_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_bottom_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_pad_right_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_right_reg_t; - typedef struct packed { - logic [5:0] q; - } dma_reg2hw_pad_left_reg_t; + typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_left_reg_t; - typedef struct packed { - logic [12:0] q; - } dma_reg2hw_window_size_reg_t; + typedef struct packed {logic [12:0] q;} dma_reg2hw_window_size_reg_t; - typedef struct packed { - logic [7:0] q; - } dma_reg2hw_window_count_reg_t; + typedef struct packed {logic [7:0] q;} dma_reg2hw_window_count_reg_t; typedef struct packed { - struct packed { - logic q; - } transaction_done; - struct packed { - logic q; - } window_done; + struct packed {logic q;} transaction_done; + struct packed {logic q;} window_done; } dma_reg2hw_interrupt_en_reg_t; typedef struct packed { - logic q; - logic re; + logic q; + logic re; } dma_reg2hw_transaction_ifr_reg_t; typedef struct packed { - logic q; - logic re; + logic q; + logic re; } dma_reg2hw_window_ifr_reg_t; typedef struct packed { - struct packed { - logic d; - } ready; - struct packed { - logic d; - } window_done; + struct packed {logic d;} ready; + struct packed {logic d;} window_done; } dma_hw2reg_status_reg_t; typedef struct packed { - logic [7:0] d; - logic de; + logic [7:0] d; + logic de; } dma_hw2reg_window_count_reg_t; - typedef struct packed { - logic d; - } dma_hw2reg_transaction_ifr_reg_t; + typedef struct packed {logic d;} dma_hw2reg_transaction_ifr_reg_t; - typedef struct packed { - logic d; - } dma_hw2reg_window_ifr_reg_t; + typedef struct packed {logic d;} dma_hw2reg_window_ifr_reg_t; // Register -> HW type typedef struct packed { - dma_reg2hw_src_ptr_reg_t src_ptr; // [283:252] - dma_reg2hw_dst_ptr_reg_t dst_ptr; // [251:220] - dma_reg2hw_addr_ptr_reg_t addr_ptr; // [219:188] - dma_reg2hw_size_d1_reg_t size_d1; // [187:171] - dma_reg2hw_size_d2_reg_t size_d2; // [170:155] - dma_reg2hw_status_reg_t status; // [154:151] - dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1; // [150:145] - dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2; // [144:122] - dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1; // [121:116] - dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2; // [115:93] - dma_reg2hw_slot_reg_t slot; // [92:61] - dma_reg2hw_src_data_type_reg_t src_data_type; // [60:59] - dma_reg2hw_dst_data_type_reg_t dst_data_type; // [58:57] - dma_reg2hw_sign_ext_reg_t sign_ext; // [56:56] - dma_reg2hw_mode_reg_t mode; // [55:53] - dma_reg2hw_dim_config_reg_t dim_config; // [52:52] - dma_reg2hw_dim_inv_reg_t dim_inv; // [51:51] - dma_reg2hw_pad_top_reg_t pad_top; // [50:45] - dma_reg2hw_pad_bottom_reg_t pad_bottom; // [44:39] - dma_reg2hw_pad_right_reg_t pad_right; // [38:33] - dma_reg2hw_pad_left_reg_t pad_left; // [32:27] - dma_reg2hw_window_size_reg_t window_size; // [26:14] - dma_reg2hw_window_count_reg_t window_count; // [13:6] - dma_reg2hw_interrupt_en_reg_t interrupt_en; // [5:4] - dma_reg2hw_transaction_ifr_reg_t transaction_ifr; // [3:2] - dma_reg2hw_window_ifr_reg_t window_ifr; // [1:0] + dma_reg2hw_src_ptr_reg_t src_ptr; // [283:252] + dma_reg2hw_dst_ptr_reg_t dst_ptr; // [251:220] + dma_reg2hw_addr_ptr_reg_t addr_ptr; // [219:188] + dma_reg2hw_size_d1_reg_t size_d1; // [187:171] + dma_reg2hw_size_d2_reg_t size_d2; // [170:155] + dma_reg2hw_status_reg_t status; // [154:151] + dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1; // [150:145] + dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2; // [144:122] + dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1; // [121:116] + dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2; // [115:93] + dma_reg2hw_slot_reg_t slot; // [92:61] + dma_reg2hw_src_data_type_reg_t src_data_type; // [60:59] + dma_reg2hw_dst_data_type_reg_t dst_data_type; // [58:57] + dma_reg2hw_sign_ext_reg_t sign_ext; // [56:56] + dma_reg2hw_mode_reg_t mode; // [55:53] + dma_reg2hw_dim_config_reg_t dim_config; // [52:52] + dma_reg2hw_dim_inv_reg_t dim_inv; // [51:51] + dma_reg2hw_pad_top_reg_t pad_top; // [50:45] + dma_reg2hw_pad_bottom_reg_t pad_bottom; // [44:39] + dma_reg2hw_pad_right_reg_t pad_right; // [38:33] + dma_reg2hw_pad_left_reg_t pad_left; // [32:27] + dma_reg2hw_window_size_reg_t window_size; // [26:14] + dma_reg2hw_window_count_reg_t window_count; // [13:6] + dma_reg2hw_interrupt_en_reg_t interrupt_en; // [5:4] + dma_reg2hw_transaction_ifr_reg_t transaction_ifr; // [3:2] + dma_reg2hw_window_ifr_reg_t window_ifr; // [1:0] } dma_reg2hw_t; // HW -> register type typedef struct packed { - dma_hw2reg_status_reg_t status; // [12:11] - dma_hw2reg_window_count_reg_t window_count; // [10:2] - dma_hw2reg_transaction_ifr_reg_t transaction_ifr; // [1:1] - dma_hw2reg_window_ifr_reg_t window_ifr; // [0:0] + dma_hw2reg_status_reg_t status; // [12:11] + dma_hw2reg_window_count_reg_t window_count; // [10:2] + dma_hw2reg_transaction_ifr_reg_t transaction_ifr; // [1:1] + dma_hw2reg_window_ifr_reg_t window_ifr; // [0:0] } dma_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] DMA_SIZE_D1_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] DMA_SIZE_D2_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D1_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D2_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D1_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D2_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] DMA_SRC_DATA_TYPE_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] DMA_DST_DATA_TYPE_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] DMA_SIGN_EXT_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] DMA_DIM_INV_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] DMA_PAD_TOP_OFFSET = 7'h 44; - parameter logic [BlockAw-1:0] DMA_PAD_BOTTOM_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] DMA_PAD_RIGHT_OFFSET = 7'h 4c; - parameter logic [BlockAw-1:0] DMA_PAD_LEFT_OFFSET = 7'h 50; - parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h 54; - parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h 5c; - parameter logic [BlockAw-1:0] DMA_TRANSACTION_IFR_OFFSET = 7'h 60; - parameter logic [BlockAw-1:0] DMA_WINDOW_IFR_OFFSET = 7'h 64; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h0; + parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h4; + parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h8; + parameter logic [BlockAw-1:0] DMA_SIZE_D1_OFFSET = 7'hc; + parameter logic [BlockAw-1:0] DMA_SIZE_D2_OFFSET = 7'h10; + parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h14; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D1_OFFSET = 7'h18; + parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D2_OFFSET = 7'h1c; + parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D1_OFFSET = 7'h20; + parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D2_OFFSET = 7'h24; + parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h28; + parameter logic [BlockAw-1:0] DMA_SRC_DATA_TYPE_OFFSET = 7'h2c; + parameter logic [BlockAw-1:0] DMA_DST_DATA_TYPE_OFFSET = 7'h30; + parameter logic [BlockAw-1:0] DMA_SIGN_EXT_OFFSET = 7'h34; + parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h38; + parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h3c; + parameter logic [BlockAw-1:0] DMA_DIM_INV_OFFSET = 7'h40; + parameter logic [BlockAw-1:0] DMA_PAD_TOP_OFFSET = 7'h44; + parameter logic [BlockAw-1:0] DMA_PAD_BOTTOM_OFFSET = 7'h48; + parameter logic [BlockAw-1:0] DMA_PAD_RIGHT_OFFSET = 7'h4c; + parameter logic [BlockAw-1:0] DMA_PAD_LEFT_OFFSET = 7'h50; + parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h54; + parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h58; + parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h5c; + parameter logic [BlockAw-1:0] DMA_TRANSACTION_IFR_OFFSET = 7'h60; + parameter logic [BlockAw-1:0] DMA_WINDOW_IFR_OFFSET = 7'h64; // Reset values for hwext registers and their fields - parameter logic [1:0] DMA_STATUS_RESVAL = 2'h 1; - parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h 1; - parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h 0; - parameter logic [0:0] DMA_TRANSACTION_IFR_RESVAL = 1'h 0; - parameter logic [0:0] DMA_TRANSACTION_IFR_FLAG_RESVAL = 1'h 0; - parameter logic [0:0] DMA_WINDOW_IFR_RESVAL = 1'h 0; - parameter logic [0:0] DMA_WINDOW_IFR_FLAG_RESVAL = 1'h 0; + parameter logic [1:0] DMA_STATUS_RESVAL = 2'h1; + parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h1; + parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h0; + parameter logic [0:0] DMA_TRANSACTION_IFR_RESVAL = 1'h0; + parameter logic [0:0] DMA_TRANSACTION_IFR_FLAG_RESVAL = 1'h0; + parameter logic [0:0] DMA_WINDOW_IFR_RESVAL = 1'h0; + parameter logic [0:0] DMA_WINDOW_IFR_FLAG_RESVAL = 1'h0; // Register index typedef enum int { @@ -265,33 +209,33 @@ package dma_reg_pkg; } dma_id_e; // Register width information to check illegal writes - parameter logic [3:0] DMA_PERMIT [26] = '{ - 4'b 1111, // index[ 0] DMA_SRC_PTR - 4'b 1111, // index[ 1] DMA_DST_PTR - 4'b 1111, // index[ 2] DMA_ADDR_PTR - 4'b 0011, // index[ 3] DMA_SIZE_D1 - 4'b 0011, // index[ 4] DMA_SIZE_D2 - 4'b 0001, // index[ 5] DMA_STATUS - 4'b 0001, // index[ 6] DMA_SRC_PTR_INC_D1 - 4'b 0111, // index[ 7] DMA_SRC_PTR_INC_D2 - 4'b 0001, // index[ 8] DMA_DST_PTR_INC_D1 - 4'b 0111, // index[ 9] DMA_DST_PTR_INC_D2 - 4'b 1111, // index[10] DMA_SLOT - 4'b 0001, // index[11] DMA_SRC_DATA_TYPE - 4'b 0001, // index[12] DMA_DST_DATA_TYPE - 4'b 0001, // index[13] DMA_SIGN_EXT - 4'b 0001, // index[14] DMA_MODE - 4'b 0001, // index[15] DMA_DIM_CONFIG - 4'b 0001, // index[16] DMA_DIM_INV - 4'b 0001, // index[17] DMA_PAD_TOP - 4'b 0001, // index[18] DMA_PAD_BOTTOM - 4'b 0001, // index[19] DMA_PAD_RIGHT - 4'b 0001, // index[20] DMA_PAD_LEFT - 4'b 0011, // index[21] DMA_WINDOW_SIZE - 4'b 0001, // index[22] DMA_WINDOW_COUNT - 4'b 0001, // index[23] DMA_INTERRUPT_EN - 4'b 0001, // index[24] DMA_TRANSACTION_IFR - 4'b 0001 // index[25] DMA_WINDOW_IFR + parameter logic [3:0] DMA_PERMIT[26] = '{ + 4'b1111, // index[ 0] DMA_SRC_PTR + 4'b1111, // index[ 1] DMA_DST_PTR + 4'b1111, // index[ 2] DMA_ADDR_PTR + 4'b0011, // index[ 3] DMA_SIZE_D1 + 4'b0011, // index[ 4] DMA_SIZE_D2 + 4'b0001, // index[ 5] DMA_STATUS + 4'b0001, // index[ 6] DMA_SRC_PTR_INC_D1 + 4'b0111, // index[ 7] DMA_SRC_PTR_INC_D2 + 4'b0001, // index[ 8] DMA_DST_PTR_INC_D1 + 4'b0111, // index[ 9] DMA_DST_PTR_INC_D2 + 4'b1111, // index[10] DMA_SLOT + 4'b0001, // index[11] DMA_SRC_DATA_TYPE + 4'b0001, // index[12] DMA_DST_DATA_TYPE + 4'b0001, // index[13] DMA_SIGN_EXT + 4'b0001, // index[14] DMA_MODE + 4'b0001, // index[15] DMA_DIM_CONFIG + 4'b0001, // index[16] DMA_DIM_INV + 4'b0001, // index[17] DMA_PAD_TOP + 4'b0001, // index[18] DMA_PAD_BOTTOM + 4'b0001, // index[19] DMA_PAD_RIGHT + 4'b0001, // index[20] DMA_PAD_LEFT + 4'b0011, // index[21] DMA_WINDOW_SIZE + 4'b0001, // index[22] DMA_WINDOW_COUNT + 4'b0001, // index[23] DMA_INTERRUPT_EN + 4'b0001, // index[24] DMA_TRANSACTION_IFR + 4'b0001 // index[25] DMA_WINDOW_IFR }; endpackage diff --git a/hw/ip/dma/rtl/dma_reg_top.sv b/hw/ip/dma/rtl/dma_reg_top.sv index 57c732e0e..728a7c469 100644 --- a/hw/ip/dma/rtl/dma_reg_top.sv +++ b/hw/ip/dma/rtl/dma_reg_top.sv @@ -8,44 +8,44 @@ `include "common_cells/assertions.svh" module dma_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 7 + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 ) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write - input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write + input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access + // Config + input devmode_i // If 1, explicit error return for unmapped register access ); - import dma_reg_pkg::* ; + import dma_reg_pkg::*; localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width + localparam int DBW = DW / 8; // Byte Width // register signals logic reg_we; logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; + logic [ AW-1:0] reg_addr; + logic [ DW-1:0] reg_wdata; logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; + logic [ DW-1:0] reg_rdata; logic reg_error; - logic addrmiss, wr_err; + logic addrmiss, wr_err; logic [DW-1:0] reg_rdata_next; // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; assign reg_intf_req = reg_req_i; @@ -61,7 +61,7 @@ module dma_reg_top #( assign reg_intf_rsp.error = reg_error; assign reg_intf_rsp.ready = 1'b1; - assign reg_rdata = reg_rdata_next ; + assign reg_rdata = reg_rdata_next; assign reg_error = (devmode_i & addrmiss) | wr_err; @@ -154,135 +154,135 @@ module dma_reg_top #( // R[src_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_src_ptr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (src_ptr_we), - .wd (src_ptr_wd), + // from register interface + .we(src_ptr_we), + .wd(src_ptr_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.src_ptr.q ), + // to internal hardware + .qe(), + .q (reg2hw.src_ptr.q), - // to register interface (read) - .qs (src_ptr_qs) + // to register interface (read) + .qs(src_ptr_qs) ); // R[dst_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_dst_ptr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dst_ptr_we), - .wd (dst_ptr_wd), + // from register interface + .we(dst_ptr_we), + .wd(dst_ptr_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dst_ptr.q ), + // to internal hardware + .qe(), + .q (reg2hw.dst_ptr.q), - // to register interface (read) - .qs (dst_ptr_qs) + // to register interface (read) + .qs(dst_ptr_qs) ); // R[addr_ptr]: V(False) prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) ) u_addr_ptr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (addr_ptr_we), - .wd (addr_ptr_wd), + // from register interface + .we(addr_ptr_we), + .wd(addr_ptr_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.addr_ptr.q ), + // to internal hardware + .qe(), + .q (reg2hw.addr_ptr.q), - // to register interface (read) - .qs (addr_ptr_qs) + // to register interface (read) + .qs(addr_ptr_qs) ); // R[size_d1]: V(False) prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_size_d1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (size_d1_we), - .wd (size_d1_wd), + // from register interface + .we(size_d1_we), + .wd(size_d1_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (reg2hw.size_d1.qe), - .q (reg2hw.size_d1.q ), + // to internal hardware + .qe(reg2hw.size_d1.qe), + .q (reg2hw.size_d1.q), - // to register interface (read) - .qs (size_d1_qs) + // to register interface (read) + .qs(size_d1_qs) ); // R[size_d2]: V(False) prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_size_d2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (size_d2_we), - .wd (size_d2_wd), + // from register interface + .we(size_d2_we), + .wd(size_d2_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.size_d2.q ), + // to internal hardware + .qe(), + .q (reg2hw.size_d2.q), - // to register interface (read) - .qs (size_d2_qs) + // to register interface (read) + .qs(size_d2_qs) ); @@ -290,139 +290,139 @@ module dma_reg_top #( // F[ready]: 0:0 prim_subreg_ext #( - .DW (1) + .DW(1) ) u_status_ready ( - .re (status_ready_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.ready.d), - .qre (reg2hw.status.ready.re), - .qe (), - .q (reg2hw.status.ready.q ), - .qs (status_ready_qs) + .re (status_ready_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ready.d), + .qre(reg2hw.status.ready.re), + .qe (), + .q (reg2hw.status.ready.q), + .qs (status_ready_qs) ); // F[window_done]: 1:1 prim_subreg_ext #( - .DW (1) + .DW(1) ) u_status_window_done ( - .re (status_window_done_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.window_done.d), - .qre (reg2hw.status.window_done.re), - .qe (), - .q (reg2hw.status.window_done.q ), - .qs (status_window_done_qs) + .re (status_window_done_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.window_done.d), + .qre(reg2hw.status.window_done.re), + .qe (), + .q (reg2hw.status.window_done.q), + .qs (status_window_done_qs) ); // R[src_ptr_inc_d1]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h4) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h4) ) u_src_ptr_inc_d1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (src_ptr_inc_d1_we), - .wd (src_ptr_inc_d1_wd), + // from register interface + .we(src_ptr_inc_d1_we), + .wd(src_ptr_inc_d1_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.src_ptr_inc_d1.q ), + // to internal hardware + .qe(), + .q (reg2hw.src_ptr_inc_d1.q), - // to register interface (read) - .qs (src_ptr_inc_d1_qs) + // to register interface (read) + .qs(src_ptr_inc_d1_qs) ); // R[src_ptr_inc_d2]: V(False) prim_subreg #( - .DW (23), - .SWACCESS("RW"), - .RESVAL (23'h4) + .DW (23), + .SWACCESS("RW"), + .RESVAL (23'h4) ) u_src_ptr_inc_d2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (src_ptr_inc_d2_we), - .wd (src_ptr_inc_d2_wd), + // from register interface + .we(src_ptr_inc_d2_we), + .wd(src_ptr_inc_d2_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.src_ptr_inc_d2.q ), + // to internal hardware + .qe(), + .q (reg2hw.src_ptr_inc_d2.q), - // to register interface (read) - .qs (src_ptr_inc_d2_qs) + // to register interface (read) + .qs(src_ptr_inc_d2_qs) ); // R[dst_ptr_inc_d1]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h4) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h4) ) u_dst_ptr_inc_d1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dst_ptr_inc_d1_we), - .wd (dst_ptr_inc_d1_wd), + // from register interface + .we(dst_ptr_inc_d1_we), + .wd(dst_ptr_inc_d1_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dst_ptr_inc_d1.q ), + // to internal hardware + .qe(), + .q (reg2hw.dst_ptr_inc_d1.q), - // to register interface (read) - .qs (dst_ptr_inc_d1_qs) + // to register interface (read) + .qs(dst_ptr_inc_d1_qs) ); // R[dst_ptr_inc_d2]: V(False) prim_subreg #( - .DW (23), - .SWACCESS("RW"), - .RESVAL (23'h4) + .DW (23), + .SWACCESS("RW"), + .RESVAL (23'h4) ) u_dst_ptr_inc_d2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dst_ptr_inc_d2_we), - .wd (dst_ptr_inc_d2_wd), + // from register interface + .we(dst_ptr_inc_d2_we), + .wd(dst_ptr_inc_d2_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dst_ptr_inc_d2.q ), + // to internal hardware + .qe(), + .q (reg2hw.dst_ptr_inc_d2.q), - // to register interface (read) - .qs (dst_ptr_inc_d2_qs) + // to register interface (read) + .qs(dst_ptr_inc_d2_qs) ); @@ -430,376 +430,376 @@ module dma_reg_top #( // F[rx_trigger_slot]: 15:0 prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_slot_rx_trigger_slot ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (slot_rx_trigger_slot_we), - .wd (slot_rx_trigger_slot_wd), + // from register interface + .we(slot_rx_trigger_slot_we), + .wd(slot_rx_trigger_slot_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.slot.rx_trigger_slot.q ), + // to internal hardware + .qe(), + .q (reg2hw.slot.rx_trigger_slot.q), - // to register interface (read) - .qs (slot_rx_trigger_slot_qs) + // to register interface (read) + .qs(slot_rx_trigger_slot_qs) ); // F[tx_trigger_slot]: 31:16 prim_subreg #( - .DW (16), - .SWACCESS("RW"), - .RESVAL (16'h0) + .DW (16), + .SWACCESS("RW"), + .RESVAL (16'h0) ) u_slot_tx_trigger_slot ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (slot_tx_trigger_slot_we), - .wd (slot_tx_trigger_slot_wd), + // from register interface + .we(slot_tx_trigger_slot_we), + .wd(slot_tx_trigger_slot_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.slot.tx_trigger_slot.q ), + // to internal hardware + .qe(), + .q (reg2hw.slot.tx_trigger_slot.q), - // to register interface (read) - .qs (slot_tx_trigger_slot_qs) + // to register interface (read) + .qs(slot_tx_trigger_slot_qs) ); // R[src_data_type]: V(False) prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) ) u_src_data_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (src_data_type_we), - .wd (src_data_type_wd), + // from register interface + .we(src_data_type_we), + .wd(src_data_type_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.src_data_type.q ), + // to internal hardware + .qe(), + .q (reg2hw.src_data_type.q), - // to register interface (read) - .qs (src_data_type_qs) + // to register interface (read) + .qs(src_data_type_qs) ); // R[dst_data_type]: V(False) prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) ) u_dst_data_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dst_data_type_we), - .wd (dst_data_type_wd), + // from register interface + .we(dst_data_type_we), + .wd(dst_data_type_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dst_data_type.q ), + // to internal hardware + .qe(), + .q (reg2hw.dst_data_type.q), - // to register interface (read) - .qs (dst_data_type_qs) + // to register interface (read) + .qs(dst_data_type_qs) ); // R[sign_ext]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_sign_ext ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (sign_ext_we), - .wd (sign_ext_wd), + // from register interface + .we(sign_ext_we), + .wd(sign_ext_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.sign_ext.q ), + // to internal hardware + .qe(), + .q (reg2hw.sign_ext.q), - // to register interface (read) - .qs (sign_ext_qs) + // to register interface (read) + .qs(sign_ext_qs) ); // R[mode]: V(False) prim_subreg #( - .DW (3), - .SWACCESS("RW"), - .RESVAL (3'h0) + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) ) u_mode ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (mode_we), - .wd (mode_wd), + // from register interface + .we(mode_we), + .wd(mode_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.mode.q ), + // to internal hardware + .qe(), + .q (reg2hw.mode.q), - // to register interface (read) - .qs (mode_qs) + // to register interface (read) + .qs(mode_qs) ); // R[dim_config]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_dim_config ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dim_config_we), - .wd (dim_config_wd), + // from register interface + .we(dim_config_we), + .wd(dim_config_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dim_config.q ), + // to internal hardware + .qe(), + .q (reg2hw.dim_config.q), - // to register interface (read) - .qs (dim_config_qs) + // to register interface (read) + .qs(dim_config_qs) ); // R[dim_inv]: V(False) prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_dim_inv ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (dim_inv_we), - .wd (dim_inv_wd), + // from register interface + .we(dim_inv_we), + .wd(dim_inv_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.dim_inv.q ), + // to internal hardware + .qe(), + .q (reg2hw.dim_inv.q), - // to register interface (read) - .qs (dim_inv_qs) + // to register interface (read) + .qs(dim_inv_qs) ); // R[pad_top]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_top ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (pad_top_we), - .wd (pad_top_wd), + // from register interface + .we(pad_top_we), + .wd(pad_top_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.pad_top.q ), + // to internal hardware + .qe(), + .q (reg2hw.pad_top.q), - // to register interface (read) - .qs (pad_top_qs) + // to register interface (read) + .qs(pad_top_qs) ); // R[pad_bottom]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_bottom ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (pad_bottom_we), - .wd (pad_bottom_wd), + // from register interface + .we(pad_bottom_we), + .wd(pad_bottom_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.pad_bottom.q ), + // to internal hardware + .qe(), + .q (reg2hw.pad_bottom.q), - // to register interface (read) - .qs (pad_bottom_qs) + // to register interface (read) + .qs(pad_bottom_qs) ); // R[pad_right]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_right ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (pad_right_we), - .wd (pad_right_wd), + // from register interface + .we(pad_right_we), + .wd(pad_right_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.pad_right.q ), + // to internal hardware + .qe(), + .q (reg2hw.pad_right.q), - // to register interface (read) - .qs (pad_right_qs) + // to register interface (read) + .qs(pad_right_qs) ); // R[pad_left]: V(False) prim_subreg #( - .DW (6), - .SWACCESS("RW"), - .RESVAL (6'h0) + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h0) ) u_pad_left ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (pad_left_we), - .wd (pad_left_wd), + // from register interface + .we(pad_left_we), + .wd(pad_left_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.pad_left.q ), + // to internal hardware + .qe(), + .q (reg2hw.pad_left.q), - // to register interface (read) - .qs (pad_left_qs) + // to register interface (read) + .qs(pad_left_qs) ); // R[window_size]: V(False) prim_subreg #( - .DW (13), - .SWACCESS("RW"), - .RESVAL (13'h0) + .DW (13), + .SWACCESS("RW"), + .RESVAL (13'h0) ) u_window_size ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (window_size_we), - .wd (window_size_wd), + // from register interface + .we(window_size_we), + .wd(window_size_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.window_size.q ), + // to internal hardware + .qe(), + .q (reg2hw.window_size.q), - // to register interface (read) - .qs (window_size_qs) + // to register interface (read) + .qs(window_size_qs) ); // R[window_count]: V(False) prim_subreg #( - .DW (8), - .SWACCESS("RO"), - .RESVAL (8'h0) + .DW (8), + .SWACCESS("RO"), + .RESVAL (8'h0) ) u_window_count ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - .we (1'b0), - .wd ('0 ), + .we(1'b0), + .wd('0), - // from internal hardware - .de (hw2reg.window_count.de), - .d (hw2reg.window_count.d ), + // from internal hardware + .de(hw2reg.window_count.de), + .d (hw2reg.window_count.d), - // to internal hardware - .qe (), - .q (reg2hw.window_count.q ), + // to internal hardware + .qe(), + .q (reg2hw.window_count.q), - // to register interface (read) - .qs (window_count_qs) + // to register interface (read) + .qs(window_count_qs) ); @@ -807,85 +807,85 @@ module dma_reg_top #( // F[transaction_done]: 0:0 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_interrupt_en_transaction_done ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (interrupt_en_transaction_done_we), - .wd (interrupt_en_transaction_done_wd), + // from register interface + .we(interrupt_en_transaction_done_we), + .wd(interrupt_en_transaction_done_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.interrupt_en.transaction_done.q ), + // to internal hardware + .qe(), + .q (reg2hw.interrupt_en.transaction_done.q), - // to register interface (read) - .qs (interrupt_en_transaction_done_qs) + // to register interface (read) + .qs(interrupt_en_transaction_done_qs) ); // F[window_done]: 1:1 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) ) u_interrupt_en_window_done ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + .clk_i (clk_i), + .rst_ni(rst_ni), - // from register interface - .we (interrupt_en_window_done_we), - .wd (interrupt_en_window_done_wd), + // from register interface + .we(interrupt_en_window_done_we), + .wd(interrupt_en_window_done_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // from internal hardware + .de(1'b0), + .d ('0), - // to internal hardware - .qe (), - .q (reg2hw.interrupt_en.window_done.q ), + // to internal hardware + .qe(), + .q (reg2hw.interrupt_en.window_done.q), - // to register interface (read) - .qs (interrupt_en_window_done_qs) + // to register interface (read) + .qs(interrupt_en_window_done_qs) ); // R[transaction_ifr]: V(True) prim_subreg_ext #( - .DW (1) + .DW(1) ) u_transaction_ifr ( - .re (transaction_ifr_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.transaction_ifr.d), - .qre (reg2hw.transaction_ifr.re), - .qe (), - .q (reg2hw.transaction_ifr.q ), - .qs (transaction_ifr_qs) + .re (transaction_ifr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.transaction_ifr.d), + .qre(reg2hw.transaction_ifr.re), + .qe (), + .q (reg2hw.transaction_ifr.q), + .qs (transaction_ifr_qs) ); // R[window_ifr]: V(True) prim_subreg_ext #( - .DW (1) + .DW(1) ) u_window_ifr ( - .re (window_ifr_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.window_ifr.d), - .qre (reg2hw.window_ifr.re), - .qe (), - .q (reg2hw.window_ifr.q ), - .qs (window_ifr_qs) + .re (window_ifr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.window_ifr.d), + .qre(reg2hw.window_ifr.re), + .qe (), + .q (reg2hw.window_ifr.q), + .qs (window_ifr_qs) ); @@ -894,16 +894,16 @@ module dma_reg_top #( logic [25:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[ 0] = (reg_addr == DMA_SRC_PTR_OFFSET); - addr_hit[ 1] = (reg_addr == DMA_DST_PTR_OFFSET); - addr_hit[ 2] = (reg_addr == DMA_ADDR_PTR_OFFSET); - addr_hit[ 3] = (reg_addr == DMA_SIZE_D1_OFFSET); - addr_hit[ 4] = (reg_addr == DMA_SIZE_D2_OFFSET); - addr_hit[ 5] = (reg_addr == DMA_STATUS_OFFSET); - addr_hit[ 6] = (reg_addr == DMA_SRC_PTR_INC_D1_OFFSET); - addr_hit[ 7] = (reg_addr == DMA_SRC_PTR_INC_D2_OFFSET); - addr_hit[ 8] = (reg_addr == DMA_DST_PTR_INC_D1_OFFSET); - addr_hit[ 9] = (reg_addr == DMA_DST_PTR_INC_D2_OFFSET); + addr_hit[0] = (reg_addr == DMA_SRC_PTR_OFFSET); + addr_hit[1] = (reg_addr == DMA_DST_PTR_OFFSET); + addr_hit[2] = (reg_addr == DMA_ADDR_PTR_OFFSET); + addr_hit[3] = (reg_addr == DMA_SIZE_D1_OFFSET); + addr_hit[4] = (reg_addr == DMA_SIZE_D2_OFFSET); + addr_hit[5] = (reg_addr == DMA_STATUS_OFFSET); + addr_hit[6] = (reg_addr == DMA_SRC_PTR_INC_D1_OFFSET); + addr_hit[7] = (reg_addr == DMA_SRC_PTR_INC_D2_OFFSET); + addr_hit[8] = (reg_addr == DMA_DST_PTR_INC_D1_OFFSET); + addr_hit[9] = (reg_addr == DMA_DST_PTR_INC_D2_OFFSET); addr_hit[10] = (reg_addr == DMA_SLOT_OFFSET); addr_hit[11] = (reg_addr == DMA_SRC_DATA_TYPE_OFFSET); addr_hit[12] = (reg_addr == DMA_DST_DATA_TYPE_OFFSET); @@ -922,7 +922,7 @@ module dma_reg_top #( addr_hit[25] = (reg_addr == DMA_WINDOW_IFR_OFFSET); end - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0; // Check sub-word write is permitted always_comb begin @@ -1081,7 +1081,7 @@ module dma_reg_top #( end addr_hit[10]: begin - reg_rdata_next[15:0] = slot_rx_trigger_slot_qs; + reg_rdata_next[15:0] = slot_rx_trigger_slot_qs; reg_rdata_next[31:16] = slot_tx_trigger_slot_qs; end @@ -1166,24 +1166,23 @@ module dma_reg_top #( endmodule -module dma_reg_top_intf -#( - parameter int AW = 7, - localparam int DW = 32 +module dma_reg_top_intf #( + parameter int AW = 7, + localparam int DW = 32 ) ( - input logic clk_i, - input logic rst_ni, - REG_BUS.in regbus_slave, - // To HW - output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write - input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output dma_reg_pkg::dma_reg2hw_t reg2hw, // Write + input dma_reg_pkg::dma_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access ); - localparam int unsigned STRB_WIDTH = DW/8; + localparam int unsigned STRB_WIDTH = DW / 8; -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" + `include "register_interface/typedef.svh" + `include "register_interface/assign.svh" // Define structs for reg_bus typedef logic [AW-1:0] addr_t; @@ -1193,27 +1192,27 @@ module dma_reg_top_intf reg_bus_req_t s_reg_req; reg_bus_rsp_t s_reg_rsp; - + // Assign SV interface to structs `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - + dma_reg_top #( - .reg_req_t(reg_bus_req_t), - .reg_rsp_t(reg_bus_rsp_t), - .AW(AW) + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) ) i_regs ( - .clk_i, - .rst_ni, - .reg_req_i(s_reg_req), - .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write - .hw2reg, // Read - .devmode_i + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i ); - + endmodule From 0f8679ea1b90637849ba0d73290133e31127de39 Mon Sep 17 00:00:00 2001 From: Luigi2898 Date: Mon, 28 Oct 2024 18:58:18 +0100 Subject: [PATCH 8/9] Debug in CI --- .github/workflows/sim-apps-job/test_apps.py | 36 +++++++++++++++++++- sw/applications/example_power_manager/main.c | 14 ++------ 2 files changed, 37 insertions(+), 13 deletions(-) diff --git a/.github/workflows/sim-apps-job/test_apps.py b/.github/workflows/sim-apps-job/test_apps.py index d22b876bd..b7e178f8e 100755 --- a/.github/workflows/sim-apps-job/test_apps.py +++ b/.github/workflows/sim-apps-job/test_apps.py @@ -24,7 +24,7 @@ class BColors: # Define parameters for the test_apps.py script SIMULATOR = "verilator" -SIM_TIMEOUT_S = 600 +SIM_TIMEOUT_S = 600000 LINKER = "on_chip" COMPILER = "gcc" @@ -33,6 +33,40 @@ class BColors: "example_spi_read", "example_spidma_powergate", "example_spi_write", + "coremark", + "example_ams_peripheral", + "example_asm", + "example_cpp", + "example_data_processing_from_flash", + "example_dma", + "example_dma_2d", + "example_dma_external", + "example_dma_multichannel", + "example_dma_sdk", + "example_dma_subaddressing", + "example_ext_memory", + "example_fft", + "example_freertos_blinky", + "example_gpio_intr", + "example_gpio_toggle", + "example_i2s", + "example_iffifo", + "example_im2col", + "example_matadd", + "example_matadd_interleaved", + "example_matfadd", + "example_matmul", + "example_pdm2pcm", + "example_sdk_spi_flash", + "example_simple_accelerator", + "example_spi_read", + "example_spi_write", + "example_spidma_powergate", + "example_tensor_format_conv", + "example_timer_sdk", + "hello_world", + "memtest", + "minver" ] app_list = [app for app in os.listdir("sw/applications")] diff --git a/sw/applications/example_power_manager/main.c b/sw/applications/example_power_manager/main.c index e1fe60e90..30e82e714 100644 --- a/sw/applications/example_power_manager/main.c +++ b/sw/applications/example_power_manager/main.c @@ -26,7 +26,7 @@ /* By default, printfs are activated for FPGA and disabled for simulation. */ #define PRINTF_IN_FPGA 1 -#define PRINTF_IN_SIM 0 +#define PRINTF_IN_SIM 1 #if TARGET_SIM && PRINTF_IN_SIM #define PRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) @@ -193,17 +193,7 @@ int main(int argc, char *argv[]) tgt_src.inc_d2_du = 0; tgt_dst.ptr = (uint8_t *)copied_data_4B; - tgt_dst.inc_d1_du = 1; - tgt_dst.trig = DMA_TRIG_MEMORY; - tgt_dst.type = DMA_DATA_TYPE_WORD; - tgt_dst.env = NULL; - tgt_dst.inc_d2_du = 0; - - trans.size_d1_du = TEST_DATA_SIZE; - trans.src = &tgt_src; - trans.dst = &tgt_dst; - trans.src_type = DMA_DATA_TYPE_WORD; - trans.dst_type = DMA_DATA_TYPE_WORD; + tgt_dst.inc_d1_du = 1;EXTERNAL_DOMAINS trans.mode = DMA_TRANS_MODE_SINGLE; trans.win_du = 0; trans.sign_ext = 0; From 9c44b9c9db7f8a4b05430509221a1add40be37b6 Mon Sep 17 00:00:00 2001 From: alessionaclerio22 Date: Tue, 29 Oct 2024 11:02:23 +0100 Subject: [PATCH 9/9] Delete commented parts in dma.sv and uncomment test sections in example_dma_subaddressing. Restore original version of example_power_manager. --- hw/ip/dma/rtl/dma.sv | 35 ------------------- .../example_dma_subaddressing/main.c | 4 +-- sw/applications/example_power_manager/main.c | 14 ++++++-- 3 files changed, 14 insertions(+), 39 deletions(-) diff --git a/hw/ip/dma/rtl/dma.sv b/hw/ip/dma/rtl/dma.sv index 62ddcb72a..ebf2b9e79 100644 --- a/hw/ip/dma/rtl/dma.sv +++ b/hw/ip/dma/rtl/dma.sv @@ -188,29 +188,6 @@ module dma #( assign clk_cg = clk_i & clk_gate_en_ni; `endif - - - /* Read FIFOs */ - // fifo_v3 #( - // .DEPTH(FIFO_DEPTH), - // .FALL_THROUGH(1'b1) - // ) dma_read_fifo_i ( - // .clk_i(clk_cg), - // .rst_ni, - // .flush_i(fifo_flush), - // .testmode_i(1'b0), - // // status flags - // .full_o(read_fifo_full), - // .empty_o(read_fifo_empty), - // .usage_o(read_fifo_usage), - // // as long as the queue is not full we can push new data - // .data_i(read_fifo_input), - // .push_i(data_in_rvalid), - // // as long as the queue is not empty we can pop new elements - // .data_o(read_fifo_output), - // .pop_i(read_fifo_pop) - // ); - fifo_v3 #( .DEPTH(FIFO_DEPTH), .FALL_THROUGH(1'b1), @@ -698,18 +675,6 @@ module dma #( end end - /*always_comb begin - if(subaddressing_mode == 1'b1) begin - if (read_fifo_pop_pad == 1'b1) begin - read_fifo_pop_act = read_fifo_pop; - end else begin - read_fifo_pop_act = 4'b0000; - end - end else begin - - end - end*/ - /*_________________________________________________________________________________________________________________________________ */ /* Signal assignments */ diff --git a/sw/applications/example_dma_subaddressing/main.c b/sw/applications/example_dma_subaddressing/main.c index c2704d0ec..14ed76ee0 100644 --- a/sw/applications/example_dma_subaddressing/main.c +++ b/sw/applications/example_dma_subaddressing/main.c @@ -97,7 +97,7 @@ int main(int argc, char *argv[]) { // Test simple read with DMA PRINTF("Testing read with DMA in SUBADDRESS mode...\n"); -/* + dma_data_type = TYPE_WORD; errors += test_read_dma(TEST_BUFFER_WORDS, LENGTH, dma_data_type, 0); dma_data_type = TYPE_HALF_WORD; @@ -105,7 +105,7 @@ int main(int argc, char *argv[]) { errors += test_read_dma(TEST_BUFFER_SE_HALF_WORDS, LENGTH, dma_data_type, 1); dma_data_type = TYPE_BYTE; errors += test_read_dma(TEST_BUFFER_BYTES, LENGTH, dma_data_type, 0); - errors += test_read_dma(TEST_BUFFER_SE_BYTES, LENGTH, dma_data_type, 1); */ + errors += test_read_dma(TEST_BUFFER_SE_BYTES, LENGTH, dma_data_type, 1); // Test quad read with DMA dma_data_type = TYPE_WORD; diff --git a/sw/applications/example_power_manager/main.c b/sw/applications/example_power_manager/main.c index 30e82e714..7e07ce2d2 100644 --- a/sw/applications/example_power_manager/main.c +++ b/sw/applications/example_power_manager/main.c @@ -193,7 +193,17 @@ int main(int argc, char *argv[]) tgt_src.inc_d2_du = 0; tgt_dst.ptr = (uint8_t *)copied_data_4B; - tgt_dst.inc_d1_du = 1;EXTERNAL_DOMAINS + tgt_dst.inc_d1_du = 1; + tgt_dst.trig = DMA_TRIG_MEMORY; + tgt_dst.type = DMA_DATA_TYPE_WORD; + tgt_dst.env = NULL; + tgt_dst.inc_d2_du = 0; + + trans.size_d1_du = TEST_DATA_SIZE; + trans.src = &tgt_src; + trans.dst = &tgt_dst; + trans.src_type = DMA_DATA_TYPE_WORD; + trans.dst_type = DMA_DATA_TYPE_WORD; trans.mode = DMA_TRANS_MODE_SINGLE; trans.win_du = 0; trans.sign_ext = 0; @@ -450,4 +460,4 @@ int main(int argc, char *argv[]) #endif return EXIT_SUCCESS; -} +} \ No newline at end of file