diff --git a/esp32h2/src/clint.rs b/esp32h2/src/clint.rs new file mode 100644 index 000000000..f073ef40e --- /dev/null +++ b/esp32h2/src/clint.rs @@ -0,0 +1,89 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x1800], + msip: MSIP, + mtimectl: MTIMECTL, + mtime: MTIME, + mtimecmp: MTIMECMP, + _reserved4: [u8; 0x03e8], + usip: USIP, + utimectl: UTIMECTL, + utime: UTIME, + utimecmp: UTIMECMP, +} +impl RegisterBlock { + #[doc = "0x1800 - "] + #[inline(always)] + pub const fn msip(&self) -> &MSIP { + &self.msip + } + #[doc = "0x1804 - "] + #[inline(always)] + pub const fn mtimectl(&self) -> &MTIMECTL { + &self.mtimectl + } + #[doc = "0x1808..0x1810 - "] + #[inline(always)] + pub const fn mtime(&self) -> &MTIME { + &self.mtime + } + #[doc = "0x1810..0x1818 - "] + #[inline(always)] + pub const fn mtimecmp(&self) -> &MTIMECMP { + &self.mtimecmp + } + #[doc = "0x1c00 - "] + #[inline(always)] + pub const fn usip(&self) -> &USIP { + &self.usip + } + #[doc = "0x1c04 - "] + #[inline(always)] + pub const fn utimectl(&self) -> &UTIMECTL { + &self.utimectl + } + #[doc = "0x1c08..0x1c10 - "] + #[inline(always)] + pub const fn utime(&self) -> &UTIME { + &self.utime + } + #[doc = "0x1c10..0x1c18 - "] + #[inline(always)] + pub const fn utimecmp(&self) -> &UTIMECMP { + &self.utimecmp + } +} +#[doc = "MSIP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip`] module"] +pub type MSIP = crate::Reg; +#[doc = ""] +pub mod msip; +#[doc = "MTIMECTL (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtimectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimectl`] module"] +pub type MTIMECTL = crate::Reg; +#[doc = ""] +pub mod mtimectl; +#[doc = "MTIME (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtime::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime`] module"] +pub type MTIME = crate::Reg; +#[doc = ""] +pub mod mtime; +#[doc = "MTIMECMP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp`] module"] +pub type MTIMECMP = crate::Reg; +#[doc = ""] +pub mod mtimecmp; +#[doc = "USIP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`usip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usip`] module"] +pub type USIP = crate::Reg; +#[doc = ""] +pub mod usip; +#[doc = "UTIMECTL (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utimectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utimectl`] module"] +pub type UTIMECTL = crate::Reg; +#[doc = ""] +pub mod utimectl; +#[doc = "UTIME (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utime::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utime`] module"] +pub type UTIME = crate::Reg; +#[doc = ""] +pub mod utime; +#[doc = "UTIMECMP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utimecmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimecmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utimecmp`] module"] +pub type UTIMECMP = crate::Reg; +#[doc = ""] +pub mod utimecmp; diff --git a/esp32h2/src/clint/msip.rs b/esp32h2/src/clint/msip.rs new file mode 100644 index 000000000..2b28dd27f --- /dev/null +++ b/esp32h2/src/clint/msip.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MSIP` reader"] +pub type R = crate::R; +#[doc = "Register `MSIP` writer"] +pub type W = crate::W; +#[doc = "Field `MSIP` reader - Configures the pending status of the machine software interrupt."] +pub type MSIP_R = crate::BitReader; +#[doc = "Field `MSIP` writer - Configures the pending status of the machine software interrupt."] +pub type MSIP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the pending status of the machine software interrupt."] + #[inline(always)] + pub fn msip(&self) -> MSIP_R { + MSIP_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MSIP").field("msip", &self.msip()).finish() + } +} +impl W { + #[doc = "Bit 0 - Configures the pending status of the machine software interrupt."] + #[inline(always)] + #[must_use] + pub fn msip(&mut self) -> MSIP_W { + MSIP_W::new(self, 0) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MSIP_SPEC; +impl crate::RegisterSpec for MSIP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`msip::R`](R) reader structure"] +impl crate::Readable for MSIP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`msip::W`](W) writer structure"] +impl crate::Writable for MSIP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MSIP to value 0"] +impl crate::Resettable for MSIP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/clint/mtime.rs b/esp32h2/src/clint/mtime.rs new file mode 100644 index 000000000..6691c0385 --- /dev/null +++ b/esp32h2/src/clint/mtime.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MTIME` reader"] +pub type R = crate::R; +#[doc = "Register `MTIME` writer"] +pub type W = crate::W; +#[doc = "Field `MTIME` reader - Configures the 64-bit CLINT timer counter value."] +pub type MTIME_R = crate::FieldReader; +#[doc = "Field `MTIME` writer - Configures the 64-bit CLINT timer counter value."] +pub type MTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>; +impl R { + #[doc = "Bits 0:63 - Configures the 64-bit CLINT timer counter value."] + #[inline(always)] + pub fn mtime(&self) -> MTIME_R { + MTIME_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTIME") + .field("mtime", &self.mtime()) + .finish() + } +} +impl W { + #[doc = "Bits 0:63 - Configures the 64-bit CLINT timer counter value."] + #[inline(always)] + #[must_use] + pub fn mtime(&mut self) -> MTIME_W { + MTIME_W::new(self, 0) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIME_SPEC; +impl crate::RegisterSpec for MTIME_SPEC { + type Ux = u64; +} +#[doc = "`read()` method returns [`mtime::R`](R) reader structure"] +impl crate::Readable for MTIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtime::W`](W) writer structure"] +impl crate::Writable for MTIME_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0; +} +#[doc = "`reset()` method sets MTIME to value 0"] +impl crate::Resettable for MTIME_SPEC { + const RESET_VALUE: u64 = 0; +} diff --git a/esp32h2/src/clint/mtimecmp.rs b/esp32h2/src/clint/mtimecmp.rs new file mode 100644 index 000000000..267fc67d4 --- /dev/null +++ b/esp32h2/src/clint/mtimecmp.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MTIMECMP` reader"] +pub type R = crate::R; +#[doc = "Register `MTIMECMP` writer"] +pub type W = crate::W; +#[doc = "Field `MTIMECMP` reader - Configures the 64-bit machine timer compare value."] +pub type MTIMECMP_R = crate::FieldReader; +#[doc = "Field `MTIMECMP` writer - Configures the 64-bit machine timer compare value."] +pub type MTIMECMP_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>; +impl R { + #[doc = "Bits 0:63 - Configures the 64-bit machine timer compare value."] + #[inline(always)] + pub fn mtimecmp(&self) -> MTIMECMP_R { + MTIMECMP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTIMECMP") + .field("mtimecmp", &self.mtimecmp()) + .finish() + } +} +impl W { + #[doc = "Bits 0:63 - Configures the 64-bit machine timer compare value."] + #[inline(always)] + #[must_use] + pub fn mtimecmp(&mut self) -> MTIMECMP_W { + MTIMECMP_W::new(self, 0) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIMECMP_SPEC; +impl crate::RegisterSpec for MTIMECMP_SPEC { + type Ux = u64; +} +#[doc = "`read()` method returns [`mtimecmp::R`](R) reader structure"] +impl crate::Readable for MTIMECMP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtimecmp::W`](W) writer structure"] +impl crate::Writable for MTIMECMP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0; +} +#[doc = "`reset()` method sets MTIMECMP to value 0"] +impl crate::Resettable for MTIMECMP_SPEC { + const RESET_VALUE: u64 = 0; +} diff --git a/esp32h2/src/clint/mtimectl.rs b/esp32h2/src/clint/mtimectl.rs new file mode 100644 index 000000000..c4cc7738e --- /dev/null +++ b/esp32h2/src/clint/mtimectl.rs @@ -0,0 +1,88 @@ +#[doc = "Register `MTIMECTL` reader"] +pub type R = crate::R; +#[doc = "Register `MTIMECTL` writer"] +pub type W = crate::W; +#[doc = "Field `MTCE` reader - Configures whether to enable the CLINT timer counter."] +pub type MTCE_R = crate::BitReader; +#[doc = "Field `MTCE` writer - Configures whether to enable the CLINT timer counter."] +pub type MTCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MTIE` reader - Write 1 to enable the machine timer interrupt."] +pub type MTIE_R = crate::BitReader; +#[doc = "Field `MTIE` writer - Write 1 to enable the machine timer interrupt."] +pub type MTIE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MTIP` reader - Represents the pending status of the machine timer interrupt."] +pub type MTIP_R = crate::BitReader; +#[doc = "Field `MTOF` reader - Configures whether the machine timer overflows."] +pub type MTOF_R = crate::BitReader; +#[doc = "Field `MTOF` writer - Configures whether the machine timer overflows."] +pub type MTOF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."] + #[inline(always)] + pub fn mtce(&self) -> MTCE_R { + MTCE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."] + #[inline(always)] + pub fn mtie(&self) -> MTIE_R { + MTIE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents the pending status of the machine timer interrupt."] + #[inline(always)] + pub fn mtip(&self) -> MTIP_R { + MTIP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether the machine timer overflows."] + #[inline(always)] + pub fn mtof(&self) -> MTOF_R { + MTOF_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTIMECTL") + .field("mtce", &self.mtce()) + .field("mtie", &self.mtie()) + .field("mtip", &self.mtip()) + .field("mtof", &self.mtof()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."] + #[inline(always)] + #[must_use] + pub fn mtce(&mut self) -> MTCE_W { + MTCE_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."] + #[inline(always)] + #[must_use] + pub fn mtie(&mut self) -> MTIE_W { + MTIE_W::new(self, 1) + } + #[doc = "Bit 3 - Configures whether the machine timer overflows."] + #[inline(always)] + #[must_use] + pub fn mtof(&mut self) -> MTOF_W { + MTOF_W::new(self, 3) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIMECTL_SPEC; +impl crate::RegisterSpec for MTIMECTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtimectl::R`](R) reader structure"] +impl crate::Readable for MTIMECTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtimectl::W`](W) writer structure"] +impl crate::Writable for MTIMECTL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIMECTL to value 0"] +impl crate::Resettable for MTIMECTL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/clint/usip.rs b/esp32h2/src/clint/usip.rs new file mode 100644 index 000000000..6062a4f59 --- /dev/null +++ b/esp32h2/src/clint/usip.rs @@ -0,0 +1,46 @@ +#[doc = "Register `USIP` reader"] +pub type R = crate::R; +#[doc = "Register `USIP` writer"] +pub type W = crate::W; +#[doc = "Field `USIP` reader - Configures the pending status of the user software interrupt."] +pub type USIP_R = crate::BitReader; +#[doc = "Field `USIP` writer - Configures the pending status of the user software interrupt."] +pub type USIP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the pending status of the user software interrupt."] + #[inline(always)] + pub fn usip(&self) -> USIP_R { + USIP_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USIP").field("usip", &self.usip()).finish() + } +} +impl W { + #[doc = "Bit 0 - Configures the pending status of the user software interrupt."] + #[inline(always)] + #[must_use] + pub fn usip(&mut self) -> USIP_W { + USIP_W::new(self, 0) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`usip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USIP_SPEC; +impl crate::RegisterSpec for USIP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usip::R`](R) reader structure"] +impl crate::Readable for USIP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usip::W`](W) writer structure"] +impl crate::Writable for USIP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USIP to value 0"] +impl crate::Resettable for USIP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/clint/utime.rs b/esp32h2/src/clint/utime.rs new file mode 100644 index 000000000..e1df72f81 --- /dev/null +++ b/esp32h2/src/clint/utime.rs @@ -0,0 +1,30 @@ +#[doc = "Register `UTIME` reader"] +pub type R = crate::R; +#[doc = "Field `UTIME` reader - Represents the read-only 64-bit CLINT timer counter value."] +pub type UTIME_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:63 - Represents the read-only 64-bit CLINT timer counter value."] + #[inline(always)] + pub fn utime(&self) -> UTIME_R { + UTIME_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UTIME") + .field("utime", &self.utime()) + .finish() + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`utime::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UTIME_SPEC; +impl crate::RegisterSpec for UTIME_SPEC { + type Ux = u64; +} +#[doc = "`read()` method returns [`utime::R`](R) reader structure"] +impl crate::Readable for UTIME_SPEC {} +#[doc = "`reset()` method sets UTIME to value 0"] +impl crate::Resettable for UTIME_SPEC { + const RESET_VALUE: u64 = 0; +} diff --git a/esp32h2/src/clint/utimecmp.rs b/esp32h2/src/clint/utimecmp.rs new file mode 100644 index 000000000..ca2655ff9 --- /dev/null +++ b/esp32h2/src/clint/utimecmp.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UTIMECMP` reader"] +pub type R = crate::R; +#[doc = "Register `UTIMECMP` writer"] +pub type W = crate::W; +#[doc = "Field `UTIMECMP` reader - Configures the 64-bit user timer compare value."] +pub type UTIMECMP_R = crate::FieldReader; +#[doc = "Field `UTIMECMP` writer - Configures the 64-bit user timer compare value."] +pub type UTIMECMP_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>; +impl R { + #[doc = "Bits 0:63 - Configures the 64-bit user timer compare value."] + #[inline(always)] + pub fn utimecmp(&self) -> UTIMECMP_R { + UTIMECMP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UTIMECMP") + .field("utimecmp", &self.utimecmp()) + .finish() + } +} +impl W { + #[doc = "Bits 0:63 - Configures the 64-bit user timer compare value."] + #[inline(always)] + #[must_use] + pub fn utimecmp(&mut self) -> UTIMECMP_W { + UTIMECMP_W::new(self, 0) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`utimecmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimecmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UTIMECMP_SPEC; +impl crate::RegisterSpec for UTIMECMP_SPEC { + type Ux = u64; +} +#[doc = "`read()` method returns [`utimecmp::R`](R) reader structure"] +impl crate::Readable for UTIMECMP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`utimecmp::W`](W) writer structure"] +impl crate::Writable for UTIMECMP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0; +} +#[doc = "`reset()` method sets UTIMECMP to value 0"] +impl crate::Resettable for UTIMECMP_SPEC { + const RESET_VALUE: u64 = 0; +} diff --git a/esp32h2/src/clint/utimectl.rs b/esp32h2/src/clint/utimectl.rs new file mode 100644 index 000000000..97ba51f92 --- /dev/null +++ b/esp32h2/src/clint/utimectl.rs @@ -0,0 +1,72 @@ +#[doc = "Register `UTIMECTL` reader"] +pub type R = crate::R; +#[doc = "Register `UTIMECTL` writer"] +pub type W = crate::W; +#[doc = "Field `UTIE` reader - Write 1 to enable the user timer interrupt."] +pub type UTIE_R = crate::BitReader; +#[doc = "Field `UTIE` writer - Write 1 to enable the user timer interrupt."] +pub type UTIE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UTIP` reader - Represents the pending status of the user timer interrupt."] +pub type UTIP_R = crate::BitReader; +#[doc = "Field `UTOF` reader - Configures whether the user timer overflows."] +pub type UTOF_R = crate::BitReader; +#[doc = "Field `UTOF` writer - Configures whether the user timer overflows."] +pub type UTOF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Write 1 to enable the user timer interrupt."] + #[inline(always)] + pub fn utie(&self) -> UTIE_R { + UTIE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents the pending status of the user timer interrupt."] + #[inline(always)] + pub fn utip(&self) -> UTIP_R { + UTIP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether the user timer overflows."] + #[inline(always)] + pub fn utof(&self) -> UTOF_R { + UTOF_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UTIMECTL") + .field("utie", &self.utie()) + .field("utip", &self.utip()) + .field("utof", &self.utof()) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Write 1 to enable the user timer interrupt."] + #[inline(always)] + #[must_use] + pub fn utie(&mut self) -> UTIE_W { + UTIE_W::new(self, 1) + } + #[doc = "Bit 3 - Configures whether the user timer overflows."] + #[inline(always)] + #[must_use] + pub fn utof(&mut self) -> UTOF_W { + UTOF_W::new(self, 3) + } +} +#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`utimectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UTIMECTL_SPEC; +impl crate::RegisterSpec for UTIMECTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`utimectl::R`](R) reader structure"] +impl crate::Readable for UTIMECTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`utimectl::W`](W) writer structure"] +impl crate::Writable for UTIMECTL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UTIMECTL to value 0"] +impl crate::Resettable for UTIMECTL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lib.rs b/esp32h2/src/lib.rs index cfc389e79..92b8613c8 100644 --- a/esp32h2/src/lib.rs +++ b/esp32h2/src/lib.rs @@ -2755,6 +2755,52 @@ impl core::fmt::Debug for USB_DEVICE { } #[doc = "Full-speed USB Serial/JTAG Controller"] pub mod usb_device; +#[doc = "Core Local Interrupts"] +pub struct CLINT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLINT {} +impl CLINT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clint::RegisterBlock = 0x2000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clint::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CLINT { + type Target = clint::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLINT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLINT").finish() + } +} +#[doc = "Core Local Interrupts"] +pub mod clint; #[doc = "PLIC Peripheral"] pub struct PLIC_MX { _marker: PhantomData<*const ()>, @@ -2962,6 +3008,8 @@ pub struct Peripherals { pub UHCI0: UHCI0, #[doc = "USB_DEVICE"] pub USB_DEVICE: USB_DEVICE, + #[doc = "CLINT"] + pub CLINT: CLINT, #[doc = "PLIC_MX"] pub PLIC_MX: PLIC_MX, #[doc = "PLIC_UX"] @@ -3043,6 +3091,7 @@ impl Peripherals { UART1: UART1::steal(), UHCI0: UHCI0::steal(), USB_DEVICE: USB_DEVICE::steal(), + CLINT: CLINT::steal(), PLIC_MX: PLIC_MX::steal(), PLIC_UX: PLIC_UX::steal(), } diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml index 9562b4fb6..a37cb5220 100644 --- a/esp32h2/svd/patches/esp32h2.yaml +++ b/esp32h2/svd/patches/esp32h2.yaml @@ -1,6 +1,120 @@ _svd: "../esp32h2.base.svd" _add: + CLINT: + description: Core Local Interrupts + groupName: CLINT + baseAddress: 0x20000000 + addressBlocks: + - offset: 0x0 + size: 0x180 + usage: registers + registers: + MSIP: + addressOffset: 0x1800 + size: 0x20 + resetValue: 0x0 + fields: + MSIP: + description: Configures the pending status of the machine software interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + MTIMECTL: + addressOffset: 0x1804 + size: 0x20 + resetValue: 0x0 + fields: + MTCE: + description: Configures whether to enable the CLINT timer counter. + bitOffset: 0 + bitWidth: 1 + access: read-write + MTIE: + description: Write 1 to enable the machine timer interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + MTIP: + description: Represents the pending status of the machine timer interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + MTOF: + description: Configures whether the machine timer overflows. + bitOffset: 3 + bitWidth: 1 + access: read-write + MTIME: + addressOffset: 0x1808 + size: 0x40 + resetValue: 0x0 + fields: + MTIME: + description: Configures the 64-bit CLINT timer counter value. + bitOffset: 0 + bitWidth: 64 + access: read-write + MTIMECMP: + addressOffset: 0x1810 + size: 0x40 + resetValue: 0x0 + fields: + MTIMECMP: + description: Configures the 64-bit machine timer compare value. + bitOffset: 0 + bitWidth: 64 + access: read-write + USIP: + addressOffset: 0x1C00 + size: 0x20 + resetValue: 0x0 + fields: + USIP: + description: Configures the pending status of the user software interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + UTIMECTL: + addressOffset: 0x1C04 + size: 0x20 + resetValue: 0x0 + fields: + UTIE: + description: Write 1 to enable the user timer interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + UTIP: + description: Represents the pending status of the user timer interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + UTOF: + description: Configures whether the user timer overflows. + bitOffset: 3 + bitWidth: 1 + access: read-write + UTIME: + addressOffset: 0x1C08 + size: 0x40 + resetValue: 0x0 + fields: + UTIME: + description: Represents the read-only 64-bit CLINT timer counter value. + bitOffset: 0 + bitWidth: 64 + access: read-only + UTIMECMP: + addressOffset: 0x1C10 + size: 0x40 + resetValue: 0x0 + fields: + UTIMECMP: + description: Configures the 64-bit user timer compare value. + bitOffset: 0 + bitWidth: 64 + access: read-write PLIC_MX: description: PLIC Peripheral baseAddress: 0x20001000 @@ -89,6 +203,7 @@ _add: bitOffset: 0 bitWidth: 32 access: read-write + PLIC_UX: description: PLIC Peripheral baseAddress: 0x20001400