diff --git a/esp32c2/src/apb_ctrl/wifi_rst_en.rs b/esp32c2/src/apb_ctrl/wifi_rst_en.rs index b1a51f908..d20a1a342 100644 --- a/esp32c2/src/apb_ctrl/wifi_rst_en.rs +++ b/esp32c2/src/apb_ctrl/wifi_rst_en.rs @@ -6,9 +6,9 @@ pub type W = crate::W; pub type MAC_RST_R = crate::BitReader; #[doc = "Field `MAC_RST` writer - Set this bit to reset MAC module. Clear the bit to release MAC module."] pub type MAC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BLE_RPA_RST` reader - Set this bit to reset MAC module. Clear the bit to release MAC module."] +#[doc = "Field `BLE_RPA_RST` reader - Set this bit to reset BLE RPA module. Clear the bit to release BLE RPA module."] pub type BLE_RPA_RST_R = crate::BitReader; -#[doc = "Field `BLE_RPA_RST` writer - Set this bit to reset MAC module. Clear the bit to release MAC module."] +#[doc = "Field `BLE_RPA_RST` writer - Set this bit to reset BLE RPA module. Clear the bit to release BLE RPA module."] pub type BLE_RPA_RST_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 2 - Set this bit to reset MAC module. Clear the bit to release MAC module."] @@ -16,10 +16,10 @@ impl R { pub fn mac_rst(&self) -> MAC_RST_R { MAC_RST_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - Set this bit to reset MAC module. Clear the bit to release MAC module."] + #[doc = "Bit 27 - Set this bit to reset BLE RPA module. Clear the bit to release BLE RPA module."] #[inline(always)] pub fn ble_rpa_rst(&self) -> BLE_RPA_RST_R { - BLE_RPA_RST_R::new(((self.bits >> 3) & 1) != 0) + BLE_RPA_RST_R::new(((self.bits >> 27) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -37,10 +37,10 @@ impl W { pub fn mac_rst(&mut self) -> MAC_RST_W { MAC_RST_W::new(self, 2) } - #[doc = "Bit 3 - Set this bit to reset MAC module. Clear the bit to release MAC module."] + #[doc = "Bit 27 - Set this bit to reset BLE RPA module. Clear the bit to release BLE RPA module."] #[inline(always)] pub fn ble_rpa_rst(&mut self) -> BLE_RPA_RST_W { - BLE_RPA_RST_W::new(self, 3) + BLE_RPA_RST_W::new(self, 27) } } #[doc = "APB_CTRL_WIFI_RST_EN_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c2/src/lib.rs b/esp32c2/src/lib.rs index ad51fe103..8fad03ebb 100644 --- a/esp32c2/src/lib.rs +++ b/esp32c2/src/lib.rs @@ -1389,6 +1389,52 @@ impl core::fmt::Debug for XTS_AES { } #[doc = "XTS-AES-128 Flash Encryption"] pub mod xts_aes; +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub struct LP_I2C_ANA_MST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2C_ANA_MST {} +impl LP_I2C_ANA_MST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2c_ana_mst::RegisterBlock = 0x6004_e840 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2c_ana_mst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2C_ANA_MST { + type Target = lp_i2c_ana_mst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2C_ANA_MST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_ANA_MST").finish() + } +} +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub mod lp_i2c_ana_mst; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -1448,6 +1494,8 @@ pub struct Peripherals { pub UART1: UART1, #[doc = "XTS_AES"] pub XTS_AES: XTS_AES, + #[doc = "LP_I2C_ANA_MST"] + pub LP_I2C_ANA_MST: LP_I2C_ANA_MST, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -1497,6 +1545,7 @@ impl Peripherals { UART0: UART0::steal(), UART1: UART1::steal(), XTS_AES: XTS_AES::steal(), + LP_I2C_ANA_MST: LP_I2C_ANA_MST::steal(), } } } diff --git a/esp32c2/src/lp_i2c_ana_mst.rs b/esp32c2/src/lp_i2c_ana_mst.rs new file mode 100644 index 000000000..a187e7a89 --- /dev/null +++ b/esp32c2/src/lp_i2c_ana_mst.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + i2c0_conf: I2C0_CONF, + ana_config: ANA_CONFIG, + ana_config2: ANA_CONFIG2, +} +impl RegisterBlock { + #[doc = "0x00 - I2C0_CONF register"] + #[inline(always)] + pub const fn i2c0_conf(&self) -> &I2C0_CONF { + &self.i2c0_conf + } + #[doc = "0x04 - ANA_CONFIG register"] + #[inline(always)] + pub const fn ana_config(&self) -> &ANA_CONFIG { + &self.ana_config + } + #[doc = "0x08 - ANA_CONFIG2 register"] + #[inline(always)] + pub const fn ana_config2(&self) -> &ANA_CONFIG2 { + &self.ana_config2 + } +} +#[doc = "I2C0_CONF (rw) register accessor: I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_conf`] module"] +pub type I2C0_CONF = crate::Reg; +#[doc = "I2C0_CONF register"] +pub mod i2c0_conf; +#[doc = "ANA_CONFIG (rw) register accessor: ANA_CONFIG register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_config`] module"] +pub type ANA_CONFIG = crate::Reg; +#[doc = "ANA_CONFIG register"] +pub mod ana_config; +#[doc = "ANA_CONFIG2 (rw) register accessor: ANA_CONFIG2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_config2`] module"] +pub type ANA_CONFIG2 = crate::Reg; +#[doc = "ANA_CONFIG2 register"] +pub mod ana_config2; diff --git a/esp32c2/src/lp_i2c_ana_mst/ana_config.rs b/esp32c2/src/lp_i2c_ana_mst/ana_config.rs new file mode 100644 index 000000000..d96f835a7 --- /dev/null +++ b/esp32c2/src/lp_i2c_ana_mst/ana_config.rs @@ -0,0 +1,77 @@ +#[doc = "Register `ANA_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_PD` reader - Clear to enable BBPLL"] +pub type BBPLL_PD_R = crate::BitReader; +#[doc = "Field `BBPLL_PD` writer - Clear to enable BBPLL"] +pub type BBPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&self) -> BBPLL_PD_R { + BBPLL_PD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONFIG") + .field("bbpll_pd", &self.bbpll_pd()) + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .finish() + } +} +impl W { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&mut self) -> BBPLL_PD_W { + BBPLL_PD_W::new(self, 17) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONFIG register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONFIG_SPEC; +impl crate::RegisterSpec for ANA_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_config::R`](R) reader structure"] +impl crate::Readable for ANA_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_config::W`](W) writer structure"] +impl crate::Writable for ANA_CONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONFIG to value 0"] +impl crate::Resettable for ANA_CONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c2/src/lp_i2c_ana_mst/ana_config2.rs b/esp32c2/src/lp_i2c_ana_mst/ana_config2.rs new file mode 100644 index 000000000..d3d8d8d4c --- /dev/null +++ b/esp32c2/src/lp_i2c_ana_mst/ana_config2.rs @@ -0,0 +1,62 @@ +#[doc = "Register `ANA_CONFIG2` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONFIG2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONFIG2") + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .finish() + } +} +impl W { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONFIG2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONFIG2_SPEC; +impl crate::RegisterSpec for ANA_CONFIG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_config2::R`](R) reader structure"] +impl crate::Readable for ANA_CONFIG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_config2::W`](W) writer structure"] +impl crate::Writable for ANA_CONFIG2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONFIG2 to value 0"] +impl crate::Resettable for ANA_CONFIG2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c2/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32c2/src/lp_i2c_ana_mst/i2c0_conf.rs new file mode 100644 index 000000000..4ff95bc7f --- /dev/null +++ b/esp32c2/src/lp_i2c_ana_mst/i2c0_conf.rs @@ -0,0 +1,77 @@ +#[doc = "Register `I2C0_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` reader - ?"] +pub type BBPLL_STOP_FORCE_HIGH_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` writer - ?"] +pub type BBPLL_STOP_FORCE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` reader - ?"] +pub type BBPLL_STOP_FORCE_LOW_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` writer - ?"] +pub type BBPLL_STOP_FORCE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_CAL_DONE` reader - ?"] +pub type BBPLL_CAL_DONE_R = crate::BitReader; +#[doc = "Field `BBPLL_CAL_DONE` writer - ?"] +pub type BBPLL_CAL_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&self) -> BBPLL_STOP_FORCE_HIGH_R { + BBPLL_STOP_FORCE_HIGH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&self) -> BBPLL_STOP_FORCE_LOW_R { + BBPLL_STOP_FORCE_LOW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 24 - ?"] + #[inline(always)] + pub fn bbpll_cal_done(&self) -> BBPLL_CAL_DONE_R { + BBPLL_CAL_DONE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CONF") + .field("bbpll_stop_force_high", &self.bbpll_stop_force_high()) + .field("bbpll_stop_force_low", &self.bbpll_stop_force_low()) + .field("bbpll_cal_done", &self.bbpll_cal_done()) + .finish() + } +} +impl W { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&mut self) -> BBPLL_STOP_FORCE_HIGH_W { + BBPLL_STOP_FORCE_HIGH_W::new(self, 2) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&mut self) -> BBPLL_STOP_FORCE_LOW_W { + BBPLL_STOP_FORCE_LOW_W::new(self, 3) + } + #[doc = "Bit 24 - ?"] + #[inline(always)] + pub fn bbpll_cal_done(&mut self) -> BBPLL_CAL_DONE_W { + BBPLL_CAL_DONE_W::new(self, 24) + } +} +#[doc = "I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CONF_SPEC; +impl crate::RegisterSpec for I2C0_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_conf::R`](R) reader structure"] +impl crate::Readable for I2C0_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_conf::W`](W) writer structure"] +impl crate::Writable for I2C0_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0_CONF to value 0"] +impl crate::Resettable for I2C0_CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c2/svd/patches/esp32c2.yaml b/esp32c2/svd/patches/esp32c2.yaml index ed5ce1328..b60ed7866 100644 --- a/esp32c2/svd/patches/esp32c2.yaml +++ b/esp32c2/svd/patches/esp32c2.yaml @@ -208,3 +208,66 @@ DMA: name: OUT_PRI OUT_PERI_SEL_CH?: name: OUT_PERI_SEL + +_add: + LP_I2C_ANA_MST: + description: LP_I2C_ANA_MST Peripheral + baseAddress: 0x6004E840 + addressBlock: + - offset: 0x0 + size: 0x0C + usage: "Registers" + registers: + I2C0_CONF: + description: "I2C0_CONF register" + addressOffset: 0x0 + size: 32 + access: read-write + resetValue: 0x00 + fields: + BBPLL_STOP_FORCE_HIGH: + description: "?" + bitOffset: 2 + bitWidth: 1 + BBPLL_STOP_FORCE_LOW: + description: "?" + bitOffset: 3 + bitWidth: 1 + BBPLL_CAL_DONE: + description: "?" + bitOffset: 24 + bitWidth: 1 + ANA_CONFIG: + description: "ANA_CONFIG register" + addressOffset: 0x4 + size: 32 + access: read-write + resetValue: 0 + fields: + BBPLL_PD: + description: "Clear to enable BBPLL" + bitOffset: 17 + bitWidth: 1 + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 + ANA_CONFIG2: + description: "ANA_CONFIG2 register" + addressOffset: 0x8 + size: 32 + access: read-write + resetValue: 0x00 + fields: + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 diff --git a/esp32c3/src/lib.rs b/esp32c3/src/lib.rs index 0d2903e55..aba2e6fde 100644 --- a/esp32c3/src/lib.rs +++ b/esp32c3/src/lib.rs @@ -2047,6 +2047,52 @@ impl core::fmt::Debug for FE2 { } #[doc = "need des"] pub mod fe2; +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub struct LP_I2C_ANA_MST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2C_ANA_MST {} +impl LP_I2C_ANA_MST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2c_ana_mst::RegisterBlock = 0x6000_e040 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2c_ana_mst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2C_ANA_MST { + type Target = lp_i2c_ana_mst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2C_ANA_MST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_ANA_MST").finish() + } +} +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub mod lp_i2c_ana_mst; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -2132,6 +2178,8 @@ pub struct Peripherals { pub FE: FE, #[doc = "FE2"] pub FE2: FE2, + #[doc = "LP_I2C_ANA_MST"] + pub LP_I2C_ANA_MST: LP_I2C_ANA_MST, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -2194,6 +2242,7 @@ impl Peripherals { NRX: NRX::steal(), FE: FE::steal(), FE2: FE2::steal(), + LP_I2C_ANA_MST: LP_I2C_ANA_MST::steal(), } } } diff --git a/esp32c3/src/lp_i2c_ana_mst.rs b/esp32c3/src/lp_i2c_ana_mst.rs new file mode 100644 index 000000000..a187e7a89 --- /dev/null +++ b/esp32c3/src/lp_i2c_ana_mst.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + i2c0_conf: I2C0_CONF, + ana_config: ANA_CONFIG, + ana_config2: ANA_CONFIG2, +} +impl RegisterBlock { + #[doc = "0x00 - I2C0_CONF register"] + #[inline(always)] + pub const fn i2c0_conf(&self) -> &I2C0_CONF { + &self.i2c0_conf + } + #[doc = "0x04 - ANA_CONFIG register"] + #[inline(always)] + pub const fn ana_config(&self) -> &ANA_CONFIG { + &self.ana_config + } + #[doc = "0x08 - ANA_CONFIG2 register"] + #[inline(always)] + pub const fn ana_config2(&self) -> &ANA_CONFIG2 { + &self.ana_config2 + } +} +#[doc = "I2C0_CONF (rw) register accessor: I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_conf`] module"] +pub type I2C0_CONF = crate::Reg; +#[doc = "I2C0_CONF register"] +pub mod i2c0_conf; +#[doc = "ANA_CONFIG (rw) register accessor: ANA_CONFIG register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_config`] module"] +pub type ANA_CONFIG = crate::Reg; +#[doc = "ANA_CONFIG register"] +pub mod ana_config; +#[doc = "ANA_CONFIG2 (rw) register accessor: ANA_CONFIG2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_config2`] module"] +pub type ANA_CONFIG2 = crate::Reg; +#[doc = "ANA_CONFIG2 register"] +pub mod ana_config2; diff --git a/esp32c3/src/lp_i2c_ana_mst/ana_config.rs b/esp32c3/src/lp_i2c_ana_mst/ana_config.rs new file mode 100644 index 000000000..d96f835a7 --- /dev/null +++ b/esp32c3/src/lp_i2c_ana_mst/ana_config.rs @@ -0,0 +1,77 @@ +#[doc = "Register `ANA_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_PD` reader - Clear to enable BBPLL"] +pub type BBPLL_PD_R = crate::BitReader; +#[doc = "Field `BBPLL_PD` writer - Clear to enable BBPLL"] +pub type BBPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&self) -> BBPLL_PD_R { + BBPLL_PD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONFIG") + .field("bbpll_pd", &self.bbpll_pd()) + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .finish() + } +} +impl W { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&mut self) -> BBPLL_PD_W { + BBPLL_PD_W::new(self, 17) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONFIG register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONFIG_SPEC; +impl crate::RegisterSpec for ANA_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_config::R`](R) reader structure"] +impl crate::Readable for ANA_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_config::W`](W) writer structure"] +impl crate::Writable for ANA_CONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONFIG to value 0"] +impl crate::Resettable for ANA_CONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c3/src/lp_i2c_ana_mst/ana_config2.rs b/esp32c3/src/lp_i2c_ana_mst/ana_config2.rs new file mode 100644 index 000000000..d3d8d8d4c --- /dev/null +++ b/esp32c3/src/lp_i2c_ana_mst/ana_config2.rs @@ -0,0 +1,62 @@ +#[doc = "Register `ANA_CONFIG2` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONFIG2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONFIG2") + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .finish() + } +} +impl W { + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONFIG2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_config2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_config2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONFIG2_SPEC; +impl crate::RegisterSpec for ANA_CONFIG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_config2::R`](R) reader structure"] +impl crate::Readable for ANA_CONFIG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_config2::W`](W) writer structure"] +impl crate::Writable for ANA_CONFIG2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONFIG2 to value 0"] +impl crate::Resettable for ANA_CONFIG2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c3/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32c3/src/lp_i2c_ana_mst/i2c0_conf.rs new file mode 100644 index 000000000..4ff95bc7f --- /dev/null +++ b/esp32c3/src/lp_i2c_ana_mst/i2c0_conf.rs @@ -0,0 +1,77 @@ +#[doc = "Register `I2C0_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` reader - ?"] +pub type BBPLL_STOP_FORCE_HIGH_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` writer - ?"] +pub type BBPLL_STOP_FORCE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` reader - ?"] +pub type BBPLL_STOP_FORCE_LOW_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` writer - ?"] +pub type BBPLL_STOP_FORCE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_CAL_DONE` reader - ?"] +pub type BBPLL_CAL_DONE_R = crate::BitReader; +#[doc = "Field `BBPLL_CAL_DONE` writer - ?"] +pub type BBPLL_CAL_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&self) -> BBPLL_STOP_FORCE_HIGH_R { + BBPLL_STOP_FORCE_HIGH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&self) -> BBPLL_STOP_FORCE_LOW_R { + BBPLL_STOP_FORCE_LOW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 24 - ?"] + #[inline(always)] + pub fn bbpll_cal_done(&self) -> BBPLL_CAL_DONE_R { + BBPLL_CAL_DONE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CONF") + .field("bbpll_stop_force_high", &self.bbpll_stop_force_high()) + .field("bbpll_stop_force_low", &self.bbpll_stop_force_low()) + .field("bbpll_cal_done", &self.bbpll_cal_done()) + .finish() + } +} +impl W { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&mut self) -> BBPLL_STOP_FORCE_HIGH_W { + BBPLL_STOP_FORCE_HIGH_W::new(self, 2) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&mut self) -> BBPLL_STOP_FORCE_LOW_W { + BBPLL_STOP_FORCE_LOW_W::new(self, 3) + } + #[doc = "Bit 24 - ?"] + #[inline(always)] + pub fn bbpll_cal_done(&mut self) -> BBPLL_CAL_DONE_W { + BBPLL_CAL_DONE_W::new(self, 24) + } +} +#[doc = "I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CONF_SPEC; +impl crate::RegisterSpec for I2C0_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_conf::R`](R) reader structure"] +impl crate::Readable for I2C0_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_conf::W`](W) writer structure"] +impl crate::Writable for I2C0_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0_CONF to value 0"] +impl crate::Resettable for I2C0_CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c3/svd/patches/esp32c3.yaml b/esp32c3/svd/patches/esp32c3.yaml index e5f6aaf18..e6ce378ff 100644 --- a/esp32c3/svd/patches/esp32c3.yaml +++ b/esp32c3/svd/patches/esp32c3.yaml @@ -106,6 +106,68 @@ _add: bitOffset: 9 bitWidth: 1 access: read-write + LP_I2C_ANA_MST: + description: LP_I2C_ANA_MST Peripheral + baseAddress: 0x6000E040 + addressBlock: + - offset: 0x0 + size: 0x0C + usage: "Registers" + registers: + I2C0_CONF: + description: "I2C0_CONF register" + addressOffset: 0x0 + size: 32 + access: read-write + resetValue: 0x00 + fields: + BBPLL_STOP_FORCE_HIGH: + description: "?" + bitOffset: 2 + bitWidth: 1 + BBPLL_STOP_FORCE_LOW: + description: "?" + bitOffset: 3 + bitWidth: 1 + BBPLL_CAL_DONE: + description: "?" + bitOffset: 24 + bitWidth: 1 + ANA_CONFIG: + description: "ANA_CONFIG register" + addressOffset: 0x4 + size: 32 + access: read-write + resetValue: 0 + fields: + BBPLL_PD: + description: "Clear to enable BBPLL" + bitOffset: 17 + bitWidth: 1 + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 + ANA_CONFIG2: + description: "ANA_CONFIG2 register" + addressOffset: 0x8 + size: 32 + access: read-write + resetValue: 0x00 + fields: + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 + _modify: SPI?: diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml index 243b11ac6..9ef614986 100644 --- a/esp32c6/svd/patches/esp32c6.yaml +++ b/esp32c6/svd/patches/esp32c6.yaml @@ -611,3 +611,28 @@ TWAI*: _modify: ERR_CAPTURE_CODE_DIRECTION: name: ECC_DIRECTION + +LP_I2C_ANA_MST: + _modify: + I2C0_CONF: + access: read-write + I2C0_CONF: + _delete: + - LP_I2C_ANA_MAST_I2C0_CONF + - LP_I2C_ANA_MAST_I2C0_STATUS + _add: + # I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0 + BBPLL_STOP_FORCE_HIGH: + description: "?" + bitOffset: 2 + bitWidth: 1 + BBPLL_STOP_FORCE_LOW: + description: "?" + bitOffset: 3 + bitWidth: 1 + # I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0 + BBPLL_CAL_DONE: + description: "?" + bitOffset: 24 + bitWidth: 1 + access: read-only diff --git a/esp32h2/src/lib.rs b/esp32h2/src/lib.rs index 6ddf1f9f7..1226e99fe 100644 --- a/esp32h2/src/lib.rs +++ b/esp32h2/src/lib.rs @@ -2893,6 +2893,52 @@ impl core::fmt::Debug for PLIC_UX { } #[doc = "PLIC Peripheral"] pub mod plic_ux; +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub struct LP_I2C_ANA_MST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2C_ANA_MST {} +impl LP_I2C_ANA_MST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2c_ana_mst::RegisterBlock = 0x600a_d800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2c_ana_mst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2C_ANA_MST { + type Target = lp_i2c_ana_mst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2C_ANA_MST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_ANA_MST").finish() + } +} +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub mod lp_i2c_ana_mst; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -3014,6 +3060,8 @@ pub struct Peripherals { pub PLIC_MX: PLIC_MX, #[doc = "PLIC_UX"] pub PLIC_UX: PLIC_UX, + #[doc = "LP_I2C_ANA_MST"] + pub LP_I2C_ANA_MST: LP_I2C_ANA_MST, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -3094,6 +3142,7 @@ impl Peripherals { CLINT: CLINT::steal(), PLIC_MX: PLIC_MX::steal(), PLIC_UX: PLIC_UX::steal(), + LP_I2C_ANA_MST: LP_I2C_ANA_MST::steal(), } } } diff --git a/esp32h2/src/lp_i2c_ana_mst.rs b/esp32h2/src/lp_i2c_ana_mst.rs new file mode 100644 index 000000000..784902d34 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst.rs @@ -0,0 +1,147 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + i2c0_ctrl: I2C0_CTRL, + i2c1_ctrl: I2C1_CTRL, + i2c0_conf: I2C0_CONF, + i2c1_conf: I2C1_CONF, + burst_conf: BURST_CONF, + burst_status: BURST_STATUS, + ana_conf0: ANA_CONF0, + ana_conf1: ANA_CONF1, + ana_conf2: ANA_CONF2, + i2c0_ctrl1: I2C0_CTRL1, + i2c1_ctrl1: I2C1_CTRL1, + hw_i2c_ctrl: HW_I2C_CTRL, + nouse: NOUSE, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - I2C0_CTRL register"] + #[inline(always)] + pub const fn i2c0_ctrl(&self) -> &I2C0_CTRL { + &self.i2c0_ctrl + } + #[doc = "0x04 - I2C1_CTRL register"] + #[inline(always)] + pub const fn i2c1_ctrl(&self) -> &I2C1_CTRL { + &self.i2c1_ctrl + } + #[doc = "0x08 - I2C0_CONF register"] + #[inline(always)] + pub const fn i2c0_conf(&self) -> &I2C0_CONF { + &self.i2c0_conf + } + #[doc = "0x0c - I2C1_CONF register"] + #[inline(always)] + pub const fn i2c1_conf(&self) -> &I2C1_CONF { + &self.i2c1_conf + } + #[doc = "0x10 - BURST_CONF register"] + #[inline(always)] + pub const fn burst_conf(&self) -> &BURST_CONF { + &self.burst_conf + } + #[doc = "0x14 - BURST_STATUS register"] + #[inline(always)] + pub const fn burst_status(&self) -> &BURST_STATUS { + &self.burst_status + } + #[doc = "0x18 - ANA_CONF0 register"] + #[inline(always)] + pub const fn ana_conf0(&self) -> &ANA_CONF0 { + &self.ana_conf0 + } + #[doc = "0x1c - ANA_CONF1 register"] + #[inline(always)] + pub const fn ana_conf1(&self) -> &ANA_CONF1 { + &self.ana_conf1 + } + #[doc = "0x20 - ANA_CONF2 register"] + #[inline(always)] + pub const fn ana_conf2(&self) -> &ANA_CONF2 { + &self.ana_conf2 + } + #[doc = "0x24 - I2C0_CTRL1 register"] + #[inline(always)] + pub const fn i2c0_ctrl1(&self) -> &I2C0_CTRL1 { + &self.i2c0_ctrl1 + } + #[doc = "0x28 - I2C1_CTRL1 register"] + #[inline(always)] + pub const fn i2c1_ctrl1(&self) -> &I2C1_CTRL1 { + &self.i2c1_ctrl1 + } + #[doc = "0x2c - HW_I2C_CTRL register"] + #[inline(always)] + pub const fn hw_i2c_ctrl(&self) -> &HW_I2C_CTRL { + &self.hw_i2c_ctrl + } + #[doc = "0x30 - NOUSE register"] + #[inline(always)] + pub const fn nouse(&self) -> &NOUSE { + &self.nouse + } + #[doc = "0x34 - DATE register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "I2C0_CTRL (rw) register accessor: I2C0_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_ctrl`] module"] +pub type I2C0_CTRL = crate::Reg; +#[doc = "I2C0_CTRL register"] +pub mod i2c0_ctrl; +#[doc = "I2C1_CTRL (rw) register accessor: I2C1_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_ctrl`] module"] +pub type I2C1_CTRL = crate::Reg; +#[doc = "I2C1_CTRL register"] +pub mod i2c1_ctrl; +#[doc = "I2C0_CONF (rw) register accessor: I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_conf`] module"] +pub type I2C0_CONF = crate::Reg; +#[doc = "I2C0_CONF register"] +pub mod i2c0_conf; +#[doc = "I2C1_CONF (rw) register accessor: I2C1_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_conf`] module"] +pub type I2C1_CONF = crate::Reg; +#[doc = "I2C1_CONF register"] +pub mod i2c1_conf; +#[doc = "BURST_CONF (rw) register accessor: BURST_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`burst_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burst_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@burst_conf`] module"] +pub type BURST_CONF = crate::Reg; +#[doc = "BURST_CONF register"] +pub mod burst_conf; +#[doc = "BURST_STATUS (rw) register accessor: BURST_STATUS register\n\nYou can [`read`](crate::Reg::read) this register and get [`burst_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burst_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@burst_status`] module"] +pub type BURST_STATUS = crate::Reg; +#[doc = "BURST_STATUS register"] +pub mod burst_status; +#[doc = "ANA_CONF0 (rw) register accessor: ANA_CONF0 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf0`] module"] +pub type ANA_CONF0 = crate::Reg; +#[doc = "ANA_CONF0 register"] +pub mod ana_conf0; +#[doc = "ANA_CONF1 (rw) register accessor: ANA_CONF1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf1`] module"] +pub type ANA_CONF1 = crate::Reg; +#[doc = "ANA_CONF1 register"] +pub mod ana_conf1; +#[doc = "ANA_CONF2 (rw) register accessor: ANA_CONF2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf2`] module"] +pub type ANA_CONF2 = crate::Reg; +#[doc = "ANA_CONF2 register"] +pub mod ana_conf2; +#[doc = "I2C0_CTRL1 (rw) register accessor: I2C0_CTRL1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_ctrl1`] module"] +pub type I2C0_CTRL1 = crate::Reg; +#[doc = "I2C0_CTRL1 register"] +pub mod i2c0_ctrl1; +#[doc = "I2C1_CTRL1 (rw) register accessor: I2C1_CTRL1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_ctrl1`] module"] +pub type I2C1_CTRL1 = crate::Reg; +#[doc = "I2C1_CTRL1 register"] +pub mod i2c1_ctrl1; +#[doc = "HW_I2C_CTRL (rw) register accessor: HW_I2C_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_i2c_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_i2c_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_i2c_ctrl`] module"] +pub type HW_I2C_CTRL = crate::Reg; +#[doc = "HW_I2C_CTRL register"] +pub mod hw_i2c_ctrl; +#[doc = "NOUSE (rw) register accessor: NOUSE register\n\nYou can [`read`](crate::Reg::read) this register and get [`nouse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nouse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nouse`] module"] +pub type NOUSE = crate::Reg; +#[doc = "NOUSE register"] +pub mod nouse; +#[doc = "DATE (rw) register accessor: DATE register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "DATE register"] +pub mod date; diff --git a/esp32h2/src/lp_i2c_ana_mst/ana_conf0.rs b/esp32h2/src/lp_i2c_ana_mst/ana_conf0.rs new file mode 100644 index 000000000..36276f8a5 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/ana_conf0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `ANA_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `CONFIG` reader - ?"] +pub type CONFIG_R = crate::FieldReader; +#[doc = "Field `CONFIG` writer - ?"] +pub type CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `STATUS` reader - ?"] +pub type STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - ?"] + #[inline(always)] + pub fn config(&self) -> CONFIG_R { + CONFIG_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - ?"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF0") + .field("config", &self.config()) + .field("status", &self.status()) + .finish() + } +} +impl W { + #[doc = "Bits 0:23 - ?"] + #[inline(always)] + pub fn config(&mut self) -> CONFIG_W { + CONFIG_W::new(self, 0) + } +} +#[doc = "ANA_CONF0 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF0_SPEC; +impl crate::RegisterSpec for ANA_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf0::R`](R) reader structure"] +impl crate::Readable for ANA_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf0::W`](W) writer structure"] +impl crate::Writable for ANA_CONF0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONF0 to value 0"] +impl crate::Resettable for ANA_CONF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/ana_conf1.rs b/esp32h2/src/lp_i2c_ana_mst/ana_conf1.rs new file mode 100644 index 000000000..a70158a11 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/ana_conf1.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ANA_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `BIAS_RD` reader - ?"] +pub type BIAS_RD_R = crate::BitReader; +#[doc = "Field `BIAS_RD` writer - ?"] +pub type BIAS_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_RD` reader - ?"] +pub type BBPLL_RD_R = crate::BitReader; +#[doc = "Field `BBPLL_RD` writer - ?"] +pub type BBPLL_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_CAL_RD` reader - ?"] +pub type ULP_CAL_RD_R = crate::BitReader; +#[doc = "Field `ULP_CAL_RD` writer - ?"] +pub type ULP_CAL_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_I2C_RD` reader - ?"] +pub type SAR_I2C_RD_R = crate::BitReader; +#[doc = "Field `SAR_I2C_RD` writer - ?"] +pub type SAR_I2C_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIG_REG_RD` reader - ?"] +pub type DIG_REG_RD_R = crate::BitReader; +#[doc = "Field `DIG_REG_RD` writer - ?"] +pub type DIG_REG_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_PD` reader - Clear to enable BBPLL"] +pub type BBPLL_PD_R = crate::BitReader; +#[doc = "Field `BBPLL_PD` writer - Clear to enable BBPLL"] +pub type BBPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STATUS` reader - ?"] +pub type STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bit 6 - ?"] + #[inline(always)] + pub fn bias_rd(&self) -> BIAS_RD_R { + BIAS_RD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - ?"] + #[inline(always)] + pub fn bbpll_rd(&self) -> BBPLL_RD_R { + BBPLL_RD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - ?"] + #[inline(always)] + pub fn ulp_cal_rd(&self) -> ULP_CAL_RD_R { + ULP_CAL_RD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - ?"] + #[inline(always)] + pub fn sar_i2c_rd(&self) -> SAR_I2C_RD_R { + SAR_I2C_RD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - ?"] + #[inline(always)] + pub fn dig_reg_rd(&self) -> DIG_REG_RD_R { + DIG_REG_RD_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&self) -> BBPLL_PD_R { + BBPLL_PD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 24:31 - ?"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF1") + .field("bias_rd", &self.bias_rd()) + .field("bbpll_rd", &self.bbpll_rd()) + .field("ulp_cal_rd", &self.ulp_cal_rd()) + .field("sar_i2c_rd", &self.sar_i2c_rd()) + .field("dig_reg_rd", &self.dig_reg_rd()) + .field("bbpll_pd", &self.bbpll_pd()) + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .field("status", &self.status()) + .finish() + } +} +impl W { + #[doc = "Bit 6 - ?"] + #[inline(always)] + pub fn bias_rd(&mut self) -> BIAS_RD_W { + BIAS_RD_W::new(self, 6) + } + #[doc = "Bit 7 - ?"] + #[inline(always)] + pub fn bbpll_rd(&mut self) -> BBPLL_RD_W { + BBPLL_RD_W::new(self, 7) + } + #[doc = "Bit 8 - ?"] + #[inline(always)] + pub fn ulp_cal_rd(&mut self) -> ULP_CAL_RD_W { + ULP_CAL_RD_W::new(self, 8) + } + #[doc = "Bit 9 - ?"] + #[inline(always)] + pub fn sar_i2c_rd(&mut self) -> SAR_I2C_RD_W { + SAR_I2C_RD_W::new(self, 9) + } + #[doc = "Bit 10 - ?"] + #[inline(always)] + pub fn dig_reg_rd(&mut self) -> DIG_REG_RD_W { + DIG_REG_RD_W::new(self, 10) + } + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 17 - Clear to enable BBPLL"] + #[inline(always)] + pub fn bbpll_pd(&mut self) -> BBPLL_PD_W { + BBPLL_PD_W::new(self, 17) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONF1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF1_SPEC; +impl crate::RegisterSpec for ANA_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf1::R`](R) reader structure"] +impl crate::Readable for ANA_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf1::W`](W) writer structure"] +impl crate::Writable for ANA_CONF1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONF1 to value 0"] +impl crate::Resettable for ANA_CONF1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/ana_conf2.rs b/esp32h2/src/lp_i2c_ana_mst/ana_conf2.rs new file mode 100644 index 000000000..1d62df20a --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/ana_conf2.rs @@ -0,0 +1,145 @@ +#[doc = "Register `ANA_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `BIAS_MST_SEL` reader - ?"] +pub type BIAS_MST_SEL_R = crate::BitReader; +#[doc = "Field `BIAS_MST_SEL` writer - ?"] +pub type BIAS_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_MST_SEL` reader - ?"] +pub type BBPLL_MST_SEL_R = crate::BitReader; +#[doc = "Field `BBPLL_MST_SEL` writer - ?"] +pub type BBPLL_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_CAL_MST_SEL` reader - ?"] +pub type ULP_CAL_MST_SEL_R = crate::BitReader; +#[doc = "Field `ULP_CAL_MST_SEL` writer - ?"] +pub type ULP_CAL_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_I2C_MST_SEL` reader - ?"] +pub type SAR_I2C_MST_SEL_R = crate::BitReader; +#[doc = "Field `SAR_I2C_MST_SEL` writer - ?"] +pub type SAR_I2C_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIG_REG_MST_SEL` reader - ?"] +pub type DIG_REG_MST_SEL_R = crate::BitReader; +#[doc = "Field `DIG_REG_MST_SEL` writer - ?"] +pub type DIG_REG_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PU` reader - ?"] +pub type SAR_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PU` writer - ?"] +pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_FORCE_PD` reader - ?"] +pub type SAR_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SAR_FORCE_PD` writer - ?"] +pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STATUS` reader - ?"] +pub type STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bit 8 - ?"] + #[inline(always)] + pub fn bias_mst_sel(&self) -> BIAS_MST_SEL_R { + BIAS_MST_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - ?"] + #[inline(always)] + pub fn bbpll_mst_sel(&self) -> BBPLL_MST_SEL_R { + BBPLL_MST_SEL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - ?"] + #[inline(always)] + pub fn ulp_cal_mst_sel(&self) -> ULP_CAL_MST_SEL_R { + ULP_CAL_MST_SEL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - ?"] + #[inline(always)] + pub fn sar_i2c_mst_sel(&self) -> SAR_I2C_MST_SEL_R { + SAR_I2C_MST_SEL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - ?"] + #[inline(always)] + pub fn dig_reg_mst_sel(&self) -> DIG_REG_MST_SEL_R { + DIG_REG_MST_SEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R { + SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R { + SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 24:31 - ?"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF2") + .field("bias_mst_sel", &self.bias_mst_sel()) + .field("bbpll_mst_sel", &self.bbpll_mst_sel()) + .field("ulp_cal_mst_sel", &self.ulp_cal_mst_sel()) + .field("sar_i2c_mst_sel", &self.sar_i2c_mst_sel()) + .field("dig_reg_mst_sel", &self.dig_reg_mst_sel()) + .field("sar_force_pd", &self.sar_force_pd()) + .field("sar_force_pu", &self.sar_force_pu()) + .field("status", &self.status()) + .finish() + } +} +impl W { + #[doc = "Bit 8 - ?"] + #[inline(always)] + pub fn bias_mst_sel(&mut self) -> BIAS_MST_SEL_W { + BIAS_MST_SEL_W::new(self, 8) + } + #[doc = "Bit 9 - ?"] + #[inline(always)] + pub fn bbpll_mst_sel(&mut self) -> BBPLL_MST_SEL_W { + BBPLL_MST_SEL_W::new(self, 9) + } + #[doc = "Bit 10 - ?"] + #[inline(always)] + pub fn ulp_cal_mst_sel(&mut self) -> ULP_CAL_MST_SEL_W { + ULP_CAL_MST_SEL_W::new(self, 10) + } + #[doc = "Bit 11 - ?"] + #[inline(always)] + pub fn sar_i2c_mst_sel(&mut self) -> SAR_I2C_MST_SEL_W { + SAR_I2C_MST_SEL_W::new(self, 11) + } + #[doc = "Bit 12 - ?"] + #[inline(always)] + pub fn dig_reg_mst_sel(&mut self) -> DIG_REG_MST_SEL_W { + DIG_REG_MST_SEL_W::new(self, 12) + } + #[doc = "Bit 16 - ?"] + #[inline(always)] + pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W { + SAR_FORCE_PU_W::new(self, 16) + } + #[doc = "Bit 18 - ?"] + #[inline(always)] + pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W { + SAR_FORCE_PD_W::new(self, 18) + } +} +#[doc = "ANA_CONF2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF2_SPEC; +impl crate::RegisterSpec for ANA_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf2::R`](R) reader structure"] +impl crate::Readable for ANA_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf2::W`](W) writer structure"] +impl crate::Writable for ANA_CONF2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANA_CONF2 to value 0"] +impl crate::Resettable for ANA_CONF2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/burst_conf.rs b/esp32h2/src/lp_i2c_ana_mst/burst_conf.rs new file mode 100644 index 000000000..196740ab1 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/burst_conf.rs @@ -0,0 +1,47 @@ +#[doc = "Register `BURST_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `BURST_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BURST_CTRL` reader - ?"] +pub type BURST_CTRL_R = crate::FieldReader; +#[doc = "Field `BURST_CTRL` writer - ?"] +pub type BURST_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - ?"] + #[inline(always)] + pub fn burst_ctrl(&self) -> BURST_CTRL_R { + BURST_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BURST_CONF") + .field("burst_ctrl", &self.burst_ctrl()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - ?"] + #[inline(always)] + pub fn burst_ctrl(&mut self) -> BURST_CTRL_W { + BURST_CTRL_W::new(self, 0) + } +} +#[doc = "BURST_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`burst_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burst_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BURST_CONF_SPEC; +impl crate::RegisterSpec for BURST_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`burst_conf::R`](R) reader structure"] +impl crate::Readable for BURST_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`burst_conf::W`](W) writer structure"] +impl crate::Writable for BURST_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BURST_CONF to value 0"] +impl crate::Resettable for BURST_CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/burst_status.rs b/esp32h2/src/lp_i2c_ana_mst/burst_status.rs new file mode 100644 index 000000000..575de96c3 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/burst_status.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BURST_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `BURST_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `MST_BURST_DONE` reader - ?"] +pub type MST_BURST_DONE_R = crate::BitReader; +#[doc = "Field `MST0_BURST_ERR` reader - ?"] +pub type MST0_BURST_ERR_R = crate::BitReader; +#[doc = "Field `MST1_BURST_ERR` reader - ?"] +pub type MST1_BURST_ERR_R = crate::BitReader; +#[doc = "Field `TIMEOUT_CNT` reader - ?"] +pub type TIMEOUT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - ?"] + #[inline(always)] + pub fn mst_burst_done(&self) -> MST_BURST_DONE_R { + MST_BURST_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ?"] + #[inline(always)] + pub fn mst0_burst_err(&self) -> MST0_BURST_ERR_R { + MST0_BURST_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn mst1_burst_err(&self) -> MST1_BURST_ERR_R { + MST1_BURST_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:19 - ?"] + #[inline(always)] + pub fn timeout_cnt(&self) -> TIMEOUT_CNT_R { + TIMEOUT_CNT_R::new((self.bits >> 3) & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BURST_STATUS") + .field("mst_burst_done", &self.mst_burst_done()) + .field("mst0_burst_err", &self.mst0_burst_err()) + .field("mst1_burst_err", &self.mst1_burst_err()) + .field("timeout_cnt", &self.timeout_cnt()) + .finish() + } +} +impl W {} +#[doc = "BURST_STATUS register\n\nYou can [`read`](crate::Reg::read) this register and get [`burst_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burst_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BURST_STATUS_SPEC; +impl crate::RegisterSpec for BURST_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`burst_status::R`](R) reader structure"] +impl crate::Readable for BURST_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`burst_status::W`](W) writer structure"] +impl crate::Writable for BURST_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BURST_STATUS to value 0"] +impl crate::Resettable for BURST_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/date.rs b/esp32h2/src/lp_i2c_ana_mst/date.rs new file mode 100644 index 000000000..4a0d88256 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/date.rs @@ -0,0 +1,62 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - ?"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - ?"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +#[doc = "Field `CLK_EN` reader - ?"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - ?"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:27 - ?"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } + #[doc = "Bit 28 - ?"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &self.date()) + .field("clk_en", &self.clk_en()) + .finish() + } +} +impl W { + #[doc = "Bits 0:27 - ?"] + #[inline(always)] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = "Bit 28 - ?"] + #[inline(always)] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 28) + } +} +#[doc = "DATE register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1300"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: u32 = 0x0220_1300; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs b/esp32h2/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs new file mode 100644 index 000000000..a0e2f46be --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs @@ -0,0 +1,77 @@ +#[doc = "Register `HW_I2C_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HW_I2C_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_PULSE_DUR` reader - ?"] +pub type SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `SCL_PULSE_DUR` writer - ?"] +pub type SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SDA_SIDE_GUARD` reader - ?"] +pub type SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `SDA_SIDE_GUARD` writer - ?"] +pub type SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `ARBITER_DIS` reader - ?"] +pub type ARBITER_DIS_R = crate::BitReader; +#[doc = "Field `ARBITER_DIS` writer - ?"] +pub type ARBITER_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&self) -> SCL_PULSE_DUR_R { + SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&self) -> SDA_SIDE_GUARD_R { + SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 11 - ?"] + #[inline(always)] + pub fn arbiter_dis(&self) -> ARBITER_DIS_R { + ARBITER_DIS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_I2C_CTRL") + .field("scl_pulse_dur", &self.scl_pulse_dur()) + .field("sda_side_guard", &self.sda_side_guard()) + .field("arbiter_dis", &self.arbiter_dis()) + .finish() + } +} +impl W { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&mut self) -> SCL_PULSE_DUR_W { + SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&mut self) -> SDA_SIDE_GUARD_W { + SDA_SIDE_GUARD_W::new(self, 6) + } + #[doc = "Bit 11 - ?"] + #[inline(always)] + pub fn arbiter_dis(&mut self) -> ARBITER_DIS_W { + ARBITER_DIS_W::new(self, 11) + } +} +#[doc = "HW_I2C_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_i2c_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_i2c_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_I2C_CTRL_SPEC; +impl crate::RegisterSpec for HW_I2C_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_i2c_ctrl::R`](R) reader structure"] +impl crate::Readable for HW_I2C_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hw_i2c_ctrl::W`](W) writer structure"] +impl crate::Writable for HW_I2C_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HW_I2C_CTRL to value 0x42"] +impl crate::Resettable for HW_I2C_CTRL_SPEC { + const RESET_VALUE: u32 = 0x42; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32h2/src/lp_i2c_ana_mst/i2c0_conf.rs new file mode 100644 index 000000000..4a1bbff85 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c0_conf.rs @@ -0,0 +1,70 @@ +#[doc = "Register `I2C0_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` reader - ?"] +pub type BBPLL_STOP_FORCE_HIGH_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_HIGH` writer - ?"] +pub type BBPLL_STOP_FORCE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` reader - ?"] +pub type BBPLL_STOP_FORCE_LOW_R = crate::BitReader; +#[doc = "Field `BBPLL_STOP_FORCE_LOW` writer - ?"] +pub type BBPLL_STOP_FORCE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BBPLL_CAL_DONE` reader - ?"] +pub type BBPLL_CAL_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&self) -> BBPLL_STOP_FORCE_HIGH_R { + BBPLL_STOP_FORCE_HIGH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&self) -> BBPLL_STOP_FORCE_LOW_R { + BBPLL_STOP_FORCE_LOW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 24 - ?"] + #[inline(always)] + pub fn bbpll_cal_done(&self) -> BBPLL_CAL_DONE_R { + BBPLL_CAL_DONE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CONF") + .field("bbpll_stop_force_high", &self.bbpll_stop_force_high()) + .field("bbpll_stop_force_low", &self.bbpll_stop_force_low()) + .field("bbpll_cal_done", &self.bbpll_cal_done()) + .finish() + } +} +impl W { + #[doc = "Bit 2 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_high(&mut self) -> BBPLL_STOP_FORCE_HIGH_W { + BBPLL_STOP_FORCE_HIGH_W::new(self, 2) + } + #[doc = "Bit 3 - ?"] + #[inline(always)] + pub fn bbpll_stop_force_low(&mut self) -> BBPLL_STOP_FORCE_LOW_W { + BBPLL_STOP_FORCE_LOW_W::new(self, 3) + } +} +#[doc = "I2C0_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CONF_SPEC; +impl crate::RegisterSpec for I2C0_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_conf::R`](R) reader structure"] +impl crate::Readable for I2C0_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_conf::W`](W) writer structure"] +impl crate::Writable for I2C0_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0_CONF to value 0"] +impl crate::Resettable for I2C0_CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl.rs b/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl.rs new file mode 100644 index 000000000..0a848d997 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl.rs @@ -0,0 +1,55 @@ +#[doc = "Register `I2C0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CTRL` reader - ?"] +pub type CTRL_R = crate::FieldReader; +#[doc = "Field `CTRL` writer - ?"] +pub type CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[doc = "Field `BUSY` reader - ?"] +pub type BUSY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:24 - ?"] + #[inline(always)] + pub fn ctrl(&self) -> CTRL_R { + CTRL_R::new(self.bits & 0x01ff_ffff) + } + #[doc = "Bit 25 - ?"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CTRL") + .field("ctrl", &self.ctrl()) + .field("busy", &self.busy()) + .finish() + } +} +impl W { + #[doc = "Bits 0:24 - ?"] + #[inline(always)] + pub fn ctrl(&mut self) -> CTRL_W { + CTRL_W::new(self, 0) + } +} +#[doc = "I2C0_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CTRL_SPEC; +impl crate::RegisterSpec for I2C0_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_ctrl::R`](R) reader structure"] +impl crate::Readable for I2C0_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_ctrl::W`](W) writer structure"] +impl crate::Writable for I2C0_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0_CTRL to value 0"] +impl crate::Resettable for I2C0_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl1.rs b/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl1.rs new file mode 100644 index 000000000..b1f1f5532 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c0_ctrl1.rs @@ -0,0 +1,62 @@ +#[doc = "Register `I2C0_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_PULSE_DUR` reader - ?"] +pub type SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `SCL_PULSE_DUR` writer - ?"] +pub type SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SDA_SIDE_GUARD` reader - ?"] +pub type SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `SDA_SIDE_GUARD` writer - ?"] +pub type SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&self) -> SCL_PULSE_DUR_R { + SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&self) -> SDA_SIDE_GUARD_R { + SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CTRL1") + .field("scl_pulse_dur", &self.scl_pulse_dur()) + .field("sda_side_guard", &self.sda_side_guard()) + .finish() + } +} +impl W { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&mut self) -> SCL_PULSE_DUR_W { + SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&mut self) -> SDA_SIDE_GUARD_W { + SDA_SIDE_GUARD_W::new(self, 6) + } +} +#[doc = "I2C0_CTRL1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CTRL1_SPEC; +impl crate::RegisterSpec for I2C0_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_ctrl1::R`](R) reader structure"] +impl crate::Readable for I2C0_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_ctrl1::W`](W) writer structure"] +impl crate::Writable for I2C0_CTRL1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0_CTRL1 to value 0x42"] +impl crate::Resettable for I2C0_CTRL1_SPEC { + const RESET_VALUE: u32 = 0x42; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c1_conf.rs b/esp32h2/src/lp_i2c_ana_mst/i2c1_conf.rs new file mode 100644 index 000000000..4b4fed668 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c1_conf.rs @@ -0,0 +1,55 @@ +#[doc = "Register `I2C1_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CONF` reader - ?"] +pub type CONF_R = crate::FieldReader; +#[doc = "Field `CONF` writer - ?"] +pub type CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `STATUS` reader - ?"] +pub type STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - ?"] + #[inline(always)] + pub fn conf(&self) -> CONF_R { + CONF_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - ?"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CONF") + .field("conf", &self.conf()) + .field("status", &self.status()) + .finish() + } +} +impl W { + #[doc = "Bits 0:23 - ?"] + #[inline(always)] + pub fn conf(&mut self) -> CONF_W { + CONF_W::new(self, 0) + } +} +#[doc = "I2C1_CONF register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CONF_SPEC; +impl crate::RegisterSpec for I2C1_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_conf::R`](R) reader structure"] +impl crate::Readable for I2C1_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_conf::W`](W) writer structure"] +impl crate::Writable for I2C1_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C1_CONF to value 0"] +impl crate::Resettable for I2C1_CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl.rs b/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl.rs new file mode 100644 index 000000000..c2a685c01 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl.rs @@ -0,0 +1,55 @@ +#[doc = "Register `I2C1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CTRL` reader - ?"] +pub type CTRL_R = crate::FieldReader; +#[doc = "Field `CTRL` writer - ?"] +pub type CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[doc = "Field `BUSY` reader - ?"] +pub type BUSY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:24 - ?"] + #[inline(always)] + pub fn ctrl(&self) -> CTRL_R { + CTRL_R::new(self.bits & 0x01ff_ffff) + } + #[doc = "Bit 25 - ?"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CTRL") + .field("ctrl", &self.ctrl()) + .field("busy", &self.busy()) + .finish() + } +} +impl W { + #[doc = "Bits 0:24 - ?"] + #[inline(always)] + pub fn ctrl(&mut self) -> CTRL_W { + CTRL_W::new(self, 0) + } +} +#[doc = "I2C1_CTRL register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CTRL_SPEC; +impl crate::RegisterSpec for I2C1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_ctrl::R`](R) reader structure"] +impl crate::Readable for I2C1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_ctrl::W`](W) writer structure"] +impl crate::Writable for I2C1_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C1_CTRL to value 0"] +impl crate::Resettable for I2C1_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl1.rs b/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl1.rs new file mode 100644 index 000000000..447da1d4f --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/i2c1_ctrl1.rs @@ -0,0 +1,62 @@ +#[doc = "Register `I2C1_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_PULSE_DUR` reader - ?"] +pub type SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `SCL_PULSE_DUR` writer - ?"] +pub type SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SDA_SIDE_GUARD` reader - ?"] +pub type SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `SDA_SIDE_GUARD` writer - ?"] +pub type SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&self) -> SCL_PULSE_DUR_R { + SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&self) -> SDA_SIDE_GUARD_R { + SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CTRL1") + .field("scl_pulse_dur", &self.scl_pulse_dur()) + .field("sda_side_guard", &self.sda_side_guard()) + .finish() + } +} +impl W { + #[doc = "Bits 0:5 - ?"] + #[inline(always)] + pub fn scl_pulse_dur(&mut self) -> SCL_PULSE_DUR_W { + SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - ?"] + #[inline(always)] + pub fn sda_side_guard(&mut self) -> SDA_SIDE_GUARD_W { + SDA_SIDE_GUARD_W::new(self, 6) + } +} +#[doc = "I2C1_CTRL1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CTRL1_SPEC; +impl crate::RegisterSpec for I2C1_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_ctrl1::R`](R) reader structure"] +impl crate::Readable for I2C1_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_ctrl1::W`](W) writer structure"] +impl crate::Writable for I2C1_CTRL1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C1_CTRL1 to value 0x42"] +impl crate::Resettable for I2C1_CTRL1_SPEC { + const RESET_VALUE: u32 = 0x42; +} diff --git a/esp32h2/src/lp_i2c_ana_mst/nouse.rs b/esp32h2/src/lp_i2c_ana_mst/nouse.rs new file mode 100644 index 000000000..71a7f18b7 --- /dev/null +++ b/esp32h2/src/lp_i2c_ana_mst/nouse.rs @@ -0,0 +1,47 @@ +#[doc = "Register `NOUSE` reader"] +pub type R = crate::R; +#[doc = "Register `NOUSE` writer"] +pub type W = crate::W; +#[doc = "Field `NOUSE` reader - ?"] +pub type NOUSE_R = crate::FieldReader; +#[doc = "Field `NOUSE` writer - ?"] +pub type NOUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - ?"] + #[inline(always)] + pub fn nouse(&self) -> NOUSE_R { + NOUSE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NOUSE") + .field("nouse", &self.nouse()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - ?"] + #[inline(always)] + pub fn nouse(&mut self) -> NOUSE_W { + NOUSE_W::new(self, 0) + } +} +#[doc = "NOUSE register\n\nYou can [`read`](crate::Reg::read) this register and get [`nouse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nouse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NOUSE_SPEC; +impl crate::RegisterSpec for NOUSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nouse::R`](R) reader structure"] +impl crate::Readable for NOUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nouse::W`](W) writer structure"] +impl crate::Writable for NOUSE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NOUSE to value 0"] +impl crate::Resettable for NOUSE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml index 24636b30f..672e09544 100644 --- a/esp32h2/svd/patches/esp32h2.yaml +++ b/esp32h2/svd/patches/esp32h2.yaml @@ -292,6 +292,325 @@ _add: bitOffset: 0 bitWidth: 32 access: read-write + LP_I2C_ANA_MST: + description: LP_I2C_ANA_MST Peripheral + baseAddress: 0x600AD800 + addressBlock: + - offset: 0x0 + size: 0x38 + usage: "Registers" + registers: + I2C0_CTRL: + description: "I2C0_CTRL register" + addressOffset: 0x0 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0 + CTRL: + description: "?" + bitOffset: 0 + bitWidth: 25 + # I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0 + BUSY: + description: "?" + bitOffset: 25 + bitWidth: 1 + access: read-only + I2C1_CTRL: + description: "I2C1_CTRL register" + addressOffset: 0x4 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0 + CTRL: + description: "?" + bitOffset: 0 + bitWidth: 25 + # I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0 + BUSY: + description: "?" + bitOffset: 25 + bitWidth: 1 + access: read-only + I2C0_CONF: + description: "I2C0_CONF register" + addressOffset: 0x8 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0 + BBPLL_STOP_FORCE_HIGH: + description: "?" + bitOffset: 2 + bitWidth: 1 + BBPLL_STOP_FORCE_LOW: + description: "?" + bitOffset: 3 + bitWidth: 1 + # I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0 + BBPLL_CAL_DONE: + description: "?" + bitOffset: 24 + bitWidth: 1 + access: read-only + I2C1_CONF: + description: "I2C1_CONF register" + addressOffset: 0xC + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0 + CONF: + description: "?" + bitOffset: 0 + bitWidth: 24 + # I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0 + STATUS: + description: "?" + bitOffset: 24 + bitWidth: 8 + access: read-only + BURST_CONF: + description: "BURST_CONF register" + addressOffset: 0x10 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0 + BURST_CTRL: + description: "?" + bitOffset: 0 + bitWidth: 32 + BURST_STATUS: + description: "BURST_STATUS register" + addressOffset: 0x14 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0 + MST_BURST_DONE: + description: "?" + bitOffset: 0 + bitWidth: 1 + access: read-only + # I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0 + MST0_BURST_ERR: + description: "?" + bitOffset: 1 + bitWidth: 1 + access: read-only + # I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0 + MST1_BURST_ERR: + description: "?" + bitOffset: 2 + bitWidth: 1 + access: read-only + # I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0 + TIMEOUT_CNT: + description: "?" + bitOffset: 3 + bitWidth: 17 + access: read-only + ANA_CONF0: + description: "ANA_CONF0 register" + addressOffset: 0x18 + size: 32 + access: read-write + resetValue: 0 + fields: + # I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0 + CONFIG: + description: "?" + bitOffset: 0 + bitWidth: 24 + # I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0 + STATUS: + description: "?" + bitOffset: 24 + bitWidth: 8 + access: read-only + ANA_CONF1: + description: "ANA_CONF1 register" + addressOffset: 0x1C + size: 32 + access: read-write + resetValue: 0 + fields: + # I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0 + BIAS_RD: + description: "?" + bitOffset: 6 + bitWidth: 1 + BBPLL_RD: + description: "?" + bitOffset: 7 + bitWidth: 1 + ULP_CAL_RD: + description: "?" + bitOffset: 8 + bitWidth: 1 + SAR_I2C_RD: + description: "?" + bitOffset: 9 + bitWidth: 1 + DIG_REG_RD: + description: "?" + bitOffset: 10 + bitWidth: 1 + BBPLL_PD: + description: "Clear to enable BBPLL" + bitOffset: 17 + bitWidth: 1 + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 + # I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0 + STATUS: + description: "?" + bitOffset: 24 + bitWidth: 8 + access: read-only + ANA_CONF2: + description: "ANA_CONF2 register" + addressOffset: 0x20 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0 + BIAS_MST_SEL: + description: "?" + bitOffset: 8 + bitWidth: 1 + BBPLL_MST_SEL: + description: "?" + bitOffset: 9 + bitWidth: 1 + ULP_CAL_MST_SEL: + description: "?" + bitOffset: 10 + bitWidth: 1 + SAR_I2C_MST_SEL: + description: "?" + bitOffset: 11 + bitWidth: 1 + DIG_REG_MST_SEL: + description: "?" + bitOffset: 12 + bitWidth: 1 + SAR_FORCE_PD: + description: "?" + bitOffset: 18 + bitWidth: 1 + SAR_FORCE_PU: + description: "?" + bitOffset: 16 + bitWidth: 1 + # I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0 + STATUS: + description: "?" + bitOffset: 24 + bitWidth: 8 + access: read-only + I2C0_CTRL1: + description: "I2C0_CTRL1 register" + addressOffset: 0x24 + size: 32 + access: read-write + resetValue: 0x42 + fields: + # I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2 + SCL_PULSE_DUR: + description: "?" + bitOffset: 0 + bitWidth: 6 + # I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1 + SDA_SIDE_GUARD: + description: "?" + bitOffset: 6 + bitWidth: 5 + I2C1_CTRL1: + description: "I2C1_CTRL1 register" + addressOffset: 0x28 + size: 32 + access: read-write + resetValue: 0x42 + fields: + # I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2 + SCL_PULSE_DUR: + description: "?" + bitOffset: 0 + bitWidth: 6 + # I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1 + SDA_SIDE_GUARD: + description: "?" + bitOffset: 6 + bitWidth: 5 + HW_I2C_CTRL: + description: "HW_I2C_CTRL register" + addressOffset: 0x2C + size: 32 + access: read-write + resetValue: 0x42 + fields: + # I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2 + SCL_PULSE_DUR: + description: "?" + bitOffset: 0 + bitWidth: 6 + # I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1 + SDA_SIDE_GUARD: + description: "?" + bitOffset: 6 + bitWidth: 5 + # I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0 + ARBITER_DIS: + description: "?" + bitOffset: 11 + bitWidth: 1 + NOUSE: + description: "NOUSE register" + addressOffset: 0x30 + size: 32 + access: read-write + resetValue: 0x00 + fields: + # I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0 + NOUSE: + description: "?" + bitOffset: 0 + bitWidth: 32 + DATE: + description: "DATE register" + addressOffset: 0x34 + size: 32 + access: read-write + resetValue: 0x02201300 + fields: + # I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448 + DATE: + description: "?" + bitOffset: 0 + bitWidth: 28 + # I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0 + CLK_EN: + description: "?" + bitOffset: 28 + bitWidth: 1 + _modify: IEEE802154: