diff --git a/Cargo.lock b/Cargo.lock
index 169c4d9f3f..68b468211f 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -1,6 +1,6 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4
 
 [[package]]
 name = "ahash"
@@ -23,17 +23,11 @@ dependencies = [
  "memchr",
 ]
 
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-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5c6cb57a04249c6480766f7f7cef5467412af1490f8d1e243141daddada3264f"
-
 [[package]]
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-version = "0.6.15"
+version = "0.6.18"
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-checksum = "64e15c1ab1f89faffbf04a634d5e1962e9074f2741eef6d97f3c4e322426d526"
+checksum = "8acc5369981196006228e28809f761875c0327210a891e941f4c683b3a99529b"
 dependencies = [
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@@ -46,43 +40,43 @@ dependencies = [
 
 [[package]]
 name = "anstyle"
-version = "1.0.8"
+version = "1.0.10"
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-checksum = "1bec1de6f59aedf83baf9ff929c98f2ad654b97c9510f4e70cf6f661d49fd5b1"
+checksum = "55cc3b69f167a1ef2e161439aa98aed94e6028e5f9a59be9a6ffb47aef1651f9"
 
 [[package]]
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-version = "0.2.5"
+version = "0.2.6"
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-checksum = "eb47de1e80c2b463c735db5b217a0ddc39d612e7ac9e2e96a5aed1f57616c1cb"
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 dependencies = [
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 ]
 
 [[package]]
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+checksum = "79947af37f4177cfead1110013d678905c37501914fba0efea834c3fe9a8d60c"
 dependencies = [
- "windows-sys 0.52.0",
+ "windows-sys 0.59.0",
 ]
 
 [[package]]
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+version = "3.0.6"
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+checksum = "2109dbce0e72be3ec00bed26e6a7479ca384ad226efdd66db8fa2e3a38c83125"
 dependencies = [
  "anstyle",
- "windows-sys 0.52.0",
+ "windows-sys 0.59.0",
 ]
 
 [[package]]
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+version = "1.0.92"
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-checksum = "b3d1d046238990b9cf5bcde22a3fb3584ee5cf65fb2765f454ed428c7a0063da"
+checksum = "74f37166d7d48a0284b99dd824694c26119c700b53bf0d1540cdb147dbdaaf13"
 
 [[package]]
 name = "anymap2"
@@ -98,9 +92,9 @@ checksum = "7d902e3d592a523def97af8f317b08ce16b7ab854c1985a0c671e6f15cebc236"
 
 [[package]]
 name = "autocfg"
-version = "1.3.0"
+version = "1.4.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0c4b4d0bd25bd0b74681c0ad21497610ce1b7c91b1022cd21c80c6fbdd9476b0"
+checksum = "ace50bade8e6234aa140d9a2f552bbee1db4d353f69b8217bc503490fc1a9f26"
 
 [[package]]
 name = "block-buffer"
@@ -129,9 +123,9 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "clap"
-version = "4.5.16"
+version = "4.5.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ed6719fffa43d0d87e5fd8caeab59be1554fb028cd30edc88fc4369b17971019"
+checksum = "b97f376d85a664d5837dbae44bf546e6477a679ff6610010f17276f686d867e8"
 dependencies = [
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  "clap_derive",
@@ -139,9 +133,9 @@ dependencies = [
 
 [[package]]
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-version = "4.5.15"
+version = "4.5.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "216aec2b177652e3846684cbfe25c9964d18ec45234f0f5da5157b207ed1aab6"
+checksum = "19bc80abd44e4bed93ca373a0704ccbd1b710dc5749406201bb018272808dc54"
 dependencies = [
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  "anstyle",
@@ -151,9 +145,9 @@ dependencies = [
 
 [[package]]
 name = "clap_derive"
-version = "4.5.13"
+version = "4.5.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "4ac6a0c7b1a9e9a5186361f67dfa1b88213572f427fb9ab038efb2bd8c582dab"
 dependencies = [
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@@ -169,9 +163,9 @@ checksum = "1462739cb27611015575c0c11df5df7601141071f07518d56fcc1be504cbec97"
 
 [[package]]
 name = "colorchoice"
-version = "1.0.2"
+version = "1.0.3"
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-checksum = "d3fd119d74b830634cea2a0f58bbd0d54540518a14397557951e79340abc28c0"
+checksum = "5b63caa9aa9397e2d9480a9b13673856c78d8ac123288526c37d7839f2a86990"
 
 [[package]]
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@@ -190,9 +184,9 @@ dependencies = [
 
 [[package]]
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-version = "0.2.13"
+version = "0.2.14"
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-checksum = "51e852e6dc9a5bed1fae92dd2375037bf2b768725bf3be87811edee3249d09ad"
+checksum = "608697df725056feaccfa42cffdaeeec3fccc4ffc38358ecd19b243e716a78e0"
 dependencies = [
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 ]
@@ -251,6 +245,17 @@ dependencies = [
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+version = "0.2.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "97369cbbc041bc366949bc74d34658d6cda5621039731c6310521892a3a20ae0"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "doc-comment"
 version = "0.3.3"
@@ -265,9 +270,9 @@ checksum = "60b1af1c220855b6ceac025d3f6ecdd2b7c4894bfe9cd9bda4fbb4bc7c0d4cf0"
 
 [[package]]
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-version = "0.8.34"
+version = "0.8.35"
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-checksum = "b45de904aa0b010bce2ab45264d0631681847fa7b6f2eaa7dab7619943bc4f59"
+checksum = "75030f3c4f45dafd7586dd6780965a8c7e8e285a5ecb86713e63a79c5b2766f3"
 dependencies = [
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 ]
@@ -360,9 +365,9 @@ dependencies = [
 
 [[package]]
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-version = "0.4.14"
+version = "0.4.15"
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-checksum = "57da3b9b5b85bd66f31093f8c408b90a74431672542466497dcbdfdc02034be1"
+checksum = "15f1ce686646e7f1e19bf7d5533fe443a45dbfb990e00629110797578b42fb19"
 dependencies = [
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  "bstr",
@@ -384,14 +389,19 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1"
 dependencies = [
  "ahash",
- "allocator-api2",
 ]
 
+[[package]]
+name = "hashbrown"
+version = "0.15.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3a9bfc1af68b1726ea47d3d5109de126281def866b33970e10fbab11b5dafab3"
+
 [[package]]
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-version = "0.8.4"
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-checksum = "e8094feaf31ff591f651a2664fb9cfd92bba7a60ce3197265e9482ebe753c8f7"
+checksum = "6ba4ff7128dee98c7dc9794b6a411377e1404dba1c97deb8d1a55297bd25d8af"
 dependencies = [
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 ]
@@ -409,28 +419,148 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "fbf6a919d6cf397374f7dfeeea91d974c7c0a7221d0d0f4f20d859d329e53fcc"
 
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+checksum = "9a3a5bfb195931eeb336b2a7b4d761daec841b97f947d34394601737a7bba5e4"
+
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+checksum = "db2fa452206ebee18c4b5c2274dbf1de17008e874b4dc4f0aea9d01ca79e4526"
 dependencies = [
- "utf8-width",
+ "displaydoc",
+ "yoke",
+ "zerofrom",
+ "zerovec",
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-name = "humantime"
-version = "2.1.0"
+name = "icu_locid"
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+checksum = "13acbb8371917fc971be86fc8057c41a64b521c184808a698c02acc242dbf637"
+dependencies = [
+ "displaydoc",
+ "litemap",
+ "tinystr",
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+ "zerovec",
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+
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+dependencies = [
+ "displaydoc",
+ "icu_locid",
+ "icu_locid_transform_data",
+ "icu_provider",
+ "tinystr",
+ "zerovec",
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+
+[[package]]
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+
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+checksum = "19ce3e0da2ec68599d193c93d088142efd7f9c5d6fc9b803774855747dc6a84f"
+dependencies = [
+ "displaydoc",
+ "icu_collections",
+ "icu_normalizer_data",
+ "icu_properties",
+ "icu_provider",
+ "smallvec",
+ "utf16_iter",
+ "utf8_iter",
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+ "zerovec",
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+checksum = "93d6020766cfc6302c15dbbc9c8778c37e62c14427cb7f6e601d849e092aeef5"
+dependencies = [
+ "displaydoc",
+ "icu_collections",
+ "icu_locid_transform",
+ "icu_properties_data",
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+ "zerovec",
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+
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+dependencies = [
+ "displaydoc",
+ "icu_locid",
+ "icu_provider_macros",
+ "stable_deref_trait",
+ "tinystr",
+ "writeable",
+ "yoke",
+ "zerofrom",
+ "zerovec",
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+
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 dependencies = [
- "unicode-bidi",
- "unicode-normalization",
+ "idna_adapter",
+ "smallvec",
+ "utf8_iter",
+]
+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "daca1df1c957320b2cf139ac61e7bd64fed304c5040df000a745aa1de3b4ef71"
+dependencies = [
+ "icu_normalizer",
+ "icu_properties",
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 [[package]]
@@ -445,12 +575,12 @@ dependencies = [
 
 [[package]]
 name = "indexmap"
-version = "2.4.0"
+version = "2.6.0"
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+checksum = "707907fe3c25f5424cce2cb7e1cbcafee6bdbe735ca90ef77c29e84591e5b9da"
 dependencies = [
  "equivalent",
- "hashbrown 0.14.5",
+ "hashbrown 0.15.1",
 ]
 
 [[package]]
@@ -503,9 +633,9 @@ dependencies = [
 
 [[package]]
 name = "libc"
-version = "0.2.158"
+version = "0.2.161"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d8adc4bb1803a324070e64a98ae98f38934d91957a99cfb3a43dcbc01bc56439"
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 [[package]]
 name = "linked-hash-map"
@@ -570,6 +700,12 @@ dependencies = [
  "unicode-segmentation",
 ]
 
+[[package]]
+name = "litemap"
+version = "0.7.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "643cb0b8d4fcc284004d5fd0d67ccf61dfffadb7f75e1e71bc420f4688a3a704"
+
 [[package]]
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@@ -608,9 +744,9 @@ dependencies = [
 
 [[package]]
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-version = "1.19.0"
+version = "1.20.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92"
+checksum = "1261fe7e33c73b354eab43b1273a57c8f967d0391e80353e51f764ac02cf6775"
 
 [[package]]
 name = "percent-encoding"
@@ -620,9 +756,9 @@ checksum = "e3148f5046208a5d56bcfc03053e3ca6334e51da8dfb19b6cdc8b306fae3283e"
 
 [[package]]
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-version = "2.7.11"
+version = "2.7.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cd53dff83f26735fdc1ca837098ccf133605d794cdae66acfc2bfac3ec809d95"
+checksum = "879952a81a83930934cbf1786752d6dedc3b1f29e8f8fb2ad1d0a36f377cf442"
 dependencies = [
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@@ -631,9 +767,9 @@ dependencies = [
 
 [[package]]
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-version = "2.7.11"
+version = "2.7.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2a548d2beca6773b1c244554d36fcf8548a8a58e74156968211567250e48e49a"
+checksum = "d214365f632b123a47fd913301e14c946c61d1c183ee245fa76eb752e59a02dd"
 dependencies = [
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@@ -641,9 +777,9 @@ dependencies = [
 
 [[package]]
 name = "pest_generator"
-version = "2.7.11"
+version = "2.7.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3c93a82e8d145725dcbaf44e5ea887c8a869efdcc28706df2d08c69e17077183"
+checksum = "eb55586734301717aea2ac313f50b2eb8f60d2fc3dc01d190eefa2e625f60c4e"
 dependencies = [
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@@ -654,9 +790,9 @@ dependencies = [
 
 [[package]]
 name = "pest_meta"
-version = "2.7.11"
+version = "2.7.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a941429fea7e08bedec25e4f6785b6ffaacc6b755da98df5ef3e7dcf4a124c4f"
+checksum = "b75da2a70cf4d9cb76833c990ac9cd3923c9a8905a8929789ce347c84564d03d"
 dependencies = [
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@@ -713,9 +849,9 @@ checksum = "439ee305def115ba05938db6eb1644ff94165c5ab5e9420d1c1bcedbba909391"
 
 [[package]]
 name = "prettyplease"
-version = "0.2.22"
+version = "0.2.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "479cf940fbbb3426c32c5d5176f62ad57549a0bb84773423ba8be9d089f5faba"
+checksum = "64d1ec885c64d0457d564db4ec299b2dae3f9c02808b8ad9c3a089c591b18033"
 dependencies = [
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  "syn",
@@ -723,18 +859,18 @@ dependencies = [
 
 [[package]]
 name = "proc-macro2"
-version = "1.0.86"
+version = "1.0.89"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5e719e8df665df0d1c8fbfd238015744736151d4445ec0836b8e628aae103b77"
+checksum = "f139b0662de085916d1fb67d2b4169d1addddda1919e696f3252b740b629986e"
 dependencies = [
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 [[package]]
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-version = "0.31.0"
+version = "0.36.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1004a344b30a54e2ee58d66a71b32d2db2feb0a31f9a2d302bf0536f15de2a33"
+checksum = "f7649a7b4df05aed9ea7ec6f628c67c9953a43869b8bc50929569b2999d443fe"
 dependencies = [
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@@ -786,9 +922,9 @@ dependencies = [
 
 [[package]]
 name = "regex"
-version = "1.10.6"
+version = "1.11.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4219d74c6b67a3654a9fbebc4b419e22126d13d2f3c4a07ee0cb61ff79a79619"
+checksum = "b544ef1b4eac5dc2db33ea63606ae9ffcfac26c1416a2806ae0bf5f56b201191"
 dependencies = [
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@@ -798,9 +934,9 @@ dependencies = [
 
 [[package]]
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-version = "0.4.7"
+version = "0.4.8"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df"
+checksum = "368758f23274712b504848e9d5a6f010445cc8b87a7cdb4d7cbee666c1288da3"
 dependencies = [
  "aho-corasick",
  "memchr",
@@ -809,9 +945,9 @@ dependencies = [
 
 [[package]]
 name = "regex-syntax"
-version = "0.8.4"
+version = "0.8.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b"
+checksum = "2b15c43186be67a4fd63bee50d0303afffcef381492ebe2c5d87f324e1b8815c"
 
 [[package]]
 name = "roxmltree"
@@ -821,9 +957,9 @@ checksum = "6c20b6793b5c2fa6553b250154b78d6d0db37e72700ae35fad9387a46f487c97"
 
 [[package]]
 name = "rustversion"
-version = "1.0.17"
+version = "1.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "955d28af4278de8121b7ebeb796b6a45735dc01436d898801014aced2773a3d6"
+checksum = "0e819f2bc632f285be6d7cd36e25940d45b2391dd6d9b939e79de557f7014248"
 
 [[package]]
 name = "ryu"
@@ -839,18 +975,18 @@ checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b"
 
 [[package]]
 name = "serde"
-version = "1.0.209"
+version = "1.0.214"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "99fce0ffe7310761ca6bf9faf5115afbc19688edd00171d81b1bb1b116c63e09"
+checksum = "f55c3193aca71c12ad7890f1785d2b73e1b9f63a0bbc353c08ef26fe03fc56b5"
 dependencies = [
  "serde_derive",
 ]
 
 [[package]]
 name = "serde_derive"
-version = "1.0.209"
+version = "1.0.214"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a5831b979fd7b5439637af1752d535ff49f4860c0f341d1baeb6faf0f4242170"
+checksum = "de523f781f095e28fa605cdce0f8307e451cc0fd14e2eb4cd2e98a355b147766"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -859,11 +995,11 @@ dependencies = [
 
 [[package]]
 name = "serde_json"
-version = "1.0.127"
+version = "1.0.132"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8043c06d9f82bd7271361ed64f415fe5e12a77fdb52e573e7f06a516dea329ad"
+checksum = "d726bfaff4b320266d395898905d0eba0345aae23b54aee3a737e260fd46db03"
 dependencies = [
- "indexmap 2.4.0",
+ "indexmap 2.6.0",
  "itoa",
  "memchr",
  "ryu",
@@ -899,6 +1035,18 @@ version = "0.3.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "38b58827f4464d87d377d175e90bf58eb00fd8716ff0a62f80356b5e61555d0d"
 
+[[package]]
+name = "smallvec"
+version = "1.13.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3c5e1a9a646d36c3599cd173a41282daf47c44583ad367b8e6837255952e5c67"
+
+[[package]]
+name = "stable_deref_trait"
+version = "1.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
+
 [[package]]
 name = "static_assertions"
 version = "1.1.0"
@@ -947,9 +1095,9 @@ dependencies = [
 
 [[package]]
 name = "svd-parser"
-version = "0.14.6"
+version = "0.14.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fea184cbe4750f4016297660436b0620b3042369741397978915a462248de175"
+checksum = "39ba83b8a290ee3a180051e10a043691bb91d1b6be2053a570936fbdbec5ee2b"
 dependencies = [
  "anyhow",
  "roxmltree",
@@ -971,12 +1119,10 @@ dependencies = [
 
 [[package]]
 name = "svd2rust"
-version = "0.33.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3eaaec770e776adb2537ea92079daa8cb0c2344a24ceba776b1405b528d31bd8"
+version = "0.33.5"
+source = "git+https://github.com/bugadani/svd2rust?branch=xtensa-interrupt-number#bfe48e24926ad1444b08b8dd2cf573f6c18013d3"
 dependencies = [
  "anyhow",
- "html-escape",
  "inflections",
  "log",
  "proc-macro2",
@@ -991,9 +1137,9 @@ dependencies = [
 
 [[package]]
 name = "svdtools"
-version = "0.3.18"
+version = "0.3.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3d5bc2951ad100767b4adb74d035b385aea2f275f0e08a1a328472ac0cb40948"
+checksum = "4bb58d0555538bc9f4f298f6eb9e779e51477e8ff76b369f8691995f3d79528f"
 dependencies = [
  "anyhow",
  "clap",
@@ -1022,15 +1168,26 @@ dependencies = [
 
 [[package]]
 name = "syn"
-version = "2.0.76"
+version = "2.0.87"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "578e081a14e0cefc3279b0472138c513f37b41a08d5a3cca9b6e4e8ceb6cd525"
+checksum = "25aa4ce346d03a6dcd68dd8b4010bcb74e54e62c90c573f394c46eae99aba32d"
 dependencies = [
  "proc-macro2",
  "quote",
  "unicode-ident",
 ]
 
+[[package]]
+name = "synstructure"
+version = "0.13.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c8af7666ab7b6390ab78131fb5b0fce11d6b7a6951602017c35fa82800708971"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "termcolor"
 version = "1.4.1"
@@ -1042,18 +1199,18 @@ dependencies = [
 
 [[package]]
 name = "thiserror"
-version = "1.0.63"
+version = "1.0.68"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c0342370b38b6a11b6cc11d6a805569958d54cfa061a29969c3b5ce2ea405724"
+checksum = "02dd99dc800bbb97186339685293e1cc5d9df1f8fae2d0aecd9ff1c77efea892"
 dependencies = [
  "thiserror-impl",
 ]
 
 [[package]]
 name = "thiserror-impl"
-version = "1.0.63"
+version = "1.0.68"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a4558b58466b9ad7ca0f102865eccc95938dca1a74a856f2b57b6629050da261"
+checksum = "a7c61ec9a6f64d2793d8a45faba21efbe3ced62a886d44c36a009b2b519b4c7e"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -1092,20 +1249,15 @@ dependencies = [
 ]
 
 [[package]]
-name = "tinyvec"
-version = "1.8.0"
+name = "tinystr"
+version = "0.7.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "445e881f4f6d382d5f27c034e25eb92edd7c784ceab92a0937db7f2e9471b938"
+checksum = "9117f5d4db391c1cf6927e7bea3db74b9a1c1add8f7eda9ffd5364f40f57b82f"
 dependencies = [
- "tinyvec_macros",
+ "displaydoc",
+ "zerovec",
 ]
 
-[[package]]
-name = "tinyvec_macros"
-version = "0.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1f3ccbac311fea05f86f61904b462b55fb3df8837a366dfc601a0161d0532f20"
-
 [[package]]
 name = "toml_datetime"
 version = "0.6.8"
@@ -1114,11 +1266,11 @@ checksum = "0dd7358ecb8fc2f8d014bf86f6f638ce72ba252a2c3a2572f2a795f1d23efb41"
 
 [[package]]
 name = "toml_edit"
-version = "0.22.20"
+version = "0.22.22"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "583c44c02ad26b0c3f3066fe629275e50627026c51ac2e595cca4c230ce1ce1d"
+checksum = "4ae48d6208a266e853d946088ed816055e556cc6028c5e8e2b84d9fa5dd7c7f5"
 dependencies = [
- "indexmap 2.4.0",
+ "indexmap 2.6.0",
  "toml_datetime",
  "winnow",
 ]
@@ -1131,48 +1283,33 @@ checksum = "42ff0bf0c66b8238c6f3b578df37d0b7848e55df8577b3f74f92a69acceeb825"
 
 [[package]]
 name = "ucd-trie"
-version = "0.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ed646292ffc8188ef8ea4d1e0e0150fb15a5c2e12ad9b8fc191ae7a8a7f3c4b9"
-
-[[package]]
-name = "unicode-bidi"
-version = "0.3.15"
+version = "0.1.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "08f95100a766bf4f8f28f90d77e0a5461bbdb219042e7679bebe79004fed8d75"
+checksum = "2896d95c02a80c6d6a5d6e953d479f5ddf2dfdb6a244441010e373ac0fb88971"
 
 [[package]]
 name = "unicode-ident"
-version = "1.0.12"
+version = "1.0.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
-
-[[package]]
-name = "unicode-normalization"
-version = "0.1.23"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a56d1686db2308d901306f92a263857ef59ea39678a5458e7cb17f01415101f5"
-dependencies = [
- "tinyvec",
-]
+checksum = "e91b56cd4cadaeb79bbf1a5645f6b4f8dc5bde8834ad5894a8db35fda9efa1fe"
 
 [[package]]
 name = "unicode-segmentation"
-version = "1.11.0"
+version = "1.12.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d4c87d22b6e3f4a18d4d40ef354e97c90fcb14dd91d7dc0aa9d8a1172ebf7202"
+checksum = "f6ccf251212114b54433ec949fd6a7841275f9ada20dddd2f29e9ceea4501493"
 
 [[package]]
 name = "unicode-width"
-version = "0.1.13"
+version = "0.1.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0336d538f7abc86d282a4189614dfaa90810dfc2c6f6427eaf88e16311dd225d"
+checksum = "7dd6e30e90baa6f72411720665d41d89b9a3d039dc45b8faea1ddd07f617f6af"
 
 [[package]]
 name = "url"
-version = "2.5.2"
+version = "2.5.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "22784dbdf76fdde8af1aeda5622b546b422b6fc585325248a2bf9f5e41e94d6c"
+checksum = "8d157f1b96d14500ffdc1f10ba712e780825526c03d9a49b4d0324b0d9113ada"
 dependencies = [
  "form_urlencoded",
  "idna",
@@ -1181,10 +1318,16 @@ dependencies = [
 ]
 
 [[package]]
-name = "utf8-width"
-version = "0.1.7"
+name = "utf16_iter"
+version = "1.0.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "86bd8d4e895da8537e5315b8254664e6b769c4ff3db18321b297a1e7004392e3"
+checksum = "c8232dd3cdaed5356e0f716d285e4b40b932ac434100fe9b7e0e8e935b9e6246"
+
+[[package]]
+name = "utf8_iter"
+version = "1.0.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b6c140620e7ffbb22c2dee59cafe6084a59b5ffc27a8859a5f0d494b5d52b6be"
 
 [[package]]
 name = "utf8parse"
@@ -1291,18 +1434,30 @@ checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
 [[package]]
 name = "winnow"
-version = "0.6.18"
+version = "0.6.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "68a9bda4691f099d435ad181000724da8e5899daa10713c2d432552b9ccd3a6f"
+checksum = "36c1fec1a2bb5866f07c25f68c26e565c4c200aebb96d7e55710c19d3e8ac49b"
 dependencies = [
  "memchr",
 ]
 
+[[package]]
+name = "write16"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d1890f4022759daae28ed4fe62859b1236caebfc61ede2f63ed4e695f3f6d936"
+
+[[package]]
+name = "writeable"
+version = "0.5.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1e9df38ee2d2c3c5948ea468a8406ff0db0b29ae1ffde1bcf20ef305bcc95c51"
+
 [[package]]
 name = "xml-rs"
-version = "0.8.21"
+version = "0.8.22"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "539a77ee7c0de333dcc6da69b177380a0b81e0dacfa4f7344c465a36871ee601"
+checksum = "af4e2e2f7cba5a093896c1e150fbfe177d1883e7448200efb81d40b9d339ef26"
 
 [[package]]
 name = "xmltree"
@@ -1341,15 +1496,39 @@ dependencies = [
 
 [[package]]
 name = "yaml-rust2"
-version = "0.8.1"
+version = "0.9.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8902160c4e6f2fb145dbe9d6760a75e3c9522d8bf796ed7047c85919ac7115f8"
+checksum = "2a1a1c0bc9823338a3bdf8c61f994f23ac004c6fa32c08cd152984499b445e8d"
 dependencies = [
  "arraydeque",
  "encoding_rs",
  "hashlink",
 ]
 
+[[package]]
+name = "yoke"
+version = "0.7.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6c5b1314b079b0930c31e3af543d8ee1757b1951ae1e1565ec704403a7240ca5"
+dependencies = [
+ "serde",
+ "stable_deref_trait",
+ "yoke-derive",
+ "zerofrom",
+]
+
+[[package]]
+name = "yoke-derive"
+version = "0.7.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "28cc31741b18cb6f1d5ff12f5b7523e3d6eb0852bbbad19d73905511d9849b95"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+ "synstructure",
+]
+
 [[package]]
 name = "zerocopy"
 version = "0.7.35"
@@ -1369,3 +1548,46 @@ dependencies = [
  "quote",
  "syn",
 ]
+
+[[package]]
+name = "zerofrom"
+version = "0.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "91ec111ce797d0e0784a1116d0ddcdbea84322cd79e5d5ad173daeba4f93ab55"
+dependencies = [
+ "zerofrom-derive",
+]
+
+[[package]]
+name = "zerofrom-derive"
+version = "0.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0ea7b4a3637ea8669cedf0f1fd5c286a17f3de97b8dd5a70a6c167a1730e63a5"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+ "synstructure",
+]
+
+[[package]]
+name = "zerovec"
+version = "0.10.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "aa2b893d79df23bfb12d5461018d408ea19dfafe76c2c7ef6d4eba614f8ff079"
+dependencies = [
+ "yoke",
+ "zerofrom",
+ "zerovec-derive",
+]
+
+[[package]]
+name = "zerovec-derive"
+version = "0.10.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6eafa6dfb17584ea3e2bd6e76e0cc15ad7af12b09abdd1ca55961bed9b1063c6"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
diff --git a/Cargo.toml b/Cargo.toml
index 9a70157c43..1d04b3a499 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -14,3 +14,6 @@ exclude  = [
     "esp32s3",
     "esp32s3-ulp",
 ]
+
+[patch.crates-io]
+svd2rust   = { git = "https://github.com/bugadani/svd2rust", branch = "xtensa-interrupt-number" }
\ No newline at end of file
diff --git a/esp32/Cargo.toml b/esp32/Cargo.toml
index d3f77592e7..6ff014a6f4 100644
--- a/esp32/Cargo.toml
+++ b/esp32/Cargo.toml
@@ -30,7 +30,6 @@ test = false
 [dependencies]
 critical-section = { version = "1.1.3", optional = true }
 vcell = "0.1.3"
-xtensa-lx = "0.9.0"
 defmt = { version = "0.3.8", optional = true }
 
 [features]
diff --git a/esp32/src/aes/endian.rs b/esp32/src/aes/endian.rs
index 23d5e88de6..fcd28e0b94 100644
--- a/esp32/src/aes/endian.rs
+++ b/esp32/src/aes/endian.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Endianness selection register. See Table 22-2 for details."]
     #[inline(always)]
-    #[must_use]
     pub fn endian(&mut self) -> ENDIAN_W<ENDIAN_SPEC> {
         ENDIAN_W::new(self, 0)
     }
diff --git a/esp32/src/aes/key.rs b/esp32/src/aes/key.rs
index 065217e45f..5bf86d4902 100644
--- a/esp32/src/aes/key.rs
+++ b/esp32/src/aes/key.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - AES key material register."]
     #[inline(always)]
-    #[must_use]
     pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
         KEY_W::new(self, 0)
     }
diff --git a/esp32/src/aes/mode.rs b/esp32/src/aes/mode.rs
index 6908aa71ae..7441716129 100644
--- a/esp32/src/aes/mode.rs
+++ b/esp32/src/aes/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Selects the AES accelerator mode of operation. See Table 22-1 for details."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32/src/aes/start.rs b/esp32/src/aes/start.rs
index 7fb2583729..b2cbc2fc83 100644
--- a/esp32/src/aes/start.rs
+++ b/esp32/src/aes/start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start the AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<START_SPEC> {
         START_W::new(self, 0)
     }
diff --git a/esp32/src/aes/text.rs b/esp32/src/aes/text.rs
index c628136534..2149cd7eb1 100644
--- a/esp32/src/aes/text.rs
+++ b/esp32/src/aes/text.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Plaintext and ciphertext register."]
     #[inline(always)]
-    #[must_use]
     pub fn text(&mut self) -> TEXT_W<TEXT_SPEC> {
         TEXT_W::new(self, 0)
     }
diff --git a/esp32/src/apb_ctrl.rs b/esp32/src/apb_ctrl.rs
index e2e57d18fe..f1406ec96b 100644
--- a/esp32/src/apb_ctrl.rs
+++ b/esp32/src/apb_ctrl.rs
@@ -52,6 +52,8 @@ impl RegisterBlock {
         &self.apb_saradc_fsm
     }
     #[doc = "0x1c..0x2c - "]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `APB_SARADC_SAR1_PATT_TAB1` register.</div>"]
     #[inline(always)]
     pub const fn apb_saradc_sar1_patt_tab(&self, n: usize) -> &APB_SARADC_SAR1_PATT_TAB {
         &self.apb_saradc_sar1_patt_tab[n]
@@ -83,6 +85,8 @@ impl RegisterBlock {
         self.apb_saradc_sar1_patt_tab(3)
     }
     #[doc = "0x2c..0x3c - "]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `APB_SARADC_SAR2_PATT_TAB1` register.</div>"]
     #[inline(always)]
     pub const fn apb_saradc_sar2_patt_tab(&self, n: usize) -> &APB_SARADC_SAR2_PATT_TAB {
         &self.apb_saradc_sar2_patt_tab[n]
diff --git a/esp32/src/apb_ctrl/apb_saradc_ctrl.rs b/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
index 75fdcaa604..e661847407 100644
--- a/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_start_force(&mut self) -> SARADC_START_FORCE_W<APB_SARADC_CTRL_SPEC> {
         SARADC_START_FORCE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_start(&mut self) -> SARADC_START_W<APB_SARADC_CTRL_SPEC> {
         SARADC_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar2_mux(&mut self) -> SARADC_SAR2_MUX_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR2_MUX_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - 0: single mode 1: double mode 2: alternate mode"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_work_mode(&mut self) -> SARADC_WORK_MODE_W<APB_SARADC_CTRL_SPEC> {
         SARADC_WORK_MODE_W::new(self, 3)
     }
     #[doc = "Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar_sel(&mut self) -> SARADC_SAR_SEL_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR_SEL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar_clk_gated(&mut self) -> SARADC_SAR_CLK_GATED_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR_CLK_GATED_W::new(self, 6)
     }
     #[doc = "Bits 7:14 - SAR clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar_clk_div(&mut self) -> SARADC_SAR_CLK_DIV_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR_CLK_DIV_W::new(self, 7)
     }
     #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar1_patt_len(&mut self) -> SARADC_SAR1_PATT_LEN_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR1_PATT_LEN_W::new(self, 15)
     }
     #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar2_patt_len(&mut self) -> SARADC_SAR2_PATT_LEN_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR2_PATT_LEN_W::new(self, 19)
     }
     #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar1_patt_p_clear(&mut self) -> SARADC_SAR1_PATT_P_CLEAR_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR1_PATT_P_CLEAR_W::new(self, 23)
     }
     #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar2_patt_p_clear(&mut self) -> SARADC_SAR2_PATT_P_CLEAR_W<APB_SARADC_CTRL_SPEC> {
         SARADC_SAR2_PATT_P_CLEAR_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_data_sar_sel(&mut self) -> SARADC_DATA_SAR_SEL_W<APB_SARADC_CTRL_SPEC> {
         SARADC_DATA_SAR_SEL_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_data_to_i2s(&mut self) -> SARADC_DATA_TO_I2S_W<APB_SARADC_CTRL_SPEC> {
         SARADC_DATA_TO_I2S_W::new(self, 26)
     }
diff --git a/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs b/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
index cc6591efc3..8ceb5a250d 100644
--- a/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_meas_num_limit(&mut self) -> SARADC_MEAS_NUM_LIMIT_W<APB_SARADC_CTRL2_SPEC> {
         SARADC_MEAS_NUM_LIMIT_W::new(self, 0)
     }
     #[doc = "Bits 1:8 - max conversion number"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_max_meas_num(&mut self) -> SARADC_MAX_MEAS_NUM_W<APB_SARADC_CTRL2_SPEC> {
         SARADC_MAX_MEAS_NUM_W::new(self, 1)
     }
     #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted otherwise not"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar1_inv(&mut self) -> SARADC_SAR1_INV_W<APB_SARADC_CTRL2_SPEC> {
         SARADC_SAR1_INV_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted otherwise not"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar2_inv(&mut self) -> SARADC_SAR2_INV_W<APB_SARADC_CTRL2_SPEC> {
         SARADC_SAR2_INV_W::new(self, 10)
     }
diff --git a/esp32/src/apb_ctrl/apb_saradc_fsm.rs b/esp32/src/apb_ctrl/apb_saradc_fsm.rs
index 07106e8809..613544a160 100644
--- a/esp32/src/apb_ctrl/apb_saradc_fsm.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_fsm.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_rstb_wait(&mut self) -> SARADC_RSTB_WAIT_W<APB_SARADC_FSM_SPEC> {
         SARADC_RSTB_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_standby_wait(&mut self) -> SARADC_STANDBY_WAIT_W<APB_SARADC_FSM_SPEC> {
         SARADC_STANDBY_WAIT_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_start_wait(&mut self) -> SARADC_START_WAIT_W<APB_SARADC_FSM_SPEC> {
         SARADC_START_WAIT_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - sample cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sample_cycle(&mut self) -> SARADC_SAMPLE_CYCLE_W<APB_SARADC_FSM_SPEC> {
         SARADC_SAMPLE_CYCLE_W::new(self, 24)
     }
diff --git a/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs b/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
index b2897d6270..586ea7b1ec 100644
--- a/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar1_patt_tab1(
         &mut self,
     ) -> SARADC_SAR1_PATT_TAB1_W<APB_SARADC_SAR1_PATT_TAB_SPEC> {
diff --git a/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs b/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
index 74ea1cd30f..2fbf14f734 100644
--- a/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_sar2_patt_tab1(
         &mut self,
     ) -> SARADC_SAR2_PATT_TAB1_W<APB_SARADC_SAR2_PATT_TAB_SPEC> {
diff --git a/esp32/src/apb_ctrl/apll_tick_conf.rs b/esp32/src/apb_ctrl/apll_tick_conf.rs
index a0e147fae3..bb1ed6b4ef 100644
--- a/esp32/src/apb_ctrl/apll_tick_conf.rs
+++ b/esp32/src/apb_ctrl/apll_tick_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn apll_tick_num(&mut self) -> APLL_TICK_NUM_W<APLL_TICK_CONF_SPEC> {
         APLL_TICK_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/apb_ctrl/ck8m_tick_conf.rs b/esp32/src/apb_ctrl/ck8m_tick_conf.rs
index f720401750..74cca47899 100644
--- a/esp32/src/apb_ctrl/ck8m_tick_conf.rs
+++ b/esp32/src/apb_ctrl/ck8m_tick_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<CK8M_TICK_CONF_SPEC> {
         CK8M_TICK_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/apb_ctrl/date.rs b/esp32/src/apb_ctrl/date.rs
index 13e52e8aca..859e9515bb 100644
--- a/esp32/src/apb_ctrl/date.rs
+++ b/esp32/src/apb_ctrl/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/apb_ctrl/pll_tick_conf.rs b/esp32/src/apb_ctrl/pll_tick_conf.rs
index 12a93075e8..5db4424153 100644
--- a/esp32/src/apb_ctrl/pll_tick_conf.rs
+++ b/esp32/src/apb_ctrl/pll_tick_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_tick_num(&mut self) -> PLL_TICK_NUM_W<PLL_TICK_CONF_SPEC> {
         PLL_TICK_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/apb_ctrl/sysclk_conf.rs b/esp32/src/apb_ctrl/sysclk_conf.rs
index 683fb74fde..23b2a6eee0 100644
--- a/esp32/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32/src/apb_ctrl/sysclk_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
-    #[must_use]
     pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
         PRE_DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
         CLK_320M_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
         CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
         RST_TICK_CNT_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn quick_clk_chng(&mut self) -> QUICK_CLK_CHNG_W<SYSCLK_CONF_SPEC> {
         QUICK_CLK_CHNG_W::new(self, 13)
     }
diff --git a/esp32/src/apb_ctrl/xtal_tick_conf.rs b/esp32/src/apb_ctrl/xtal_tick_conf.rs
index 2f702cf38d..ed8bdcd55f 100644
--- a/esp32/src/apb_ctrl/xtal_tick_conf.rs
+++ b/esp32/src/apb_ctrl/xtal_tick_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<XTAL_TICK_CONF_SPEC> {
         XTAL_TICK_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/bb/bbpd_ctrl.rs b/esp32/src/bb/bbpd_ctrl.rs
index 968dce20ce..6de8322c9b 100644
--- a/esp32/src/bb/bbpd_ctrl.rs
+++ b/esp32/src/bb/bbpd_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pd(&mut self) -> DC_EST_FORCE_PD_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pu(&mut self) -> DC_EST_FORCE_PU_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pd(&mut self) -> FFT_FORCE_PD_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pu(&mut self) -> FFT_FORCE_PU_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PU_W::new(self, 3)
     }
diff --git a/esp32/src/dport/ahb_lite_mask.rs b/esp32/src/dport/ahb_lite_mask.rs
index 095b2098a8..ca0d6b0153 100644
--- a/esp32/src/dport/ahb_lite_mask.rs
+++ b/esp32/src/dport/ahb_lite_mask.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro(&mut self) -> PRO_W<AHB_LITE_MASK_SPEC> {
         PRO_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn app(&mut self) -> APP_W<AHB_LITE_MASK_SPEC> {
         APP_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio(&mut self) -> SDIO_W<AHB_LITE_MASK_SPEC> {
         SDIO_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn prodport(&mut self) -> PRODPORT_W<AHB_LITE_MASK_SPEC> {
         PRODPORT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn appdport(&mut self) -> APPDPORT_W<AHB_LITE_MASK_SPEC> {
         APPDPORT_W::new(self, 10)
     }
     #[doc = "Bits 11:13"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_lite_sdhost_pid(&mut self) -> AHB_LITE_SDHOST_PID_W<AHB_LITE_MASK_SPEC> {
         AHB_LITE_SDHOST_PID_W::new(self, 11)
     }
diff --git a/esp32/src/dport/ahb_mpu_table_0.rs b/esp32/src/dport/ahb_mpu_table_0.rs
index a2abc13d2b..293629f2fb 100644
--- a/esp32/src/dport/ahb_mpu_table_0.rs
+++ b/esp32/src/dport/ahb_mpu_table_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_access_grant_0(&mut self) -> AHB_ACCESS_GRANT_0_W<AHB_MPU_TABLE_0_SPEC> {
         AHB_ACCESS_GRANT_0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/ahb_mpu_table_1.rs b/esp32/src/dport/ahb_mpu_table_1.rs
index e03d388fce..d8ef0f565f 100644
--- a/esp32/src/dport/ahb_mpu_table_1.rs
+++ b/esp32/src/dport/ahb_mpu_table_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_access_grant_1(&mut self) -> AHB_ACCESS_GRANT_1_W<AHB_MPU_TABLE_1_SPEC> {
         AHB_ACCESS_GRANT_1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs b/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
index 789c3f646b..00f56194b4 100644
--- a/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
+++ b/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn apbctrl_access_grant_config(
         &mut self,
     ) -> APBCTRL_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_APB_CTRL_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_bb.rs b/esp32/src/dport/ahblite_mpu_table_bb.rs
index 9776f6393d..83251845b3 100644
--- a/esp32/src/dport/ahblite_mpu_table_bb.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bb.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_access_grant_config(
         &mut self,
     ) -> BB_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BB_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_bt.rs b/esp32/src/dport/ahblite_mpu_table_bt.rs
index fe9443180b..ddc59ad418 100644
--- a/esp32/src/dport/ahblite_mpu_table_bt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_access_grant_config(
         &mut self,
     ) -> BT_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BT_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs b/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
index 68d1e51b5b..b419328529 100644
--- a/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn btbuffer_access_grant_config(
         &mut self,
     ) -> BTBUFFER_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BT_BUFFER_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_btmac.rs b/esp32/src/dport/ahblite_mpu_table_btmac.rs
index d8eaed97bd..5796f086be 100644
--- a/esp32/src/dport/ahblite_mpu_table_btmac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_btmac.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn btmac_access_grant_config(
         &mut self,
     ) -> BTMAC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_BTMAC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_can.rs b/esp32/src/dport/ahblite_mpu_table_can.rs
index b4b545d5ba..dbb1df18cb 100644
--- a/esp32/src/dport/ahblite_mpu_table_can.rs
+++ b/esp32/src/dport/ahblite_mpu_table_can.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn can_access_grant_config(
         &mut self,
     ) -> CAN_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_CAN_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_efuse.rs b/esp32/src/dport/ahblite_mpu_table_efuse.rs
index fe5e5e5422..3468aba49a 100644
--- a/esp32/src/dport/ahblite_mpu_table_efuse.rs
+++ b/esp32/src/dport/ahblite_mpu_table_efuse.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_access_grant_config(
         &mut self,
     ) -> EFUSE_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_EFUSE_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_emac.rs b/esp32/src/dport/ahblite_mpu_table_emac.rs
index 0398bf9cfd..39a3d4f382 100644
--- a/esp32/src/dport/ahblite_mpu_table_emac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_emac.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn emac_access_grant_config(
         &mut self,
     ) -> EMAC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_EMAC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_fe.rs b/esp32/src/dport/ahblite_mpu_table_fe.rs
index 1e02748cc4..943044b942 100644
--- a/esp32/src/dport/ahblite_mpu_table_fe.rs
+++ b/esp32/src/dport/ahblite_mpu_table_fe.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn fe_access_grant_config(
         &mut self,
     ) -> FE_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_FE_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_fe2.rs b/esp32/src/dport/ahblite_mpu_table_fe2.rs
index 55a619d334..3f7ef4da34 100644
--- a/esp32/src/dport/ahblite_mpu_table_fe2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_fe2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn fe2_access_grant_config(
         &mut self,
     ) -> FE2_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_FE2_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_gpio.rs b/esp32/src/dport/ahblite_mpu_table_gpio.rs
index a49770695d..6da0a4d3bc 100644
--- a/esp32/src/dport/ahblite_mpu_table_gpio.rs
+++ b/esp32/src/dport/ahblite_mpu_table_gpio.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_access_grant_config(
         &mut self,
     ) -> GPIO_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_GPIO_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_hinf.rs b/esp32/src/dport/ahblite_mpu_table_hinf.rs
index 5d25aa7ac5..6a713ef320 100644
--- a/esp32/src/dport/ahblite_mpu_table_hinf.rs
+++ b/esp32/src/dport/ahblite_mpu_table_hinf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn hinf_access_grant_config(
         &mut self,
     ) -> HINF_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_HINF_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c.rs b/esp32/src/dport/ahblite_mpu_table_i2c.rs
index fa16369d40..36b95b7be7 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_access_grant_config(
         &mut self,
     ) -> I2C_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_I2C_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs b/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
index b33046f920..13e94df9a4 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2cext0_access_grant_config(
         &mut self,
     ) -> I2CEXT0_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_I2C_EXT0_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs b/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
index eb65f359aa..c7215d4649 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2cext1_access_grant_config(
         &mut self,
     ) -> I2CEXT1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_I2C_EXT1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_i2s0.rs b/esp32/src/dport/ahblite_mpu_table_i2s0.rs
index 0a81ef22cb..6f044e730f 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2s0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2s0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_access_grant_config(
         &mut self,
     ) -> I2S0_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_I2S0_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_i2s1.rs b/esp32/src/dport/ahblite_mpu_table_i2s1.rs
index 90833f8517..948468a124 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2s1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2s1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_access_grant_config(
         &mut self,
     ) -> I2S1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_I2S1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_io_mux.rs b/esp32/src/dport/ahblite_mpu_table_io_mux.rs
index cd2d4e2973..ceb09e58c8 100644
--- a/esp32/src/dport/ahblite_mpu_table_io_mux.rs
+++ b/esp32/src/dport/ahblite_mpu_table_io_mux.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn iomux_access_grant_config(
         &mut self,
     ) -> IOMUX_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_IO_MUX_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_ledc.rs b/esp32/src/dport/ahblite_mpu_table_ledc.rs
index 19ec671c0b..b926fb8b0b 100644
--- a/esp32/src/dport/ahblite_mpu_table_ledc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_ledc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_access_grant_config(
         &mut self,
     ) -> LEDC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_LEDC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_misc.rs b/esp32/src/dport/ahblite_mpu_table_misc.rs
index 416b2af0ea..0853b352cb 100644
--- a/esp32/src/dport/ahblite_mpu_table_misc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_misc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn misc_access_grant_config(
         &mut self,
     ) -> MISC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_MISC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pcnt.rs b/esp32/src/dport/ahblite_mpu_table_pcnt.rs
index b5a93d4036..7450fe7fb8 100644
--- a/esp32/src/dport/ahblite_mpu_table_pcnt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_access_grant_config(
         &mut self,
     ) -> PCNT_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PCNT_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm0.rs b/esp32/src/dport/ahblite_mpu_table_pwm0.rs
index 3f9b17fa3b..feea70ec1f 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_access_grant_config(
         &mut self,
     ) -> PWM0_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PWM0_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm1.rs b/esp32/src/dport/ahblite_mpu_table_pwm1.rs
index caa381cf46..9917e2d97a 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_access_grant_config(
         &mut self,
     ) -> PWM1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PWM1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm2.rs b/esp32/src/dport/ahblite_mpu_table_pwm2.rs
index 2d8be40dfc..0e83135cd5 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_access_grant_config(
         &mut self,
     ) -> PWM2_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PWM2_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm3.rs b/esp32/src/dport/ahblite_mpu_table_pwm3.rs
index 25bd7731b3..71aaf9e9e2 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm3.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_access_grant_config(
         &mut self,
     ) -> PWM3_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PWM3_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_pwr.rs b/esp32/src/dport/ahblite_mpu_table_pwr.rs
index 8f615e5079..9ce48ab926 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwr.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_access_grant_config(
         &mut self,
     ) -> PWR_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_PWR_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_rmt.rs b/esp32/src/dport/ahblite_mpu_table_rmt.rs
index 683faa9e76..55ba6ec219 100644
--- a/esp32/src/dport/ahblite_mpu_table_rmt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rmt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_access_grant_config(
         &mut self,
     ) -> RMT_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_RMT_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_rtc.rs b/esp32/src/dport/ahblite_mpu_table_rtc.rs
index 38a6179493..918b82e6e9 100644
--- a/esp32/src/dport/ahblite_mpu_table_rtc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rtc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_access_grant_config(
         &mut self,
     ) -> RTC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_RTC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_rwbt.rs b/esp32/src/dport/ahblite_mpu_table_rwbt.rs
index baf466363b..6f807a09e6 100644
--- a/esp32/src/dport/ahblite_mpu_table_rwbt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rwbt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn rwbt_access_grant_config(
         &mut self,
     ) -> RWBT_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_RWBT_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_sdio_host.rs b/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
index 1b2d3366ce..80c408d7b8 100644
--- a/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
+++ b/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn sdiohost_access_grant_config(
         &mut self,
     ) -> SDIOHOST_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SDIO_HOST_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_slc.rs b/esp32/src/dport/ahblite_mpu_table_slc.rs
index 68d93d7c73..f1a7207b4f 100644
--- a/esp32/src/dport/ahblite_mpu_table_slc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_slc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn slc_access_grant_config(
         &mut self,
     ) -> SLC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SLC_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_slchost.rs b/esp32/src/dport/ahblite_mpu_table_slchost.rs
index 4b17a3176e..3c159e0df0 100644
--- a/esp32/src/dport/ahblite_mpu_table_slchost.rs
+++ b/esp32/src/dport/ahblite_mpu_table_slchost.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn slchost_access_grant_config(
         &mut self,
     ) -> SLCHOST_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SLCHOST_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_spi0.rs b/esp32/src/dport/ahblite_mpu_table_spi0.rs
index 6e80e8c55d..073107699b 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi0_access_grant_config(
         &mut self,
     ) -> SPI0_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SPI0_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_spi1.rs b/esp32/src/dport/ahblite_mpu_table_spi1.rs
index b53839c8f2..4dcebab917 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi1_access_grant_config(
         &mut self,
     ) -> SPI1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SPI1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_spi2.rs b/esp32/src/dport/ahblite_mpu_table_spi2.rs
index 7959f193ee..7af6909e80 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_access_grant_config(
         &mut self,
     ) -> SPI2_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SPI2_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_spi3.rs b/esp32/src/dport/ahblite_mpu_table_spi3.rs
index 7d13b4d9f8..603b3b7e6f 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi3.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_access_grant_config(
         &mut self,
     ) -> SPI3_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SPI3_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs b/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
index 66cd17b759..614bb7236a 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_encrypy_access_grant_config(
         &mut self,
     ) -> SPI_ENCRYPY_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_timer.rs b/esp32/src/dport/ahblite_mpu_table_timer.rs
index 7c37768119..b978290fba 100644
--- a/esp32/src/dport/ahblite_mpu_table_timer.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timer.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_access_grant_config(
         &mut self,
     ) -> TIMER_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_TIMER_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_timergroup.rs b/esp32/src/dport/ahblite_mpu_table_timergroup.rs
index a9c20975f6..b49293d4c8 100644
--- a/esp32/src/dport/ahblite_mpu_table_timergroup.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timergroup.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_access_grant_config(
         &mut self,
     ) -> TIMERGROUP_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_TIMERGROUP_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_timergroup1.rs b/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
index b5ea0ae352..1d38948e6d 100644
--- a/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_access_grant_config(
         &mut self,
     ) -> TIMERGROUP1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_TIMERGROUP1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_uart.rs b/esp32/src/dport/ahblite_mpu_table_uart.rs
index a2ad4fd405..0f9cccf2ac 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_access_grant_config(
         &mut self,
     ) -> UART_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_UART_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_uart1.rs b/esp32/src/dport/ahblite_mpu_table_uart1.rs
index 76644d84ed..7caf5e6d4f 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_access_grant_config(
         &mut self,
     ) -> UART1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_UART1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_uart2.rs b/esp32/src/dport/ahblite_mpu_table_uart2.rs
index fab3a1584c..d763040f89 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart2.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_access_grant_config(
         &mut self,
     ) -> UART2_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_UART2_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_uhci0.rs b/esp32/src/dport/ahblite_mpu_table_uhci0.rs
index c328e4ffd1..e850f8582e 100644
--- a/esp32/src/dport/ahblite_mpu_table_uhci0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uhci0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_access_grant_config(
         &mut self,
     ) -> UHCI0_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_UHCI0_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_uhci1.rs b/esp32/src/dport/ahblite_mpu_table_uhci1.rs
index 7e35793acc..b6413986ed 100644
--- a/esp32/src/dport/ahblite_mpu_table_uhci1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uhci1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_access_grant_config(
         &mut self,
     ) -> UHCI1_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_UHCI1_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_wdg.rs b/esp32/src/dport/ahblite_mpu_table_wdg.rs
index ef8650ef9b..133593727c 100644
--- a/esp32/src/dport/ahblite_mpu_table_wdg.rs
+++ b/esp32/src/dport/ahblite_mpu_table_wdg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_access_grant_config(
         &mut self,
     ) -> WDG_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_WDG_SPEC> {
diff --git a/esp32/src/dport/ahblite_mpu_table_wifimac.rs b/esp32/src/dport/ahblite_mpu_table_wifimac.rs
index 9cb6dfd094..fa5281ba3e 100644
--- a/esp32/src/dport/ahblite_mpu_table_wifimac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_wifimac.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn wifimac_access_grant_config(
         &mut self,
     ) -> WIFIMAC_ACCESS_GRANT_CONFIG_W<AHBLITE_MPU_TABLE_WIFIMAC_SPEC> {
diff --git a/esp32/src/dport/app_bb_int_map.rs b/esp32/src/dport/app_bb_int_map.rs
index 99875c1b1c..2572343151 100644
--- a/esp32/src/dport/app_bb_int_map.rs
+++ b/esp32/src/dport/app_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_bb_int_map(&mut self) -> APP_BB_INT_MAP_W<APP_BB_INT_MAP_SPEC> {
         APP_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_boot_remap_ctrl.rs b/esp32/src/dport/app_boot_remap_ctrl.rs
index 324d959f1e..5f1167a6b2 100644
--- a/esp32/src/dport/app_boot_remap_ctrl.rs
+++ b/esp32/src/dport/app_boot_remap_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_boot_remap(&mut self) -> APP_BOOT_REMAP_W<APP_BOOT_REMAP_CTRL_SPEC> {
         APP_BOOT_REMAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_bt_bb_int_map.rs b/esp32/src/dport/app_bt_bb_int_map.rs
index 0d2a0137d2..ccfbbc0dcb 100644
--- a/esp32/src/dport/app_bt_bb_int_map.rs
+++ b/esp32/src/dport/app_bt_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_bt_bb_int_map(&mut self) -> APP_BT_BB_INT_MAP_W<APP_BT_BB_INT_MAP_SPEC> {
         APP_BT_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_bt_bb_nmi_map.rs b/esp32/src/dport/app_bt_bb_nmi_map.rs
index 97b6863695..2a9c8d925f 100644
--- a/esp32/src/dport/app_bt_bb_nmi_map.rs
+++ b/esp32/src/dport/app_bt_bb_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_bt_bb_nmi_map(&mut self) -> APP_BT_BB_NMI_MAP_W<APP_BT_BB_NMI_MAP_SPEC> {
         APP_BT_BB_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_bt_mac_int_map.rs b/esp32/src/dport/app_bt_mac_int_map.rs
index 1627e90675..eaa9383b20 100644
--- a/esp32/src/dport/app_bt_mac_int_map.rs
+++ b/esp32/src/dport/app_bt_mac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_bt_mac_int_map(&mut self) -> APP_BT_MAC_INT_MAP_W<APP_BT_MAC_INT_MAP_SPEC> {
         APP_BT_MAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_cache_ctrl.rs b/esp32/src/dport/app_cache_ctrl.rs
index f9c024bab4..0a1483e82d 100644
--- a/esp32/src/dport/app_cache_ctrl.rs
+++ b/esp32/src/dport/app_cache_ctrl.rs
@@ -138,61 +138,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mode(&mut self) -> APP_CACHE_MODE_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_enable(&mut self) -> APP_CACHE_ENABLE_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_ENABLE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_flush_ena(&mut self) -> APP_CACHE_FLUSH_ENA_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_FLUSH_ENA_W::new(self, 4)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_lock_0_en(&mut self) -> APP_CACHE_LOCK_0_EN_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_LOCK_0_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_lock_1_en(&mut self) -> APP_CACHE_LOCK_1_EN_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_LOCK_1_EN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_lock_2_en(&mut self) -> APP_CACHE_LOCK_2_EN_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_LOCK_2_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_lock_3_en(&mut self) -> APP_CACHE_LOCK_3_EN_W<APP_CACHE_CTRL_SPEC> {
         APP_CACHE_LOCK_3_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn app_single_iram_ena(&mut self) -> APP_SINGLE_IRAM_ENA_W<APP_CACHE_CTRL_SPEC> {
         APP_SINGLE_IRAM_ENA_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn app_dram_split(&mut self) -> APP_DRAM_SPLIT_W<APP_CACHE_CTRL_SPEC> {
         APP_DRAM_SPLIT_W::new(self, 11)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn app_dram_hl(&mut self) -> APP_DRAM_HL_W<APP_CACHE_CTRL_SPEC> {
         APP_DRAM_HL_W::new(self, 14)
     }
diff --git a/esp32/src/dport/app_cache_ctrl1.rs b/esp32/src/dport/app_cache_ctrl1.rs
index e091dc7565..8756c045b4 100644
--- a/esp32/src/dport/app_cache_ctrl1.rs
+++ b/esp32/src/dport/app_cache_ctrl1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_iram0(&mut self) -> APP_CACHE_MASK_IRAM0_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_IRAM0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_iram1(&mut self) -> APP_CACHE_MASK_IRAM1_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_IRAM1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_irom0(&mut self) -> APP_CACHE_MASK_IROM0_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_IROM0_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_dram1(&mut self) -> APP_CACHE_MASK_DRAM1_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_DRAM1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_drom0(&mut self) -> APP_CACHE_MASK_DROM0_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_DROM0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mask_opsdram(&mut self) -> APP_CACHE_MASK_OPSDRAM_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MASK_OPSDRAM_W::new(self, 5)
     }
     #[doc = "Bits 6:8"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cmmu_sram_page_mode(&mut self) -> APP_CMMU_SRAM_PAGE_MODE_W<APP_CACHE_CTRL1_SPEC> {
         APP_CMMU_SRAM_PAGE_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:10"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cmmu_flash_page_mode(&mut self) -> APP_CMMU_FLASH_PAGE_MODE_W<APP_CACHE_CTRL1_SPEC> {
         APP_CMMU_FLASH_PAGE_MODE_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cmmu_force_on(&mut self) -> APP_CMMU_FORCE_ON_W<APP_CACHE_CTRL1_SPEC> {
         APP_CMMU_FORCE_ON_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cmmu_pd(&mut self) -> APP_CMMU_PD_W<APP_CACHE_CTRL1_SPEC> {
         APP_CMMU_PD_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_mmu_ia_clr(&mut self) -> APP_CACHE_MMU_IA_CLR_W<APP_CACHE_CTRL1_SPEC> {
         APP_CACHE_MMU_IA_CLR_W::new(self, 13)
     }
diff --git a/esp32/src/dport/app_cache_ia_int_map.rs b/esp32/src/dport/app_cache_ia_int_map.rs
index 44f7b4bd66..d3bc0fa7af 100644
--- a/esp32/src/dport/app_cache_ia_int_map.rs
+++ b/esp32/src/dport/app_cache_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_ia_int_map(&mut self) -> APP_CACHE_IA_INT_MAP_W<APP_CACHE_IA_INT_MAP_SPEC> {
         APP_CACHE_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_cache_lock_0_addr.rs b/esp32/src/dport/app_cache_lock_0_addr.rs
index f3b75e4a4b..4bb51aded8 100644
--- a/esp32/src/dport/app_cache_lock_0_addr.rs
+++ b/esp32/src/dport/app_cache_lock_0_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<APP_CACHE_LOCK_0_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<APP_CACHE_LOCK_0_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<APP_CACHE_LOCK_0_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/app_cache_lock_1_addr.rs b/esp32/src/dport/app_cache_lock_1_addr.rs
index fbb59247f3..5ddadf04f7 100644
--- a/esp32/src/dport/app_cache_lock_1_addr.rs
+++ b/esp32/src/dport/app_cache_lock_1_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<APP_CACHE_LOCK_1_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<APP_CACHE_LOCK_1_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<APP_CACHE_LOCK_1_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/app_cache_lock_2_addr.rs b/esp32/src/dport/app_cache_lock_2_addr.rs
index f19c27d472..e8c115ef67 100644
--- a/esp32/src/dport/app_cache_lock_2_addr.rs
+++ b/esp32/src/dport/app_cache_lock_2_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/app_cache_lock_3_addr.rs b/esp32/src/dport/app_cache_lock_3_addr.rs
index 8a33531bc1..812a814cfb 100644
--- a/esp32/src/dport/app_cache_lock_3_addr.rs
+++ b/esp32/src/dport/app_cache_lock_3_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<APP_CACHE_LOCK_3_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<APP_CACHE_LOCK_3_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<APP_CACHE_LOCK_3_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/app_can_int_map.rs b/esp32/src/dport/app_can_int_map.rs
index d57cfc9168..f39e82115d 100644
--- a/esp32/src/dport/app_can_int_map.rs
+++ b/esp32/src/dport/app_can_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_can_int_map(&mut self) -> APP_CAN_INT_MAP_W<APP_CAN_INT_MAP_SPEC> {
         APP_CAN_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
index 0803394209..cb30b0386e 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_intr_from_cpu_0_map(
         &mut self,
     ) -> APP_CPU_INTR_FROM_CPU_0_MAP_W<APP_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
index e97e02f104..c7c3f98c8a 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_intr_from_cpu_1_map(
         &mut self,
     ) -> APP_CPU_INTR_FROM_CPU_1_MAP_W<APP_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
index 99808f0a31..4928cc72f5 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_intr_from_cpu_2_map(
         &mut self,
     ) -> APP_CPU_INTR_FROM_CPU_2_MAP_W<APP_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
index 9f232c4c8b..202c308bab 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_intr_from_cpu_3_map(
         &mut self,
     ) -> APP_CPU_INTR_FROM_CPU_3_MAP_W<APP_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
diff --git a/esp32/src/dport/app_cpu_record_ctrl.rs b/esp32/src/dport/app_cpu_record_ctrl.rs
index dde31a2d18..7a832f1dd7 100644
--- a/esp32/src/dport/app_cpu_record_ctrl.rs
+++ b/esp32/src/dport/app_cpu_record_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_record_enable(&mut self) -> APP_CPU_RECORD_ENABLE_W<APP_CPU_RECORD_CTRL_SPEC> {
         APP_CPU_RECORD_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_record_disable(&mut self) -> APP_CPU_RECORD_DISABLE_W<APP_CPU_RECORD_CTRL_SPEC> {
         APP_CPU_RECORD_DISABLE_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_pdebug_enable(&mut self) -> APP_CPU_PDEBUG_ENABLE_W<APP_CPU_RECORD_CTRL_SPEC> {
         APP_CPU_PDEBUG_ENABLE_W::new(self, 8)
     }
diff --git a/esp32/src/dport/app_dcache_dbug0.rs b/esp32/src/dport/app_dcache_dbug0.rs
index 0916328843..92053bf5bb 100644
--- a/esp32/src/dport/app_dcache_dbug0.rs
+++ b/esp32/src/dport/app_dcache_dbug0.rs
@@ -88,7 +88,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_slave_wdata(&mut self) -> APP_SLAVE_WDATA_W<APP_DCACHE_DBUG0_SPEC> {
         APP_SLAVE_WDATA_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_dcache_dbug3.rs b/esp32/src/dport/app_dcache_dbug3.rs
index e6e7fcd67c..38573a743c 100644
--- a/esp32/src/dport/app_dcache_dbug3.rs
+++ b/esp32/src/dport/app_dcache_dbug3.rs
@@ -122,7 +122,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_opposite(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_OPPOSITE_W<APP_DCACHE_DBUG3_SPEC> {
@@ -130,7 +129,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_dram1(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_DRAM1_W<APP_DCACHE_DBUG3_SPEC> {
@@ -138,7 +136,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_irom0(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_IROM0_W<APP_DCACHE_DBUG3_SPEC> {
@@ -146,7 +143,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_iram1(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_IRAM1_W<APP_DCACHE_DBUG3_SPEC> {
@@ -154,7 +150,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_iram0(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_IRAM0_W<APP_DCACHE_DBUG3_SPEC> {
@@ -162,7 +157,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cpu_disabled_cache_ia_drom0(
         &mut self,
     ) -> APP_CPU_DISABLED_CACHE_IA_DROM0_W<APP_DCACHE_DBUG3_SPEC> {
diff --git a/esp32/src/dport/app_dport_apb_mask0.rs b/esp32/src/dport/app_dport_apb_mask0.rs
index 8bf1eb3606..5605acc70b 100644
--- a/esp32/src/dport/app_dport_apb_mask0.rs
+++ b/esp32/src/dport/app_dport_apb_mask0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn appdport_apb_mask0(&mut self) -> APPDPORT_APB_MASK0_W<APP_DPORT_APB_MASK0_SPEC> {
         APPDPORT_APB_MASK0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_dport_apb_mask1.rs b/esp32/src/dport/app_dport_apb_mask1.rs
index 18adbcfc8b..7f1ea43007 100644
--- a/esp32/src/dport/app_dport_apb_mask1.rs
+++ b/esp32/src/dport/app_dport_apb_mask1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn appdport_apb_mask1(&mut self) -> APPDPORT_APB_MASK1_W<APP_DPORT_APB_MASK1_SPEC> {
         APPDPORT_APB_MASK1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_efuse_int_map.rs b/esp32/src/dport/app_efuse_int_map.rs
index abb98ffb8f..9a965bdf57 100644
--- a/esp32/src/dport/app_efuse_int_map.rs
+++ b/esp32/src/dport/app_efuse_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_efuse_int_map(&mut self) -> APP_EFUSE_INT_MAP_W<APP_EFUSE_INT_MAP_SPEC> {
         APP_EFUSE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_emac_int_map.rs b/esp32/src/dport/app_emac_int_map.rs
index 9e9f9705e7..5351caf9c0 100644
--- a/esp32/src/dport/app_emac_int_map.rs
+++ b/esp32/src/dport/app_emac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_emac_int_map(&mut self) -> APP_EMAC_INT_MAP_W<APP_EMAC_INT_MAP_SPEC> {
         APP_EMAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_gpio_interrupt_map.rs b/esp32/src/dport/app_gpio_interrupt_map.rs
index 9e9a578b08..5e7de57965 100644
--- a/esp32/src/dport/app_gpio_interrupt_map.rs
+++ b/esp32/src/dport/app_gpio_interrupt_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_gpio_interrupt_app_map(
         &mut self,
     ) -> APP_GPIO_INTERRUPT_APP_MAP_W<APP_GPIO_INTERRUPT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_gpio_interrupt_nmi_map.rs b/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
index 825a40e065..708ebe2bf2 100644
--- a/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
+++ b/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_gpio_interrupt_app_nmi_map(
         &mut self,
     ) -> APP_GPIO_INTERRUPT_APP_NMI_MAP_W<APP_GPIO_INTERRUPT_NMI_MAP_SPEC> {
diff --git a/esp32/src/dport/app_i2c_ext0_intr_map.rs b/esp32/src/dport/app_i2c_ext0_intr_map.rs
index ac94441ca3..da20597fe6 100644
--- a/esp32/src/dport/app_i2c_ext0_intr_map.rs
+++ b/esp32/src/dport/app_i2c_ext0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_i2c_ext0_intr_map(&mut self) -> APP_I2C_EXT0_INTR_MAP_W<APP_I2C_EXT0_INTR_MAP_SPEC> {
         APP_I2C_EXT0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_i2c_ext1_intr_map.rs b/esp32/src/dport/app_i2c_ext1_intr_map.rs
index 9e0b6a846e..c3bb1168dd 100644
--- a/esp32/src/dport/app_i2c_ext1_intr_map.rs
+++ b/esp32/src/dport/app_i2c_ext1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_i2c_ext1_intr_map(&mut self) -> APP_I2C_EXT1_INTR_MAP_W<APP_I2C_EXT1_INTR_MAP_SPEC> {
         APP_I2C_EXT1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_i2s0_int_map.rs b/esp32/src/dport/app_i2s0_int_map.rs
index ebd14a5058..3ccd372050 100644
--- a/esp32/src/dport/app_i2s0_int_map.rs
+++ b/esp32/src/dport/app_i2s0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_i2s0_int_map(&mut self) -> APP_I2S0_INT_MAP_W<APP_I2S0_INT_MAP_SPEC> {
         APP_I2S0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_i2s1_int_map.rs b/esp32/src/dport/app_i2s1_int_map.rs
index e91c500b2f..a3e505c44a 100644
--- a/esp32/src/dport/app_i2s1_int_map.rs
+++ b/esp32/src/dport/app_i2s1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_i2s1_int_map(&mut self) -> APP_I2S1_INT_MAP_W<APP_I2S1_INT_MAP_SPEC> {
         APP_I2S1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_intrusion_ctrl.rs b/esp32/src/dport/app_intrusion_ctrl.rs
index 41d739b32d..14dc2fff63 100644
--- a/esp32/src/dport/app_intrusion_ctrl.rs
+++ b/esp32/src/dport/app_intrusion_ctrl.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_intrusion_record_reset_n(
         &mut self,
     ) -> APP_INTRUSION_RECORD_RESET_N_W<APP_INTRUSION_CTRL_SPEC> {
diff --git a/esp32/src/dport/app_ledc_int_map.rs b/esp32/src/dport/app_ledc_int_map.rs
index 9d694378d8..4c2d2cd2e3 100644
--- a/esp32/src/dport/app_ledc_int_map.rs
+++ b/esp32/src/dport/app_ledc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_ledc_int_map(&mut self) -> APP_LEDC_INT_MAP_W<APP_LEDC_INT_MAP_SPEC> {
         APP_LEDC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_mac_intr_map.rs b/esp32/src/dport/app_mac_intr_map.rs
index fef04563cc..50ca9eff23 100644
--- a/esp32/src/dport/app_mac_intr_map.rs
+++ b/esp32/src/dport/app_mac_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_mac_intr_map(&mut self) -> APP_MAC_INTR_MAP_W<APP_MAC_INTR_MAP_SPEC> {
         APP_MAC_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_mac_nmi_map.rs b/esp32/src/dport/app_mac_nmi_map.rs
index 8aa9d22c9a..4b5fc6ee1a 100644
--- a/esp32/src/dport/app_mac_nmi_map.rs
+++ b/esp32/src/dport/app_mac_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_mac_nmi_map(&mut self) -> APP_MAC_NMI_MAP_W<APP_MAC_NMI_MAP_SPEC> {
         APP_MAC_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_mmu_ia_int_map.rs b/esp32/src/dport/app_mmu_ia_int_map.rs
index 29be87bed2..344f7de428 100644
--- a/esp32/src/dport/app_mmu_ia_int_map.rs
+++ b/esp32/src/dport/app_mmu_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_mmu_ia_int_map(&mut self) -> APP_MMU_IA_INT_MAP_W<APP_MMU_IA_INT_MAP_SPEC> {
         APP_MMU_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_mpu_ia_int_map.rs b/esp32/src/dport/app_mpu_ia_int_map.rs
index 43f41394a2..ab2b4d3dab 100644
--- a/esp32/src/dport/app_mpu_ia_int_map.rs
+++ b/esp32/src/dport/app_mpu_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_mpu_ia_int_map(&mut self) -> APP_MPU_IA_INT_MAP_W<APP_MPU_IA_INT_MAP_SPEC> {
         APP_MPU_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_pcnt_intr_map.rs b/esp32/src/dport/app_pcnt_intr_map.rs
index 434dab7053..9a5847bfa3 100644
--- a/esp32/src/dport/app_pcnt_intr_map.rs
+++ b/esp32/src/dport/app_pcnt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_pcnt_intr_map(&mut self) -> APP_PCNT_INTR_MAP_W<APP_PCNT_INTR_MAP_SPEC> {
         APP_PCNT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_pwm0_intr_map.rs b/esp32/src/dport/app_pwm0_intr_map.rs
index 611777f6fa..9ec552cb2d 100644
--- a/esp32/src/dport/app_pwm0_intr_map.rs
+++ b/esp32/src/dport/app_pwm0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_pwm0_intr_map(&mut self) -> APP_PWM0_INTR_MAP_W<APP_PWM0_INTR_MAP_SPEC> {
         APP_PWM0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_pwm1_intr_map.rs b/esp32/src/dport/app_pwm1_intr_map.rs
index 51aaf00df2..6b163b02bc 100644
--- a/esp32/src/dport/app_pwm1_intr_map.rs
+++ b/esp32/src/dport/app_pwm1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_pwm1_intr_map(&mut self) -> APP_PWM1_INTR_MAP_W<APP_PWM1_INTR_MAP_SPEC> {
         APP_PWM1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_pwm2_intr_map.rs b/esp32/src/dport/app_pwm2_intr_map.rs
index 0adccf31d4..6e548c33b1 100644
--- a/esp32/src/dport/app_pwm2_intr_map.rs
+++ b/esp32/src/dport/app_pwm2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_pwm2_intr_map(&mut self) -> APP_PWM2_INTR_MAP_W<APP_PWM2_INTR_MAP_SPEC> {
         APP_PWM2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_pwm3_intr_map.rs b/esp32/src/dport/app_pwm3_intr_map.rs
index 161b53bc3d..d3deb937d7 100644
--- a/esp32/src/dport/app_pwm3_intr_map.rs
+++ b/esp32/src/dport/app_pwm3_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_pwm3_intr_map(&mut self) -> APP_PWM3_INTR_MAP_W<APP_PWM3_INTR_MAP_SPEC> {
         APP_PWM3_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rmt_intr_map.rs b/esp32/src/dport/app_rmt_intr_map.rs
index 0d92542d63..ac6e6580b5 100644
--- a/esp32/src/dport/app_rmt_intr_map.rs
+++ b/esp32/src/dport/app_rmt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rmt_intr_map(&mut self) -> APP_RMT_INTR_MAP_W<APP_RMT_INTR_MAP_SPEC> {
         APP_RMT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rsa_intr_map.rs b/esp32/src/dport/app_rsa_intr_map.rs
index 5fbf439030..44ad646a3e 100644
--- a/esp32/src/dport/app_rsa_intr_map.rs
+++ b/esp32/src/dport/app_rsa_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rsa_intr_map(&mut self) -> APP_RSA_INTR_MAP_W<APP_RSA_INTR_MAP_SPEC> {
         APP_RSA_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rtc_core_intr_map.rs b/esp32/src/dport/app_rtc_core_intr_map.rs
index 2dad101a03..fe736f0225 100644
--- a/esp32/src/dport/app_rtc_core_intr_map.rs
+++ b/esp32/src/dport/app_rtc_core_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rtc_core_intr_map(&mut self) -> APP_RTC_CORE_INTR_MAP_W<APP_RTC_CORE_INTR_MAP_SPEC> {
         APP_RTC_CORE_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rwble_irq_map.rs b/esp32/src/dport/app_rwble_irq_map.rs
index 8b5dee4dc2..318e96c4da 100644
--- a/esp32/src/dport/app_rwble_irq_map.rs
+++ b/esp32/src/dport/app_rwble_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rwble_irq_map(&mut self) -> APP_RWBLE_IRQ_MAP_W<APP_RWBLE_IRQ_MAP_SPEC> {
         APP_RWBLE_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rwble_nmi_map.rs b/esp32/src/dport/app_rwble_nmi_map.rs
index 7f5f650640..63dc5dd25a 100644
--- a/esp32/src/dport/app_rwble_nmi_map.rs
+++ b/esp32/src/dport/app_rwble_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rwble_nmi_map(&mut self) -> APP_RWBLE_NMI_MAP_W<APP_RWBLE_NMI_MAP_SPEC> {
         APP_RWBLE_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rwbt_irq_map.rs b/esp32/src/dport/app_rwbt_irq_map.rs
index 0ca7a7a172..d70a1692f9 100644
--- a/esp32/src/dport/app_rwbt_irq_map.rs
+++ b/esp32/src/dport/app_rwbt_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rwbt_irq_map(&mut self) -> APP_RWBT_IRQ_MAP_W<APP_RWBT_IRQ_MAP_SPEC> {
         APP_RWBT_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_rwbt_nmi_map.rs b/esp32/src/dport/app_rwbt_nmi_map.rs
index 9117ae5c9c..95be8c0d84 100644
--- a/esp32/src/dport/app_rwbt_nmi_map.rs
+++ b/esp32/src/dport/app_rwbt_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rwbt_nmi_map(&mut self) -> APP_RWBT_NMI_MAP_W<APP_RWBT_NMI_MAP_SPEC> {
         APP_RWBT_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_sdio_host_interrupt_map.rs b/esp32/src/dport/app_sdio_host_interrupt_map.rs
index ad81894bfe..4c35d35856 100644
--- a/esp32/src/dport/app_sdio_host_interrupt_map.rs
+++ b/esp32/src/dport/app_sdio_host_interrupt_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_sdio_host_interrupt_map(
         &mut self,
     ) -> APP_SDIO_HOST_INTERRUPT_MAP_W<APP_SDIO_HOST_INTERRUPT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_slc0_intr_map.rs b/esp32/src/dport/app_slc0_intr_map.rs
index ed9da9b5e1..7e2c07601f 100644
--- a/esp32/src/dport/app_slc0_intr_map.rs
+++ b/esp32/src/dport/app_slc0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_slc0_intr_map(&mut self) -> APP_SLC0_INTR_MAP_W<APP_SLC0_INTR_MAP_SPEC> {
         APP_SLC0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_slc1_intr_map.rs b/esp32/src/dport/app_slc1_intr_map.rs
index 53a2194c5d..e2e3233b48 100644
--- a/esp32/src/dport/app_slc1_intr_map.rs
+++ b/esp32/src/dport/app_slc1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_slc1_intr_map(&mut self) -> APP_SLC1_INTR_MAP_W<APP_SLC1_INTR_MAP_SPEC> {
         APP_SLC1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi1_dma_int_map.rs b/esp32/src/dport/app_spi1_dma_int_map.rs
index 799622af18..a30e9848e1 100644
--- a/esp32/src/dport/app_spi1_dma_int_map.rs
+++ b/esp32/src/dport/app_spi1_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi1_dma_int_map(&mut self) -> APP_SPI1_DMA_INT_MAP_W<APP_SPI1_DMA_INT_MAP_SPEC> {
         APP_SPI1_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi2_dma_int_map.rs b/esp32/src/dport/app_spi2_dma_int_map.rs
index a7149dcf08..71249fba73 100644
--- a/esp32/src/dport/app_spi2_dma_int_map.rs
+++ b/esp32/src/dport/app_spi2_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi2_dma_int_map(&mut self) -> APP_SPI2_DMA_INT_MAP_W<APP_SPI2_DMA_INT_MAP_SPEC> {
         APP_SPI2_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi3_dma_int_map.rs b/esp32/src/dport/app_spi3_dma_int_map.rs
index 41f69c6be2..6680955b22 100644
--- a/esp32/src/dport/app_spi3_dma_int_map.rs
+++ b/esp32/src/dport/app_spi3_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi3_dma_int_map(&mut self) -> APP_SPI3_DMA_INT_MAP_W<APP_SPI3_DMA_INT_MAP_SPEC> {
         APP_SPI3_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi_intr_0_map.rs b/esp32/src/dport/app_spi_intr_0_map.rs
index 6df2e1938c..0cf70d38e2 100644
--- a/esp32/src/dport/app_spi_intr_0_map.rs
+++ b/esp32/src/dport/app_spi_intr_0_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi_intr_0_map(&mut self) -> APP_SPI_INTR_0_MAP_W<APP_SPI_INTR_0_MAP_SPEC> {
         APP_SPI_INTR_0_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi_intr_1_map.rs b/esp32/src/dport/app_spi_intr_1_map.rs
index 0596641479..5f6db2e5f1 100644
--- a/esp32/src/dport/app_spi_intr_1_map.rs
+++ b/esp32/src/dport/app_spi_intr_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi_intr_1_map(&mut self) -> APP_SPI_INTR_1_MAP_W<APP_SPI_INTR_1_MAP_SPEC> {
         APP_SPI_INTR_1_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi_intr_2_map.rs b/esp32/src/dport/app_spi_intr_2_map.rs
index 2eb55a0c4d..fff8a6e2a3 100644
--- a/esp32/src/dport/app_spi_intr_2_map.rs
+++ b/esp32/src/dport/app_spi_intr_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi_intr_2_map(&mut self) -> APP_SPI_INTR_2_MAP_W<APP_SPI_INTR_2_MAP_SPEC> {
         APP_SPI_INTR_2_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_spi_intr_3_map.rs b/esp32/src/dport/app_spi_intr_3_map.rs
index 58d4efd86f..dff9783248 100644
--- a/esp32/src/dport/app_spi_intr_3_map.rs
+++ b/esp32/src/dport/app_spi_intr_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_spi_intr_3_map(&mut self) -> APP_SPI_INTR_3_MAP_W<APP_SPI_INTR_3_MAP_SPEC> {
         APP_SPI_INTR_3_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_tg1_lact_edge_int_map.rs b/esp32/src/dport/app_tg1_lact_edge_int_map.rs
index 482de05f50..9f835d3fb4 100644
--- a/esp32/src/dport/app_tg1_lact_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_lact_edge_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_lact_edge_int_map(
         &mut self,
     ) -> APP_TG1_LACT_EDGE_INT_MAP_W<APP_TG1_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_lact_level_int_map.rs b/esp32/src/dport/app_tg1_lact_level_int_map.rs
index ec94749fb2..651e07a01c 100644
--- a/esp32/src/dport/app_tg1_lact_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_lact_level_int_map(
         &mut self,
     ) -> APP_TG1_LACT_LEVEL_INT_MAP_W<APP_TG1_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_t0_edge_int_map.rs b/esp32/src/dport/app_tg1_t0_edge_int_map.rs
index b2a4679531..1317e55786 100644
--- a/esp32/src/dport/app_tg1_t0_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_t0_edge_int_map(
         &mut self,
     ) -> APP_TG1_T0_EDGE_INT_MAP_W<APP_TG1_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_t0_level_int_map.rs b/esp32/src/dport/app_tg1_t0_level_int_map.rs
index 3c445491b5..54744e1463 100644
--- a/esp32/src/dport/app_tg1_t0_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_t0_level_int_map(
         &mut self,
     ) -> APP_TG1_T0_LEVEL_INT_MAP_W<APP_TG1_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_t1_edge_int_map.rs b/esp32/src/dport/app_tg1_t1_edge_int_map.rs
index e2baa8eb12..855040c7d8 100644
--- a/esp32/src/dport/app_tg1_t1_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_t1_edge_int_map(
         &mut self,
     ) -> APP_TG1_T1_EDGE_INT_MAP_W<APP_TG1_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_t1_level_int_map.rs b/esp32/src/dport/app_tg1_t1_level_int_map.rs
index 11e254110b..efb1a0c849 100644
--- a/esp32/src/dport/app_tg1_t1_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_t1_level_int_map(
         &mut self,
     ) -> APP_TG1_T1_LEVEL_INT_MAP_W<APP_TG1_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_wdt_edge_int_map.rs b/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
index 89bdc59c4f..fa5e4f83fe 100644
--- a/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_wdt_edge_int_map(
         &mut self,
     ) -> APP_TG1_WDT_EDGE_INT_MAP_W<APP_TG1_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg1_wdt_level_int_map.rs b/esp32/src/dport/app_tg1_wdt_level_int_map.rs
index 97a9a6b6b5..2492242b3e 100644
--- a/esp32/src/dport/app_tg1_wdt_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_wdt_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg1_wdt_level_int_map(
         &mut self,
     ) -> APP_TG1_WDT_LEVEL_INT_MAP_W<APP_TG1_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_lact_edge_int_map.rs b/esp32/src/dport/app_tg_lact_edge_int_map.rs
index cbc4039946..0062c7be45 100644
--- a/esp32/src/dport/app_tg_lact_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_lact_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_lact_edge_int_map(
         &mut self,
     ) -> APP_TG_LACT_EDGE_INT_MAP_W<APP_TG_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_lact_level_int_map.rs b/esp32/src/dport/app_tg_lact_level_int_map.rs
index dd1269d741..b9aeb71819 100644
--- a/esp32/src/dport/app_tg_lact_level_int_map.rs
+++ b/esp32/src/dport/app_tg_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_lact_level_int_map(
         &mut self,
     ) -> APP_TG_LACT_LEVEL_INT_MAP_W<APP_TG_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_t0_edge_int_map.rs b/esp32/src/dport/app_tg_t0_edge_int_map.rs
index b8d07796c2..c463592177 100644
--- a/esp32/src/dport/app_tg_t0_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_t0_edge_int_map(
         &mut self,
     ) -> APP_TG_T0_EDGE_INT_MAP_W<APP_TG_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_t0_level_int_map.rs b/esp32/src/dport/app_tg_t0_level_int_map.rs
index 95607cbb23..0964097318 100644
--- a/esp32/src/dport/app_tg_t0_level_int_map.rs
+++ b/esp32/src/dport/app_tg_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_t0_level_int_map(
         &mut self,
     ) -> APP_TG_T0_LEVEL_INT_MAP_W<APP_TG_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_t1_edge_int_map.rs b/esp32/src/dport/app_tg_t1_edge_int_map.rs
index 41976915a9..a85b6585a6 100644
--- a/esp32/src/dport/app_tg_t1_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_t1_edge_int_map(
         &mut self,
     ) -> APP_TG_T1_EDGE_INT_MAP_W<APP_TG_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_t1_level_int_map.rs b/esp32/src/dport/app_tg_t1_level_int_map.rs
index 550582b31e..4dae482148 100644
--- a/esp32/src/dport/app_tg_t1_level_int_map.rs
+++ b/esp32/src/dport/app_tg_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_t1_level_int_map(
         &mut self,
     ) -> APP_TG_T1_LEVEL_INT_MAP_W<APP_TG_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_wdt_edge_int_map.rs b/esp32/src/dport/app_tg_wdt_edge_int_map.rs
index 7dd06ecaca..10a1b7f4a0 100644
--- a/esp32/src/dport/app_tg_wdt_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_wdt_edge_int_map(
         &mut self,
     ) -> APP_TG_WDT_EDGE_INT_MAP_W<APP_TG_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_tg_wdt_level_int_map.rs b/esp32/src/dport/app_tg_wdt_level_int_map.rs
index 587aed5507..6a98c4c11e 100644
--- a/esp32/src/dport/app_tg_wdt_level_int_map.rs
+++ b/esp32/src/dport/app_tg_wdt_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tg_wdt_level_int_map(
         &mut self,
     ) -> APP_TG_WDT_LEVEL_INT_MAP_W<APP_TG_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/app_timer_int1_map.rs b/esp32/src/dport/app_timer_int1_map.rs
index 245c289ad5..4195cf1407 100644
--- a/esp32/src/dport/app_timer_int1_map.rs
+++ b/esp32/src/dport/app_timer_int1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_timer_int1_map(&mut self) -> APP_TIMER_INT1_MAP_W<APP_TIMER_INT1_MAP_SPEC> {
         APP_TIMER_INT1_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_timer_int2_map.rs b/esp32/src/dport/app_timer_int2_map.rs
index 7eb79f8f73..028e448a06 100644
--- a/esp32/src/dport/app_timer_int2_map.rs
+++ b/esp32/src/dport/app_timer_int2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_timer_int2_map(&mut self) -> APP_TIMER_INT2_MAP_W<APP_TIMER_INT2_MAP_SPEC> {
         APP_TIMER_INT2_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_tracemem_ena.rs b/esp32/src/dport/app_tracemem_ena.rs
index 0ad79e04b0..2f27a2edae 100644
--- a/esp32/src/dport/app_tracemem_ena.rs
+++ b/esp32/src/dport/app_tracemem_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn app_tracemem_ena(&mut self) -> APP_TRACEMEM_ENA_W<APP_TRACEMEM_ENA_SPEC> {
         APP_TRACEMEM_ENA_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_uart1_intr_map.rs b/esp32/src/dport/app_uart1_intr_map.rs
index 514741b8fe..2ea9019a70 100644
--- a/esp32/src/dport/app_uart1_intr_map.rs
+++ b/esp32/src/dport/app_uart1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_uart1_intr_map(&mut self) -> APP_UART1_INTR_MAP_W<APP_UART1_INTR_MAP_SPEC> {
         APP_UART1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_uart2_intr_map.rs b/esp32/src/dport/app_uart2_intr_map.rs
index d95792bdcc..262b228064 100644
--- a/esp32/src/dport/app_uart2_intr_map.rs
+++ b/esp32/src/dport/app_uart2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_uart2_intr_map(&mut self) -> APP_UART2_INTR_MAP_W<APP_UART2_INTR_MAP_SPEC> {
         APP_UART2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_uart_intr_map.rs b/esp32/src/dport/app_uart_intr_map.rs
index 588b7084c8..093d3bb84f 100644
--- a/esp32/src/dport/app_uart_intr_map.rs
+++ b/esp32/src/dport/app_uart_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_uart_intr_map(&mut self) -> APP_UART_INTR_MAP_W<APP_UART_INTR_MAP_SPEC> {
         APP_UART_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_uhci0_intr_map.rs b/esp32/src/dport/app_uhci0_intr_map.rs
index be41304e60..d8cb7bf88d 100644
--- a/esp32/src/dport/app_uhci0_intr_map.rs
+++ b/esp32/src/dport/app_uhci0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_uhci0_intr_map(&mut self) -> APP_UHCI0_INTR_MAP_W<APP_UHCI0_INTR_MAP_SPEC> {
         APP_UHCI0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_uhci1_intr_map.rs b/esp32/src/dport/app_uhci1_intr_map.rs
index f7ebfc2408..d6f908cb26 100644
--- a/esp32/src/dport/app_uhci1_intr_map.rs
+++ b/esp32/src/dport/app_uhci1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_uhci1_intr_map(&mut self) -> APP_UHCI1_INTR_MAP_W<APP_UHCI1_INTR_MAP_SPEC> {
         APP_UHCI1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_vecbase_ctrl.rs b/esp32/src/dport/app_vecbase_ctrl.rs
index 4df76e1d5e..55d5ddc0f4 100644
--- a/esp32/src/dport/app_vecbase_ctrl.rs
+++ b/esp32/src/dport/app_vecbase_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn app_out_vecbase_sel(&mut self) -> APP_OUT_VECBASE_SEL_W<APP_VECBASE_CTRL_SPEC> {
         APP_OUT_VECBASE_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_vecbase_set.rs b/esp32/src/dport/app_vecbase_set.rs
index a425b403e3..ffff7e05c8 100644
--- a/esp32/src/dport/app_vecbase_set.rs
+++ b/esp32/src/dport/app_vecbase_set.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21"]
     #[inline(always)]
-    #[must_use]
     pub fn app_out_vecbase(&mut self) -> APP_OUT_VECBASE_W<APP_VECBASE_SET_SPEC> {
         APP_OUT_VECBASE_W::new(self, 0)
     }
diff --git a/esp32/src/dport/app_wdg_int_map.rs b/esp32/src/dport/app_wdg_int_map.rs
index 540c96fca0..5eaed31ce5 100644
--- a/esp32/src/dport/app_wdg_int_map.rs
+++ b/esp32/src/dport/app_wdg_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn app_wdg_int_map(&mut self) -> APP_WDG_INT_MAP_W<APP_WDG_INT_MAP_SPEC> {
         APP_WDG_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/appcpu_ctrl_a.rs b/esp32/src/dport/appcpu_ctrl_a.rs
index 5701d226eb..2480c4833b 100644
--- a/esp32/src/dport/appcpu_ctrl_a.rs
+++ b/esp32/src/dport/appcpu_ctrl_a.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_resetting(&mut self) -> APPCPU_RESETTING_W<APPCPU_CTRL_A_SPEC> {
         APPCPU_RESETTING_W::new(self, 0)
     }
diff --git a/esp32/src/dport/appcpu_ctrl_b.rs b/esp32/src/dport/appcpu_ctrl_b.rs
index be1b7b496e..4273aab810 100644
--- a/esp32/src/dport/appcpu_ctrl_b.rs
+++ b/esp32/src/dport/appcpu_ctrl_b.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_clkgate_en(&mut self) -> APPCPU_CLKGATE_EN_W<APPCPU_CTRL_B_SPEC> {
         APPCPU_CLKGATE_EN_W::new(self, 0)
     }
diff --git a/esp32/src/dport/appcpu_ctrl_c.rs b/esp32/src/dport/appcpu_ctrl_c.rs
index 96c2182d7d..4400bf3846 100644
--- a/esp32/src/dport/appcpu_ctrl_c.rs
+++ b/esp32/src/dport/appcpu_ctrl_c.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_runstall(&mut self) -> APPCPU_RUNSTALL_W<APPCPU_CTRL_C_SPEC> {
         APPCPU_RUNSTALL_W::new(self, 0)
     }
diff --git a/esp32/src/dport/appcpu_ctrl_d.rs b/esp32/src/dport/appcpu_ctrl_d.rs
index f19ac34129..d80eae61ca 100644
--- a/esp32/src/dport/appcpu_ctrl_d.rs
+++ b/esp32/src/dport/appcpu_ctrl_d.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_boot_addr(&mut self) -> APPCPU_BOOT_ADDR_W<APPCPU_CTRL_D_SPEC> {
         APPCPU_BOOT_ADDR_W::new(self, 0)
     }
diff --git a/esp32/src/dport/bt_lpck_div_frac.rs b/esp32/src/dport/bt_lpck_div_frac.rs
index 0047939543..07aa3a2a30 100644
--- a/esp32/src/dport/bt_lpck_div_frac.rs
+++ b/esp32/src/dport/bt_lpck_div_frac.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_b(&mut self) -> BT_LPCK_DIV_B_W<BT_LPCK_DIV_FRAC_SPEC> {
         BT_LPCK_DIV_B_W::new(self, 0)
     }
     #[doc = "Bits 12:23"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_a(&mut self) -> BT_LPCK_DIV_A_W<BT_LPCK_DIV_FRAC_SPEC> {
         BT_LPCK_DIV_A_W::new(self, 12)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_RTC_SLOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_8M_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL32K_W::new(self, 27)
     }
diff --git a/esp32/src/dport/bt_lpck_div_int.rs b/esp32/src/dport/bt_lpck_div_int.rs
index c77fd8f105..c978bd84dd 100644
--- a/esp32/src/dport/bt_lpck_div_int.rs
+++ b/esp32/src/dport/bt_lpck_div_int.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_num(&mut self) -> BT_LPCK_DIV_NUM_W<BT_LPCK_DIV_INT_SPEC> {
         BT_LPCK_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn btextwakeup_req(&mut self) -> BTEXTWAKEUP_REQ_W<BT_LPCK_DIV_INT_SPEC> {
         BTEXTWAKEUP_REQ_W::new(self, 12)
     }
diff --git a/esp32/src/dport/cache_ia_int_en.rs b/esp32/src/dport/cache_ia_int_en.rs
index ece38d6fe3..e40bc210fd 100644
--- a/esp32/src/dport/cache_ia_int_en.rs
+++ b/esp32/src/dport/cache_ia_int_en.rs
@@ -150,43 +150,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Interrupt enable bits for various invalid cache access reasons"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_en(&mut self) -> CACHE_IA_INT_EN_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_EN_W::new(self, 0)
     }
     #[doc = "Bit 0 - APP CPU invalid access to DROM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_drom0(&mut self) -> CACHE_IA_INT_APP_DROM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_APP_DROM0_W::new(self, 0)
     }
     #[doc = "Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_iram0(&mut self) -> CACHE_IA_INT_APP_IRAM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_APP_IRAM0_W::new(self, 1)
     }
     #[doc = "Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_iram1(&mut self) -> CACHE_IA_INT_APP_IRAM1_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_APP_IRAM1_W::new(self, 2)
     }
     #[doc = "Bit 3 - APP CPU invalid access to IROM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_irom0(&mut self) -> CACHE_IA_INT_APP_IROM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_APP_IROM0_W::new(self, 3)
     }
     #[doc = "Bit 4 - APP CPU invalid access to DRAM1 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_dram1(&mut self) -> CACHE_IA_INT_APP_DRAM1_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_APP_DRAM1_W::new(self, 4)
     }
     #[doc = "Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_app_opposite(
         &mut self,
     ) -> CACHE_IA_INT_APP_OPPOSITE_W<CACHE_IA_INT_EN_SPEC> {
@@ -194,37 +187,31 @@ impl W {
     }
     #[doc = "Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_drom0(&mut self) -> CACHE_IA_INT_PRO_DROM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_PRO_DROM0_W::new(self, 14)
     }
     #[doc = "Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_iram0(&mut self) -> CACHE_IA_INT_PRO_IRAM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_PRO_IRAM0_W::new(self, 15)
     }
     #[doc = "Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_iram1(&mut self) -> CACHE_IA_INT_PRO_IRAM1_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_PRO_IRAM1_W::new(self, 16)
     }
     #[doc = "Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_irom0(&mut self) -> CACHE_IA_INT_PRO_IROM0_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_PRO_IROM0_W::new(self, 17)
     }
     #[doc = "Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_dram1(&mut self) -> CACHE_IA_INT_PRO_DRAM1_W<CACHE_IA_INT_EN_SPEC> {
         CACHE_IA_INT_PRO_DRAM1_W::new(self, 18)
     }
     #[doc = "Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_pro_opposite(
         &mut self,
     ) -> CACHE_IA_INT_PRO_OPPOSITE_W<CACHE_IA_INT_EN_SPEC> {
diff --git a/esp32/src/dport/cache_mux_mode.rs b/esp32/src/dport/cache_mux_mode.rs
index 4b4291a65b..5b4f16b985 100644
--- a/esp32/src/dport/cache_mux_mode.rs
+++ b/esp32/src/dport/cache_mux_mode.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mux_mode(&mut self) -> CACHE_MUX_MODE_W<CACHE_MUX_MODE_SPEC> {
         CACHE_MUX_MODE_W::new(self, 0)
     }
diff --git a/esp32/src/dport/core_rst_en.rs b/esp32/src/dport/core_rst_en.rs
index 03e0efe68f..0b27d5fdd8 100644
--- a/esp32/src/dport/core_rst_en.rs
+++ b/esp32/src/dport/core_rst_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_rst(&mut self) -> CORE_RST_W<CORE_RST_EN_SPEC> {
         CORE_RST_W::new(self, 0)
     }
diff --git a/esp32/src/dport/cpu_intr_from_cpu_0.rs b/esp32/src/dport/cpu_intr_from_cpu_0.rs
index 6668ba4c7c..ca7aa48022 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_0.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_0(&mut self) -> CPU_INTR_FROM_CPU_0_W<CPU_INTR_FROM_CPU_0_SPEC> {
         CPU_INTR_FROM_CPU_0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/cpu_intr_from_cpu_1.rs b/esp32/src/dport/cpu_intr_from_cpu_1.rs
index 5421f9cc5b..815b5229ef 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_1.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_1(&mut self) -> CPU_INTR_FROM_CPU_1_W<CPU_INTR_FROM_CPU_1_SPEC> {
         CPU_INTR_FROM_CPU_1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/cpu_intr_from_cpu_2.rs b/esp32/src/dport/cpu_intr_from_cpu_2.rs
index dc046caf80..42d02cc885 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_2.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_2(&mut self) -> CPU_INTR_FROM_CPU_2_W<CPU_INTR_FROM_CPU_2_SPEC> {
         CPU_INTR_FROM_CPU_2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/cpu_intr_from_cpu_3.rs b/esp32/src/dport/cpu_intr_from_cpu_3.rs
index de0bb3f51b..51a3f73d92 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_3.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_3(&mut self) -> CPU_INTR_FROM_CPU_3_W<CPU_INTR_FROM_CPU_3_SPEC> {
         CPU_INTR_FROM_CPU_3_W::new(self, 0)
     }
diff --git a/esp32/src/dport/cpu_per_conf.rs b/esp32/src/dport/cpu_per_conf.rs
index 518e3463aa..e4b1031778 100644
--- a/esp32/src/dport/cpu_per_conf.rs
+++ b/esp32/src/dport/cpu_per_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PER_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn lowspeed_clk_sel(&mut self) -> LOWSPEED_CLK_SEL_W<CPU_PER_CONF_SPEC> {
         LOWSPEED_CLK_SEL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CPU_PER_CONF_SPEC> {
         FAST_CLK_RTC_SEL_W::new(self, 3)
     }
diff --git a/esp32/src/dport/date.rs b/esp32/src/dport/date.rs
index e10531cbfa..5cdc80604c 100644
--- a/esp32/src/dport/date.rs
+++ b/esp32/src/dport/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_page_mode.rs b/esp32/src/dport/dmmu_page_mode.rs
index 558cd7a095..5d8c82f147 100644
--- a/esp32/src/dport/dmmu_page_mode.rs
+++ b/esp32/src/dport/dmmu_page_mode.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_dmmu_ena(&mut self) -> INTERNAL_SRAM_DMMU_ENA_W<DMMU_PAGE_MODE_SPEC> {
         INTERNAL_SRAM_DMMU_ENA_W::new(self, 0)
     }
     #[doc = "Bits 1:2"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_page_mode(&mut self) -> DMMU_PAGE_MODE_W<DMMU_PAGE_MODE_SPEC> {
         DMMU_PAGE_MODE_W::new(self, 1)
     }
diff --git a/esp32/src/dport/dmmu_table0.rs b/esp32/src/dport/dmmu_table0.rs
index 83d6a61da6..1b1552f9d7 100644
--- a/esp32/src/dport/dmmu_table0.rs
+++ b/esp32/src/dport/dmmu_table0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table0(&mut self) -> DMMU_TABLE0_W<DMMU_TABLE0_SPEC> {
         DMMU_TABLE0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table1.rs b/esp32/src/dport/dmmu_table1.rs
index 4f0dd610eb..040270a7cf 100644
--- a/esp32/src/dport/dmmu_table1.rs
+++ b/esp32/src/dport/dmmu_table1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table1(&mut self) -> DMMU_TABLE1_W<DMMU_TABLE1_SPEC> {
         DMMU_TABLE1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table10.rs b/esp32/src/dport/dmmu_table10.rs
index 28211a001d..b96421faf2 100644
--- a/esp32/src/dport/dmmu_table10.rs
+++ b/esp32/src/dport/dmmu_table10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table10(&mut self) -> DMMU_TABLE10_W<DMMU_TABLE10_SPEC> {
         DMMU_TABLE10_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table11.rs b/esp32/src/dport/dmmu_table11.rs
index 3efe9fd316..89ea6d6bdc 100644
--- a/esp32/src/dport/dmmu_table11.rs
+++ b/esp32/src/dport/dmmu_table11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table11(&mut self) -> DMMU_TABLE11_W<DMMU_TABLE11_SPEC> {
         DMMU_TABLE11_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table12.rs b/esp32/src/dport/dmmu_table12.rs
index 019fe06f17..4677a58f91 100644
--- a/esp32/src/dport/dmmu_table12.rs
+++ b/esp32/src/dport/dmmu_table12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table12(&mut self) -> DMMU_TABLE12_W<DMMU_TABLE12_SPEC> {
         DMMU_TABLE12_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table13.rs b/esp32/src/dport/dmmu_table13.rs
index 3c5465fff2..f5cc7595c7 100644
--- a/esp32/src/dport/dmmu_table13.rs
+++ b/esp32/src/dport/dmmu_table13.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table13(&mut self) -> DMMU_TABLE13_W<DMMU_TABLE13_SPEC> {
         DMMU_TABLE13_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table14.rs b/esp32/src/dport/dmmu_table14.rs
index 68e9d8e38c..6a8c75afef 100644
--- a/esp32/src/dport/dmmu_table14.rs
+++ b/esp32/src/dport/dmmu_table14.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table14(&mut self) -> DMMU_TABLE14_W<DMMU_TABLE14_SPEC> {
         DMMU_TABLE14_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table15.rs b/esp32/src/dport/dmmu_table15.rs
index 4eaf59efd1..7ba925e3b0 100644
--- a/esp32/src/dport/dmmu_table15.rs
+++ b/esp32/src/dport/dmmu_table15.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table15(&mut self) -> DMMU_TABLE15_W<DMMU_TABLE15_SPEC> {
         DMMU_TABLE15_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table2.rs b/esp32/src/dport/dmmu_table2.rs
index 9b4becdb7f..4b9644b0c4 100644
--- a/esp32/src/dport/dmmu_table2.rs
+++ b/esp32/src/dport/dmmu_table2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table2(&mut self) -> DMMU_TABLE2_W<DMMU_TABLE2_SPEC> {
         DMMU_TABLE2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table3.rs b/esp32/src/dport/dmmu_table3.rs
index b8db45dc2d..62aaebf945 100644
--- a/esp32/src/dport/dmmu_table3.rs
+++ b/esp32/src/dport/dmmu_table3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table3(&mut self) -> DMMU_TABLE3_W<DMMU_TABLE3_SPEC> {
         DMMU_TABLE3_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table4.rs b/esp32/src/dport/dmmu_table4.rs
index 449e07a8d1..e0294dc1fd 100644
--- a/esp32/src/dport/dmmu_table4.rs
+++ b/esp32/src/dport/dmmu_table4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table4(&mut self) -> DMMU_TABLE4_W<DMMU_TABLE4_SPEC> {
         DMMU_TABLE4_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table5.rs b/esp32/src/dport/dmmu_table5.rs
index d98c2002ee..bbf7c9089b 100644
--- a/esp32/src/dport/dmmu_table5.rs
+++ b/esp32/src/dport/dmmu_table5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table5(&mut self) -> DMMU_TABLE5_W<DMMU_TABLE5_SPEC> {
         DMMU_TABLE5_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table6.rs b/esp32/src/dport/dmmu_table6.rs
index 6cd617bd23..6062288508 100644
--- a/esp32/src/dport/dmmu_table6.rs
+++ b/esp32/src/dport/dmmu_table6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table6(&mut self) -> DMMU_TABLE6_W<DMMU_TABLE6_SPEC> {
         DMMU_TABLE6_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table7.rs b/esp32/src/dport/dmmu_table7.rs
index c996edc270..bf6557be70 100644
--- a/esp32/src/dport/dmmu_table7.rs
+++ b/esp32/src/dport/dmmu_table7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table7(&mut self) -> DMMU_TABLE7_W<DMMU_TABLE7_SPEC> {
         DMMU_TABLE7_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table8.rs b/esp32/src/dport/dmmu_table8.rs
index cde54d1356..edf209c50a 100644
--- a/esp32/src/dport/dmmu_table8.rs
+++ b/esp32/src/dport/dmmu_table8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table8(&mut self) -> DMMU_TABLE8_W<DMMU_TABLE8_SPEC> {
         DMMU_TABLE8_W::new(self, 0)
     }
diff --git a/esp32/src/dport/dmmu_table9.rs b/esp32/src/dport/dmmu_table9.rs
index dbd79faf6c..46aa2e8bcd 100644
--- a/esp32/src/dport/dmmu_table9.rs
+++ b/esp32/src/dport/dmmu_table9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn dmmu_table9(&mut self) -> DMMU_TABLE9_W<DMMU_TABLE9_SPEC> {
         DMMU_TABLE9_W::new(self, 0)
     }
diff --git a/esp32/src/dport/front_end_mem_pd.rs b/esp32/src/dport/front_end_mem_pd.rs
index 2f53663e4c..ac7fb5049b 100644
--- a/esp32/src/dport/front_end_mem_pd.rs
+++ b/esp32/src/dport/front_end_mem_pd.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pu(&mut self) -> AGC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PU_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pd(&mut self) -> AGC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pu(&mut self) -> PBUS_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PU_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pd(&mut self) -> PBUS_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PD_W::new(self, 3)
     }
diff --git a/esp32/src/dport/host_inf_sel.rs b/esp32/src/dport/host_inf_sel.rs
index 41c1fe5cdb..71ceb1ac99 100644
--- a/esp32/src/dport/host_inf_sel.rs
+++ b/esp32/src/dport/host_inf_sel.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_io_swap(&mut self) -> PERI_IO_SWAP_W<HOST_INF_SEL_SPEC> {
         PERI_IO_SWAP_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn link_device_sel(&mut self) -> LINK_DEVICE_SEL_W<HOST_INF_SEL_SPEC> {
         LINK_DEVICE_SEL_W::new(self, 8)
     }
diff --git a/esp32/src/dport/immu_page_mode.rs b/esp32/src/dport/immu_page_mode.rs
index dd85131d28..d49a43f314 100644
--- a/esp32/src/dport/immu_page_mode.rs
+++ b/esp32/src/dport/immu_page_mode.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_immu_ena(&mut self) -> INTERNAL_SRAM_IMMU_ENA_W<IMMU_PAGE_MODE_SPEC> {
         INTERNAL_SRAM_IMMU_ENA_W::new(self, 0)
     }
     #[doc = "Bits 1:2"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_page_mode(&mut self) -> IMMU_PAGE_MODE_W<IMMU_PAGE_MODE_SPEC> {
         IMMU_PAGE_MODE_W::new(self, 1)
     }
diff --git a/esp32/src/dport/immu_table0.rs b/esp32/src/dport/immu_table0.rs
index 54b723d8cf..75b51ff1a5 100644
--- a/esp32/src/dport/immu_table0.rs
+++ b/esp32/src/dport/immu_table0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table0(&mut self) -> IMMU_TABLE0_W<IMMU_TABLE0_SPEC> {
         IMMU_TABLE0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table1.rs b/esp32/src/dport/immu_table1.rs
index 41e5f98424..7afb17edf0 100644
--- a/esp32/src/dport/immu_table1.rs
+++ b/esp32/src/dport/immu_table1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table1(&mut self) -> IMMU_TABLE1_W<IMMU_TABLE1_SPEC> {
         IMMU_TABLE1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table10.rs b/esp32/src/dport/immu_table10.rs
index ed33c380b1..2398ec80a4 100644
--- a/esp32/src/dport/immu_table10.rs
+++ b/esp32/src/dport/immu_table10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table10(&mut self) -> IMMU_TABLE10_W<IMMU_TABLE10_SPEC> {
         IMMU_TABLE10_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table11.rs b/esp32/src/dport/immu_table11.rs
index 9b6b216d15..88f2d1b27a 100644
--- a/esp32/src/dport/immu_table11.rs
+++ b/esp32/src/dport/immu_table11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table11(&mut self) -> IMMU_TABLE11_W<IMMU_TABLE11_SPEC> {
         IMMU_TABLE11_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table12.rs b/esp32/src/dport/immu_table12.rs
index 3aa5205493..67b15c75fa 100644
--- a/esp32/src/dport/immu_table12.rs
+++ b/esp32/src/dport/immu_table12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table12(&mut self) -> IMMU_TABLE12_W<IMMU_TABLE12_SPEC> {
         IMMU_TABLE12_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table13.rs b/esp32/src/dport/immu_table13.rs
index 604f0b3f14..ece958b07f 100644
--- a/esp32/src/dport/immu_table13.rs
+++ b/esp32/src/dport/immu_table13.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table13(&mut self) -> IMMU_TABLE13_W<IMMU_TABLE13_SPEC> {
         IMMU_TABLE13_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table14.rs b/esp32/src/dport/immu_table14.rs
index 7b935f3ab3..1b8e366596 100644
--- a/esp32/src/dport/immu_table14.rs
+++ b/esp32/src/dport/immu_table14.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table14(&mut self) -> IMMU_TABLE14_W<IMMU_TABLE14_SPEC> {
         IMMU_TABLE14_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table15.rs b/esp32/src/dport/immu_table15.rs
index f2a9e1fc45..2fc7ea75fc 100644
--- a/esp32/src/dport/immu_table15.rs
+++ b/esp32/src/dport/immu_table15.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table15(&mut self) -> IMMU_TABLE15_W<IMMU_TABLE15_SPEC> {
         IMMU_TABLE15_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table2.rs b/esp32/src/dport/immu_table2.rs
index 70c2beb401..9540c38179 100644
--- a/esp32/src/dport/immu_table2.rs
+++ b/esp32/src/dport/immu_table2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table2(&mut self) -> IMMU_TABLE2_W<IMMU_TABLE2_SPEC> {
         IMMU_TABLE2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table3.rs b/esp32/src/dport/immu_table3.rs
index 5e69ba80c5..076e027943 100644
--- a/esp32/src/dport/immu_table3.rs
+++ b/esp32/src/dport/immu_table3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table3(&mut self) -> IMMU_TABLE3_W<IMMU_TABLE3_SPEC> {
         IMMU_TABLE3_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table4.rs b/esp32/src/dport/immu_table4.rs
index 03faa3e152..72acfa63dd 100644
--- a/esp32/src/dport/immu_table4.rs
+++ b/esp32/src/dport/immu_table4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table4(&mut self) -> IMMU_TABLE4_W<IMMU_TABLE4_SPEC> {
         IMMU_TABLE4_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table5.rs b/esp32/src/dport/immu_table5.rs
index 85f43f7a65..e606687882 100644
--- a/esp32/src/dport/immu_table5.rs
+++ b/esp32/src/dport/immu_table5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table5(&mut self) -> IMMU_TABLE5_W<IMMU_TABLE5_SPEC> {
         IMMU_TABLE5_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table6.rs b/esp32/src/dport/immu_table6.rs
index 2eec32385c..3632e185ad 100644
--- a/esp32/src/dport/immu_table6.rs
+++ b/esp32/src/dport/immu_table6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table6(&mut self) -> IMMU_TABLE6_W<IMMU_TABLE6_SPEC> {
         IMMU_TABLE6_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table7.rs b/esp32/src/dport/immu_table7.rs
index 5e4094e4e6..d400d74260 100644
--- a/esp32/src/dport/immu_table7.rs
+++ b/esp32/src/dport/immu_table7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table7(&mut self) -> IMMU_TABLE7_W<IMMU_TABLE7_SPEC> {
         IMMU_TABLE7_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table8.rs b/esp32/src/dport/immu_table8.rs
index e205d6c506..fd791144d3 100644
--- a/esp32/src/dport/immu_table8.rs
+++ b/esp32/src/dport/immu_table8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table8(&mut self) -> IMMU_TABLE8_W<IMMU_TABLE8_SPEC> {
         IMMU_TABLE8_W::new(self, 0)
     }
diff --git a/esp32/src/dport/immu_table9.rs b/esp32/src/dport/immu_table9.rs
index 4fdca6411b..6bfe04aeef 100644
--- a/esp32/src/dport/immu_table9.rs
+++ b/esp32/src/dport/immu_table9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn immu_table9(&mut self) -> IMMU_TABLE9_W<IMMU_TABLE9_SPEC> {
         IMMU_TABLE9_W::new(self, 0)
     }
diff --git a/esp32/src/dport/iram_dram_ahb_sel.rs b/esp32/src/dport/iram_dram_ahb_sel.rs
index 8e3eff809e..f14c701b3a 100644
--- a/esp32/src/dport/iram_dram_ahb_sel.rs
+++ b/esp32/src/dport/iram_dram_ahb_sel.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_pro_iram(&mut self) -> MASK_PRO_IRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MASK_PRO_IRAM_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_app_iram(&mut self) -> MASK_APP_IRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MASK_APP_IRAM_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_pro_dram(&mut self) -> MASK_PRO_DRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MASK_PRO_DRAM_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_app_dram(&mut self) -> MASK_APP_DRAM_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MASK_APP_DRAM_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_ahb(&mut self) -> MASK_AHB_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MASK_AHB_W::new(self, 4)
     }
     #[doc = "Bits 5:6"]
     #[inline(always)]
-    #[must_use]
     pub fn mac_dump_mode(&mut self) -> MAC_DUMP_MODE_W<IRAM_DRAM_AHB_SEL_SPEC> {
         MAC_DUMP_MODE_W::new(self, 5)
     }
diff --git a/esp32/src/dport/mem_pd_mask.rs b/esp32/src/dport/mem_pd_mask.rs
index 5725af8864..cb6970fdbb 100644
--- a/esp32/src/dport/mem_pd_mask.rs
+++ b/esp32/src/dport/mem_pd_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_pd_mask(&mut self) -> LSLP_MEM_PD_MASK_W<MEM_PD_MASK_SPEC> {
         LSLP_MEM_PD_MASK_W::new(self, 0)
     }
diff --git a/esp32/src/dport/mmu_ia_int_en.rs b/esp32/src/dport/mmu_ia_int_en.rs
index 713a44b990..e4b82d279a 100644
--- a/esp32/src/dport/mmu_ia_int_en.rs
+++ b/esp32/src/dport/mmu_ia_int_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn mmu_ia_int_en(&mut self) -> MMU_IA_INT_EN_W<MMU_IA_INT_EN_SPEC> {
         MMU_IA_INT_EN_W::new(self, 0)
     }
diff --git a/esp32/src/dport/mpu_ia_int_en.rs b/esp32/src/dport/mpu_ia_int_en.rs
index 8e30e03b1f..6be89a8599 100644
--- a/esp32/src/dport/mpu_ia_int_en.rs
+++ b/esp32/src/dport/mpu_ia_int_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:16"]
     #[inline(always)]
-    #[must_use]
     pub fn mpu_ia_int_en(&mut self) -> MPU_IA_INT_EN_W<MPU_IA_INT_EN_SPEC> {
         MPU_IA_INT_EN_W::new(self, 0)
     }
diff --git a/esp32/src/dport/peri_clk_en.rs b/esp32/src/dport/peri_clk_en.rs
index cc00229d49..cb81a00d4c 100644
--- a/esp32/src/dport/peri_clk_en.rs
+++ b/esp32/src/dport/peri_clk_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_clk_en(&mut self) -> PERI_CLK_EN_W<PERI_CLK_EN_SPEC> {
         PERI_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32/src/dport/peri_rst_en.rs b/esp32/src/dport/peri_rst_en.rs
index aabaa24990..92c8fa65b5 100644
--- a/esp32/src/dport/peri_rst_en.rs
+++ b/esp32/src/dport/peri_rst_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_rst_en(&mut self) -> PERI_RST_EN_W<PERI_RST_EN_SPEC> {
         PERI_RST_EN_W::new(self, 0)
     }
diff --git a/esp32/src/dport/perip_clk_en.rs b/esp32/src/dport/perip_clk_en.rs
index 83e7eecdad..b95b54efe9 100644
--- a/esp32/src/dport/perip_clk_en.rs
+++ b/esp32/src/dport/perip_clk_en.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         TIMERS_CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         SPI01_CLK_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UART_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         WDG_CLK_EN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         I2S0_CLK_EN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UART1_CLK_EN_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         SPI2_CLK_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c0_ext0_clk_en(&mut self) -> I2C0_EXT0_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         I2C0_EXT0_CLK_EN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UHCI0_CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         RMT_CLK_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         PCNT_CLK_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         LEDC_CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UHCI1_CLK_EN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         TIMERGROUP_CLK_EN_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         EFUSE_CLK_EN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         TIMERGROUP1_CLK_EN_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         SPI3_CLK_EN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         PWM0_CLK_EN_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_clk_en(&mut self) -> I2C_EXT1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         I2C_EXT1_CLK_EN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         TWAI_CLK_EN_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         PWM1_CLK_EN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         I2S1_CLK_EN_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_dma_clk_en(&mut self) -> SPI_DMA_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         SPI_DMA_CLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UART2_CLK_EN_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         UART_MEM_CLK_EN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         PWM2_CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN_SPEC> {
         PWM3_CLK_EN_W::new(self, 26)
     }
diff --git a/esp32/src/dport/perip_rst_en.rs b/esp32/src/dport/perip_rst_en.rs
index 4104814c0a..552fd2f7ba 100644
--- a/esp32/src/dport/perip_rst_en.rs
+++ b/esp32/src/dport/perip_rst_en.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn timers_rst(&mut self) -> TIMERS_RST_W<PERIP_RST_EN_SPEC> {
         TIMERS_RST_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_rst(&mut self) -> SPI01_RST_W<PERIP_RST_EN_SPEC> {
         SPI01_RST_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rst(&mut self) -> UART_RST_W<PERIP_RST_EN_SPEC> {
         UART_RST_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_rst(&mut self) -> WDG_RST_W<PERIP_RST_EN_SPEC> {
         WDG_RST_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_rst(&mut self) -> I2S0_RST_W<PERIP_RST_EN_SPEC> {
         I2S0_RST_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_rst(&mut self) -> UART1_RST_W<PERIP_RST_EN_SPEC> {
         UART1_RST_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_rst(&mut self) -> SPI2_RST_W<PERIP_RST_EN_SPEC> {
         SPI2_RST_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c0_ext0_rst(&mut self) -> I2C0_EXT0_RST_W<PERIP_RST_EN_SPEC> {
         I2C0_EXT0_RST_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_rst(&mut self) -> UHCI0_RST_W<PERIP_RST_EN_SPEC> {
         UHCI0_RST_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_rst(&mut self) -> RMT_RST_W<PERIP_RST_EN_SPEC> {
         RMT_RST_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_rst(&mut self) -> PCNT_RST_W<PERIP_RST_EN_SPEC> {
         PCNT_RST_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_rst(&mut self) -> LEDC_RST_W<PERIP_RST_EN_SPEC> {
         LEDC_RST_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_rst(&mut self) -> UHCI1_RST_W<PERIP_RST_EN_SPEC> {
         UHCI1_RST_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_rst(&mut self) -> TIMERGROUP_RST_W<PERIP_RST_EN_SPEC> {
         TIMERGROUP_RST_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_rst(&mut self) -> EFUSE_RST_W<PERIP_RST_EN_SPEC> {
         EFUSE_RST_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_rst(&mut self) -> TIMERGROUP1_RST_W<PERIP_RST_EN_SPEC> {
         TIMERGROUP1_RST_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_rst(&mut self) -> SPI3_RST_W<PERIP_RST_EN_SPEC> {
         SPI3_RST_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_rst(&mut self) -> PWM0_RST_W<PERIP_RST_EN_SPEC> {
         PWM0_RST_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_rst(&mut self) -> I2C_EXT1_RST_W<PERIP_RST_EN_SPEC> {
         I2C_EXT1_RST_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn twai_rst(&mut self) -> TWAI_RST_W<PERIP_RST_EN_SPEC> {
         TWAI_RST_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_rst(&mut self) -> PWM1_RST_W<PERIP_RST_EN_SPEC> {
         PWM1_RST_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_rst(&mut self) -> I2S1_RST_W<PERIP_RST_EN_SPEC> {
         I2S1_RST_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_dma_rst(&mut self) -> SPI_DMA_RST_W<PERIP_RST_EN_SPEC> {
         SPI_DMA_RST_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_rst(&mut self) -> UART2_RST_W<PERIP_RST_EN_SPEC> {
         UART2_RST_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_rst(&mut self) -> UART_MEM_RST_W<PERIP_RST_EN_SPEC> {
         UART_MEM_RST_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_rst(&mut self) -> PWM2_RST_W<PERIP_RST_EN_SPEC> {
         PWM2_RST_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_rst(&mut self) -> PWM3_RST_W<PERIP_RST_EN_SPEC> {
         PWM3_RST_W::new(self, 26)
     }
diff --git a/esp32/src/dport/pro_bb_int_map.rs b/esp32/src/dport/pro_bb_int_map.rs
index 7b2133dda8..483afab3a4 100644
--- a/esp32/src/dport/pro_bb_int_map.rs
+++ b/esp32/src/dport/pro_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bb_int_map(&mut self) -> PRO_BB_INT_MAP_W<PRO_BB_INT_MAP_SPEC> {
         PRO_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_boot_remap_ctrl.rs b/esp32/src/dport/pro_boot_remap_ctrl.rs
index 50d965109c..a0f1c3ed5a 100644
--- a/esp32/src/dport/pro_boot_remap_ctrl.rs
+++ b/esp32/src/dport/pro_boot_remap_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_boot_remap(&mut self) -> PRO_BOOT_REMAP_W<PRO_BOOT_REMAP_CTRL_SPEC> {
         PRO_BOOT_REMAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_bt_bb_int_map.rs b/esp32/src/dport/pro_bt_bb_int_map.rs
index 86f338e12d..18894a00da 100644
--- a/esp32/src/dport/pro_bt_bb_int_map.rs
+++ b/esp32/src/dport/pro_bt_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_bb_int_map(&mut self) -> PRO_BT_BB_INT_MAP_W<PRO_BT_BB_INT_MAP_SPEC> {
         PRO_BT_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_bt_bb_nmi_map.rs b/esp32/src/dport/pro_bt_bb_nmi_map.rs
index f1f45a5a7f..4e5c3fd40f 100644
--- a/esp32/src/dport/pro_bt_bb_nmi_map.rs
+++ b/esp32/src/dport/pro_bt_bb_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_bb_nmi_map(&mut self) -> PRO_BT_BB_NMI_MAP_W<PRO_BT_BB_NMI_MAP_SPEC> {
         PRO_BT_BB_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_bt_mac_int_map.rs b/esp32/src/dport/pro_bt_mac_int_map.rs
index 00109763ce..f452d3013a 100644
--- a/esp32/src/dport/pro_bt_mac_int_map.rs
+++ b/esp32/src/dport/pro_bt_mac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_mac_int_map(&mut self) -> PRO_BT_MAC_INT_MAP_W<PRO_BT_MAC_INT_MAP_SPEC> {
         PRO_BT_MAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_cache_ctrl.rs b/esp32/src/dport/pro_cache_ctrl.rs
index a57e358628..22cef8a971 100644
--- a/esp32/src/dport/pro_cache_ctrl.rs
+++ b/esp32/src/dport/pro_cache_ctrl.rs
@@ -154,61 +154,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mode(&mut self) -> PRO_CACHE_MODE_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_enable(&mut self) -> PRO_CACHE_ENABLE_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_ENABLE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_flush_ena(&mut self) -> PRO_CACHE_FLUSH_ENA_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_FLUSH_ENA_W::new(self, 4)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_lock_0_en(&mut self) -> PRO_CACHE_LOCK_0_EN_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_LOCK_0_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_lock_1_en(&mut self) -> PRO_CACHE_LOCK_1_EN_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_LOCK_1_EN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_lock_2_en(&mut self) -> PRO_CACHE_LOCK_2_EN_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_LOCK_2_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_lock_3_en(&mut self) -> PRO_CACHE_LOCK_3_EN_W<PRO_CACHE_CTRL_SPEC> {
         PRO_CACHE_LOCK_3_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_single_iram_ena(&mut self) -> PRO_SINGLE_IRAM_ENA_W<PRO_CACHE_CTRL_SPEC> {
         PRO_SINGLE_IRAM_ENA_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram_split(&mut self) -> PRO_DRAM_SPLIT_W<PRO_CACHE_CTRL_SPEC> {
         PRO_DRAM_SPLIT_W::new(self, 11)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram_hl(&mut self) -> PRO_DRAM_HL_W<PRO_CACHE_CTRL_SPEC> {
         PRO_DRAM_HL_W::new(self, 16)
     }
diff --git a/esp32/src/dport/pro_cache_ctrl1.rs b/esp32/src/dport/pro_cache_ctrl1.rs
index 8ce5c51c0f..3d659875d7 100644
--- a/esp32/src/dport/pro_cache_ctrl1.rs
+++ b/esp32/src/dport/pro_cache_ctrl1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_iram0(&mut self) -> PRO_CACHE_MASK_IRAM0_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_IRAM0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_iram1(&mut self) -> PRO_CACHE_MASK_IRAM1_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_IRAM1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_irom0(&mut self) -> PRO_CACHE_MASK_IROM0_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_IROM0_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_dram1(&mut self) -> PRO_CACHE_MASK_DRAM1_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_DRAM1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_drom0(&mut self) -> PRO_CACHE_MASK_DROM0_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_DROM0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mask_opsdram(&mut self) -> PRO_CACHE_MASK_OPSDRAM_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MASK_OPSDRAM_W::new(self, 5)
     }
     #[doc = "Bits 6:8"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cmmu_sram_page_mode(&mut self) -> PRO_CMMU_SRAM_PAGE_MODE_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CMMU_SRAM_PAGE_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:10"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cmmu_flash_page_mode(&mut self) -> PRO_CMMU_FLASH_PAGE_MODE_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CMMU_FLASH_PAGE_MODE_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cmmu_force_on(&mut self) -> PRO_CMMU_FORCE_ON_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CMMU_FORCE_ON_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cmmu_pd(&mut self) -> PRO_CMMU_PD_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CMMU_PD_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mmu_ia_clr(&mut self) -> PRO_CACHE_MMU_IA_CLR_W<PRO_CACHE_CTRL1_SPEC> {
         PRO_CACHE_MMU_IA_CLR_W::new(self, 13)
     }
diff --git a/esp32/src/dport/pro_cache_ia_int_map.rs b/esp32/src/dport/pro_cache_ia_int_map.rs
index d403cc062c..6739a1ec71 100644
--- a/esp32/src/dport/pro_cache_ia_int_map.rs
+++ b/esp32/src/dport/pro_cache_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ia_int_map(&mut self) -> PRO_CACHE_IA_INT_MAP_W<PRO_CACHE_IA_INT_MAP_SPEC> {
         PRO_CACHE_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_cache_lock_0_addr.rs b/esp32/src/dport/pro_cache_lock_0_addr.rs
index 861c034a06..dff4726b05 100644
--- a/esp32/src/dport/pro_cache_lock_0_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_0_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<PRO_CACHE_LOCK_0_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<PRO_CACHE_LOCK_0_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<PRO_CACHE_LOCK_0_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/pro_cache_lock_1_addr.rs b/esp32/src/dport/pro_cache_lock_1_addr.rs
index 7b48424971..f0ccf31598 100644
--- a/esp32/src/dport/pro_cache_lock_1_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_1_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<PRO_CACHE_LOCK_1_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<PRO_CACHE_LOCK_1_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<PRO_CACHE_LOCK_1_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/pro_cache_lock_2_addr.rs b/esp32/src/dport/pro_cache_lock_2_addr.rs
index b69fcfb655..451af3d899 100644
--- a/esp32/src/dport/pro_cache_lock_2_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_2_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<PRO_CACHE_LOCK_2_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<PRO_CACHE_LOCK_2_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<PRO_CACHE_LOCK_2_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/pro_cache_lock_3_addr.rs b/esp32/src/dport/pro_cache_lock_3_addr.rs
index 0a0f282983..daf35f5346 100644
--- a/esp32/src/dport/pro_cache_lock_3_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_3_addr.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
-    #[must_use]
     pub fn pre(&mut self) -> PRE_W<PRO_CACHE_LOCK_3_ADDR_SPEC> {
         PRE_W::new(self, 0)
     }
     #[doc = "Bits 14:17"]
     #[inline(always)]
-    #[must_use]
     pub fn min(&mut self) -> MIN_W<PRO_CACHE_LOCK_3_ADDR_SPEC> {
         MIN_W::new(self, 14)
     }
     #[doc = "Bits 18:21"]
     #[inline(always)]
-    #[must_use]
     pub fn max(&mut self) -> MAX_W<PRO_CACHE_LOCK_3_ADDR_SPEC> {
         MAX_W::new(self, 18)
     }
diff --git a/esp32/src/dport/pro_can_int_map.rs b/esp32/src/dport/pro_can_int_map.rs
index 65e58003ed..2691ede81f 100644
--- a/esp32/src/dport/pro_can_int_map.rs
+++ b/esp32/src/dport/pro_can_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_can_int_map(&mut self) -> PRO_CAN_INT_MAP_W<PRO_CAN_INT_MAP_SPEC> {
         PRO_CAN_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
index 27d8745590..aa62537938 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_0_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_0_MAP_W<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
index 67672558cf..b3db597d68 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_1_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_1_MAP_W<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
index 08d714b67c..d95064e381 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_2_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_2_MAP_W<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
index d8c316e86f..27c9bf0df6 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_3_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_3_MAP_W<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_record_ctrl.rs b/esp32/src/dport/pro_cpu_record_ctrl.rs
index f3a799af2c..2f71ea7531 100644
--- a/esp32/src/dport/pro_cpu_record_ctrl.rs
+++ b/esp32/src/dport/pro_cpu_record_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_record_enable(&mut self) -> PRO_CPU_RECORD_ENABLE_W<PRO_CPU_RECORD_CTRL_SPEC> {
         PRO_CPU_RECORD_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_record_disable(&mut self) -> PRO_CPU_RECORD_DISABLE_W<PRO_CPU_RECORD_CTRL_SPEC> {
         PRO_CPU_RECORD_DISABLE_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_pdebug_enable(&mut self) -> PRO_CPU_PDEBUG_ENABLE_W<PRO_CPU_RECORD_CTRL_SPEC> {
         PRO_CPU_PDEBUG_ENABLE_W::new(self, 8)
     }
diff --git a/esp32/src/dport/pro_cpu_record_pdebugdata.rs b/esp32/src/dport/pro_cpu_record_pdebugdata.rs
index 801ddbb104..a8253bafb8 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugdata.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugdata.rs
@@ -419,7 +419,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep_other(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_OTHER_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -427,7 +426,6 @@ impl W {
     }
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_excvec(
         &mut self,
     ) -> RECORD_PDEBUGDATA_EXCVEC_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -435,7 +433,6 @@ impl W {
     }
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_sr(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_SR_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -443,7 +440,6 @@ impl W {
     }
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_rer(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_RER_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -451,7 +447,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_buff(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_BUFF_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -459,7 +454,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_wer(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_WER_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -467,7 +461,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_buffconfl(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_BUFFCONFL_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -475,7 +468,6 @@ impl W {
     }
     #[doc = "Bits 2:13"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_er(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_ER_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -483,7 +475,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_dcm(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_DCM_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -491,7 +482,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_lsu(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_LSU_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -499,7 +489,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_icm(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_ICM_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -507,7 +496,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_irambusy(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_IRAMBUSY_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -515,7 +503,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep_lsu(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_LSU_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -523,7 +510,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_ipif(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_IPIF_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -531,7 +517,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_rsr(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_RSR_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -539,7 +524,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_tie(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_TIE_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -547,7 +531,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_wsr(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_WSR_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -555,7 +538,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_run(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_RUN_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -563,7 +545,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_insntype_xsr(
         &mut self,
     ) -> RECORD_PDEBUGDATA_INSNTYPE_XSR_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -571,7 +552,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep_str(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_STR_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -579,7 +559,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -587,7 +566,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_bpifetch(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_BPIFETCH_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -595,7 +573,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_l32r(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_L32R_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -603,7 +580,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_lsproc(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_LSPROC_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -611,7 +587,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_bpload(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_BPLOAD_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -619,7 +594,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep_memw(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_MEMW_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -627,7 +601,6 @@ impl W {
     }
     #[doc = "Bits 16:21"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_exccause(
         &mut self,
     ) -> RECORD_PDEBUGDATA_EXCCAUSE_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -635,7 +608,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_bankconfl(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_BANKCONFL_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -643,7 +615,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_dep_halt(
         &mut self,
     ) -> RECORD_PDEBUGDATA_DEP_HALT_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -651,7 +622,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_itermul(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_ITERMUL_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
@@ -659,7 +629,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugdata_stall_iterdiv(
         &mut self,
     ) -> RECORD_PDEBUGDATA_STALL_ITERDIV_W<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_record_pdebuginst.rs b/esp32/src/dport/pro_cpu_record_pdebuginst.rs
index 79134d66e6..1569fbd9fb 100644
--- a/esp32/src/dport/pro_cpu_record_pdebuginst.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebuginst.rs
@@ -75,7 +75,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebuginst_sz(
         &mut self,
     ) -> RECORD_PDEBUGINST_SZ_W<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
@@ -83,7 +82,6 @@ impl W {
     }
     #[doc = "Bits 12:14"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebuginst_isrc(
         &mut self,
     ) -> RECORD_PDEBUGINST_ISRC_W<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
@@ -91,7 +89,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebuginst_loop_rep(
         &mut self,
     ) -> RECORD_PDEBUGINST_LOOP_REP_W<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
@@ -99,7 +96,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebuginst_loop(
         &mut self,
     ) -> RECORD_PDEBUGINST_LOOP_W<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
@@ -107,7 +103,6 @@ impl W {
     }
     #[doc = "Bits 24:27"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebuginst_cintl(
         &mut self,
     ) -> RECORD_PDEBUGINST_CINTL_W<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs b/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
index a331c28c5e..39a1e8148a 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
@@ -131,7 +131,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_type(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_TYPE_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -139,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_sz(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_SZ_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -147,7 +145,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_dtlbm(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_DTLBM_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -155,7 +152,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_dcm(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_DCM_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -163,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_dch(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_DCH_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -171,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_uc(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_UC_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -179,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_wb(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_WB_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -187,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_coh(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_COH_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -195,7 +187,6 @@ impl W {
     }
     #[doc = "Bits 17:18"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_stcoh(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_STCOH_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
@@ -203,7 +194,6 @@ impl W {
     }
     #[doc = "Bits 20:23"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugls0stat_tgt(
         &mut self,
     ) -> RECORD_PDEBUGLS0STAT_TGT_W<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
diff --git a/esp32/src/dport/pro_cpu_record_pdebugstatus.rs b/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
index 25b14953ba..45f27d8c67 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugstatus_bbcause(
         &mut self,
     ) -> RECORD_PDEBUGSTATUS_BBCAUSE_W<PRO_CPU_RECORD_PDEBUGSTATUS_SPEC> {
@@ -56,7 +55,6 @@ impl W {
     }
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn record_pdebugstatus_insntype(
         &mut self,
     ) -> RECORD_PDEBUGSTATUS_INSNTYPE_W<PRO_CPU_RECORD_PDEBUGSTATUS_SPEC> {
diff --git a/esp32/src/dport/pro_dcache_dbug0.rs b/esp32/src/dport/pro_dcache_dbug0.rs
index b73260d638..b4ea46a8fb 100644
--- a/esp32/src/dport/pro_dcache_dbug0.rs
+++ b/esp32/src/dport/pro_dcache_dbug0.rs
@@ -88,7 +88,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_slave_wdata(&mut self) -> PRO_SLAVE_WDATA_W<PRO_DCACHE_DBUG0_SPEC> {
         PRO_SLAVE_WDATA_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_dcache_dbug3.rs b/esp32/src/dport/pro_dcache_dbug3.rs
index 26e677c029..ff42bffc92 100644
--- a/esp32/src/dport/pro_dcache_dbug3.rs
+++ b/esp32/src/dport/pro_dcache_dbug3.rs
@@ -122,7 +122,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_opposite(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_W<PRO_DCACHE_DBUG3_SPEC> {
@@ -130,7 +129,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_dram1(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_DRAM1_W<PRO_DCACHE_DBUG3_SPEC> {
@@ -138,7 +136,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_irom0(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_IROM0_W<PRO_DCACHE_DBUG3_SPEC> {
@@ -146,7 +143,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_iram1(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_IRAM1_W<PRO_DCACHE_DBUG3_SPEC> {
@@ -154,7 +150,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_iram0(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_IRAM0_W<PRO_DCACHE_DBUG3_SPEC> {
@@ -162,7 +157,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_disabled_cache_ia_drom0(
         &mut self,
     ) -> PRO_CPU_DISABLED_CACHE_IA_DROM0_W<PRO_DCACHE_DBUG3_SPEC> {
diff --git a/esp32/src/dport/pro_dport_apb_mask0.rs b/esp32/src/dport/pro_dport_apb_mask0.rs
index 7c77b4ffbb..30f8136ac9 100644
--- a/esp32/src/dport/pro_dport_apb_mask0.rs
+++ b/esp32/src/dport/pro_dport_apb_mask0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn prodport_apb_mask0(&mut self) -> PRODPORT_APB_MASK0_W<PRO_DPORT_APB_MASK0_SPEC> {
         PRODPORT_APB_MASK0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_dport_apb_mask1.rs b/esp32/src/dport/pro_dport_apb_mask1.rs
index e7cff38da7..aac3ee5e51 100644
--- a/esp32/src/dport/pro_dport_apb_mask1.rs
+++ b/esp32/src/dport/pro_dport_apb_mask1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn prodport_apb_mask1(&mut self) -> PRODPORT_APB_MASK1_W<PRO_DPORT_APB_MASK1_SPEC> {
         PRODPORT_APB_MASK1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_efuse_int_map.rs b/esp32/src/dport/pro_efuse_int_map.rs
index 2f4f68b56d..992dac7e09 100644
--- a/esp32/src/dport/pro_efuse_int_map.rs
+++ b/esp32/src/dport/pro_efuse_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_efuse_int_map(&mut self) -> PRO_EFUSE_INT_MAP_W<PRO_EFUSE_INT_MAP_SPEC> {
         PRO_EFUSE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_emac_int_map.rs b/esp32/src/dport/pro_emac_int_map.rs
index b946d44d09..2f4a338cfa 100644
--- a/esp32/src/dport/pro_emac_int_map.rs
+++ b/esp32/src/dport/pro_emac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_emac_int_map(&mut self) -> PRO_EMAC_INT_MAP_W<PRO_EMAC_INT_MAP_SPEC> {
         PRO_EMAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_gpio_interrupt_map.rs b/esp32/src/dport/pro_gpio_interrupt_map.rs
index ee4af59c84..e9ddf63923 100644
--- a/esp32/src/dport/pro_gpio_interrupt_map.rs
+++ b/esp32/src/dport/pro_gpio_interrupt_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_pro_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_PRO_MAP_W<PRO_GPIO_INTERRUPT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs b/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
index aad671b32c..82b1813b1d 100644
--- a/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
+++ b/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_pro_nmi_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_PRO_NMI_MAP_W<PRO_GPIO_INTERRUPT_NMI_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_i2c_ext0_intr_map.rs b/esp32/src/dport/pro_i2c_ext0_intr_map.rs
index a8799de9f2..ff9820b992 100644
--- a/esp32/src/dport/pro_i2c_ext0_intr_map.rs
+++ b/esp32/src/dport/pro_i2c_ext0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2c_ext0_intr_map(&mut self) -> PRO_I2C_EXT0_INTR_MAP_W<PRO_I2C_EXT0_INTR_MAP_SPEC> {
         PRO_I2C_EXT0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_i2c_ext1_intr_map.rs b/esp32/src/dport/pro_i2c_ext1_intr_map.rs
index 78b256f42f..cf5d011722 100644
--- a/esp32/src/dport/pro_i2c_ext1_intr_map.rs
+++ b/esp32/src/dport/pro_i2c_ext1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2c_ext1_intr_map(&mut self) -> PRO_I2C_EXT1_INTR_MAP_W<PRO_I2C_EXT1_INTR_MAP_SPEC> {
         PRO_I2C_EXT1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_i2s0_int_map.rs b/esp32/src/dport/pro_i2s0_int_map.rs
index e60e0e3e3c..8021f9981d 100644
--- a/esp32/src/dport/pro_i2s0_int_map.rs
+++ b/esp32/src/dport/pro_i2s0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2s0_int_map(&mut self) -> PRO_I2S0_INT_MAP_W<PRO_I2S0_INT_MAP_SPEC> {
         PRO_I2S0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_i2s1_int_map.rs b/esp32/src/dport/pro_i2s1_int_map.rs
index d0f36694f1..9d0747d40d 100644
--- a/esp32/src/dport/pro_i2s1_int_map.rs
+++ b/esp32/src/dport/pro_i2s1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2s1_int_map(&mut self) -> PRO_I2S1_INT_MAP_W<PRO_I2S1_INT_MAP_SPEC> {
         PRO_I2S1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_intrusion_ctrl.rs b/esp32/src/dport/pro_intrusion_ctrl.rs
index 0c3bd3b4ba..ab99a5161e 100644
--- a/esp32/src/dport/pro_intrusion_ctrl.rs
+++ b/esp32/src/dport/pro_intrusion_ctrl.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_intrusion_record_reset_n(
         &mut self,
     ) -> PRO_INTRUSION_RECORD_RESET_N_W<PRO_INTRUSION_CTRL_SPEC> {
diff --git a/esp32/src/dport/pro_ledc_int_map.rs b/esp32/src/dport/pro_ledc_int_map.rs
index 48e3d8743c..d80244eb9c 100644
--- a/esp32/src/dport/pro_ledc_int_map.rs
+++ b/esp32/src/dport/pro_ledc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ledc_int_map(&mut self) -> PRO_LEDC_INT_MAP_W<PRO_LEDC_INT_MAP_SPEC> {
         PRO_LEDC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_mac_intr_map.rs b/esp32/src/dport/pro_mac_intr_map.rs
index abc879cee7..f6912cdb06 100644
--- a/esp32/src/dport/pro_mac_intr_map.rs
+++ b/esp32/src/dport/pro_mac_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mac_intr_map(&mut self) -> PRO_MAC_INTR_MAP_W<PRO_MAC_INTR_MAP_SPEC> {
         PRO_MAC_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_mac_nmi_map.rs b/esp32/src/dport/pro_mac_nmi_map.rs
index fdb05aab02..4ff29c8750 100644
--- a/esp32/src/dport/pro_mac_nmi_map.rs
+++ b/esp32/src/dport/pro_mac_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mac_nmi_map(&mut self) -> PRO_MAC_NMI_MAP_W<PRO_MAC_NMI_MAP_SPEC> {
         PRO_MAC_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_mmu_ia_int_map.rs b/esp32/src/dport/pro_mmu_ia_int_map.rs
index ce66ca0d81..e84ac2b9cd 100644
--- a/esp32/src/dport/pro_mmu_ia_int_map.rs
+++ b/esp32/src/dport/pro_mmu_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mmu_ia_int_map(&mut self) -> PRO_MMU_IA_INT_MAP_W<PRO_MMU_IA_INT_MAP_SPEC> {
         PRO_MMU_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_mpu_ia_int_map.rs b/esp32/src/dport/pro_mpu_ia_int_map.rs
index 549d529e7f..ae82f0bcf5 100644
--- a/esp32/src/dport/pro_mpu_ia_int_map.rs
+++ b/esp32/src/dport/pro_mpu_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mpu_ia_int_map(&mut self) -> PRO_MPU_IA_INT_MAP_W<PRO_MPU_IA_INT_MAP_SPEC> {
         PRO_MPU_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_pcnt_intr_map.rs b/esp32/src/dport/pro_pcnt_intr_map.rs
index 13294fb8f4..e222e12184 100644
--- a/esp32/src/dport/pro_pcnt_intr_map.rs
+++ b/esp32/src/dport/pro_pcnt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pcnt_intr_map(&mut self) -> PRO_PCNT_INTR_MAP_W<PRO_PCNT_INTR_MAP_SPEC> {
         PRO_PCNT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_pwm0_intr_map.rs b/esp32/src/dport/pro_pwm0_intr_map.rs
index d8b194f10a..5d7970c313 100644
--- a/esp32/src/dport/pro_pwm0_intr_map.rs
+++ b/esp32/src/dport/pro_pwm0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm0_intr_map(&mut self) -> PRO_PWM0_INTR_MAP_W<PRO_PWM0_INTR_MAP_SPEC> {
         PRO_PWM0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_pwm1_intr_map.rs b/esp32/src/dport/pro_pwm1_intr_map.rs
index 7076581a20..19a4b44613 100644
--- a/esp32/src/dport/pro_pwm1_intr_map.rs
+++ b/esp32/src/dport/pro_pwm1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm1_intr_map(&mut self) -> PRO_PWM1_INTR_MAP_W<PRO_PWM1_INTR_MAP_SPEC> {
         PRO_PWM1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_pwm2_intr_map.rs b/esp32/src/dport/pro_pwm2_intr_map.rs
index 561c653a56..2f59e31532 100644
--- a/esp32/src/dport/pro_pwm2_intr_map.rs
+++ b/esp32/src/dport/pro_pwm2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm2_intr_map(&mut self) -> PRO_PWM2_INTR_MAP_W<PRO_PWM2_INTR_MAP_SPEC> {
         PRO_PWM2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_pwm3_intr_map.rs b/esp32/src/dport/pro_pwm3_intr_map.rs
index 8a0bacc471..ef010e0f46 100644
--- a/esp32/src/dport/pro_pwm3_intr_map.rs
+++ b/esp32/src/dport/pro_pwm3_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm3_intr_map(&mut self) -> PRO_PWM3_INTR_MAP_W<PRO_PWM3_INTR_MAP_SPEC> {
         PRO_PWM3_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rmt_intr_map.rs b/esp32/src/dport/pro_rmt_intr_map.rs
index 22fd70238c..9666aadc14 100644
--- a/esp32/src/dport/pro_rmt_intr_map.rs
+++ b/esp32/src/dport/pro_rmt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rmt_intr_map(&mut self) -> PRO_RMT_INTR_MAP_W<PRO_RMT_INTR_MAP_SPEC> {
         PRO_RMT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rsa_intr_map.rs b/esp32/src/dport/pro_rsa_intr_map.rs
index 778ee4a611..e2b85db008 100644
--- a/esp32/src/dport/pro_rsa_intr_map.rs
+++ b/esp32/src/dport/pro_rsa_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rsa_intr_map(&mut self) -> PRO_RSA_INTR_MAP_W<PRO_RSA_INTR_MAP_SPEC> {
         PRO_RSA_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rtc_core_intr_map.rs b/esp32/src/dport/pro_rtc_core_intr_map.rs
index cbe76bfd7e..2f75b50559 100644
--- a/esp32/src/dport/pro_rtc_core_intr_map.rs
+++ b/esp32/src/dport/pro_rtc_core_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rtc_core_intr_map(&mut self) -> PRO_RTC_CORE_INTR_MAP_W<PRO_RTC_CORE_INTR_MAP_SPEC> {
         PRO_RTC_CORE_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rwble_irq_map.rs b/esp32/src/dport/pro_rwble_irq_map.rs
index c27ea91bbd..b5a85213e7 100644
--- a/esp32/src/dport/pro_rwble_irq_map.rs
+++ b/esp32/src/dport/pro_rwble_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwble_irq_map(&mut self) -> PRO_RWBLE_IRQ_MAP_W<PRO_RWBLE_IRQ_MAP_SPEC> {
         PRO_RWBLE_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rwble_nmi_map.rs b/esp32/src/dport/pro_rwble_nmi_map.rs
index 9fe487a020..b14b55ea7d 100644
--- a/esp32/src/dport/pro_rwble_nmi_map.rs
+++ b/esp32/src/dport/pro_rwble_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwble_nmi_map(&mut self) -> PRO_RWBLE_NMI_MAP_W<PRO_RWBLE_NMI_MAP_SPEC> {
         PRO_RWBLE_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rwbt_irq_map.rs b/esp32/src/dport/pro_rwbt_irq_map.rs
index 0ca6f34149..38b2deff79 100644
--- a/esp32/src/dport/pro_rwbt_irq_map.rs
+++ b/esp32/src/dport/pro_rwbt_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwbt_irq_map(&mut self) -> PRO_RWBT_IRQ_MAP_W<PRO_RWBT_IRQ_MAP_SPEC> {
         PRO_RWBT_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_rwbt_nmi_map.rs b/esp32/src/dport/pro_rwbt_nmi_map.rs
index f8184b32f5..d5477d429a 100644
--- a/esp32/src/dport/pro_rwbt_nmi_map.rs
+++ b/esp32/src/dport/pro_rwbt_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwbt_nmi_map(&mut self) -> PRO_RWBT_NMI_MAP_W<PRO_RWBT_NMI_MAP_SPEC> {
         PRO_RWBT_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_sdio_host_interrupt_map.rs b/esp32/src/dport/pro_sdio_host_interrupt_map.rs
index d958c288a4..9904a32f61 100644
--- a/esp32/src/dport/pro_sdio_host_interrupt_map.rs
+++ b/esp32/src/dport/pro_sdio_host_interrupt_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_sdio_host_interrupt_map(
         &mut self,
     ) -> PRO_SDIO_HOST_INTERRUPT_MAP_W<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_slc0_intr_map.rs b/esp32/src/dport/pro_slc0_intr_map.rs
index ea96de9ecb..60e7883443 100644
--- a/esp32/src/dport/pro_slc0_intr_map.rs
+++ b/esp32/src/dport/pro_slc0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_slc0_intr_map(&mut self) -> PRO_SLC0_INTR_MAP_W<PRO_SLC0_INTR_MAP_SPEC> {
         PRO_SLC0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_slc1_intr_map.rs b/esp32/src/dport/pro_slc1_intr_map.rs
index edee196688..2c6d68b1c3 100644
--- a/esp32/src/dport/pro_slc1_intr_map.rs
+++ b/esp32/src/dport/pro_slc1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_slc1_intr_map(&mut self) -> PRO_SLC1_INTR_MAP_W<PRO_SLC1_INTR_MAP_SPEC> {
         PRO_SLC1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi1_dma_int_map.rs b/esp32/src/dport/pro_spi1_dma_int_map.rs
index f12b0dcf0d..68270aa2ac 100644
--- a/esp32/src/dport/pro_spi1_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi1_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi1_dma_int_map(&mut self) -> PRO_SPI1_DMA_INT_MAP_W<PRO_SPI1_DMA_INT_MAP_SPEC> {
         PRO_SPI1_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi2_dma_int_map.rs b/esp32/src/dport/pro_spi2_dma_int_map.rs
index 62f71b3724..909a93338a 100644
--- a/esp32/src/dport/pro_spi2_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi2_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi2_dma_int_map(&mut self) -> PRO_SPI2_DMA_INT_MAP_W<PRO_SPI2_DMA_INT_MAP_SPEC> {
         PRO_SPI2_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi3_dma_int_map.rs b/esp32/src/dport/pro_spi3_dma_int_map.rs
index 335688ace4..032c4e53ef 100644
--- a/esp32/src/dport/pro_spi3_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi3_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi3_dma_int_map(&mut self) -> PRO_SPI3_DMA_INT_MAP_W<PRO_SPI3_DMA_INT_MAP_SPEC> {
         PRO_SPI3_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi_intr_0_map.rs b/esp32/src/dport/pro_spi_intr_0_map.rs
index be7891b10e..f40eaf4901 100644
--- a/esp32/src/dport/pro_spi_intr_0_map.rs
+++ b/esp32/src/dport/pro_spi_intr_0_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_0_map(&mut self) -> PRO_SPI_INTR_0_MAP_W<PRO_SPI_INTR_0_MAP_SPEC> {
         PRO_SPI_INTR_0_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi_intr_1_map.rs b/esp32/src/dport/pro_spi_intr_1_map.rs
index 3070c0fdea..4a966d01e5 100644
--- a/esp32/src/dport/pro_spi_intr_1_map.rs
+++ b/esp32/src/dport/pro_spi_intr_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_1_map(&mut self) -> PRO_SPI_INTR_1_MAP_W<PRO_SPI_INTR_1_MAP_SPEC> {
         PRO_SPI_INTR_1_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi_intr_2_map.rs b/esp32/src/dport/pro_spi_intr_2_map.rs
index 3c119a8c05..9a4c8e4f0b 100644
--- a/esp32/src/dport/pro_spi_intr_2_map.rs
+++ b/esp32/src/dport/pro_spi_intr_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_2_map(&mut self) -> PRO_SPI_INTR_2_MAP_W<PRO_SPI_INTR_2_MAP_SPEC> {
         PRO_SPI_INTR_2_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_spi_intr_3_map.rs b/esp32/src/dport/pro_spi_intr_3_map.rs
index b5e26ab237..08997c953a 100644
--- a/esp32/src/dport/pro_spi_intr_3_map.rs
+++ b/esp32/src/dport/pro_spi_intr_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_3_map(&mut self) -> PRO_SPI_INTR_3_MAP_W<PRO_SPI_INTR_3_MAP_SPEC> {
         PRO_SPI_INTR_3_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_tg1_lact_edge_int_map.rs b/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
index 0e100ac81d..532df2e217 100644
--- a/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_lact_edge_int_map(
         &mut self,
     ) -> PRO_TG1_LACT_EDGE_INT_MAP_W<PRO_TG1_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_lact_level_int_map.rs b/esp32/src/dport/pro_tg1_lact_level_int_map.rs
index 8833e15b74..fc93d99685 100644
--- a/esp32/src/dport/pro_tg1_lact_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_lact_level_int_map(
         &mut self,
     ) -> PRO_TG1_LACT_LEVEL_INT_MAP_W<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_t0_edge_int_map.rs b/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
index bd81de1fd1..2e0b0bcb3f 100644
--- a/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t0_edge_int_map(
         &mut self,
     ) -> PRO_TG1_T0_EDGE_INT_MAP_W<PRO_TG1_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_t0_level_int_map.rs b/esp32/src/dport/pro_tg1_t0_level_int_map.rs
index 560e953e45..9fc229ddc4 100644
--- a/esp32/src/dport/pro_tg1_t0_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t0_level_int_map(
         &mut self,
     ) -> PRO_TG1_T0_LEVEL_INT_MAP_W<PRO_TG1_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_t1_edge_int_map.rs b/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
index e6b253004a..86d7c77fee 100644
--- a/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t1_edge_int_map(
         &mut self,
     ) -> PRO_TG1_T1_EDGE_INT_MAP_W<PRO_TG1_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_t1_level_int_map.rs b/esp32/src/dport/pro_tg1_t1_level_int_map.rs
index beb0c3e826..d428b0dd0e 100644
--- a/esp32/src/dport/pro_tg1_t1_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t1_level_int_map(
         &mut self,
     ) -> PRO_TG1_T1_LEVEL_INT_MAP_W<PRO_TG1_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs b/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
index 617d4fec28..23287d5608 100644
--- a/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_wdt_edge_int_map(
         &mut self,
     ) -> PRO_TG1_WDT_EDGE_INT_MAP_W<PRO_TG1_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg1_wdt_level_int_map.rs b/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
index 0ae6facf26..9413a1f0e4 100644
--- a/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_wdt_level_int_map(
         &mut self,
     ) -> PRO_TG1_WDT_LEVEL_INT_MAP_W<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_lact_edge_int_map.rs b/esp32/src/dport/pro_tg_lact_edge_int_map.rs
index 9a15535af0..fd2ed70090 100644
--- a/esp32/src/dport/pro_tg_lact_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_lact_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_lact_edge_int_map(
         &mut self,
     ) -> PRO_TG_LACT_EDGE_INT_MAP_W<PRO_TG_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_lact_level_int_map.rs b/esp32/src/dport/pro_tg_lact_level_int_map.rs
index 5b25fe3820..074bf4957b 100644
--- a/esp32/src/dport/pro_tg_lact_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_lact_level_int_map(
         &mut self,
     ) -> PRO_TG_LACT_LEVEL_INT_MAP_W<PRO_TG_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_t0_edge_int_map.rs b/esp32/src/dport/pro_tg_t0_edge_int_map.rs
index d65cae8b3b..e7edeebe06 100644
--- a/esp32/src/dport/pro_tg_t0_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t0_edge_int_map(
         &mut self,
     ) -> PRO_TG_T0_EDGE_INT_MAP_W<PRO_TG_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_t0_level_int_map.rs b/esp32/src/dport/pro_tg_t0_level_int_map.rs
index a82a07c85a..170d476dd1 100644
--- a/esp32/src/dport/pro_tg_t0_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t0_level_int_map(
         &mut self,
     ) -> PRO_TG_T0_LEVEL_INT_MAP_W<PRO_TG_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_t1_edge_int_map.rs b/esp32/src/dport/pro_tg_t1_edge_int_map.rs
index ee860a074c..157a1bcc87 100644
--- a/esp32/src/dport/pro_tg_t1_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t1_edge_int_map(
         &mut self,
     ) -> PRO_TG_T1_EDGE_INT_MAP_W<PRO_TG_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_t1_level_int_map.rs b/esp32/src/dport/pro_tg_t1_level_int_map.rs
index 3e2bb19cbd..bb553ae732 100644
--- a/esp32/src/dport/pro_tg_t1_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t1_level_int_map(
         &mut self,
     ) -> PRO_TG_T1_LEVEL_INT_MAP_W<PRO_TG_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_wdt_edge_int_map.rs b/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
index ad8a291107..52791cc730 100644
--- a/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_wdt_edge_int_map(
         &mut self,
     ) -> PRO_TG_WDT_EDGE_INT_MAP_W<PRO_TG_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_tg_wdt_level_int_map.rs b/esp32/src/dport/pro_tg_wdt_level_int_map.rs
index 3b02ceac72..6ee1124530 100644
--- a/esp32/src/dport/pro_tg_wdt_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_wdt_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_wdt_level_int_map(
         &mut self,
     ) -> PRO_TG_WDT_LEVEL_INT_MAP_W<PRO_TG_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32/src/dport/pro_timer_int1_map.rs b/esp32/src/dport/pro_timer_int1_map.rs
index 2a12d3692c..7547b33a89 100644
--- a/esp32/src/dport/pro_timer_int1_map.rs
+++ b/esp32/src/dport/pro_timer_int1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_timer_int1_map(&mut self) -> PRO_TIMER_INT1_MAP_W<PRO_TIMER_INT1_MAP_SPEC> {
         PRO_TIMER_INT1_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_timer_int2_map.rs b/esp32/src/dport/pro_timer_int2_map.rs
index a357206abc..33264b0b14 100644
--- a/esp32/src/dport/pro_timer_int2_map.rs
+++ b/esp32/src/dport/pro_timer_int2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_timer_int2_map(&mut self) -> PRO_TIMER_INT2_MAP_W<PRO_TIMER_INT2_MAP_SPEC> {
         PRO_TIMER_INT2_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_tracemem_ena.rs b/esp32/src/dport/pro_tracemem_ena.rs
index f689797397..7046c4fa02 100644
--- a/esp32/src/dport/pro_tracemem_ena.rs
+++ b/esp32/src/dport/pro_tracemem_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tracemem_ena(&mut self) -> PRO_TRACEMEM_ENA_W<PRO_TRACEMEM_ENA_SPEC> {
         PRO_TRACEMEM_ENA_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_uart1_intr_map.rs b/esp32/src/dport/pro_uart1_intr_map.rs
index 95dc4e8007..e3c16c67ef 100644
--- a/esp32/src/dport/pro_uart1_intr_map.rs
+++ b/esp32/src/dport/pro_uart1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart1_intr_map(&mut self) -> PRO_UART1_INTR_MAP_W<PRO_UART1_INTR_MAP_SPEC> {
         PRO_UART1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_uart2_intr_map.rs b/esp32/src/dport/pro_uart2_intr_map.rs
index 1dac694acb..b10296a49f 100644
--- a/esp32/src/dport/pro_uart2_intr_map.rs
+++ b/esp32/src/dport/pro_uart2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart2_intr_map(&mut self) -> PRO_UART2_INTR_MAP_W<PRO_UART2_INTR_MAP_SPEC> {
         PRO_UART2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_uart_intr_map.rs b/esp32/src/dport/pro_uart_intr_map.rs
index a7a2d00c56..e169eb8466 100644
--- a/esp32/src/dport/pro_uart_intr_map.rs
+++ b/esp32/src/dport/pro_uart_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart_intr_map(&mut self) -> PRO_UART_INTR_MAP_W<PRO_UART_INTR_MAP_SPEC> {
         PRO_UART_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_uhci0_intr_map.rs b/esp32/src/dport/pro_uhci0_intr_map.rs
index 5a04441763..c5f3f18b44 100644
--- a/esp32/src/dport/pro_uhci0_intr_map.rs
+++ b/esp32/src/dport/pro_uhci0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uhci0_intr_map(&mut self) -> PRO_UHCI0_INTR_MAP_W<PRO_UHCI0_INTR_MAP_SPEC> {
         PRO_UHCI0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_uhci1_intr_map.rs b/esp32/src/dport/pro_uhci1_intr_map.rs
index be2c274802..be4c0d222b 100644
--- a/esp32/src/dport/pro_uhci1_intr_map.rs
+++ b/esp32/src/dport/pro_uhci1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uhci1_intr_map(&mut self) -> PRO_UHCI1_INTR_MAP_W<PRO_UHCI1_INTR_MAP_SPEC> {
         PRO_UHCI1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_vecbase_ctrl.rs b/esp32/src/dport/pro_vecbase_ctrl.rs
index c5c1c6e597..6b180e4e3c 100644
--- a/esp32/src/dport/pro_vecbase_ctrl.rs
+++ b/esp32/src/dport/pro_vecbase_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_out_vecbase_sel(&mut self) -> PRO_OUT_VECBASE_SEL_W<PRO_VECBASE_CTRL_SPEC> {
         PRO_OUT_VECBASE_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_vecbase_set.rs b/esp32/src/dport/pro_vecbase_set.rs
index 47826e3e89..5a50355752 100644
--- a/esp32/src/dport/pro_vecbase_set.rs
+++ b/esp32/src/dport/pro_vecbase_set.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_out_vecbase(&mut self) -> PRO_OUT_VECBASE_W<PRO_VECBASE_SET_SPEC> {
         PRO_OUT_VECBASE_W::new(self, 0)
     }
diff --git a/esp32/src/dport/pro_wdg_int_map.rs b/esp32/src/dport/pro_wdg_int_map.rs
index 1c278f1e5c..5f1ea75bf3 100644
--- a/esp32/src/dport/pro_wdg_int_map.rs
+++ b/esp32/src/dport/pro_wdg_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_wdg_int_map(&mut self) -> PRO_WDG_INT_MAP_W<PRO_WDG_INT_MAP_SPEC> {
         PRO_WDG_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32/src/dport/rom_fo_ctrl.rs b/esp32/src/dport/rom_fo_ctrl.rs
index 01ae0ae57a..42f903723b 100644
--- a/esp32/src/dport/rom_fo_ctrl.rs
+++ b/esp32/src/dport/rom_fo_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rom_fo(&mut self) -> PRO_ROM_FO_W<ROM_FO_CTRL_SPEC> {
         PRO_ROM_FO_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rom_fo(&mut self) -> APP_ROM_FO_W<ROM_FO_CTRL_SPEC> {
         APP_ROM_FO_W::new(self, 1)
     }
     #[doc = "Bits 2:7"]
     #[inline(always)]
-    #[must_use]
     pub fn share_rom_fo(&mut self) -> SHARE_ROM_FO_W<ROM_FO_CTRL_SPEC> {
         SHARE_ROM_FO_W::new(self, 2)
     }
diff --git a/esp32/src/dport/rom_mpu_ena.rs b/esp32/src/dport/rom_mpu_ena.rs
index af181664a6..00abe31d6e 100644
--- a/esp32/src/dport/rom_mpu_ena.rs
+++ b/esp32/src/dport/rom_mpu_ena.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn share_rom_mpu_ena(&mut self) -> SHARE_ROM_MPU_ENA_W<ROM_MPU_ENA_SPEC> {
         SHARE_ROM_MPU_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rom_mpu_ena(&mut self) -> PRO_ROM_MPU_ENA_W<ROM_MPU_ENA_SPEC> {
         PRO_ROM_MPU_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rom_mpu_ena(&mut self) -> APP_ROM_MPU_ENA_W<ROM_MPU_ENA_SPEC> {
         APP_ROM_MPU_ENA_W::new(self, 2)
     }
diff --git a/esp32/src/dport/rom_mpu_table0.rs b/esp32/src/dport/rom_mpu_table0.rs
index 96b877bdc4..cd2343ed6f 100644
--- a/esp32/src/dport/rom_mpu_table0.rs
+++ b/esp32/src/dport/rom_mpu_table0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_mpu_table0(&mut self) -> ROM_MPU_TABLE0_W<ROM_MPU_TABLE0_SPEC> {
         ROM_MPU_TABLE0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/rom_mpu_table1.rs b/esp32/src/dport/rom_mpu_table1.rs
index a692c83414..43be4d2d5a 100644
--- a/esp32/src/dport/rom_mpu_table1.rs
+++ b/esp32/src/dport/rom_mpu_table1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_mpu_table1(&mut self) -> ROM_MPU_TABLE1_W<ROM_MPU_TABLE1_SPEC> {
         ROM_MPU_TABLE1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/rom_mpu_table2.rs b/esp32/src/dport/rom_mpu_table2.rs
index afc73d23f8..1203dab14a 100644
--- a/esp32/src/dport/rom_mpu_table2.rs
+++ b/esp32/src/dport/rom_mpu_table2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_mpu_table2(&mut self) -> ROM_MPU_TABLE2_W<ROM_MPU_TABLE2_SPEC> {
         ROM_MPU_TABLE2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/rom_mpu_table3.rs b/esp32/src/dport/rom_mpu_table3.rs
index 529539b1d5..c4b6bc4349 100644
--- a/esp32/src/dport/rom_mpu_table3.rs
+++ b/esp32/src/dport/rom_mpu_table3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_mpu_table3(&mut self) -> ROM_MPU_TABLE3_W<ROM_MPU_TABLE3_SPEC> {
         ROM_MPU_TABLE3_W::new(self, 0)
     }
diff --git a/esp32/src/dport/rom_pd_ctrl.rs b/esp32/src/dport/rom_pd_ctrl.rs
index 08e7564eca..3af3b2c3dc 100644
--- a/esp32/src/dport/rom_pd_ctrl.rs
+++ b/esp32/src/dport/rom_pd_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rom_pd(&mut self) -> PRO_ROM_PD_W<ROM_PD_CTRL_SPEC> {
         PRO_ROM_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn app_rom_pd(&mut self) -> APP_ROM_PD_W<ROM_PD_CTRL_SPEC> {
         APP_ROM_PD_W::new(self, 1)
     }
     #[doc = "Bits 2:7"]
     #[inline(always)]
-    #[must_use]
     pub fn share_rom_pd(&mut self) -> SHARE_ROM_PD_W<ROM_PD_CTRL_SPEC> {
         SHARE_ROM_PD_W::new(self, 2)
     }
diff --git a/esp32/src/dport/rsa_pd_ctrl.rs b/esp32/src/dport/rsa_pd_ctrl.rs
index ce484c14c9..82d098e6a9 100644
--- a/esp32/src/dport/rsa_pd_ctrl.rs
+++ b/esp32/src/dport/rsa_pd_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_pd(&mut self) -> RSA_PD_W<RSA_PD_CTRL_SPEC> {
         RSA_PD_W::new(self, 0)
     }
diff --git a/esp32/src/dport/secure_boot_ctrl.rs b/esp32/src/dport/secure_boot_ctrl.rs
index 716f2f9fb6..0a59b5895b 100644
--- a/esp32/src/dport/secure_boot_ctrl.rs
+++ b/esp32/src/dport/secure_boot_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_bootloader_sel(&mut self) -> SW_BOOTLOADER_SEL_W<SECURE_BOOT_CTRL_SPEC> {
         SW_BOOTLOADER_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table0.rs b/esp32/src/dport/shrom_mpu_table0.rs
index 0cf69b8fcf..d43f91d2ab 100644
--- a/esp32/src/dport/shrom_mpu_table0.rs
+++ b/esp32/src/dport/shrom_mpu_table0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table0(&mut self) -> SHROM_MPU_TABLE0_W<SHROM_MPU_TABLE0_SPEC> {
         SHROM_MPU_TABLE0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table1.rs b/esp32/src/dport/shrom_mpu_table1.rs
index 413fe7d001..328679dfd2 100644
--- a/esp32/src/dport/shrom_mpu_table1.rs
+++ b/esp32/src/dport/shrom_mpu_table1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table1(&mut self) -> SHROM_MPU_TABLE1_W<SHROM_MPU_TABLE1_SPEC> {
         SHROM_MPU_TABLE1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table10.rs b/esp32/src/dport/shrom_mpu_table10.rs
index 39ff88188f..16e7117d14 100644
--- a/esp32/src/dport/shrom_mpu_table10.rs
+++ b/esp32/src/dport/shrom_mpu_table10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table10(&mut self) -> SHROM_MPU_TABLE10_W<SHROM_MPU_TABLE10_SPEC> {
         SHROM_MPU_TABLE10_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table11.rs b/esp32/src/dport/shrom_mpu_table11.rs
index 257c611b9d..07e232ce37 100644
--- a/esp32/src/dport/shrom_mpu_table11.rs
+++ b/esp32/src/dport/shrom_mpu_table11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table11(&mut self) -> SHROM_MPU_TABLE11_W<SHROM_MPU_TABLE11_SPEC> {
         SHROM_MPU_TABLE11_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table12.rs b/esp32/src/dport/shrom_mpu_table12.rs
index 9c79f55f43..3677a85876 100644
--- a/esp32/src/dport/shrom_mpu_table12.rs
+++ b/esp32/src/dport/shrom_mpu_table12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table12(&mut self) -> SHROM_MPU_TABLE12_W<SHROM_MPU_TABLE12_SPEC> {
         SHROM_MPU_TABLE12_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table13.rs b/esp32/src/dport/shrom_mpu_table13.rs
index 605b671c4c..9e4e61813b 100644
--- a/esp32/src/dport/shrom_mpu_table13.rs
+++ b/esp32/src/dport/shrom_mpu_table13.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table13(&mut self) -> SHROM_MPU_TABLE13_W<SHROM_MPU_TABLE13_SPEC> {
         SHROM_MPU_TABLE13_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table14.rs b/esp32/src/dport/shrom_mpu_table14.rs
index 70f4c8fcc3..dc514b1c9d 100644
--- a/esp32/src/dport/shrom_mpu_table14.rs
+++ b/esp32/src/dport/shrom_mpu_table14.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table14(&mut self) -> SHROM_MPU_TABLE14_W<SHROM_MPU_TABLE14_SPEC> {
         SHROM_MPU_TABLE14_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table15.rs b/esp32/src/dport/shrom_mpu_table15.rs
index 0cdb9a83dc..e908159acd 100644
--- a/esp32/src/dport/shrom_mpu_table15.rs
+++ b/esp32/src/dport/shrom_mpu_table15.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table15(&mut self) -> SHROM_MPU_TABLE15_W<SHROM_MPU_TABLE15_SPEC> {
         SHROM_MPU_TABLE15_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table16.rs b/esp32/src/dport/shrom_mpu_table16.rs
index 16d3d7b782..e186ff1ce9 100644
--- a/esp32/src/dport/shrom_mpu_table16.rs
+++ b/esp32/src/dport/shrom_mpu_table16.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table16(&mut self) -> SHROM_MPU_TABLE16_W<SHROM_MPU_TABLE16_SPEC> {
         SHROM_MPU_TABLE16_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table17.rs b/esp32/src/dport/shrom_mpu_table17.rs
index 9f83c37313..060e871b36 100644
--- a/esp32/src/dport/shrom_mpu_table17.rs
+++ b/esp32/src/dport/shrom_mpu_table17.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table17(&mut self) -> SHROM_MPU_TABLE17_W<SHROM_MPU_TABLE17_SPEC> {
         SHROM_MPU_TABLE17_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table18.rs b/esp32/src/dport/shrom_mpu_table18.rs
index f00218af36..e90cbc94e5 100644
--- a/esp32/src/dport/shrom_mpu_table18.rs
+++ b/esp32/src/dport/shrom_mpu_table18.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table18(&mut self) -> SHROM_MPU_TABLE18_W<SHROM_MPU_TABLE18_SPEC> {
         SHROM_MPU_TABLE18_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table19.rs b/esp32/src/dport/shrom_mpu_table19.rs
index 29eaa63687..fa1b8f1019 100644
--- a/esp32/src/dport/shrom_mpu_table19.rs
+++ b/esp32/src/dport/shrom_mpu_table19.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table19(&mut self) -> SHROM_MPU_TABLE19_W<SHROM_MPU_TABLE19_SPEC> {
         SHROM_MPU_TABLE19_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table2.rs b/esp32/src/dport/shrom_mpu_table2.rs
index e17dac55ef..8dcbb7bae1 100644
--- a/esp32/src/dport/shrom_mpu_table2.rs
+++ b/esp32/src/dport/shrom_mpu_table2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table2(&mut self) -> SHROM_MPU_TABLE2_W<SHROM_MPU_TABLE2_SPEC> {
         SHROM_MPU_TABLE2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table20.rs b/esp32/src/dport/shrom_mpu_table20.rs
index 49cac7b6dd..8385c894bc 100644
--- a/esp32/src/dport/shrom_mpu_table20.rs
+++ b/esp32/src/dport/shrom_mpu_table20.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table20(&mut self) -> SHROM_MPU_TABLE20_W<SHROM_MPU_TABLE20_SPEC> {
         SHROM_MPU_TABLE20_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table21.rs b/esp32/src/dport/shrom_mpu_table21.rs
index fae65b1ed7..b3423cdf7a 100644
--- a/esp32/src/dport/shrom_mpu_table21.rs
+++ b/esp32/src/dport/shrom_mpu_table21.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table21(&mut self) -> SHROM_MPU_TABLE21_W<SHROM_MPU_TABLE21_SPEC> {
         SHROM_MPU_TABLE21_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table22.rs b/esp32/src/dport/shrom_mpu_table22.rs
index b659849a27..c0521e8c85 100644
--- a/esp32/src/dport/shrom_mpu_table22.rs
+++ b/esp32/src/dport/shrom_mpu_table22.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table22(&mut self) -> SHROM_MPU_TABLE22_W<SHROM_MPU_TABLE22_SPEC> {
         SHROM_MPU_TABLE22_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table23.rs b/esp32/src/dport/shrom_mpu_table23.rs
index 7a52bbc1ab..f97f445374 100644
--- a/esp32/src/dport/shrom_mpu_table23.rs
+++ b/esp32/src/dport/shrom_mpu_table23.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table23(&mut self) -> SHROM_MPU_TABLE23_W<SHROM_MPU_TABLE23_SPEC> {
         SHROM_MPU_TABLE23_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table3.rs b/esp32/src/dport/shrom_mpu_table3.rs
index 6bb3079f67..9cb2a247b8 100644
--- a/esp32/src/dport/shrom_mpu_table3.rs
+++ b/esp32/src/dport/shrom_mpu_table3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table3(&mut self) -> SHROM_MPU_TABLE3_W<SHROM_MPU_TABLE3_SPEC> {
         SHROM_MPU_TABLE3_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table4.rs b/esp32/src/dport/shrom_mpu_table4.rs
index 060c011c58..d4e2e675d4 100644
--- a/esp32/src/dport/shrom_mpu_table4.rs
+++ b/esp32/src/dport/shrom_mpu_table4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table4(&mut self) -> SHROM_MPU_TABLE4_W<SHROM_MPU_TABLE4_SPEC> {
         SHROM_MPU_TABLE4_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table5.rs b/esp32/src/dport/shrom_mpu_table5.rs
index 9bedf5c810..17ada85d56 100644
--- a/esp32/src/dport/shrom_mpu_table5.rs
+++ b/esp32/src/dport/shrom_mpu_table5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table5(&mut self) -> SHROM_MPU_TABLE5_W<SHROM_MPU_TABLE5_SPEC> {
         SHROM_MPU_TABLE5_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table6.rs b/esp32/src/dport/shrom_mpu_table6.rs
index 22a916a4a3..4105dcd03f 100644
--- a/esp32/src/dport/shrom_mpu_table6.rs
+++ b/esp32/src/dport/shrom_mpu_table6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table6(&mut self) -> SHROM_MPU_TABLE6_W<SHROM_MPU_TABLE6_SPEC> {
         SHROM_MPU_TABLE6_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table7.rs b/esp32/src/dport/shrom_mpu_table7.rs
index da2744e299..66c3eed26a 100644
--- a/esp32/src/dport/shrom_mpu_table7.rs
+++ b/esp32/src/dport/shrom_mpu_table7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table7(&mut self) -> SHROM_MPU_TABLE7_W<SHROM_MPU_TABLE7_SPEC> {
         SHROM_MPU_TABLE7_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table8.rs b/esp32/src/dport/shrom_mpu_table8.rs
index 0701713887..8804e42b0b 100644
--- a/esp32/src/dport/shrom_mpu_table8.rs
+++ b/esp32/src/dport/shrom_mpu_table8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table8(&mut self) -> SHROM_MPU_TABLE8_W<SHROM_MPU_TABLE8_SPEC> {
         SHROM_MPU_TABLE8_W::new(self, 0)
     }
diff --git a/esp32/src/dport/shrom_mpu_table9.rs b/esp32/src/dport/shrom_mpu_table9.rs
index c7ad9b5762..c0b83ffcec 100644
--- a/esp32/src/dport/shrom_mpu_table9.rs
+++ b/esp32/src/dport/shrom_mpu_table9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn shrom_mpu_table9(&mut self) -> SHROM_MPU_TABLE9_W<SHROM_MPU_TABLE9_SPEC> {
         SHROM_MPU_TABLE9_W::new(self, 0)
     }
diff --git a/esp32/src/dport/slave_spi_config.rs b/esp32/src/dport/slave_spi_config.rs
index 35d007a86f..5b13db732f 100644
--- a/esp32/src/dport/slave_spi_config.rs
+++ b/esp32/src/dport/slave_spi_config.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_spi_mask_pro(&mut self) -> SLAVE_SPI_MASK_PRO_W<SLAVE_SPI_CONFIG_SPEC> {
         SLAVE_SPI_MASK_PRO_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_spi_mask_app(&mut self) -> SLAVE_SPI_MASK_APP_W<SLAVE_SPI_CONFIG_SPEC> {
         SLAVE_SPI_MASK_APP_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_encrypt_enable(&mut self) -> SPI_ENCRYPT_ENABLE_W<SLAVE_SPI_CONFIG_SPEC> {
         SPI_ENCRYPT_ENABLE_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_decrypt_enable(&mut self) -> SPI_DECRYPT_ENABLE_W<SLAVE_SPI_CONFIG_SPEC> {
         SPI_DECRYPT_ENABLE_W::new(self, 12)
     }
diff --git a/esp32/src/dport/spi_dma_chan_sel.rs b/esp32/src/dport/spi_dma_chan_sel.rs
index 76f4043a8c..0cdc95c214 100644
--- a/esp32/src/dport/spi_dma_chan_sel.rs
+++ b/esp32/src/dport/spi_dma_chan_sel.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn spi1_dma_chan_sel(&mut self) -> SPI1_DMA_CHAN_SEL_W<SPI_DMA_CHAN_SEL_SPEC> {
         SPI1_DMA_CHAN_SEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_chan_sel(&mut self) -> SPI2_DMA_CHAN_SEL_W<SPI_DMA_CHAN_SEL_SPEC> {
         SPI2_DMA_CHAN_SEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_chan_sel(&mut self) -> SPI3_DMA_CHAN_SEL_W<SPI_DMA_CHAN_SEL_SPEC> {
         SPI3_DMA_CHAN_SEL_W::new(self, 4)
     }
diff --git a/esp32/src/dport/sram_fo_ctrl_0.rs b/esp32/src/dport/sram_fo_ctrl_0.rs
index be28b87573..3ab48c5982 100644
--- a/esp32/src/dport/sram_fo_ctrl_0.rs
+++ b/esp32/src/dport/sram_fo_ctrl_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_fo_0(&mut self) -> SRAM_FO_0_W<SRAM_FO_CTRL_0_SPEC> {
         SRAM_FO_0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/sram_fo_ctrl_1.rs b/esp32/src/dport/sram_fo_ctrl_1.rs
index e692fba91c..e0497b03ad 100644
--- a/esp32/src/dport/sram_fo_ctrl_1.rs
+++ b/esp32/src/dport/sram_fo_ctrl_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_fo_1(&mut self) -> SRAM_FO_1_W<SRAM_FO_CTRL_1_SPEC> {
         SRAM_FO_1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/sram_pd_ctrl_0.rs b/esp32/src/dport/sram_pd_ctrl_0.rs
index 23f0a777eb..ba513792f9 100644
--- a/esp32/src/dport/sram_pd_ctrl_0.rs
+++ b/esp32/src/dport/sram_pd_ctrl_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_pd_0(&mut self) -> SRAM_PD_0_W<SRAM_PD_CTRL_0_SPEC> {
         SRAM_PD_0_W::new(self, 0)
     }
diff --git a/esp32/src/dport/sram_pd_ctrl_1.rs b/esp32/src/dport/sram_pd_ctrl_1.rs
index 158f792667..148e5af943 100644
--- a/esp32/src/dport/sram_pd_ctrl_1.rs
+++ b/esp32/src/dport/sram_pd_ctrl_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_pd_1(&mut self) -> SRAM_PD_1_W<SRAM_PD_CTRL_1_SPEC> {
         SRAM_PD_1_W::new(self, 0)
     }
diff --git a/esp32/src/dport/tag_fo_ctrl.rs b/esp32/src/dport/tag_fo_ctrl.rs
index d44dfc5a39..e4199825d4 100644
--- a/esp32/src/dport/tag_fo_ctrl.rs
+++ b/esp32/src/dport/tag_fo_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_tag_force_on(&mut self) -> PRO_CACHE_TAG_FORCE_ON_W<TAG_FO_CTRL_SPEC> {
         PRO_CACHE_TAG_FORCE_ON_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_tag_pd(&mut self) -> PRO_CACHE_TAG_PD_W<TAG_FO_CTRL_SPEC> {
         PRO_CACHE_TAG_PD_W::new(self, 1)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_tag_force_on(&mut self) -> APP_CACHE_TAG_FORCE_ON_W<TAG_FO_CTRL_SPEC> {
         APP_CACHE_TAG_FORCE_ON_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn app_cache_tag_pd(&mut self) -> APP_CACHE_TAG_PD_W<TAG_FO_CTRL_SPEC> {
         APP_CACHE_TAG_PD_W::new(self, 9)
     }
diff --git a/esp32/src/dport/tracemem_mux_mode.rs b/esp32/src/dport/tracemem_mux_mode.rs
index d483030c9b..e13ea59b29 100644
--- a/esp32/src/dport/tracemem_mux_mode.rs
+++ b/esp32/src/dport/tracemem_mux_mode.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn tracemem_mux_mode(&mut self) -> TRACEMEM_MUX_MODE_W<TRACEMEM_MUX_MODE_SPEC> {
         TRACEMEM_MUX_MODE_W::new(self, 0)
     }
diff --git a/esp32/src/dport/wifi_bb_cfg.rs b/esp32/src/dport/wifi_bb_cfg.rs
index d7bb7244d6..5bde8ca55e 100644
--- a/esp32/src/dport/wifi_bb_cfg.rs
+++ b/esp32/src/dport/wifi_bb_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg(&mut self) -> WIFI_BB_CFG_W<WIFI_BB_CFG_SPEC> {
         WIFI_BB_CFG_W::new(self, 0)
     }
diff --git a/esp32/src/dport/wifi_bb_cfg_2.rs b/esp32/src/dport/wifi_bb_cfg_2.rs
index f27054d4db..b9b3de76a1 100644
--- a/esp32/src/dport/wifi_bb_cfg_2.rs
+++ b/esp32/src/dport/wifi_bb_cfg_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg_2(&mut self) -> WIFI_BB_CFG_2_W<WIFI_BB_CFG_2_SPEC> {
         WIFI_BB_CFG_2_W::new(self, 0)
     }
diff --git a/esp32/src/dport/wifi_clk_en.rs b/esp32/src/dport/wifi_clk_en.rs
index 27dc7e51cf..d3759ebed3 100644
--- a/esp32/src/dport/wifi_clk_en.rs
+++ b/esp32/src/dport/wifi_clk_en.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_EN_W::new(self, 0)
     }
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_wifi_en(&mut self) -> WIFI_CLK_WIFI_EN_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_WIFI_EN_W::new(self, 0)
     }
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_wifi_bt_common(&mut self) -> WIFI_CLK_WIFI_BT_COMMON_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_WIFI_BT_COMMON_W::new(self, 0)
     }
     #[doc = "Bits 11:13"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_bt_en(&mut self) -> WIFI_CLK_BT_EN_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_BT_EN_W::new(self, 11)
     }
diff --git a/esp32/src/efuse/blk0_rdata2.rs b/esp32/src/efuse/blk0_rdata2.rs
index c34474760e..0fe1f5d66b 100644
--- a/esp32/src/efuse/blk0_rdata2.rs
+++ b/esp32/src/efuse/blk0_rdata2.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_88(&mut self) -> RD_RESERVE_0_88_W<BLK0_RDATA2_SPEC> {
         RD_RESERVE_0_88_W::new(self, 24)
     }
diff --git a/esp32/src/efuse/blk0_rdata3.rs b/esp32/src/efuse/blk0_rdata3.rs
index 8ec79c034e..bee1596b3a 100644
--- a/esp32/src/efuse/blk0_rdata3.rs
+++ b/esp32/src/efuse/blk0_rdata3.rs
@@ -114,37 +114,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 9:11"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_chip_package(&mut self) -> RD_CHIP_PACKAGE_W<BLK0_RDATA3_SPEC> {
         RD_CHIP_PACKAGE_W::new(self, 9)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_chip_cpu_freq_low(&mut self) -> RD_CHIP_CPU_FREQ_LOW_W<BLK0_RDATA3_SPEC> {
         RD_CHIP_CPU_FREQ_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_chip_cpu_freq_rated(&mut self) -> RD_CHIP_CPU_FREQ_RATED_W<BLK0_RDATA3_SPEC> {
         RD_CHIP_CPU_FREQ_RATED_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_blk3_part_reserve(&mut self) -> RD_BLK3_PART_RESERVE_W<BLK0_RDATA3_SPEC> {
         RD_BLK3_PART_RESERVE_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_chip_ver_rev1(&mut self) -> RD_CHIP_VER_REV1_W<BLK0_RDATA3_SPEC> {
         RD_CHIP_VER_REV1_W::new(self, 15)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_112(&mut self) -> RD_RESERVE_0_112_W<BLK0_RDATA3_SPEC> {
         RD_RESERVE_0_112_W::new(self, 16)
     }
diff --git a/esp32/src/efuse/blk0_rdata4.rs b/esp32/src/efuse/blk0_rdata4.rs
index 91f4afe71d..75ed6513d5 100644
--- a/esp32/src/efuse/blk0_rdata4.rs
+++ b/esp32/src/efuse/blk0_rdata4.rs
@@ -76,19 +76,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:12"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_adc_vref(&mut self) -> RD_ADC_VREF_W<BLK0_RDATA4_SPEC> {
         RD_ADC_VREF_W::new(self, 8)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_141(&mut self) -> RD_RESERVE_0_141_W<BLK0_RDATA4_SPEC> {
         RD_RESERVE_0_141_W::new(self, 13)
     }
     #[doc = "Bits 17:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_145(&mut self) -> RD_RESERVE_0_145_W<BLK0_RDATA4_SPEC> {
         RD_RESERVE_0_145_W::new(self, 17)
     }
diff --git a/esp32/src/efuse/blk0_rdata5.rs b/esp32/src/efuse/blk0_rdata5.rs
index 9ed7ded75f..bc66c2e04d 100644
--- a/esp32/src/efuse/blk0_rdata5.rs
+++ b/esp32/src/efuse/blk0_rdata5.rs
@@ -98,13 +98,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_181(&mut self) -> RD_RESERVE_0_181_W<BLK0_RDATA5_SPEC> {
         RD_RESERVE_0_181_W::new(self, 21)
     }
     #[doc = "Bits 26:27"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_186(&mut self) -> RD_RESERVE_0_186_W<BLK0_RDATA5_SPEC> {
         RD_RESERVE_0_186_W::new(self, 26)
     }
diff --git a/esp32/src/efuse/blk0_rdata6.rs b/esp32/src/efuse/blk0_rdata6.rs
index cc0a5ab74e..24e525fc77 100644
--- a/esp32/src/efuse/blk0_rdata6.rs
+++ b/esp32/src/efuse/blk0_rdata6.rs
@@ -104,7 +104,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 11:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_reserve_0_203(&mut self) -> RD_RESERVE_0_203_W<BLK0_RDATA6_SPEC> {
         RD_RESERVE_0_203_W::new(self, 11)
     }
diff --git a/esp32/src/efuse/blk0_wdata0.rs b/esp32/src/efuse/blk0_wdata0.rs
index 3217e4fce3..bfc57f05f0 100644
--- a/esp32/src/efuse/blk0_wdata0.rs
+++ b/esp32/src/efuse/blk0_wdata0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn wr_dis(&mut self) -> WR_DIS_W<BLK0_WDATA0_SPEC> {
         WR_DIS_W::new(self, 0)
     }
     #[doc = "Bits 16:19"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_dis(&mut self) -> RD_DIS_W<BLK0_WDATA0_SPEC> {
         RD_DIS_W::new(self, 16)
     }
     #[doc = "Bits 20:26"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_crypt_cnt(&mut self) -> FLASH_CRYPT_CNT_W<BLK0_WDATA0_SPEC> {
         FLASH_CRYPT_CNT_W::new(self, 20)
     }
diff --git a/esp32/src/efuse/blk0_wdata1.rs b/esp32/src/efuse/blk0_wdata1.rs
index c67c47f13c..ab4d803219 100644
--- a/esp32/src/efuse/blk0_wdata1.rs
+++ b/esp32/src/efuse/blk0_wdata1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_mac_crc_low(&mut self) -> WIFI_MAC_CRC_LOW_W<BLK0_WDATA1_SPEC> {
         WIFI_MAC_CRC_LOW_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk0_wdata2.rs b/esp32/src/efuse/blk0_wdata2.rs
index 3a27152f29..b6d9d73fb0 100644
--- a/esp32/src/efuse/blk0_wdata2.rs
+++ b/esp32/src/efuse/blk0_wdata2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_mac_crc_high(&mut self) -> WIFI_MAC_CRC_HIGH_W<BLK0_WDATA2_SPEC> {
         WIFI_MAC_CRC_HIGH_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk0_wdata3.rs b/esp32/src/efuse/blk0_wdata3.rs
index a758a47e25..12884e920b 100644
--- a/esp32/src/efuse/blk0_wdata3.rs
+++ b/esp32/src/efuse/blk0_wdata3.rs
@@ -114,37 +114,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 9:11"]
     #[inline(always)]
-    #[must_use]
     pub fn chip_package(&mut self) -> CHIP_PACKAGE_W<BLK0_WDATA3_SPEC> {
         CHIP_PACKAGE_W::new(self, 9)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn chip_cpu_freq_low(&mut self) -> CHIP_CPU_FREQ_LOW_W<BLK0_WDATA3_SPEC> {
         CHIP_CPU_FREQ_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn chip_cpu_freq_rated(&mut self) -> CHIP_CPU_FREQ_RATED_W<BLK0_WDATA3_SPEC> {
         CHIP_CPU_FREQ_RATED_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_part_reserve(&mut self) -> BLK3_PART_RESERVE_W<BLK0_WDATA3_SPEC> {
         BLK3_PART_RESERVE_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn chip_ver_rev1(&mut self) -> CHIP_VER_REV1_W<BLK0_WDATA3_SPEC> {
         CHIP_VER_REV1_W::new(self, 15)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn reserve_0_112(&mut self) -> RESERVE_0_112_W<BLK0_WDATA3_SPEC> {
         RESERVE_0_112_W::new(self, 16)
     }
diff --git a/esp32/src/efuse/blk0_wdata4.rs b/esp32/src/efuse/blk0_wdata4.rs
index e988cec462..a8397426aa 100644
--- a/esp32/src/efuse/blk0_wdata4.rs
+++ b/esp32/src/efuse/blk0_wdata4.rs
@@ -76,19 +76,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:12"]
     #[inline(always)]
-    #[must_use]
     pub fn adc_vref(&mut self) -> ADC_VREF_W<BLK0_WDATA4_SPEC> {
         ADC_VREF_W::new(self, 8)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn reserve_0_141(&mut self) -> RESERVE_0_141_W<BLK0_WDATA4_SPEC> {
         RESERVE_0_141_W::new(self, 13)
     }
     #[doc = "Bits 17:31"]
     #[inline(always)]
-    #[must_use]
     pub fn reserve_0_145(&mut self) -> RESERVE_0_145_W<BLK0_WDATA4_SPEC> {
         RESERVE_0_145_W::new(self, 17)
     }
diff --git a/esp32/src/efuse/blk0_wdata5.rs b/esp32/src/efuse/blk0_wdata5.rs
index 8f874fa112..0fbd68d1d1 100644
--- a/esp32/src/efuse/blk0_wdata5.rs
+++ b/esp32/src/efuse/blk0_wdata5.rs
@@ -98,13 +98,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn reserve_0_181(&mut self) -> RESERVE_0_181_W<BLK0_WDATA5_SPEC> {
         RESERVE_0_181_W::new(self, 21)
     }
     #[doc = "Bits 26:27"]
     #[inline(always)]
-    #[must_use]
     pub fn reserve_0_186(&mut self) -> RESERVE_0_186_W<BLK0_WDATA5_SPEC> {
         RESERVE_0_186_W::new(self, 26)
     }
diff --git a/esp32/src/efuse/blk0_wdata6.rs b/esp32/src/efuse/blk0_wdata6.rs
index defb29195f..39b745b622 100644
--- a/esp32/src/efuse/blk0_wdata6.rs
+++ b/esp32/src/efuse/blk0_wdata6.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn coding_scheme(&mut self) -> CODING_SCHEME_W<BLK0_WDATA6_SPEC> {
         CODING_SCHEME_W::new(self, 0)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn console_debug_disable(&mut self) -> CONSOLE_DEBUG_DISABLE_W<BLK0_WDATA6_SPEC> {
         CONSOLE_DEBUG_DISABLE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_sdio_host(&mut self) -> DISABLE_SDIO_HOST_W<BLK0_WDATA6_SPEC> {
         DISABLE_SDIO_HOST_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn abs_done_0(&mut self) -> ABS_DONE_0_W<BLK0_WDATA6_SPEC> {
         ABS_DONE_0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn abs_done_1(&mut self) -> ABS_DONE_1_W<BLK0_WDATA6_SPEC> {
         ABS_DONE_1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_jtag(&mut self) -> DISABLE_JTAG_W<BLK0_WDATA6_SPEC> {
         DISABLE_JTAG_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_dl_encrypt(&mut self) -> DISABLE_DL_ENCRYPT_W<BLK0_WDATA6_SPEC> {
         DISABLE_DL_ENCRYPT_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_dl_decrypt(&mut self) -> DISABLE_DL_DECRYPT_W<BLK0_WDATA6_SPEC> {
         DISABLE_DL_DECRYPT_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_dl_cache(&mut self) -> DISABLE_DL_CACHE_W<BLK0_WDATA6_SPEC> {
         DISABLE_DL_CACHE_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn key_status(&mut self) -> KEY_STATUS_W<BLK0_WDATA6_SPEC> {
         KEY_STATUS_W::new(self, 10)
     }
diff --git a/esp32/src/efuse/blk1_wdata0.rs b/esp32/src/efuse/blk1_wdata0.rs
index 44ba9a1a2d..50327bdecf 100644
--- a/esp32/src/efuse/blk1_wdata0.rs
+++ b/esp32/src/efuse/blk1_wdata0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din0(&mut self) -> BLK1_DIN0_W<BLK1_WDATA0_SPEC> {
         BLK1_DIN0_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata1.rs b/esp32/src/efuse/blk1_wdata1.rs
index 4974d2ba7c..1b82691edb 100644
--- a/esp32/src/efuse/blk1_wdata1.rs
+++ b/esp32/src/efuse/blk1_wdata1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din1(&mut self) -> BLK1_DIN1_W<BLK1_WDATA1_SPEC> {
         BLK1_DIN1_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata2.rs b/esp32/src/efuse/blk1_wdata2.rs
index 0904d0a855..2d5d3862b2 100644
--- a/esp32/src/efuse/blk1_wdata2.rs
+++ b/esp32/src/efuse/blk1_wdata2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din2(&mut self) -> BLK1_DIN2_W<BLK1_WDATA2_SPEC> {
         BLK1_DIN2_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata3.rs b/esp32/src/efuse/blk1_wdata3.rs
index 5f5b9781a0..37db9ad588 100644
--- a/esp32/src/efuse/blk1_wdata3.rs
+++ b/esp32/src/efuse/blk1_wdata3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din3(&mut self) -> BLK1_DIN3_W<BLK1_WDATA3_SPEC> {
         BLK1_DIN3_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata4.rs b/esp32/src/efuse/blk1_wdata4.rs
index 8c9d6ea10c..bf01ad456e 100644
--- a/esp32/src/efuse/blk1_wdata4.rs
+++ b/esp32/src/efuse/blk1_wdata4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din4(&mut self) -> BLK1_DIN4_W<BLK1_WDATA4_SPEC> {
         BLK1_DIN4_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata5.rs b/esp32/src/efuse/blk1_wdata5.rs
index 835030c9b8..e4f2bd8548 100644
--- a/esp32/src/efuse/blk1_wdata5.rs
+++ b/esp32/src/efuse/blk1_wdata5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din5(&mut self) -> BLK1_DIN5_W<BLK1_WDATA5_SPEC> {
         BLK1_DIN5_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata6.rs b/esp32/src/efuse/blk1_wdata6.rs
index f7d7336c49..d4289fc1cb 100644
--- a/esp32/src/efuse/blk1_wdata6.rs
+++ b/esp32/src/efuse/blk1_wdata6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din6(&mut self) -> BLK1_DIN6_W<BLK1_WDATA6_SPEC> {
         BLK1_DIN6_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk1_wdata7.rs b/esp32/src/efuse/blk1_wdata7.rs
index d78932d65e..e7907e5246 100644
--- a/esp32/src/efuse/blk1_wdata7.rs
+++ b/esp32/src/efuse/blk1_wdata7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk1_din7(&mut self) -> BLK1_DIN7_W<BLK1_WDATA7_SPEC> {
         BLK1_DIN7_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata0.rs b/esp32/src/efuse/blk2_wdata0.rs
index 0da8e92cc0..5d65cce493 100644
--- a/esp32/src/efuse/blk2_wdata0.rs
+++ b/esp32/src/efuse/blk2_wdata0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din0(&mut self) -> BLK2_DIN0_W<BLK2_WDATA0_SPEC> {
         BLK2_DIN0_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata1.rs b/esp32/src/efuse/blk2_wdata1.rs
index 8ed0352f61..4cf91110e6 100644
--- a/esp32/src/efuse/blk2_wdata1.rs
+++ b/esp32/src/efuse/blk2_wdata1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din1(&mut self) -> BLK2_DIN1_W<BLK2_WDATA1_SPEC> {
         BLK2_DIN1_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata2.rs b/esp32/src/efuse/blk2_wdata2.rs
index 64d81d1f1f..96b923ba46 100644
--- a/esp32/src/efuse/blk2_wdata2.rs
+++ b/esp32/src/efuse/blk2_wdata2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din2(&mut self) -> BLK2_DIN2_W<BLK2_WDATA2_SPEC> {
         BLK2_DIN2_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata3.rs b/esp32/src/efuse/blk2_wdata3.rs
index d5f290224e..b292894c54 100644
--- a/esp32/src/efuse/blk2_wdata3.rs
+++ b/esp32/src/efuse/blk2_wdata3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din3(&mut self) -> BLK2_DIN3_W<BLK2_WDATA3_SPEC> {
         BLK2_DIN3_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata4.rs b/esp32/src/efuse/blk2_wdata4.rs
index 3020570e29..3ff75b04d2 100644
--- a/esp32/src/efuse/blk2_wdata4.rs
+++ b/esp32/src/efuse/blk2_wdata4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din4(&mut self) -> BLK2_DIN4_W<BLK2_WDATA4_SPEC> {
         BLK2_DIN4_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata5.rs b/esp32/src/efuse/blk2_wdata5.rs
index 380ead8525..f84a7590e6 100644
--- a/esp32/src/efuse/blk2_wdata5.rs
+++ b/esp32/src/efuse/blk2_wdata5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din5(&mut self) -> BLK2_DIN5_W<BLK2_WDATA5_SPEC> {
         BLK2_DIN5_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata6.rs b/esp32/src/efuse/blk2_wdata6.rs
index ce4a035cd5..c9f5e8c1a6 100644
--- a/esp32/src/efuse/blk2_wdata6.rs
+++ b/esp32/src/efuse/blk2_wdata6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din6(&mut self) -> BLK2_DIN6_W<BLK2_WDATA6_SPEC> {
         BLK2_DIN6_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk2_wdata7.rs b/esp32/src/efuse/blk2_wdata7.rs
index fa38cfb29f..98f147b6bd 100644
--- a/esp32/src/efuse/blk2_wdata7.rs
+++ b/esp32/src/efuse/blk2_wdata7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk2_din7(&mut self) -> BLK2_DIN7_W<BLK2_WDATA7_SPEC> {
         BLK2_DIN7_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_rdata3.rs b/esp32/src/efuse/blk3_rdata3.rs
index b2e6acd025..54de3a604d 100644
--- a/esp32/src/efuse/blk3_rdata3.rs
+++ b/esp32/src/efuse/blk3_rdata3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_adc1_tp_low(&mut self) -> RD_ADC1_TP_LOW_W<BLK3_RDATA3_SPEC> {
         RD_ADC1_TP_LOW_W::new(self, 0)
     }
     #[doc = "Bits 7:15"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_adc1_tp_high(&mut self) -> RD_ADC1_TP_HIGH_W<BLK3_RDATA3_SPEC> {
         RD_ADC1_TP_HIGH_W::new(self, 7)
     }
     #[doc = "Bits 16:22"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_adc2_tp_low(&mut self) -> RD_ADC2_TP_LOW_W<BLK3_RDATA3_SPEC> {
         RD_ADC2_TP_LOW_W::new(self, 16)
     }
     #[doc = "Bits 23:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_adc2_tp_high(&mut self) -> RD_ADC2_TP_HIGH_W<BLK3_RDATA3_SPEC> {
         RD_ADC2_TP_HIGH_W::new(self, 23)
     }
diff --git a/esp32/src/efuse/blk3_wdata0.rs b/esp32/src/efuse/blk3_wdata0.rs
index f32fa54e10..6f60b74779 100644
--- a/esp32/src/efuse/blk3_wdata0.rs
+++ b/esp32/src/efuse/blk3_wdata0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din0(&mut self) -> BLK3_DIN0_W<BLK3_WDATA0_SPEC> {
         BLK3_DIN0_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_wdata1.rs b/esp32/src/efuse/blk3_wdata1.rs
index 1dce75b61d..cb09e5f297 100644
--- a/esp32/src/efuse/blk3_wdata1.rs
+++ b/esp32/src/efuse/blk3_wdata1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din1(&mut self) -> BLK3_DIN1_W<BLK3_WDATA1_SPEC> {
         BLK3_DIN1_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_wdata2.rs b/esp32/src/efuse/blk3_wdata2.rs
index 1bc550d65e..da10fcdf8b 100644
--- a/esp32/src/efuse/blk3_wdata2.rs
+++ b/esp32/src/efuse/blk3_wdata2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din2(&mut self) -> BLK3_DIN2_W<BLK3_WDATA2_SPEC> {
         BLK3_DIN2_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_wdata3.rs b/esp32/src/efuse/blk3_wdata3.rs
index 467a5893f9..86150d6a13 100644
--- a/esp32/src/efuse/blk3_wdata3.rs
+++ b/esp32/src/efuse/blk3_wdata3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_tp_low(&mut self) -> ADC1_TP_LOW_W<BLK3_WDATA3_SPEC> {
         ADC1_TP_LOW_W::new(self, 0)
     }
     #[doc = "Bits 7:15"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_tp_high(&mut self) -> ADC1_TP_HIGH_W<BLK3_WDATA3_SPEC> {
         ADC1_TP_HIGH_W::new(self, 7)
     }
     #[doc = "Bits 16:22"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_tp_low(&mut self) -> ADC2_TP_LOW_W<BLK3_WDATA3_SPEC> {
         ADC2_TP_LOW_W::new(self, 16)
     }
     #[doc = "Bits 23:31"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_tp_high(&mut self) -> ADC2_TP_HIGH_W<BLK3_WDATA3_SPEC> {
         ADC2_TP_HIGH_W::new(self, 23)
     }
diff --git a/esp32/src/efuse/blk3_wdata5.rs b/esp32/src/efuse/blk3_wdata5.rs
index 2f74715490..0d84224d22 100644
--- a/esp32/src/efuse/blk3_wdata5.rs
+++ b/esp32/src/efuse/blk3_wdata5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din5(&mut self) -> BLK3_DIN5_W<BLK3_WDATA5_SPEC> {
         BLK3_DIN5_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_wdata6.rs b/esp32/src/efuse/blk3_wdata6.rs
index e03566d304..eabe2d977b 100644
--- a/esp32/src/efuse/blk3_wdata6.rs
+++ b/esp32/src/efuse/blk3_wdata6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din6(&mut self) -> BLK3_DIN6_W<BLK3_WDATA6_SPEC> {
         BLK3_DIN6_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/blk3_wdata7.rs b/esp32/src/efuse/blk3_wdata7.rs
index 01c022b079..6671fd5232 100644
--- a/esp32/src/efuse/blk3_wdata7.rs
+++ b/esp32/src/efuse/blk3_wdata7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn blk3_din7(&mut self) -> BLK3_DIN7_W<BLK3_WDATA7_SPEC> {
         BLK3_DIN7_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/clk.rs b/esp32/src/efuse/clk.rs
index 3c62ee8551..fe3957a158 100644
--- a/esp32/src/efuse/clk.rs
+++ b/esp32/src/efuse/clk.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn sel0(&mut self) -> SEL0_W<CLK_SPEC> {
         SEL0_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sel1(&mut self) -> SEL1_W<CLK_SPEC> {
         SEL1_W::new(self, 8)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CLK_SPEC> {
         EN_W::new(self, 16)
     }
diff --git a/esp32/src/efuse/cmd.rs b/esp32/src/efuse/cmd.rs
index e12f5509cf..c158990141 100644
--- a/esp32/src/efuse/cmd.rs
+++ b/esp32/src/efuse/cmd.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn read_cmd(&mut self) -> READ_CMD_W<CMD_SPEC> {
         READ_CMD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_cmd(&mut self) -> PGM_CMD_W<CMD_SPEC> {
         PGM_CMD_W::new(self, 1)
     }
diff --git a/esp32/src/efuse/conf.rs b/esp32/src/efuse/conf.rs
index d24c460030..40db3126ea 100644
--- a/esp32/src/efuse/conf.rs
+++ b/esp32/src/efuse/conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn op_code(&mut self) -> OP_CODE_W<CONF_SPEC> {
         OP_CODE_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn force_no_wr_rd_dis(&mut self) -> FORCE_NO_WR_RD_DIS_W<CONF_SPEC> {
         FORCE_NO_WR_RD_DIS_W::new(self, 16)
     }
diff --git a/esp32/src/efuse/dac_conf.rs b/esp32/src/efuse/dac_conf.rs
index 8c01fbb6bb..ba3f88a04a 100644
--- a/esp32/src/efuse/dac_conf.rs
+++ b/esp32/src/efuse/dac_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_div(&mut self) -> DAC_CLK_DIV_W<DAC_CONF_SPEC> {
         DAC_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_pad_sel(&mut self) -> DAC_CLK_PAD_SEL_W<DAC_CONF_SPEC> {
         DAC_CLK_PAD_SEL_W::new(self, 8)
     }
diff --git a/esp32/src/efuse/date.rs b/esp32/src/efuse/date.rs
index 8e271a127a..677aa8b8ff 100644
--- a/esp32/src/efuse/date.rs
+++ b/esp32/src/efuse/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/efuse/int_clr.rs b/esp32/src/efuse/int_clr.rs
index 21aedf9c22..91b4788062 100644
--- a/esp32/src/efuse/int_clr.rs
+++ b/esp32/src/efuse/int_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_CLR_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_CLR_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32/src/efuse/int_ena.rs b/esp32/src/efuse/int_ena.rs
index 1c4746ae5c..67e7cfaa8e 100644
--- a/esp32/src/efuse/int_ena.rs
+++ b/esp32/src/efuse/int_ena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_ENA_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_ENA_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32/src/emac_dma/dmabusmode.rs b/esp32/src/emac_dma/dmabusmode.rs
index 4e1843d119..e227cda9de 100644
--- a/esp32/src/emac_dma/dmabusmode.rs
+++ b/esp32/src/emac_dma/dmabusmode.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_rst(&mut self) -> SW_RST_W<DMABUSMODE_SPEC> {
         SW_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit\\[15:14\\]). 1'b1 Fixed priority (Rx priority to Tx)."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_arb_sch(&mut self) -> DMA_ARB_SCH_W<DMABUSMODE_SPEC> {
         DMA_ARB_SCH_W::new(self, 1)
     }
     #[doc = "Bits 2:6 - This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode."]
     #[inline(always)]
-    #[must_use]
     pub fn desc_skip_len(&mut self) -> DESC_SKIP_LEN_W<DMABUSMODE_SPEC> {
         DESC_SKIP_LEN_W::new(self, 2)
     }
     #[doc = "Bit 7 - When set the size of the alternate descriptor increases to 32 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn alt_desc_size(&mut self) -> ALT_DESC_SIZE_W<DMABUSMODE_SPEC> {
         ALT_DESC_SIZE_W::new(self, 7)
     }
     #[doc = "Bits 8:13 - These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN)."]
     #[inline(always)]
-    #[must_use]
     pub fn prog_burst_len(&mut self) -> PROG_BURST_LEN_W<DMABUSMODE_SPEC> {
         PROG_BURST_LEN_W::new(self, 8)
     }
     #[doc = "Bits 14:15 - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_ratio(&mut self) -> PRI_RATIO_W<DMABUSMODE_SPEC> {
         PRI_RATIO_W::new(self, 14)
     }
     #[doc = "Bit 16 - This bit controls whether the AHB master interface performs fixed burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations."]
     #[inline(always)]
-    #[must_use]
     pub fn fixed_burst(&mut self) -> FIXED_BURST_W<DMABUSMODE_SPEC> {
         FIXED_BURST_W::new(self, 16)
     }
     #[doc = "Bits 17:22 - This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dma_pbl(&mut self) -> RX_DMA_PBL_W<DMABUSMODE_SPEC> {
         RX_DMA_PBL_W::new(self, 17)
     }
     #[doc = "Bit 23 - When set high this bit configures the Rx DMA to use the value configured in Bits\\[22:17\\] as PBL. The PBL value in Bits\\[13:8\\] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits\\[13:8\\] is applicable for both DMA engines."]
     #[inline(always)]
-    #[must_use]
     pub fn use_sep_pbl(&mut self) -> USE_SEP_PBL_W<DMABUSMODE_SPEC> {
         USE_SEP_PBL_W::new(self, 23)
     }
     #[doc = "Bit 24 - When set high this bit multiplies the programmed PBL value (Bits\\[22:17\\] and Bits\\[13:8\\]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value."]
     #[inline(always)]
-    #[must_use]
     pub fn pblx8_mode(&mut self) -> PBLX8_MODE_W<DMABUSMODE_SPEC> {
         PBLX8_MODE_W::new(self, 24)
     }
     #[doc = "Bit 25 - When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address."]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddralibea(&mut self) -> DMAADDRALIBEA_W<DMABUSMODE_SPEC> {
         DMAADDRALIBEA_W::new(self, 25)
     }
     #[doc = "Bit 26 - When this bit is set high and the FIXED_BURST bit is low the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less."]
     #[inline(always)]
-    #[must_use]
     pub fn dmamixedburst(&mut self) -> DMAMIXEDBURST_W<DMABUSMODE_SPEC> {
         DMAMIXEDBURST_W::new(self, 26)
     }
diff --git a/esp32/src/emac_dma/dmain_en.rs b/esp32/src/emac_dma/dmain_en.rs
index 735da67c4c..12c1508d96 100644
--- a/esp32/src/emac_dma/dmain_en.rs
+++ b/esp32/src/emac_dma/dmain_en.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When this bit is set with Normal Interrupt Summary Enable (Bit\\[16\\]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_tie(&mut self) -> DMAIN_TIE_W<DMAIN_EN_SPEC> {
         DMAIN_TIE_W::new(self, 0)
     }
     #[doc = "Bit 1 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_tse(&mut self) -> DMAIN_TSE_W<DMAIN_EN_SPEC> {
         DMAIN_TSE_W::new(self, 1)
     }
     #[doc = "Bit 2 - When this bit is set with Normal Interrupt Summary Enable (Bit 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_tbue(&mut self) -> DMAIN_TBUE_W<DMAIN_EN_SPEC> {
         DMAIN_TBUE_W::new(self, 2)
     }
     #[doc = "Bit 3 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_tjte(&mut self) -> DMAIN_TJTE_W<DMAIN_EN_SPEC> {
         DMAIN_TJTE_W::new(self, 3)
     }
     #[doc = "Bit 4 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_oie(&mut self) -> DMAIN_OIE_W<DMAIN_EN_SPEC> {
         DMAIN_OIE_W::new(self, 4)
     }
     #[doc = "Bit 5 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_uie(&mut self) -> DMAIN_UIE_W<DMAIN_EN_SPEC> {
         DMAIN_UIE_W::new(self, 5)
     }
     #[doc = "Bit 6 - When this bit is set with Normal Interrupt Summary Enable (Bit\\[16\\]) the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_rie(&mut self) -> DMAIN_RIE_W<DMAIN_EN_SPEC> {
         DMAIN_RIE_W::new(self, 6)
     }
     #[doc = "Bit 7 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_rbue(&mut self) -> DMAIN_RBUE_W<DMAIN_EN_SPEC> {
         DMAIN_RBUE_W::new(self, 7)
     }
     #[doc = "Bit 8 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_rse(&mut self) -> DMAIN_RSE_W<DMAIN_EN_SPEC> {
         DMAIN_RSE_W::new(self, 8)
     }
     #[doc = "Bit 9 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_rwte(&mut self) -> DMAIN_RWTE_W<DMAIN_EN_SPEC> {
         DMAIN_RWTE_W::new(self, 9)
     }
     #[doc = "Bit 10 - When this bit is set with an Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_etie(&mut self) -> DMAIN_ETIE_W<DMAIN_EN_SPEC> {
         DMAIN_ETIE_W::new(self, 10)
     }
     #[doc = "Bit 13 - When this bit is set with Abnormal Interrupt Summary Enable (Bit\\[15\\]) the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_fbee(&mut self) -> DMAIN_FBEE_W<DMAIN_EN_SPEC> {
         DMAIN_FBEE_W::new(self, 13)
     }
     #[doc = "Bit 14 - When this bit is set with Normal Interrupt Summary Enable (Bit\\[16\\]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_erie(&mut self) -> DMAIN_ERIE_W<DMAIN_EN_SPEC> {
         DMAIN_ERIE_W::new(self, 14)
     }
     #[doc = "Bit 15 - When this bit is set abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit\\[1\\]: Transmit Process Stopped. Bit\\[3\\]: Transmit Jabber Timeout. Bit\\[4\\]: Receive Overflow. Bit\\[5\\]: Transmit Underflow. Bit\\[7\\]: Receive Buffer Unavailable. Bit\\[8\\]: Receive Process Stopped. Bit\\[9\\]: Receive Watchdog Timeout. Bit\\[10\\]: Early Transmit Interrupt. Bit\\[13\\]: Fatal Bus Error."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_aise(&mut self) -> DMAIN_AISE_W<DMAIN_EN_SPEC> {
         DMAIN_AISE_W::new(self, 15)
     }
     #[doc = "Bit 16 - When this bit is set normal interrupt summary is enabled. When this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit\\[0\\]: Transmit Interrupt. Bit\\[2\\]: Transmit Buffer Unavailable. Bit\\[6\\]: Receive Interrupt. Bit\\[14\\]: Early Receive Interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dmain_nise(&mut self) -> DMAIN_NISE_W<DMAIN_EN_SPEC> {
         DMAIN_NISE_W::new(self, 16)
     }
diff --git a/esp32/src/emac_dma/dmamissedfr.rs b/esp32/src/emac_dma/dmamissedfr.rs
index 31323fb7bd..a986cdf017 100644
--- a/esp32/src/emac_dma/dmamissedfr.rs
+++ b/esp32/src/emac_dma/dmamissedfr.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read."]
     #[inline(always)]
-    #[must_use]
     pub fn missed_fc(&mut self) -> MISSED_FC_W<DMAMISSEDFR_SPEC> {
         MISSED_FC_W::new(self, 0)
     }
     #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened."]
     #[inline(always)]
-    #[must_use]
     pub fn overflow_bmfc(&mut self) -> OVERFLOW_BMFC_W<DMAMISSEDFR_SPEC> {
         OVERFLOW_BMFC_W::new(self, 16)
     }
     #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read."]
     #[inline(always)]
-    #[must_use]
     pub fn overflow_fc(&mut self) -> OVERFLOW_FC_W<DMAMISSEDFR_SPEC> {
         OVERFLOW_FC_W::new(self, 17)
     }
     #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened."]
     #[inline(always)]
-    #[must_use]
     pub fn overflow_bfoc(&mut self) -> OVERFLOW_BFOC_W<DMAMISSEDFR_SPEC> {
         OVERFLOW_BFOC_W::new(self, 28)
     }
diff --git a/esp32/src/emac_dma/dmaoperation_mode.rs b/esp32/src/emac_dma/dmaoperation_mode.rs
index 0924c34c2d..2d9769ea45 100644
--- a/esp32/src/emac_dma/dmaoperation_mode.rs
+++ b/esp32/src/emac_dma/dmaoperation_mode.rs
@@ -147,43 +147,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame."]
     #[inline(always)]
-    #[must_use]
     pub fn start_stop_rx(&mut self) -> START_STOP_RX_W<DMAOPERATION_MODE_SPEC> {
         START_STOP_RX_W::new(self, 1)
     }
     #[doc = "Bit 2 - When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained."]
     #[inline(always)]
-    #[must_use]
     pub fn opt_second_frame(&mut self) -> OPT_SECOND_FRAME_W<DMAOPERATION_MODE_SPEC> {
         OPT_SECOND_FRAME_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 ."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_thresh_ctrl(&mut self) -> RX_THRESH_CTRL_W<DMAOPERATION_MODE_SPEC> {
         RX_THRESH_CTRL_W::new(self, 3)
     }
     #[doc = "Bit 5 - When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit."]
     #[inline(always)]
-    #[must_use]
     pub fn drop_gfrm(&mut self) -> DROP_GFRM_W<DMAOPERATION_MODE_SPEC> {
         DROP_GFRM_W::new(self, 5)
     }
     #[doc = "Bit 6 - When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC."]
     #[inline(always)]
-    #[must_use]
     pub fn fwd_under_gf(&mut self) -> FWD_UNDER_GF_W<DMAOPERATION_MODE_SPEC> {
         FWD_UNDER_GF_W::new(self, 6)
     }
     #[doc = "Bit 7 - When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow)."]
     #[inline(always)]
-    #[must_use]
     pub fn fwd_err_frame(&mut self) -> FWD_ERR_FRAME_W<DMAOPERATION_MODE_SPEC> {
         FWD_ERR_FRAME_W::new(self, 7)
     }
     #[doc = "Bit 13 - When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame."]
     #[inline(always)]
-    #[must_use]
     pub fn start_stop_transmission_command(
         &mut self,
     ) -> START_STOP_TRANSMISSION_COMMAND_W<DMAOPERATION_MODE_SPEC> {
@@ -191,37 +184,31 @@ impl W {
     }
     #[doc = "Bits 14:16 - These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 ."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_thresh_ctrl(&mut self) -> TX_THRESH_CTRL_W<DMAOPERATION_MODE_SPEC> {
         TX_THRESH_CTRL_W::new(self, 14)
     }
     #[doc = "Bit 20 - When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete."]
     #[inline(always)]
-    #[must_use]
     pub fn flush_tx_fifo(&mut self) -> FLUSH_TX_FIFO_W<DMAOPERATION_MODE_SPEC> {
         FLUSH_TX_FIFO_W::new(self, 20)
     }
     #[doc = "Bit 21 - When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_str_fwd(&mut self) -> TX_STR_FWD_W<DMAOPERATION_MODE_SPEC> {
         TX_STR_FWD_W::new(self, 21)
     }
     #[doc = "Bit 24 - When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers."]
     #[inline(always)]
-    #[must_use]
     pub fn dis_flush_recv_frames(&mut self) -> DIS_FLUSH_RECV_FRAMES_W<DMAOPERATION_MODE_SPEC> {
         DIS_FLUSH_RECV_FRAMES_W::new(self, 24)
     }
     #[doc = "Bit 25 - When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_store_forward(&mut self) -> RX_STORE_FORWARD_W<DMAOPERATION_MODE_SPEC> {
         RX_STORE_FORWARD_W::new(self, 25)
     }
     #[doc = "Bit 26 - When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset."]
     #[inline(always)]
-    #[must_use]
     pub fn dis_drop_tcpip_err_fram(&mut self) -> DIS_DROP_TCPIP_ERR_FRAM_W<DMAOPERATION_MODE_SPEC> {
         DIS_DROP_TCPIP_ERR_FRAM_W::new(self, 26)
     }
diff --git a/esp32/src/emac_dma/dmarintwdtimer.rs b/esp32/src/emac_dma/dmarintwdtimer.rs
index 760520c550..16147efd12 100644
--- a/esp32/src/emac_dma/dmarintwdtimer.rs
+++ b/esp32/src/emac_dma/dmarintwdtimer.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1\\[31\\]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1\\[31\\] of any received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn riwtc(&mut self) -> RIWTC_W<DMARINTWDTIMER_SPEC> {
         RIWTC_W::new(self, 0)
     }
diff --git a/esp32/src/emac_dma/dmastatus.rs b/esp32/src/emac_dma/dmastatus.rs
index 65897e4516..0ca1fd9de1 100644
--- a/esp32/src/emac_dma/dmastatus.rs
+++ b/esp32/src/emac_dma/dmastatus.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit indicates that the frame transmission is complete. When transmission is complete Bit\\[31\\] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_int(&mut self) -> TRANS_INT_W<DMASTATUS_SPEC> {
         TRANS_INT_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit is set when the transmission is stopped."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_proc_stop(&mut self) -> TRANS_PROC_STOP_W<DMASTATUS_SPEC> {
         TRANS_PROC_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2 - This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits\\[22:20\\] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0\\[31\\] and then issue a Transmit Poll Demand Command."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_buf_unavail(&mut self) -> TRANS_BUF_UNAVAIL_W<DMASTATUS_SPEC> {
         TRANS_BUF_UNAVAIL_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit indicates that the Transmit Jabber Timer expired which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0\\[14\\] flag to assert."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_jabber_to(&mut self) -> TRANS_JABBER_TO_W<DMASTATUS_SPEC> {
         TRANS_JABBER_TO_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0\\[11\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_ovflow(&mut self) -> RECV_OVFLOW_W<DMASTATUS_SPEC> {
         RECV_OVFLOW_W::new(self, 4)
     }
     #[doc = "Bit 5 - This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0\\[1\\] is set."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_undflow(&mut self) -> TRANS_UNDFLOW_W<DMASTATUS_SPEC> {
         TRANS_UNDFLOW_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit indicates that the frame reception is complete. When reception is complete the Bit\\[31\\] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_int(&mut self) -> RECV_INT_W<DMASTATUS_SPEC> {
         RECV_INT_W::new(self, 6)
     }
     #[doc = "Bit 7 - This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_buf_unavail(&mut self) -> RECV_BUF_UNAVAIL_W<DMASTATUS_SPEC> {
         RECV_BUF_UNAVAIL_W::new(self, 7)
     }
     #[doc = "Bit 8 - This bit is asserted when the Receive Process enters the Stopped state."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_proc_stop(&mut self) -> RECV_PROC_STOP_W<DMASTATUS_SPEC> {
         RECV_PROC_STOP_W::new(self, 8)
     }
     #[doc = "Bit 9 - When set this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_wdt_to(&mut self) -> RECV_WDT_TO_W<DMASTATUS_SPEC> {
         RECV_WDT_TO_W::new(self, 9)
     }
     #[doc = "Bit 10 - This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn early_trans_int(&mut self) -> EARLY_TRANS_INT_W<DMASTATUS_SPEC> {
         EARLY_TRANS_INT_W::new(self, 10)
     }
     #[doc = "Bit 13 - This bit indicates that a bus error occurred as described in Bits \\[25:23\\]. When this bit is set the corresponding DMA engine disables all of its bus accesses."]
     #[inline(always)]
-    #[must_use]
     pub fn fatal_bus_err_int(&mut self) -> FATAL_BUS_ERR_INT_W<DMASTATUS_SPEC> {
         FATAL_BUS_ERR_INT_W::new(self, 13)
     }
     #[doc = "Bit 14 - This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit\\[6\\] (RI) of this register is set (whichever occurs earlier)."]
     #[inline(always)]
-    #[must_use]
     pub fn early_recv_int(&mut self) -> EARLY_RECV_INT_W<DMASTATUS_SPEC> {
         EARLY_RECV_INT_W::new(self, 14)
     }
     #[doc = "Bit 15 - Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit\\[1\\]: Transmit Process Stopped. Bit\\[3\\]: Transmit Jabber Timeout. Bit\\[4\\]: Receive FIFO Overflow. Bit\\[5\\]: Transmit Underflow. Bit\\[7\\]: Receive Buffer Unavailable. Bit\\[8\\]: Receive Process Stopped. Bit\\[9\\]: Receive Watchdog Timeout. Bit\\[10\\]: Early Transmit Interrupt. Bit\\[13\\]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn abn_int_summ(&mut self) -> ABN_INT_SUMM_W<DMASTATUS_SPEC> {
         ABN_INT_SUMM_W::new(self, 15)
     }
     #[doc = "Bit 16 - Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit\\[0\\]: Transmit Interrupt. Bit\\[2\\]: Transmit Buffer Unavailable. Bit\\[6\\]: Receive Interrupt. Bit\\[14\\]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn norm_int_summ(&mut self) -> NORM_INT_SUMM_W<DMASTATUS_SPEC> {
         NORM_INT_SUMM_W::new(self, 16)
     }
     #[doc = "Bits 17:19 - This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory."]
     #[inline(always)]
-    #[must_use]
     pub fn recv_proc_state(&mut self) -> RECV_PROC_STATE_W<DMASTATUS_SPEC> {
         RECV_PROC_STATE_W::new(self, 17)
     }
     #[doc = "Bits 20:22 - This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_proc_state(&mut self) -> TRANS_PROC_STATE_W<DMASTATUS_SPEC> {
         TRANS_PROC_STATE_W::new(self, 20)
     }
     #[doc = "Bits 23:25 - This field indicates the type of error that caused a Bus Error for example error response on the AHB interface. This field is valid only when Bit\\[13\\] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access."]
     #[inline(always)]
-    #[must_use]
     pub fn error_bits(&mut self) -> ERROR_BITS_W<DMASTATUS_SPEC> {
         ERROR_BITS_W::new(self, 23)
     }
     #[doc = "Bit 28 - This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0."]
     #[inline(always)]
-    #[must_use]
     pub fn pmt_int(&mut self) -> PMT_INT_W<DMASTATUS_SPEC> {
         PMT_INT_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0."]
     #[inline(always)]
-    #[must_use]
     pub fn ts_tri_int(&mut self) -> TS_TRI_INT_W<DMASTATUS_SPEC> {
         TS_TRI_INT_W::new(self, 29)
     }
diff --git a/esp32/src/emac_ext/ex_clk_ctrl.rs b/esp32/src/emac_ext/ex_clk_ctrl.rs
index 7db69b46c7..c2105617b0 100644
--- a/esp32/src/emac_ext/ex_clk_ctrl.rs
+++ b/esp32/src/emac_ext/ex_clk_ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_en(&mut self) -> EXT_EN_W<EX_CLK_CTRL_SPEC> {
         EXT_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn int_en(&mut self) -> INT_EN_W<EX_CLK_CTRL_SPEC> {
         INT_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_125_clk_en(&mut self) -> RX_125_CLK_EN_W<EX_CLK_CTRL_SPEC> {
         RX_125_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn mii_clk_tx_en(&mut self) -> MII_CLK_TX_EN_W<EX_CLK_CTRL_SPEC> {
         MII_CLK_TX_EN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn mii_clk_rx_en(&mut self) -> MII_CLK_RX_EN_W<EX_CLK_CTRL_SPEC> {
         MII_CLK_RX_EN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<EX_CLK_CTRL_SPEC> {
         CLK_EN_W::new(self, 5)
     }
diff --git a/esp32/src/emac_ext/ex_clkout_conf.rs b/esp32/src/emac_ext/ex_clkout_conf.rs
index c334b0fe95..443032e059 100644
--- a/esp32/src/emac_ext/ex_clkout_conf.rs
+++ b/esp32/src/emac_ext/ex_clkout_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn div_num(&mut self) -> DIV_NUM_W<EX_CLKOUT_CONF_SPEC> {
         DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn h_div_num(&mut self) -> H_DIV_NUM_W<EX_CLKOUT_CONF_SPEC> {
         H_DIV_NUM_W::new(self, 4)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn dly_num(&mut self) -> DLY_NUM_W<EX_CLKOUT_CONF_SPEC> {
         DLY_NUM_W::new(self, 8)
     }
diff --git a/esp32/src/emac_ext/ex_oscclk_conf.rs b/esp32/src/emac_ext/ex_oscclk_conf.rs
index af4574c4ef..1e10ed9647 100644
--- a/esp32/src/emac_ext/ex_oscclk_conf.rs
+++ b/esp32/src/emac_ext/ex_oscclk_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn div_num_10m(&mut self) -> DIV_NUM_10M_W<EX_OSCCLK_CONF_SPEC> {
         DIV_NUM_10M_W::new(self, 0)
     }
     #[doc = "Bits 6:11"]
     #[inline(always)]
-    #[must_use]
     pub fn h_div_num_10m(&mut self) -> H_DIV_NUM_10M_W<EX_OSCCLK_CONF_SPEC> {
         H_DIV_NUM_10M_W::new(self, 6)
     }
     #[doc = "Bits 12:17"]
     #[inline(always)]
-    #[must_use]
     pub fn div_num_100m(&mut self) -> DIV_NUM_100M_W<EX_OSCCLK_CONF_SPEC> {
         DIV_NUM_100M_W::new(self, 12)
     }
     #[doc = "Bits 18:23"]
     #[inline(always)]
-    #[must_use]
     pub fn h_div_num_100m(&mut self) -> H_DIV_NUM_100M_W<EX_OSCCLK_CONF_SPEC> {
         H_DIV_NUM_100M_W::new(self, 18)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<EX_OSCCLK_CONF_SPEC> {
         CLK_SEL_W::new(self, 24)
     }
diff --git a/esp32/src/emac_ext/ex_phyinf_conf.rs b/esp32/src/emac_ext/ex_phyinf_conf.rs
index 2f38f5b04a..63f1879da6 100644
--- a/esp32/src/emac_ext/ex_phyinf_conf.rs
+++ b/esp32/src/emac_ext/ex_phyinf_conf.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn int_revmii_rx_clk_sel(&mut self) -> INT_REVMII_RX_CLK_SEL_W<EX_PHYINF_CONF_SPEC> {
         INT_REVMII_RX_CLK_SEL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_revmii_rx_clk_sel(&mut self) -> EXT_REVMII_RX_CLK_SEL_W<EX_PHYINF_CONF_SPEC> {
         EXT_REVMII_RX_CLK_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sbd_flowctrl(&mut self) -> SBD_FLOWCTRL_W<EX_PHYINF_CONF_SPEC> {
         SBD_FLOWCTRL_W::new(self, 2)
     }
     #[doc = "Bits 3:7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_phy_addr(&mut self) -> CORE_PHY_ADDR_W<EX_PHYINF_CONF_SPEC> {
         CORE_PHY_ADDR_W::new(self, 3)
     }
     #[doc = "Bits 8:12"]
     #[inline(always)]
-    #[must_use]
     pub fn revmii_phy_addr(&mut self) -> REVMII_PHY_ADDR_W<EX_PHYINF_CONF_SPEC> {
         REVMII_PHY_ADDR_W::new(self, 8)
     }
     #[doc = "Bits 13:15"]
     #[inline(always)]
-    #[must_use]
     pub fn phy_intf_sel(&mut self) -> PHY_INTF_SEL_W<EX_PHYINF_CONF_SPEC> {
         PHY_INTF_SEL_W::new(self, 13)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ss_mode(&mut self) -> SS_MODE_W<EX_PHYINF_CONF_SPEC> {
         SS_MODE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sbd_clk_gating_en(&mut self) -> SBD_CLK_GATING_EN_W<EX_PHYINF_CONF_SPEC> {
         SBD_CLK_GATING_EN_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn pmt_ctrl_en(&mut self) -> PMT_CTRL_EN_W<EX_PHYINF_CONF_SPEC> {
         PMT_CTRL_EN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn scr_smi_dly_rx_sync(&mut self) -> SCR_SMI_DLY_RX_SYNC_W<EX_PHYINF_CONF_SPEC> {
         SCR_SMI_DLY_RX_SYNC_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_err_out_en(&mut self) -> TX_ERR_OUT_EN_W<EX_PHYINF_CONF_SPEC> {
         TX_ERR_OUT_EN_W::new(self, 20)
     }
diff --git a/esp32/src/emac_ext/pd_sel.rs b/esp32/src/emac_ext/pd_sel.rs
index e91eae2827..7d803b8a6a 100644
--- a/esp32/src/emac_ext/pd_sel.rs
+++ b/esp32/src/emac_ext/pd_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn ram_pd_en(&mut self) -> RAM_PD_EN_W<PD_SEL_SPEC> {
         RAM_PD_EN_W::new(self, 0)
     }
diff --git a/esp32/src/emac_mac/emacaddr0high.rs b/esp32/src/emac_mac/emacaddr0high.rs
index ec83cdb10a..722e9903eb 100644
--- a/esp32/src/emac_mac/emacaddr0high.rs
+++ b/esp32/src/emac_mac/emacaddr0high.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames."]
     #[inline(always)]
-    #[must_use]
     pub fn address0_hi(&mut self) -> ADDRESS0_HI_W<EMACADDR0HIGH_SPEC> {
         ADDRESS0_HI_W::new(self, 0)
     }
     #[doc = "Bit 31 - This bit is always set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable0(&mut self) -> ADDRESS_ENABLE0_W<EMACADDR0HIGH_SPEC> {
         ADDRESS_ENABLE0_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr1high.rs b/esp32/src/emac_mac/emacaddr1high.rs
index c3c3595429..f0f13089c4 100644
--- a/esp32/src/emac_mac/emacaddr1high.rs
+++ b/esp32/src/emac_mac/emacaddr1high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the second 6-byte MAC Address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address1_hi(&mut self) -> MAC_ADDRESS1_HI_W<EMACADDR1HIGH_SPEC> {
         MAC_ADDRESS1_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR1 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR1 High \\[15:8\\]. Bit\\[28\\]: EMACADDR1 High \\[7:0\\]. Bit\\[27\\]: EMACADDR1 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR1 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control(&mut self) -> MASK_BYTE_CONTROL_W<EMACADDR1HIGH_SPEC> {
         MASK_BYTE_CONTROL_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR1\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR1\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address(&mut self) -> SOURCE_ADDRESS_W<EMACADDR1HIGH_SPEC> {
         SOURCE_ADDRESS_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable1(&mut self) -> ADDRESS_ENABLE1_W<EMACADDR1HIGH_SPEC> {
         ADDRESS_ENABLE1_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr2high.rs b/esp32/src/emac_mac/emacaddr2high.rs
index cc0d83a06c..0f31bfbff6 100644
--- a/esp32/src/emac_mac/emacaddr2high.rs
+++ b/esp32/src/emac_mac/emacaddr2high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the third 6-byte MAC address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address2_hi(&mut self) -> MAC_ADDRESS2_HI_W<EMACADDR2HIGH_SPEC> {
         MAC_ADDRESS2_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR2 High \\[15:8\\]. Bit\\[28\\]: EMACADDR2 High \\[7:0\\]. Bit\\[27\\]: EMACADDR2 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR2 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control2(&mut self) -> MASK_BYTE_CONTROL2_W<EMACADDR2HIGH_SPEC> {
         MASK_BYTE_CONTROL2_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR2\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR2\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address2(&mut self) -> SOURCE_ADDRESS2_W<EMACADDR2HIGH_SPEC> {
         SOURCE_ADDRESS2_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the third MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable2(&mut self) -> ADDRESS_ENABLE2_W<EMACADDR2HIGH_SPEC> {
         ADDRESS_ENABLE2_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr3high.rs b/esp32/src/emac_mac/emacaddr3high.rs
index 628b4910ab..c162634a25 100644
--- a/esp32/src/emac_mac/emacaddr3high.rs
+++ b/esp32/src/emac_mac/emacaddr3high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the fourth 6-byte MAC address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address3_hi(&mut self) -> MAC_ADDRESS3_HI_W<EMACADDR3HIGH_SPEC> {
         MAC_ADDRESS3_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR3 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR3 High \\[15:8\\]. Bit\\[28\\]: EMACADDR3 High \\[7:0\\]. Bit\\[27\\]: EMACADDR3 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR3 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control3(&mut self) -> MASK_BYTE_CONTROL3_W<EMACADDR3HIGH_SPEC> {
         MASK_BYTE_CONTROL3_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR3\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address3(&mut self) -> SOURCE_ADDRESS3_W<EMACADDR3HIGH_SPEC> {
         SOURCE_ADDRESS3_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the fourth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable3(&mut self) -> ADDRESS_ENABLE3_W<EMACADDR3HIGH_SPEC> {
         ADDRESS_ENABLE3_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr4high.rs b/esp32/src/emac_mac/emacaddr4high.rs
index cad341a937..462c6627ac 100644
--- a/esp32/src/emac_mac/emacaddr4high.rs
+++ b/esp32/src/emac_mac/emacaddr4high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the fifth 6-byte MAC address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address4_hi(&mut self) -> MAC_ADDRESS4_HI_W<EMACADDR4HIGH_SPEC> {
         MAC_ADDRESS4_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR4 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR4 High \\[15:8\\]. Bit\\[28\\]: EMACADDR4 High \\[7:0\\]. Bit\\[27\\]: EMACADDR4 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR4 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control4(&mut self) -> MASK_BYTE_CONTROL4_W<EMACADDR4HIGH_SPEC> {
         MASK_BYTE_CONTROL4_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR4\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR4\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address4(&mut self) -> SOURCE_ADDRESS4_W<EMACADDR4HIGH_SPEC> {
         SOURCE_ADDRESS4_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the fifth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable4(&mut self) -> ADDRESS_ENABLE4_W<EMACADDR4HIGH_SPEC> {
         ADDRESS_ENABLE4_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr5high.rs b/esp32/src/emac_mac/emacaddr5high.rs
index 060362e1cc..d2290addcf 100644
--- a/esp32/src/emac_mac/emacaddr5high.rs
+++ b/esp32/src/emac_mac/emacaddr5high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the sixth 6-byte MAC address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address5_hi(&mut self) -> MAC_ADDRESS5_HI_W<EMACADDR5HIGH_SPEC> {
         MAC_ADDRESS5_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR5 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR5 High \\[15:8\\]. Bit\\[28\\]: EMACADDR5 High \\[7:0\\]. Bit\\[27\\]: EMACADDR5 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR5 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control5(&mut self) -> MASK_BYTE_CONTROL5_W<EMACADDR5HIGH_SPEC> {
         MASK_BYTE_CONTROL5_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR5\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR5\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address5(&mut self) -> SOURCE_ADDRESS5_W<EMACADDR5HIGH_SPEC> {
         SOURCE_ADDRESS5_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable5(&mut self) -> ADDRESS_ENABLE5_W<EMACADDR5HIGH_SPEC> {
         ADDRESS_ENABLE5_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr6high.rs b/esp32/src/emac_mac/emacaddr6high.rs
index ff43b92f62..30ea34f927 100644
--- a/esp32/src/emac_mac/emacaddr6high.rs
+++ b/esp32/src/emac_mac/emacaddr6high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the seventh 6-byte MAC Address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address6_hi(&mut self) -> MAC_ADDRESS6_HI_W<EMACADDR6HIGH_SPEC> {
         MAC_ADDRESS6_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR6 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR6 High \\[15:8\\]. Bit\\[28\\]: EMACADDR6 High \\[7:0\\]. Bit\\[27\\]: EMACADDR6 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR6 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control6(&mut self) -> MASK_BYTE_CONTROL6_W<EMACADDR6HIGH_SPEC> {
         MASK_BYTE_CONTROL6_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR6\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR6\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address6(&mut self) -> SOURCE_ADDRESS6_W<EMACADDR6HIGH_SPEC> {
         SOURCE_ADDRESS6_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the seventh MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable6(&mut self) -> ADDRESS_ENABLE6_W<EMACADDR6HIGH_SPEC> {
         ADDRESS_ENABLE6_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacaddr7high.rs b/esp32/src/emac_mac/emacaddr7high.rs
index 81d41aa00f..9470888703 100644
--- a/esp32/src/emac_mac/emacaddr7high.rs
+++ b/esp32/src/emac_mac/emacaddr7high.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the eighth 6-byte MAC Address."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_address7_hi(&mut self) -> MAC_ADDRESS7_HI_W<EMACADDR7HIGH_SPEC> {
         MAC_ADDRESS7_HI_W::new(self, 0)
     }
     #[doc = "Bits 24:29 - These bits are mask control bits for comparison of each of the EMACADDR7 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows: Bit\\[29\\]: EMACADDR7 High \\[15:8\\]. Bit\\[28\\]: EMACADDR7 High \\[7:0\\]. Bit\\[27\\]: EMACADDR7 Low \\[31:24\\]. Bit\\[24\\]: EMACADDR7 Low \\[7:0\\].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address."]
     #[inline(always)]
-    #[must_use]
     pub fn mask_byte_control7(&mut self) -> MASK_BYTE_CONTROL7_W<EMACADDR7HIGH_SPEC> {
         MASK_BYTE_CONTROL7_W::new(self, 24)
     }
     #[doc = "Bit 30 - When this bit is set the EMACADDR7\\[47:0\\] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR7\\[47:0\\] is used to compare with the DA fields of the received frame."]
     #[inline(always)]
-    #[must_use]
     pub fn source_address7(&mut self) -> SOURCE_ADDRESS7_W<EMACADDR7HIGH_SPEC> {
         SOURCE_ADDRESS7_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering."]
     #[inline(always)]
-    #[must_use]
     pub fn address_enable7(&mut self) -> ADDRESS_ENABLE7_W<EMACADDR7HIGH_SPEC> {
         ADDRESS_ENABLE7_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacconfig.rs b/esp32/src/emac_mac/emacconfig.rs
index 6e1ac18ce8..27546db54d 100644
--- a/esp32/src/emac_mac/emacconfig.rs
+++ b/esp32/src/emac_mac/emacconfig.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble."]
     #[inline(always)]
-    #[must_use]
     pub fn pltf(&mut self) -> PLTF_W<EMACCONFIG_SPEC> {
         PLTF_W::new(self, 0)
     }
     #[doc = "Bit 2 - When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII."]
     #[inline(always)]
-    #[must_use]
     pub fn rx(&mut self) -> RX_W<EMACCONFIG_SPEC> {
         RX_W::new(self, 2)
     }
     #[doc = "Bit 3 - When this bit is set the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames."]
     #[inline(always)]
-    #[must_use]
     pub fn tx(&mut self) -> TX_W<EMACCONFIG_SPEC> {
         TX_W::new(self, 3)
     }
     #[doc = "Bit 4 - Deferral Check."]
     #[inline(always)]
-    #[must_use]
     pub fn deferralcheck(&mut self) -> DEFERRALCHECK_W<EMACCONFIG_SPEC> {
         DEFERRALCHECK_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000."]
     #[inline(always)]
-    #[must_use]
     pub fn backofflimit(&mut self) -> BACKOFFLIMIT_W<EMACCONFIG_SPEC> {
         BACKOFFLIMIT_W::new(self, 5)
     }
     #[doc = "Bit 7 - When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host."]
     #[inline(always)]
-    #[must_use]
     pub fn padcrcstrip(&mut self) -> PADCRCSTRIP_W<EMACCONFIG_SPEC> {
         PADCRCSTRIP_W::new(self, 7)
     }
     #[doc = "Bit 9 - When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits \\[6:5\\]). This bit is applicable only in the half-duplex Mode."]
     #[inline(always)]
-    #[must_use]
     pub fn retry(&mut self) -> RETRY_W<EMACCONFIG_SPEC> {
         RETRY_W::new(self, 9)
     }
     #[doc = "Bit 10 - When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rxipcoffload(&mut self) -> RXIPCOFFLOAD_W<EMACCONFIG_SPEC> {
         RXIPCOFFLOAD_W::new(self, 10)
     }
     #[doc = "Bit 11 - When this bit is set the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn duplex(&mut self) -> DUPLEX_W<EMACCONFIG_SPEC> {
         DUPLEX_W::new(self, 11)
     }
     #[doc = "Bit 12 - When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally."]
     #[inline(always)]
-    #[must_use]
     pub fn loopback(&mut self) -> LOOPBACK_W<EMACCONFIG_SPEC> {
         LOOPBACK_W::new(self, 12)
     }
     #[doc = "Bit 13 - When this bit is set the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rxown(&mut self) -> RXOWN_W<EMACCONFIG_SPEC> {
         RXOWN_W::new(self, 13)
     }
     #[doc = "Bit 14 - This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps."]
     #[inline(always)]
-    #[must_use]
     pub fn fespeed(&mut self) -> FESPEED_W<EMACCONFIG_SPEC> {
         FESPEED_W::new(self, 14)
     }
     #[doc = "Bit 15 - This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1."]
     #[inline(always)]
-    #[must_use]
     pub fn mii(&mut self) -> MII_W<EMACCONFIG_SPEC> {
         MII_W::new(self, 15)
     }
     #[doc = "Bit 16 - When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions."]
     #[inline(always)]
-    #[must_use]
     pub fn disablecrs(&mut self) -> DISABLECRS_W<EMACCONFIG_SPEC> {
         DISABLECRS_W::new(self, 16)
     }
     #[doc = "Bits 17:19 - These bits control the minimum IFG between frames during transmission. 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered."]
     #[inline(always)]
-    #[must_use]
     pub fn interframegap(&mut self) -> INTERFRAMEGAP_W<EMACCONFIG_SPEC> {
         INTERFRAMEGAP_W::new(self, 17)
     }
     #[doc = "Bit 20 - When this bit is set the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status."]
     #[inline(always)]
-    #[must_use]
     pub fn jumboframe(&mut self) -> JUMBOFRAME_W<EMACCONFIG_SPEC> {
         JUMBOFRAME_W::new(self, 20)
     }
     #[doc = "Bit 22 - When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission."]
     #[inline(always)]
-    #[must_use]
     pub fn jabber(&mut self) -> JABBER_W<EMACCONFIG_SPEC> {
         JABBER_W::new(self, 22)
     }
     #[doc = "Bit 23 - When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn watchdog(&mut self) -> WATCHDOG_W<EMACCONFIG_SPEC> {
         WATCHDOG_W::new(self, 23)
     }
     #[doc = "Bit 27 - When set the MAC considers all frames with up to 2 000 bytes length as normal packets.When Bit\\[20\\] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit\\[20\\] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit\\[20\\] is set setting this bit has no effect on Giant Frame status."]
     #[inline(always)]
-    #[must_use]
     pub fn ass2kp(&mut self) -> ASS2KP_W<EMACCONFIG_SPEC> {
         ASS2KP_W::new(self, 27)
     }
     #[doc = "Bits 28:30 - This field controls the source address insertion or replacement for all transmitted frames.Bit\\[30\\] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits \\[29:28\\]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit\\[30\\] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit\\[30\\] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit\\[30\\] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit\\[30\\] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames."]
     #[inline(always)]
-    #[must_use]
     pub fn sairc(&mut self) -> SAIRC_W<EMACCONFIG_SPEC> {
         SAIRC_W::new(self, 28)
     }
diff --git a/esp32/src/emac_mac/emacfc.rs b/esp32/src/emac_mac/emacfc.rs
index 2f97ae73fb..1b1a8cbacc 100644
--- a/esp32/src/emac_mac/emacfc.rs
+++ b/esp32/src/emac_mac/emacfc.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fcbba(&mut self) -> FCBBA_W<EMACFC_SPEC> {
         FCBBA_W::new(self, 0)
     }
     #[doc = "Bit 1 - In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn tfce(&mut self) -> TFCE_W<EMACFC_SPEC> {
         TFCE_W::new(self, 1)
     }
     #[doc = "Bit 2 - When this bit is set the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rfce(&mut self) -> RFCE_W<EMACFC_SPEC> {
         RFCE_W::new(self, 2)
     }
     #[doc = "Bit 3 - A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address."]
     #[inline(always)]
-    #[must_use]
     pub fn upfd(&mut self) -> UPFD_W<EMACFC_SPEC> {
         UPFD_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits\\[31:16\\]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface."]
     #[inline(always)]
-    #[must_use]
     pub fn plt(&mut self) -> PLT_W<EMACFC_SPEC> {
         PLT_W::new(self, 4)
     }
     #[doc = "Bit 7 - When this bit is set it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn dzpq(&mut self) -> DZPQ_W<EMACFC_SPEC> {
         DZPQ_W::new(self, 7)
     }
     #[doc = "Bits 16:31 - This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain."]
     #[inline(always)]
-    #[must_use]
     pub fn pause_time(&mut self) -> PAUSE_TIME_W<EMACFC_SPEC> {
         PAUSE_TIME_W::new(self, 16)
     }
diff --git a/esp32/src/emac_mac/emacff.rs b/esp32/src/emac_mac/emacff.rs
index 434d80934b..747c709f72 100644
--- a/esp32/src/emac_mac/emacff.rs
+++ b/esp32/src/emac_mac/emacff.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set."]
     #[inline(always)]
-    #[must_use]
     pub fn pmode(&mut self) -> PMODE_W<EMACFF_SPEC> {
         PMODE_W::new(self, 0)
     }
     #[doc = "Bit 3 - When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed."]
     #[inline(always)]
-    #[must_use]
     pub fn daif(&mut self) -> DAIF_W<EMACFF_SPEC> {
         DAIF_W::new(self, 3)
     }
     #[doc = "Bit 4 - When set this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed."]
     #[inline(always)]
-    #[must_use]
     pub fn pam(&mut self) -> PAM_W<EMACFF_SPEC> {
         PAM_W::new(self, 4)
     }
     #[doc = "Bit 5 - When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames."]
     #[inline(always)]
-    #[must_use]
     pub fn dbf(&mut self) -> DBF_W<EMACFF_SPEC> {
         DBF_W::new(self, 5)
     }
     #[doc = "Bits 6:7 - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001."]
     #[inline(always)]
-    #[must_use]
     pub fn pcf(&mut self) -> PCF_W<EMACFF_SPEC> {
         PCF_W::new(self, 6)
     }
     #[doc = "Bit 8 - When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter."]
     #[inline(always)]
-    #[must_use]
     pub fn saif(&mut self) -> SAIF_W<EMACFF_SPEC> {
         SAIF_W::new(self, 8)
     }
     #[doc = "Bit 9 - When this bit is set the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison."]
     #[inline(always)]
-    #[must_use]
     pub fn safe(&mut self) -> SAFE_W<EMACFF_SPEC> {
         SAFE_W::new(self, 9)
     }
     #[doc = "Bit 31 - When this bit is set the MAC Receiver module passes all received frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter."]
     #[inline(always)]
-    #[must_use]
     pub fn receive_all(&mut self) -> RECEIVE_ALL_W<EMACFF_SPEC> {
         RECEIVE_ALL_W::new(self, 31)
     }
diff --git a/esp32/src/emac_mac/emacgmiiaddr.rs b/esp32/src/emac_mac/emacgmiiaddr.rs
index 4d1f796f2d..fd3b1c9689 100644
--- a/esp32/src/emac_mac/emacgmiiaddr.rs
+++ b/esp32/src/emac_mac/emacgmiiaddr.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present."]
     #[inline(always)]
-    #[must_use]
     pub fn miibusy(&mut self) -> MIIBUSY_W<EMACGMIIADDR_SPEC> {
         MIIBUSY_W::new(self, 0)
     }
     #[doc = "Bit 1 - When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register."]
     #[inline(always)]
-    #[must_use]
     pub fn miiwrite(&mut self) -> MIIWRITE_W<EMACGMIIADDR_SPEC> {
         MIIWRITE_W::new(self, 1)
     }
     #[doc = "Bits 2:5 - CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0011: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26."]
     #[inline(always)]
-    #[must_use]
     pub fn miicsrclk(&mut self) -> MIICSRCLK_W<EMACGMIIADDR_SPEC> {
         MIICSRCLK_W::new(self, 2)
     }
     #[doc = "Bits 6:10 - These bits select the desired MII register in the selected PHY device."]
     #[inline(always)]
-    #[must_use]
     pub fn miireg(&mut self) -> MIIREG_W<EMACGMIIADDR_SPEC> {
         MIIREG_W::new(self, 6)
     }
     #[doc = "Bits 11:15 - This field indicates which of the 32 possible PHY devices are being accessed."]
     #[inline(always)]
-    #[must_use]
     pub fn miidev(&mut self) -> MIIDEV_W<EMACGMIIADDR_SPEC> {
         MIIDEV_W::new(self, 11)
     }
diff --git a/esp32/src/emac_mac/emacintmask.rs b/esp32/src/emac_mac/emacintmask.rs
index cf81aa4ad9..4f3394f590 100644
--- a/esp32/src/emac_mac/emacintmask.rs
+++ b/esp32/src/emac_mac/emacintmask.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - When set this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register)."]
     #[inline(always)]
-    #[must_use]
     pub fn pmtintmask(&mut self) -> PMTINTMASK_W<EMACINTMASK_SPEC> {
         PMTINTMASK_W::new(self, 3)
     }
     #[doc = "Bit 10 - When set this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register)."]
     #[inline(always)]
-    #[must_use]
     pub fn lpiintmask(&mut self) -> LPIINTMASK_W<EMACINTMASK_SPEC> {
         LPIINTMASK_W::new(self, 10)
     }
diff --git a/esp32/src/emac_mac/emacmiidata.rs b/esp32/src/emac_mac/emacmiidata.rs
index 1196820304..dcdd0f7a0e 100644
--- a/esp32/src/emac_mac/emacmiidata.rs
+++ b/esp32/src/emac_mac/emacmiidata.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."]
     #[inline(always)]
-    #[must_use]
     pub fn mii_data(&mut self) -> MII_DATA_W<EMACMIIDATA_SPEC> {
         MII_DATA_W::new(self, 0)
     }
diff --git a/esp32/src/emac_mac/emacwdogto.rs b/esp32/src/emac_mac/emacwdogto.rs
index 1b6a6639d5..2f418844cb 100644
--- a/esp32/src/emac_mac/emacwdogto.rs
+++ b/esp32/src/emac_mac/emacwdogto.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - When Bit\\[16\\] (PWE) is set and Bit\\[23\\] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame."]
     #[inline(always)]
-    #[must_use]
     pub fn wdogto(&mut self) -> WDOGTO_W<EMACWDOGTO_SPEC> {
         WDOGTO_W::new(self, 0)
     }
     #[doc = "Bit 16 - When this bit is set and Bit\\[23\\] (WD) of EMACCONFIG_REG is reset the WTO field (Bits\\[13:0\\]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit\\[23\\] (WD) and Bit\\[20\\] (JE) in EMACCONFIG_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pwdogen(&mut self) -> PWDOGEN_W<EMACWDOGTO_SPEC> {
         PWDOGEN_W::new(self, 16)
     }
diff --git a/esp32/src/flash_encryption/address.rs b/esp32/src/flash_encryption/address.rs
index 84669a00aa..f9d5c4802c 100644
--- a/esp32/src/flash_encryption/address.rs
+++ b/esp32/src/flash_encryption/address.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ADDRESS_SPEC> {
 impl W {
     #[doc = "Bits 0:7 - The physical address on the off-chip flash must be 8-word boundary aligned."]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<ADDRESS_SPEC> {
         ADDRESS_W::new(self, 0)
     }
diff --git a/esp32/src/flash_encryption/buffer_.rs b/esp32/src/flash_encryption/buffer_.rs
index e7640490ed..54f4f3006d 100644
--- a/esp32/src/flash_encryption/buffer_.rs
+++ b/esp32/src/flash_encryption/buffer_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<BUFFER__SPEC> {
 impl W {
     #[doc = "Bits 0:7 - Data buffers for encryption."]
     #[inline(always)]
-    #[must_use]
     pub fn buffer(&mut self) -> BUFFER_W<BUFFER__SPEC> {
         BUFFER_W::new(self, 0)
     }
diff --git a/esp32/src/flash_encryption/start.rs b/esp32/src/flash_encryption/start.rs
index 09aaedf5df..1701f1842f 100644
--- a/esp32/src/flash_encryption/start.rs
+++ b/esp32/src/flash_encryption/start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
 impl W {
     #[doc = "Bits 0:7 - Set this bit to start encryption operation on data buffer."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_start(&mut self) -> FLASH_START_W<START_SPEC> {
         FLASH_START_W::new(self, 0)
     }
diff --git a/esp32/src/frc_timer/timer_alarm.rs b/esp32/src/frc_timer/timer_alarm.rs
index f7f84a2d10..6f645f6a80 100644
--- a/esp32/src/frc_timer/timer_alarm.rs
+++ b/esp32/src/frc_timer/timer_alarm.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_alarm(&mut self) -> TIMER_ALARM_W<TIMER_ALARM_SPEC> {
         TIMER_ALARM_W::new(self, 0)
     }
diff --git a/esp32/src/frc_timer/timer_count.rs b/esp32/src/frc_timer/timer_count.rs
index fe630b3e24..4cd3519786 100644
--- a/esp32/src/frc_timer/timer_count.rs
+++ b/esp32/src/frc_timer/timer_count.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_count(&mut self) -> TIMER_COUNT_W<TIMER_COUNT_SPEC> {
         TIMER_COUNT_W::new(self, 0)
     }
diff --git a/esp32/src/frc_timer/timer_ctrl.rs b/esp32/src/frc_timer/timer_ctrl.rs
index 76b2868221..8017afd1bf 100644
--- a/esp32/src/frc_timer/timer_ctrl.rs
+++ b/esp32/src/frc_timer/timer_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:8"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_prescaler(&mut self) -> TIMER_PRESCALER_W<TIMER_CTRL_SPEC> {
         TIMER_PRESCALER_W::new(self, 1)
     }
diff --git a/esp32/src/frc_timer/timer_int.rs b/esp32/src/frc_timer/timer_int.rs
index 73d9fbedf3..6fc439ad55 100644
--- a/esp32/src/frc_timer/timer_int.rs
+++ b/esp32/src/frc_timer/timer_int.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clr(&mut self) -> CLR_W<TIMER_INT_SPEC> {
         CLR_W::new(self, 0)
     }
diff --git a/esp32/src/frc_timer/timer_load.rs b/esp32/src/frc_timer/timer_load.rs
index b215dcce68..2057770df6 100644
--- a/esp32/src/frc_timer/timer_load.rs
+++ b/esp32/src/frc_timer/timer_load.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn value(&mut self) -> VALUE_W<TIMER_LOAD_SPEC> {
         VALUE_W::new(self, 0)
     }
diff --git a/esp32/src/generic.rs b/esp32/src/generic.rs
index d57106cb27..a7cb020aef 100644
--- a/esp32/src/generic.rs
+++ b/esp32/src/generic.rs
@@ -524,18 +524,60 @@ impl<REG: Resettable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " In the latter case, other fields will be set to their reset value."]
     #[inline(always)]
-    pub fn write<F>(&self, f: F)
+    pub fn write<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes bits to a `Writable` register and produce a value."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[doc = ""]
+    #[doc = " Values can be returned from the closure:"]
+    #[doc = " ```ignore"]
+    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn from_write<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Writable> Reg<REG> {
@@ -547,17 +589,37 @@ impl<REG: Writable> Reg<REG> {
     #[doc = ""]
     #[doc = " Unsafe to use with registers which don't allow to write 0."]
     #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F)
+    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::Ux::default(),
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes 0 to a `Writable` register and produces a value."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable + Writable> Reg<REG> {
@@ -587,25 +649,75 @@ impl<REG: Readable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " Other fields will have the value they had before the call to `modify`."]
     #[inline(always)]
-    pub fn modify<F>(&self, f: F)
+    pub fn modify<F>(&self, f: F) -> REG::Ux
     where
         for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
     {
         let bits = self.register.get();
-        self.register.set(
-            f(
-                &R {
-                    bits,
-                    _reg: marker::PhantomData,
-                },
-                &mut W {
-                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                    _reg: marker::PhantomData,
-                },
-            )
-            .bits,
+        let value = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut W {
+                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            },
+        )
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Modifies the contents of the register by reading and then writing it"]
+    #[doc = " and produces a value."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.modify(|r, w| {"]
+    #[doc = "     let new_bits = r.bits() | 3;"]
+    #[doc = "     unsafe {"]
+    #[doc = "         w.bits(new_bits);"]
+    #[doc = "     }"]
+    #[doc = ""]
+    #[doc = "     new_bits"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn from_modify<F, T>(&self, f: F) -> T
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+    {
+        let bits = self.register.get();
+        let mut writer = W {
+            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut writer,
         );
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
diff --git a/esp32/src/generic/raw.rs b/esp32/src/generic/raw.rs
index 81f5779524..d60a23a7cc 100644
--- a/esp32/src/generic/raw.rs
+++ b/esp32/src/generic/raw.rs
@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
         }
     }
 }
+#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
         }
     }
 }
+#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32/src/gpio/bt_select.rs b/esp32/src/gpio/bt_select.rs
index b4311a7023..eb9bea3878 100644
--- a/esp32/src/gpio/bt_select.rs
+++ b/esp32/src/gpio/bt_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_sel(&mut self) -> BT_SEL_W<BT_SELECT_SPEC> {
         BT_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/cali_conf.rs b/esp32/src/gpio/cali_conf.rs
index f7129cdf75..edee3944c8 100644
--- a/esp32/src/gpio/cali_conf.rs
+++ b/esp32/src/gpio/cali_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
-    #[must_use]
     pub fn cali_rtc_max(&mut self) -> CALI_RTC_MAX_W<CALI_CONF_SPEC> {
         CALI_RTC_MAX_W::new(self, 0)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn cali_start(&mut self) -> CALI_START_W<CALI_CONF_SPEC> {
         CALI_START_W::new(self, 31)
     }
diff --git a/esp32/src/gpio/cpusdio_int1.rs b/esp32/src/gpio/cpusdio_int1.rs
index 2618545cef..04b5ef3020 100644
--- a/esp32/src/gpio/cpusdio_int1.rs
+++ b/esp32/src/gpio/cpusdio_int1.rs
@@ -72,31 +72,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_pad_driver(&mut self) -> PIN_PAD_DRIVER_W<CPUSDIO_INT1_SPEC> {
         PIN_PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 7:9"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_int_type(&mut self) -> PIN_INT_TYPE_W<CPUSDIO_INT1_SPEC> {
         PIN_INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_wakeup_enable(&mut self) -> PIN_WAKEUP_ENABLE_W<CPUSDIO_INT1_SPEC> {
         PIN_WAKEUP_ENABLE_W::new(self, 10)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_config(&mut self) -> PIN_CONFIG_W<CPUSDIO_INT1_SPEC> {
         PIN_CONFIG_W::new(self, 11)
     }
     #[doc = "Bits 13:17"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_int_ena(&mut self) -> PIN_INT_ENA_W<CPUSDIO_INT1_SPEC> {
         PIN_INT_ENA_W::new(self, 13)
     }
diff --git a/esp32/src/gpio/enable.rs b/esp32/src/gpio/enable.rs
index 7ef0e5677b..1ac1db47af 100644
--- a/esp32/src/gpio/enable.rs
+++ b/esp32/src/gpio/enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/enable1.rs b/esp32/src/gpio/enable1.rs
index b3b9075169..6fe0f474c7 100644
--- a/esp32/src/gpio/enable1.rs
+++ b/esp32/src/gpio/enable1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE1_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/enable1_w1tc.rs b/esp32/src/gpio/enable1_w1tc.rs
index 781431cf7d..c85fbaf0d1 100644
--- a/esp32/src/gpio/enable1_w1tc.rs
+++ b/esp32/src/gpio/enable1_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_data_w1tc(&mut self) -> ENABLE1_DATA_W1TC_W<ENABLE1_W1TC_SPEC> {
         ENABLE1_DATA_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/enable1_w1ts.rs b/esp32/src/gpio/enable1_w1ts.rs
index 26fb52d661..582697ff8c 100644
--- a/esp32/src/gpio/enable1_w1ts.rs
+++ b/esp32/src/gpio/enable1_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_data_w1ts(&mut self) -> ENABLE1_DATA_W1TS_W<ENABLE1_W1TS_SPEC> {
         ENABLE1_DATA_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/enable_w1tc.rs b/esp32/src/gpio/enable_w1tc.rs
index 39ece6b404..bfd43335b1 100644
--- a/esp32/src/gpio/enable_w1tc.rs
+++ b/esp32/src/gpio/enable_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_data_w1tc(&mut self) -> ENABLE_DATA_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_DATA_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/enable_w1ts.rs b/esp32/src/gpio/enable_w1ts.rs
index 897b43aaff..c586d8e86e 100644
--- a/esp32/src/gpio/enable_w1ts.rs
+++ b/esp32/src/gpio/enable_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_data_w1ts(&mut self) -> ENABLE_DATA_W1TS_W<ENABLE_W1TS_SPEC> {
         ENABLE_DATA_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/func_in_sel_cfg.rs b/esp32/src/gpio/func_in_sel_cfg.rs
index ae920faba0..3233ed4a3f 100644
--- a/esp32/src/gpio/func_in_sel_cfg.rs
+++ b/esp32/src/gpio/func_in_sel_cfg.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - select one of the 256 inputs"]
     #[inline(always)]
-    #[must_use]
     pub fn in_sel(&mut self) -> IN_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_SEL_W::new(self, 0)
     }
     #[doc = "Bit 6 - revert the value of the input if you want to revert please set the value to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn in_inv_sel(&mut self) -> IN_INV_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_INV_SEL_W::new(self, 6)
     }
     #[doc = "Bit 7 - if the slow signal bypass the io matrix or not if you want setting the value to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         SEL_W::new(self, 7)
     }
diff --git a/esp32/src/gpio/func_out_sel_cfg.rs b/esp32/src/gpio/func_out_sel_cfg.rs
index 6adc93a909..a2980b79b2 100644
--- a/esp32/src/gpio/func_out_sel_cfg.rs
+++ b/esp32/src/gpio/func_out_sel_cfg.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - select one of the 256 output to 40 GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn out_sel(&mut self) -> OUT_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OUT_SEL_W::new(self, 0)
     }
     #[doc = "Bit 9 - invert the output value if you want to revert the output value setting the value to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn inv_sel(&mut self) -> INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         INV_SEL_W::new(self, 9)
     }
     #[doc = "Bit 10 - weather using the logical oen signal or not using the value setting by the register"]
     #[inline(always)]
-    #[must_use]
     pub fn oen_sel(&mut self) -> OEN_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_SEL_W::new(self, 10)
     }
     #[doc = "Bit 11 - invert the output enable value if you want to revert the output enable value setting the value to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn oen_inv_sel(&mut self) -> OEN_INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_INV_SEL_W::new(self, 11)
     }
diff --git a/esp32/src/gpio/in1.rs b/esp32/src/gpio/in1.rs
index 09c027d36a..bf7d841392 100644
--- a/esp32/src/gpio/in1.rs
+++ b/esp32/src/gpio/in1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 input value"]
     #[inline(always)]
-    #[must_use]
     pub fn data_next(&mut self) -> DATA_NEXT_W<IN1_SPEC> {
         DATA_NEXT_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/in_.rs b/esp32/src/gpio/in_.rs
index 0e7a035e1e..ca49ae4178 100644
--- a/esp32/src/gpio/in_.rs
+++ b/esp32/src/gpio/in_.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 input value"]
     #[inline(always)]
-    #[must_use]
     pub fn data_next(&mut self) -> DATA_NEXT_W<IN_SPEC> {
         DATA_NEXT_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out.rs b/esp32/src/gpio/out.rs
index a1dd921944..322be1d88c 100644
--- a/esp32/src/gpio/out.rs
+++ b/esp32/src/gpio/out.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output value"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<OUT_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out1.rs b/esp32/src/gpio/out1.rs
index a29f7e448b..7d17ede1e8 100644
--- a/esp32/src/gpio/out1.rs
+++ b/esp32/src/gpio/out1.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output value"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<OUT1_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out1_w1tc.rs b/esp32/src/gpio/out1_w1tc.rs
index 31c009a60f..b7f3f0b0c2 100644
--- a/esp32/src/gpio/out1_w1tc.rs
+++ b/esp32/src/gpio/out1_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output value write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn out1_data_w1tc(&mut self) -> OUT1_DATA_W1TC_W<OUT1_W1TC_SPEC> {
         OUT1_DATA_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out1_w1ts.rs b/esp32/src/gpio/out1_w1ts.rs
index 4c3de9954b..15d48f4262 100644
--- a/esp32/src/gpio/out1_w1ts.rs
+++ b/esp32/src/gpio/out1_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output value write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn out1_data_w1ts(&mut self) -> OUT1_DATA_W1TS_W<OUT1_W1TS_SPEC> {
         OUT1_DATA_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out_w1tc.rs b/esp32/src/gpio/out_w1tc.rs
index a76654aadc..2a32a6c11a 100644
--- a/esp32/src/gpio/out_w1tc.rs
+++ b/esp32/src/gpio/out_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output value write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_w1tc(&mut self) -> OUT_DATA_W1TC_W<OUT_W1TC_SPEC> {
         OUT_DATA_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/out_w1ts.rs b/esp32/src/gpio/out_w1ts.rs
index 1d6dbdccf3..d6e44a6cc8 100644
--- a/esp32/src/gpio/out_w1ts.rs
+++ b/esp32/src/gpio/out_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output value write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_w1ts(&mut self) -> OUT_DATA_W1TS_W<OUT_W1TS_SPEC> {
         OUT_DATA_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/pin.rs b/esp32/src/gpio/pin.rs
index 08155298ff..f7bf2dae0f 100644
--- a/esp32/src/gpio/pin.rs
+++ b/esp32/src/gpio/pin.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
         INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - GPIO wake up enable only available in light sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
         WAKEUP_ENABLE_W::new(self, 10)
     }
     #[doc = "Bits 11:12 - NA"]
     #[inline(always)]
-    #[must_use]
     pub fn config(&mut self) -> CONFIG_W<PIN_SPEC> {
         CONFIG_W::new(self, 11)
     }
     #[doc = "Bits 13:17 - bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<PIN_SPEC> {
         INT_ENA_W::new(self, 13)
     }
diff --git a/esp32/src/gpio/sdio_select.rs b/esp32/src/gpio/sdio_select.rs
index 591c7f3a6f..63a3ea2bbe 100644
--- a/esp32/src/gpio/sdio_select.rs
+++ b/esp32/src/gpio/sdio_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - SDIO PADS on/off control from outside"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_sel(&mut self) -> SDIO_SEL_W<SDIO_SELECT_SPEC> {
         SDIO_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status.rs b/esp32/src/gpio/status.rs
index 8335e5efd2..07e39fc28f 100644
--- a/esp32/src/gpio/status.rs
+++ b/esp32/src/gpio/status.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 interrupt status"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<STATUS_SPEC> {
         INT_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status1.rs b/esp32/src/gpio/status1.rs
index c6f3215bd4..975cf5f1ff 100644
--- a/esp32/src/gpio/status1.rs
+++ b/esp32/src/gpio/status1.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 interrupt status"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<STATUS1_SPEC> {
         INT_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status1_w1tc.rs b/esp32/src/gpio/status1_w1tc.rs
index c0d73b6b0c..ce7b50fe7e 100644
--- a/esp32/src/gpio/status1_w1tc.rs
+++ b/esp32/src/gpio/status1_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 interrupt status write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn status1_int_w1tc(&mut self) -> STATUS1_INT_W1TC_W<STATUS1_W1TC_SPEC> {
         STATUS1_INT_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status1_w1ts.rs b/esp32/src/gpio/status1_w1ts.rs
index c323d455a3..bf7ba29dff 100644
--- a/esp32/src/gpio/status1_w1ts.rs
+++ b/esp32/src/gpio/status1_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 interrupt status write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn status1_int_w1ts(&mut self) -> STATUS1_INT_W1TS_W<STATUS1_W1TS_SPEC> {
         STATUS1_INT_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status_w1tc.rs b/esp32/src/gpio/status_w1tc.rs
index a633c2c4b6..c0a333b61d 100644
--- a/esp32/src/gpio/status_w1tc.rs
+++ b/esp32/src/gpio/status_w1tc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 interrupt status write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn status_int_w1tc(&mut self) -> STATUS_INT_W1TC_W<STATUS_W1TC_SPEC> {
         STATUS_INT_W1TC_W::new(self, 0)
     }
diff --git a/esp32/src/gpio/status_w1ts.rs b/esp32/src/gpio/status_w1ts.rs
index 0a720ce613..d23d21780d 100644
--- a/esp32/src/gpio/status_w1ts.rs
+++ b/esp32/src/gpio/status_w1ts.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 interrupt status write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn status_int_w1ts(&mut self) -> STATUS_INT_W1TS_W<STATUS_W1TS_SPEC> {
         STATUS_INT_W1TS_W::new(self, 0)
     }
diff --git a/esp32/src/gpio_sd/clock_gate.rs b/esp32/src/gpio_sd/clock_gate.rs
index 811d25f758..a0cfa37381 100644
--- a/esp32/src/gpio_sd/clock_gate.rs
+++ b/esp32/src/gpio_sd/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32/src/gpio_sd/sigmadelta.rs b/esp32/src/gpio_sd/sigmadelta.rs
index fa57f324fe..ae5037f778 100644
--- a/esp32/src/gpio_sd/sigmadelta.rs
+++ b/esp32/src/gpio_sd/sigmadelta.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn in_(&mut self) -> IN_W<SIGMADELTA_SPEC> {
         IN_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<SIGMADELTA_SPEC> {
         PRESCALE_W::new(self, 8)
     }
diff --git a/esp32/src/gpio_sd/sigmadelta_misc.rs b/esp32/src/gpio_sd/sigmadelta_misc.rs
index 885dbae645..90b8ba5e29 100644
--- a/esp32/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32/src/gpio_sd/sigmadelta_misc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_swap(&mut self) -> SPI_SWAP_W<SIGMADELTA_MISC_SPEC> {
         SPI_SWAP_W::new(self, 31)
     }
diff --git a/esp32/src/gpio_sd/version.rs b/esp32/src/gpio_sd/version.rs
index 6745f0c45b..ce3c596e0a 100644
--- a/esp32/src/gpio_sd/version.rs
+++ b/esp32/src/gpio_sd/version.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W<VERSION_SPEC> {
         GPIO_SD_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cfg_data0.rs b/esp32/src/hinf/cfg_data0.rs
index 0e399732a3..6fea552b6f 100644
--- a/esp32/src/hinf/cfg_data0.rs
+++ b/esp32/src/hinf/cfg_data0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn user_id_fn1(&mut self) -> USER_ID_FN1_W<CFG_DATA0_SPEC> {
         USER_ID_FN1_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn device_id_fn1(&mut self) -> DEVICE_ID_FN1_W<CFG_DATA0_SPEC> {
         DEVICE_ID_FN1_W::new(self, 16)
     }
diff --git a/esp32/src/hinf/cfg_data1.rs b/esp32/src/hinf/cfg_data1.rs
index 68da92486c..2d193d3239 100644
--- a/esp32/src/hinf/cfg_data1.rs
+++ b/esp32/src/hinf/cfg_data1.rs
@@ -160,55 +160,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_enable(&mut self) -> SDIO_ENABLE_W<CFG_DATA1_SPEC> {
         SDIO_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_ioready1(&mut self) -> SDIO_IOREADY1_W<CFG_DATA1_SPEC> {
         SDIO_IOREADY1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn highspeed_enable(&mut self) -> HIGHSPEED_ENABLE_W<CFG_DATA1_SPEC> {
         HIGHSPEED_ENABLE_W::new(self, 2)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_cd_enable(&mut self) -> SDIO_CD_ENABLE_W<CFG_DATA1_SPEC> {
         SDIO_CD_ENABLE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_ioready2(&mut self) -> SDIO_IOREADY2_W<CFG_DATA1_SPEC> {
         SDIO_IOREADY2_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<CFG_DATA1_SPEC> {
         SDIO_INT_MASK_W::new(self, 6)
     }
     #[doc = "Bits 12:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio20_conf0(&mut self) -> SDIO20_CONF0_W<CFG_DATA1_SPEC> {
         SDIO20_CONF0_W::new(self, 12)
     }
     #[doc = "Bits 16:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_ver(&mut self) -> SDIO_VER_W<CFG_DATA1_SPEC> {
         SDIO_VER_W::new(self, 16)
     }
     #[doc = "Bits 29:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio20_conf1(&mut self) -> SDIO20_CONF1_W<CFG_DATA1_SPEC> {
         SDIO20_CONF1_W::new(self, 29)
     }
diff --git a/esp32/src/hinf/cfg_data16.rs b/esp32/src/hinf/cfg_data16.rs
index 41b3302860..b057441bb6 100644
--- a/esp32/src/hinf/cfg_data16.rs
+++ b/esp32/src/hinf/cfg_data16.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn user_id_fn2(&mut self) -> USER_ID_FN2_W<CFG_DATA16_SPEC> {
         USER_ID_FN2_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn device_id_fn2(&mut self) -> DEVICE_ID_FN2_W<CFG_DATA16_SPEC> {
         DEVICE_ID_FN2_W::new(self, 16)
     }
diff --git a/esp32/src/hinf/cfg_data7.rs b/esp32/src/hinf/cfg_data7.rs
index 370a77e3c1..d1af600630 100644
--- a/esp32/src/hinf/cfg_data7.rs
+++ b/esp32/src/hinf/cfg_data7.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn pin_state(&mut self) -> PIN_STATE_W<CFG_DATA7_SPEC> {
         PIN_STATE_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn chip_state(&mut self) -> CHIP_STATE_W<CFG_DATA7_SPEC> {
         CHIP_STATE_W::new(self, 8)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_rst(&mut self) -> SDIO_RST_W<CFG_DATA7_SPEC> {
         SDIO_RST_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_ioready0(&mut self) -> SDIO_IOREADY0_W<CFG_DATA7_SPEC> {
         SDIO_IOREADY0_W::new(self, 17)
     }
diff --git a/esp32/src/hinf/cis_conf0.rs b/esp32/src/hinf/cis_conf0.rs
index aea73f2eff..9a62f385fd 100644
--- a/esp32/src/hinf/cis_conf0.rs
+++ b/esp32/src/hinf/cis_conf0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w0(&mut self) -> CIS_CONF_W0_W<CIS_CONF0_SPEC> {
         CIS_CONF_W0_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf1.rs b/esp32/src/hinf/cis_conf1.rs
index 7ce2f2a730..2ed97a1a09 100644
--- a/esp32/src/hinf/cis_conf1.rs
+++ b/esp32/src/hinf/cis_conf1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w1(&mut self) -> CIS_CONF_W1_W<CIS_CONF1_SPEC> {
         CIS_CONF_W1_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf2.rs b/esp32/src/hinf/cis_conf2.rs
index fa6534aee0..3faa6123b2 100644
--- a/esp32/src/hinf/cis_conf2.rs
+++ b/esp32/src/hinf/cis_conf2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w2(&mut self) -> CIS_CONF_W2_W<CIS_CONF2_SPEC> {
         CIS_CONF_W2_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf3.rs b/esp32/src/hinf/cis_conf3.rs
index 07f3f1fdea..2172866ee4 100644
--- a/esp32/src/hinf/cis_conf3.rs
+++ b/esp32/src/hinf/cis_conf3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w3(&mut self) -> CIS_CONF_W3_W<CIS_CONF3_SPEC> {
         CIS_CONF_W3_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf4.rs b/esp32/src/hinf/cis_conf4.rs
index 2da6b6b57f..6f7e1020ef 100644
--- a/esp32/src/hinf/cis_conf4.rs
+++ b/esp32/src/hinf/cis_conf4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w4(&mut self) -> CIS_CONF_W4_W<CIS_CONF4_SPEC> {
         CIS_CONF_W4_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf5.rs b/esp32/src/hinf/cis_conf5.rs
index 1a82d3b504..9f980e04e3 100644
--- a/esp32/src/hinf/cis_conf5.rs
+++ b/esp32/src/hinf/cis_conf5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w5(&mut self) -> CIS_CONF_W5_W<CIS_CONF5_SPEC> {
         CIS_CONF_W5_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf6.rs b/esp32/src/hinf/cis_conf6.rs
index 8ca1f710c4..9589730535 100644
--- a/esp32/src/hinf/cis_conf6.rs
+++ b/esp32/src/hinf/cis_conf6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w6(&mut self) -> CIS_CONF_W6_W<CIS_CONF6_SPEC> {
         CIS_CONF_W6_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/cis_conf7.rs b/esp32/src/hinf/cis_conf7.rs
index afae759cbf..edb51541de 100644
--- a/esp32/src/hinf/cis_conf7.rs
+++ b/esp32/src/hinf/cis_conf7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cis_conf_w7(&mut self) -> CIS_CONF_W7_W<CIS_CONF7_SPEC> {
         CIS_CONF_W7_W::new(self, 0)
     }
diff --git a/esp32/src/hinf/date.rs b/esp32/src/hinf/date.rs
index aff9a71966..20cb4dae5e 100644
--- a/esp32/src/hinf/date.rs
+++ b/esp32/src/hinf/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_date(&mut self) -> SDIO_DATE_W<DATE_SPEC> {
         SDIO_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/comd.rs b/esp32/src/i2c0/comd.rs
index 34e71d2194..f13c770e16 100644
--- a/esp32/src/i2c0/comd.rs
+++ b/esp32/src/i2c0/comd.rs
@@ -170,37 +170,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Number of bytes to be sent or received for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_num(&mut self) -> BYTE_NUM_W<COMD_SPEC> {
         BYTE_NUM_W::new(self, 0)
     }
     #[doc = "Bit 8 - Acknowledge check enable for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_check_en(&mut self) -> ACK_CHECK_EN_W<COMD_SPEC> {
         ACK_CHECK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Acknowledge expected for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_exp(&mut self) -> ACK_EXP_W<COMD_SPEC> {
         ACK_EXP_W::new(self, 9)
     }
     #[doc = "Bit 10 - Acknowledge value for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_value(&mut self) -> ACK_VALUE_W<COMD_SPEC> {
         ACK_VALUE_W::new(self, 10)
     }
     #[doc = "Bits 11:13 - Opcode part of command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn opcode(&mut self) -> OPCODE_W<COMD_SPEC> {
         OPCODE_W::new(self, 11)
     }
     #[doc = "Bit 31 - When command0 is done in I2C Master mode this bit changes to high level."]
     #[inline(always)]
-    #[must_use]
     pub fn command_done(&mut self) -> COMMAND_DONE_W<COMD_SPEC> {
         COMMAND_DONE_W::new(self, 31)
     }
diff --git a/esp32/src/i2c0/ctr.rs b/esp32/src/i2c0/ctr.rs
index 275c9004cb..454e6f7fbb 100644
--- a/esp32/src/i2c0/ctr.rs
+++ b/esp32/src/i2c0/ctr.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level."]
     #[inline(always)]
-    #[must_use]
     pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
         SAMPLE_SCL_LEVEL_W::new(self, 2)
     }
     #[doc = "Bit 4 - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave."]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
         MS_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to start sending data in txfifo."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
         TRANS_START_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
         TX_LSB_FIRST_W::new(self, 6)
     }
     #[doc = "Bit 7 - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
         RX_LSB_FIRST_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the clock gating control bit for reading or writing registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
         CLK_EN_W::new(self, 8)
     }
diff --git a/esp32/src/i2c0/date.rs b/esp32/src/i2c0/date.rs
index 13e52e8aca..859e9515bb 100644
--- a/esp32/src/i2c0/date.rs
+++ b/esp32/src/i2c0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/fifo_conf.rs b/esp32/src/i2c0/fifo_conf.rs
index e4daca64ce..4849f63bd4 100644
--- a/esp32/src/i2c0/fifo_conf.rs
+++ b/esp32/src/i2c0/fifo_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<FIFO_CONF_SPEC> {
         RXFIFO_FULL_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - Config txfifo empty threhd value when using apb fifo access"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<FIFO_CONF_SPEC> {
         TXFIFO_EMPTY_THRHD_W::new(self, 5)
     }
     #[doc = "Bit 10 - Set this bit to enble apb nonfifo access."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<FIFO_CONF_SPEC> {
         NONFIFO_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W<FIFO_CONF_SPEC> {
         FIFO_ADDR_CFG_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to reset rx fifo when using apb fifo access."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<FIFO_CONF_SPEC> {
         RX_FIFO_RST_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to reset tx fifo when using apb fifo access."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<FIFO_CONF_SPEC> {
         TX_FIFO_RST_W::new(self, 13)
     }
     #[doc = "Bits 14:19 - when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_rx_thres(&mut self) -> NONFIFO_RX_THRES_W<FIFO_CONF_SPEC> {
         NONFIFO_RX_THRES_W::new(self, 14)
     }
     #[doc = "Bits 20:25 - when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_tx_thres(&mut self) -> NONFIFO_TX_THRES_W<FIFO_CONF_SPEC> {
         NONFIFO_TX_THRES_W::new(self, 20)
     }
diff --git a/esp32/src/i2c0/int_clr.rs b/esp32/src/i2c0/int_clr.rs
index 48a32da26a..6c2e774c6f 100644
--- a/esp32/src/i2c0/int_clr.rs
+++ b/esp32/src/i2c0/int_clr.rs
@@ -35,79 +35,66 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the txfifo_empty_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the rxfifo_ovf_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the end_detect_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the slave_tran_comp_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_CLR_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the arbitration_lost_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the master_tran_comp interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_CLR_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the trans_complete_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the time_out_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the trans_start_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the ack_err_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the rx_rec_full_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rec_full(&mut self) -> RX_REC_FULL_W<INT_CLR_SPEC> {
         RX_REC_FULL_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear the tx_send_empty_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_send_empty(&mut self) -> TX_SEND_EMPTY_W<INT_CLR_SPEC> {
         TX_SEND_EMPTY_W::new(self, 12)
     }
diff --git a/esp32/src/i2c0/int_ena.rs b/esp32/src/i2c0/int_ena.rs
index ef73c90ab5..58424f86e9 100644
--- a/esp32/src/i2c0/int_ena.rs
+++ b/esp32/src/i2c0/int_ena.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for rxfifo_full_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for txfifo_empty_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for rxfifo_ovf_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for end_detect_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for slave_tran_comp_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for arbitration_lost_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for master_tran_comp_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for trans_complete_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - The enable bit for time_out_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - The enable bit for trans_start_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - The enable bit for ack_err_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - The enable bit for rx_rec_full_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rec_full(&mut self) -> RX_REC_FULL_W<INT_ENA_SPEC> {
         RX_REC_FULL_W::new(self, 11)
     }
     #[doc = "Bit 12 - The enable bit for tx_send_empty_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_send_empty(&mut self) -> TX_SEND_EMPTY_W<INT_ENA_SPEC> {
         TX_SEND_EMPTY_W::new(self, 12)
     }
diff --git a/esp32/src/i2c0/scl_filter_cfg.rs b/esp32/src/i2c0/scl_filter_cfg.rs
index cf1aac5995..ca9407c1bb 100644
--- a/esp32/src/i2c0/scl_filter_cfg.rs
+++ b/esp32/src/i2c0/scl_filter_cfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - When input SCL's pulse width is smaller than this register value I2C ignores this pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<SCL_FILTER_CFG_SPEC> {
         SCL_FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 3 - This is the filter enable bit for SCL."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<SCL_FILTER_CFG_SPEC> {
         SCL_FILTER_EN_W::new(self, 3)
     }
diff --git a/esp32/src/i2c0/scl_high_period.rs b/esp32/src/i2c0/scl_high_period.rs
index b44e27a437..8d9f9ecf7f 100644
--- a/esp32/src/i2c0/scl_high_period.rs
+++ b/esp32/src/i2c0/scl_high_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the clock num during SCL is low level."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_HIGH_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/scl_low_period.rs b/esp32/src/i2c0/scl_low_period.rs
index eb54303ac3..e434d8923d 100644
--- a/esp32/src/i2c0/scl_low_period.rs
+++ b/esp32/src/i2c0/scl_low_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the low level width of SCL clock."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<SCL_LOW_PERIOD_SPEC> {
         SCL_LOW_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/scl_rstart_setup.rs b/esp32/src/i2c0/scl_rstart_setup.rs
index 92b1bc6f91..cf1b837677 100644
--- a/esp32/src/i2c0/scl_rstart_setup.rs
+++ b/esp32/src/i2c0/scl_rstart_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_RSTART_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/scl_start_hold.rs b/esp32/src/i2c0/scl_start_hold.rs
index ba3fc4f9f7..7d9183684d 100644
--- a/esp32/src/i2c0/scl_start_hold.rs
+++ b/esp32/src/i2c0/scl_start_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_START_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/scl_stop_hold.rs b/esp32/src/i2c0/scl_stop_hold.rs
index f93559ca81..72440c296f 100644
--- a/esp32/src/i2c0/scl_stop_hold.rs
+++ b/esp32/src/i2c0/scl_stop_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the clock num after the STOP bit's posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/scl_stop_setup.rs b/esp32/src/i2c0/scl_stop_setup.rs
index 8dd5dbfbd9..ca94c4ff49 100644
--- a/esp32/src/i2c0/scl_stop_setup.rs
+++ b/esp32/src/i2c0/scl_stop_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the posedge of SCL and the posedge of SDA."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/sda_filter_cfg.rs b/esp32/src/i2c0/sda_filter_cfg.rs
index 177d6af7c5..0da15fb953 100644
--- a/esp32/src/i2c0/sda_filter_cfg.rs
+++ b/esp32/src/i2c0/sda_filter_cfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - When input SCL's pulse width is smaller than this register value I2C ignores this pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<SDA_FILTER_CFG_SPEC> {
         SDA_FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 3 - This is the filter enable bit for SDA."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<SDA_FILTER_CFG_SPEC> {
         SDA_FILTER_EN_W::new(self, 3)
     }
diff --git a/esp32/src/i2c0/sda_hold.rs b/esp32/src/i2c0/sda_hold.rs
index 2acfdcebd8..b0f3b6e7b8 100644
--- a/esp32/src/i2c0/sda_hold.rs
+++ b/esp32/src/i2c0/sda_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num I2C used to hold the data after the negedge of SCL."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/sda_sample.rs b/esp32/src/i2c0/sda_sample.rs
index 6a5b5a169c..6b5212f08c 100644
--- a/esp32/src/i2c0/sda_sample.rs
+++ b/esp32/src/i2c0/sda_sample.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL"]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_SAMPLE_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32/src/i2c0/slave_addr.rs b/esp32/src/i2c0/slave_addr.rs
index 74653fdf23..b0846d3db9 100644
--- a/esp32/src/i2c0/slave_addr.rs
+++ b/esp32/src/i2c0/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - when configured as i2c slave this register is used to configure slave's address."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - This register is used to enable slave 10bit address mode."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
         ADDR_10BIT_EN_W::new(self, 31)
     }
diff --git a/esp32/src/i2c0/to.rs b/esp32/src/i2c0/to.rs
index e748ad9e5e..fda21a38ae 100644
--- a/esp32/src/i2c0/to.rs
+++ b/esp32/src/i2c0/to.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure the max clock number of receiving a data."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<TO_SPEC> {
         TIME_OUT_W::new(self, 0)
     }
diff --git a/esp32/src/i2s0/ahb_test.rs b/esp32/src/i2s0/ahb_test.rs
index f08e85fc77..6556bb57fa 100644
--- a/esp32/src/i2s0/ahb_test.rs
+++ b/esp32/src/i2s0/ahb_test.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
         AHB_TESTMODE_W::new(self, 0)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
         AHB_TESTADDR_W::new(self, 4)
     }
diff --git a/esp32/src/i2s0/clkm_conf.rs b/esp32/src/i2s0/clkm_conf.rs
index 25792bf7b6..eea000a3c4 100644
--- a/esp32/src/i2s0/clkm_conf.rs
+++ b/esp32/src/i2s0/clkm_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
         CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:13"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
         CLKM_DIV_B_W::new(self, 8)
     }
     #[doc = "Bits 14:19"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
         CLKM_DIV_A_W::new(self, 14)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
         CLK_EN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn clka_ena(&mut self) -> CLKA_ENA_W<CLKM_CONF_SPEC> {
         CLKA_ENA_W::new(self, 21)
     }
diff --git a/esp32/src/i2s0/conf.rs b/esp32/src/i2s0/conf.rs
index 33231e3402..a9dae3dfe1 100644
--- a/esp32/src/i2s0/conf.rs
+++ b/esp32/src/i2s0/conf.rs
@@ -204,115 +204,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_reset(&mut self) -> TX_RESET_W<CONF_SPEC> {
         TX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_reset(&mut self) -> RX_RESET_W<CONF_SPEC> {
         RX_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<CONF_SPEC> {
         TX_FIFO_RESET_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<CONF_SPEC> {
         RX_FIFO_RESET_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<CONF_SPEC> {
         TX_START_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<CONF_SPEC> {
         RX_START_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<CONF_SPEC> {
         TX_SLAVE_MOD_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<CONF_SPEC> {
         RX_SLAVE_MOD_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_right_first(&mut self) -> TX_RIGHT_FIRST_W<CONF_SPEC> {
         TX_RIGHT_FIRST_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_right_first(&mut self) -> RX_RIGHT_FIRST_W<CONF_SPEC> {
         RX_RIGHT_FIRST_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<CONF_SPEC> {
         TX_MSB_SHIFT_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<CONF_SPEC> {
         RX_MSB_SHIFT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_short_sync(&mut self) -> TX_SHORT_SYNC_W<CONF_SPEC> {
         TX_SHORT_SYNC_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_short_sync(&mut self) -> RX_SHORT_SYNC_W<CONF_SPEC> {
         RX_SHORT_SYNC_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono(&mut self) -> TX_MONO_W<CONF_SPEC> {
         TX_MONO_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono(&mut self) -> RX_MONO_W<CONF_SPEC> {
         RX_MONO_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_right(&mut self) -> TX_MSB_RIGHT_W<CONF_SPEC> {
         TX_MSB_RIGHT_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_right(&mut self) -> RX_MSB_RIGHT_W<CONF_SPEC> {
         RX_MSB_RIGHT_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<CONF_SPEC> {
         SIG_LOOPBACK_W::new(self, 18)
     }
diff --git a/esp32/src/i2s0/conf1.rs b/esp32/src/i2s0/conf1.rs
index c68e66c38f..61b51fbbab 100644
--- a/esp32/src/i2s0/conf1.rs
+++ b/esp32/src/i2s0/conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<CONF1_SPEC> {
         TX_PCM_CONF_W::new(self, 0)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<CONF1_SPEC> {
         TX_PCM_BYPASS_W::new(self, 3)
     }
     #[doc = "Bits 4:6"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<CONF1_SPEC> {
         RX_PCM_CONF_W::new(self, 4)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<CONF1_SPEC> {
         RX_PCM_BYPASS_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<CONF1_SPEC> {
         TX_STOP_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_zeros_rm_en(&mut self) -> TX_ZEROS_RM_EN_W<CONF1_SPEC> {
         TX_ZEROS_RM_EN_W::new(self, 9)
     }
diff --git a/esp32/src/i2s0/conf2.rs b/esp32/src/i2s0/conf2.rs
index 400831a255..da1adf2143 100644
--- a/esp32/src/i2s0/conf2.rs
+++ b/esp32/src/i2s0/conf2.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn camera_en(&mut self) -> CAMERA_EN_W<CONF2_SPEC> {
         CAMERA_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_tx_wrx2_en(&mut self) -> LCD_TX_WRX2_EN_W<CONF2_SPEC> {
         LCD_TX_WRX2_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_tx_sdx2_en(&mut self) -> LCD_TX_SDX2_EN_W<CONF2_SPEC> {
         LCD_TX_SDX2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable_test_en(&mut self) -> DATA_ENABLE_TEST_EN_W<CONF2_SPEC> {
         DATA_ENABLE_TEST_EN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable(&mut self) -> DATA_ENABLE_W<CONF2_SPEC> {
         DATA_ENABLE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_en(&mut self) -> LCD_EN_W<CONF2_SPEC> {
         LCD_EN_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_adc_start_en(&mut self) -> EXT_ADC_START_EN_W<CONF2_SPEC> {
         EXT_ADC_START_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_valid_en(&mut self) -> INTER_VALID_EN_W<CONF2_SPEC> {
         INTER_VALID_EN_W::new(self, 7)
     }
diff --git a/esp32/src/i2s0/conf_chan.rs b/esp32/src/i2s0/conf_chan.rs
index 503feb2248..3c149fa6a8 100644
--- a/esp32/src/i2s0/conf_chan.rs
+++ b/esp32/src/i2s0/conf_chan.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<CONF_CHAN_SPEC> {
         TX_CHAN_MOD_W::new(self, 0)
     }
     #[doc = "Bits 3:4"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_chan_mod(&mut self) -> RX_CHAN_MOD_W<CONF_CHAN_SPEC> {
         RX_CHAN_MOD_W::new(self, 3)
     }
diff --git a/esp32/src/i2s0/conf_sigle_data.rs b/esp32/src/i2s0/conf_sigle_data.rs
index c1f9e52e40..6d613f2eaa 100644
--- a/esp32/src/i2s0/conf_sigle_data.rs
+++ b/esp32/src/i2s0/conf_sigle_data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sigle_data(&mut self) -> SIGLE_DATA_W<CONF_SIGLE_DATA_SPEC> {
         SIGLE_DATA_W::new(self, 0)
     }
diff --git a/esp32/src/i2s0/cvsd_conf0.rs b/esp32/src/i2s0/cvsd_conf0.rs
index 8c100a2d3a..944371b686 100644
--- a/esp32/src/i2s0/cvsd_conf0.rs
+++ b/esp32/src/i2s0/cvsd_conf0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_y_max(&mut self) -> CVSD_Y_MAX_W<CVSD_CONF0_SPEC> {
         CVSD_Y_MAX_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_y_min(&mut self) -> CVSD_Y_MIN_W<CVSD_CONF0_SPEC> {
         CVSD_Y_MIN_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/cvsd_conf1.rs b/esp32/src/i2s0/cvsd_conf1.rs
index 952bb5ccf3..7be2d30f64 100644
--- a/esp32/src/i2s0/cvsd_conf1.rs
+++ b/esp32/src/i2s0/cvsd_conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_sigma_max(&mut self) -> CVSD_SIGMA_MAX_W<CVSD_CONF1_SPEC> {
         CVSD_SIGMA_MAX_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_sigma_min(&mut self) -> CVSD_SIGMA_MIN_W<CVSD_CONF1_SPEC> {
         CVSD_SIGMA_MIN_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/cvsd_conf2.rs b/esp32/src/i2s0/cvsd_conf2.rs
index 890db515d7..597dde0b12 100644
--- a/esp32/src/i2s0/cvsd_conf2.rs
+++ b/esp32/src/i2s0/cvsd_conf2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_k(&mut self) -> CVSD_K_W<CVSD_CONF2_SPEC> {
         CVSD_K_W::new(self, 0)
     }
     #[doc = "Bits 3:5"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_j(&mut self) -> CVSD_J_W<CVSD_CONF2_SPEC> {
         CVSD_J_W::new(self, 3)
     }
     #[doc = "Bits 6:15"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_beta(&mut self) -> CVSD_BETA_W<CVSD_CONF2_SPEC> {
         CVSD_BETA_W::new(self, 6)
     }
     #[doc = "Bits 16:18"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_h(&mut self) -> CVSD_H_W<CVSD_CONF2_SPEC> {
         CVSD_H_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/date.rs b/esp32/src/i2s0/date.rs
index 6491c96072..a3505b6f6e 100644
--- a/esp32/src/i2s0/date.rs
+++ b/esp32/src/i2s0/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn i2sdate(&mut self) -> I2SDATE_W<DATE_SPEC> {
         I2SDATE_W::new(self, 0)
     }
diff --git a/esp32/src/i2s0/esco_conf0.rs b/esp32/src/i2s0/esco_conf0.rs
index ff5f6a9db3..d8a40e8abb 100644
--- a/esp32/src/i2s0/esco_conf0.rs
+++ b/esp32/src/i2s0/esco_conf0.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn esco_en(&mut self) -> ESCO_EN_W<ESCO_CONF0_SPEC> {
         ESCO_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn esco_chan_mod(&mut self) -> ESCO_CHAN_MOD_W<ESCO_CONF0_SPEC> {
         ESCO_CHAN_MOD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn esco_cvsd_dec_pack_err(&mut self) -> ESCO_CVSD_DEC_PACK_ERR_W<ESCO_CONF0_SPEC> {
         ESCO_CVSD_DEC_PACK_ERR_W::new(self, 2)
     }
     #[doc = "Bits 3:7"]
     #[inline(always)]
-    #[must_use]
     pub fn esco_cvsd_pack_len_8k(&mut self) -> ESCO_CVSD_PACK_LEN_8K_W<ESCO_CONF0_SPEC> {
         ESCO_CVSD_PACK_LEN_8K_W::new(self, 3)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn esco_cvsd_inf_en(&mut self) -> ESCO_CVSD_INF_EN_W<ESCO_CONF0_SPEC> {
         ESCO_CVSD_INF_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_dec_start(&mut self) -> CVSD_DEC_START_W<ESCO_CONF0_SPEC> {
         CVSD_DEC_START_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_dec_reset(&mut self) -> CVSD_DEC_RESET_W<ESCO_CONF0_SPEC> {
         CVSD_DEC_RESET_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn plc_en(&mut self) -> PLC_EN_W<ESCO_CONF0_SPEC> {
         PLC_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn plc2dma_en(&mut self) -> PLC2DMA_EN_W<ESCO_CONF0_SPEC> {
         PLC2DMA_EN_W::new(self, 12)
     }
diff --git a/esp32/src/i2s0/fifo_conf.rs b/esp32/src/i2s0/fifo_conf.rs
index c041bde1d0..106c2bfdf4 100644
--- a/esp32/src/i2s0/fifo_conf.rs
+++ b/esp32/src/i2s0/fifo_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data_num(&mut self) -> RX_DATA_NUM_W<FIFO_CONF_SPEC> {
         RX_DATA_NUM_W::new(self, 0)
     }
     #[doc = "Bits 6:11"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data_num(&mut self) -> TX_DATA_NUM_W<FIFO_CONF_SPEC> {
         TX_DATA_NUM_W::new(self, 6)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn dscr_en(&mut self) -> DSCR_EN_W<FIFO_CONF_SPEC> {
         DSCR_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:15"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_mod(&mut self) -> TX_FIFO_MOD_W<FIFO_CONF_SPEC> {
         TX_FIFO_MOD_W::new(self, 13)
     }
     #[doc = "Bits 16:18"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_mod(&mut self) -> RX_FIFO_MOD_W<FIFO_CONF_SPEC> {
         RX_FIFO_MOD_W::new(self, 16)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_mod_force_en(&mut self) -> TX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
         TX_FIFO_MOD_FORCE_EN_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_mod_force_en(&mut self) -> RX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
         RX_FIFO_MOD_FORCE_EN_W::new(self, 20)
     }
diff --git a/esp32/src/i2s0/in_link.rs b/esp32/src/i2s0/in_link.rs
index 03db062c09..3c3ac8b8e8 100644
--- a/esp32/src/i2s0/in_link.rs
+++ b/esp32/src/i2s0/in_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/i2s0/infifo_pop.rs b/esp32/src/i2s0/infifo_pop.rs
index b4741f82ee..2976fdf693 100644
--- a/esp32/src/i2s0/infifo_pop.rs
+++ b/esp32/src/i2s0/infifo_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_pop(&mut self) -> INFIFO_POP_W<INFIFO_POP_SPEC> {
         INFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/int_clr.rs b/esp32/src/i2s0/int_clr.rs
index ad21f51b81..a67867e6fc 100644
--- a/esp32/src/i2s0/int_clr.rs
+++ b/esp32/src/i2s0/int_clr.rs
@@ -43,103 +43,86 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn take_data(&mut self) -> TAKE_DATA_W<INT_CLR_SPEC> {
         TAKE_DATA_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn put_data(&mut self) -> PUT_DATA_W<INT_CLR_SPEC> {
         PUT_DATA_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wfull(&mut self) -> RX_WFULL_W<INT_CLR_SPEC> {
         RX_WFULL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rempty(&mut self) -> RX_REMPTY_W<INT_CLR_SPEC> {
         RX_REMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wfull(&mut self) -> TX_WFULL_W<INT_CLR_SPEC> {
         TX_WFULL_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rempty(&mut self) -> TX_REMPTY_W<INT_CLR_SPEC> {
         TX_REMPTY_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
         IN_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
         IN_DSCR_ERR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
         OUT_DSCR_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/int_ena.rs b/esp32/src/i2s0/int_ena.rs
index 962754ad07..99f3d12585 100644
--- a/esp32/src/i2s0/int_ena.rs
+++ b/esp32/src/i2s0/int_ena.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_take_data(&mut self) -> RX_TAKE_DATA_W<INT_ENA_SPEC> {
         RX_TAKE_DATA_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_put_data(&mut self) -> TX_PUT_DATA_W<INT_ENA_SPEC> {
         TX_PUT_DATA_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wfull(&mut self) -> RX_WFULL_W<INT_ENA_SPEC> {
         RX_WFULL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rempty(&mut self) -> RX_REMPTY_W<INT_ENA_SPEC> {
         RX_REMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wfull(&mut self) -> TX_WFULL_W<INT_ENA_SPEC> {
         TX_WFULL_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rempty(&mut self) -> TX_REMPTY_W<INT_ENA_SPEC> {
         TX_REMPTY_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_ENA_SPEC> {
         IN_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_ENA_SPEC> {
         IN_DSCR_ERR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_ENA_SPEC> {
         OUT_DSCR_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_ENA_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/lc_conf.rs b/esp32/src/i2s0/lc_conf.rs
index 4286d3324e..ddd3f3deb2 100644
--- a/esp32/src/i2s0/lc_conf.rs
+++ b/esp32/src/i2s0/lc_conf.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<LC_CONF_SPEC> {
         IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<LC_CONF_SPEC> {
         OUT_RST_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<LC_CONF_SPEC> {
         AHBM_FIFO_RST_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<LC_CONF_SPEC> {
         AHBM_RST_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<LC_CONF_SPEC> {
         OUT_LOOP_TEST_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<LC_CONF_SPEC> {
         IN_LOOP_TEST_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<LC_CONF_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<LC_CONF_SPEC> {
         OUT_NO_RESTART_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<LC_CONF_SPEC> {
         OUT_EOF_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<LC_CONF_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<LC_CONF_SPEC> {
         INDSCR_BURST_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<LC_CONF_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn check_owner(&mut self) -> CHECK_OWNER_W<LC_CONF_SPEC> {
         CHECK_OWNER_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<LC_CONF_SPEC> {
         MEM_TRANS_EN_W::new(self, 13)
     }
diff --git a/esp32/src/i2s0/lc_hung_conf.rs b/esp32/src/i2s0/lc_hung_conf.rs
index 8e9023e194..ed8fa5af57 100644
--- a/esp32/src/i2s0/lc_hung_conf.rs
+++ b/esp32/src/i2s0/lc_hung_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
     }
diff --git a/esp32/src/i2s0/out_link.rs b/esp32/src/i2s0/out_link.rs
index 6c99d12845..064cc51823 100644
--- a/esp32/src/i2s0/out_link.rs
+++ b/esp32/src/i2s0/out_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/i2s0/outfifo_push.rs b/esp32/src/i2s0/outfifo_push.rs
index 66c8688437..fb2684cffb 100644
--- a/esp32/src/i2s0/outfifo_push.rs
+++ b/esp32/src/i2s0/outfifo_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<OUTFIFO_PUSH_SPEC> {
         OUTFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<OUTFIFO_PUSH_SPEC> {
         OUTFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32/src/i2s0/pd_conf.rs b/esp32/src/i2s0/pd_conf.rs
index 95739a9491..1f72926eaf 100644
--- a/esp32/src/i2s0/pd_conf.rs
+++ b/esp32/src/i2s0/pd_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_force_pd(&mut self) -> FIFO_FORCE_PD_W<PD_CONF_SPEC> {
         FIFO_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_force_pu(&mut self) -> FIFO_FORCE_PU_W<PD_CONF_SPEC> {
         FIFO_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn plc_mem_force_pd(&mut self) -> PLC_MEM_FORCE_PD_W<PD_CONF_SPEC> {
         PLC_MEM_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn plc_mem_force_pu(&mut self) -> PLC_MEM_FORCE_PU_W<PD_CONF_SPEC> {
         PLC_MEM_FORCE_PU_W::new(self, 3)
     }
diff --git a/esp32/src/i2s0/pdm_conf.rs b/esp32/src/i2s0/pdm_conf.rs
index 5db4eca59f..8424bf3bd2 100644
--- a/esp32/src/i2s0/pdm_conf.rs
+++ b/esp32/src/i2s0/pdm_conf.rs
@@ -137,73 +137,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<PDM_CONF_SPEC> {
         TX_PDM_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<PDM_CONF_SPEC> {
         RX_PDM_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pcm2pdm_conv_en(&mut self) -> PCM2PDM_CONV_EN_W<PDM_CONF_SPEC> {
         PCM2PDM_CONV_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pdm2pcm_conv_en(&mut self) -> PDM2PCM_CONV_EN_W<PDM_CONF_SPEC> {
         PDM2PCM_CONV_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sinc_osr2(&mut self) -> TX_PDM_SINC_OSR2_W<PDM_CONF_SPEC> {
         TX_PDM_SINC_OSR2_W::new(self, 4)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_prescale(&mut self) -> TX_PDM_PRESCALE_W<PDM_CONF_SPEC> {
         TX_PDM_PRESCALE_W::new(self, 8)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_hp_in_shift(&mut self) -> TX_PDM_HP_IN_SHIFT_W<PDM_CONF_SPEC> {
         TX_PDM_HP_IN_SHIFT_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_lp_in_shift(&mut self) -> TX_PDM_LP_IN_SHIFT_W<PDM_CONF_SPEC> {
         TX_PDM_LP_IN_SHIFT_W::new(self, 18)
     }
     #[doc = "Bits 20:21"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sinc_in_shift(&mut self) -> TX_PDM_SINC_IN_SHIFT_W<PDM_CONF_SPEC> {
         TX_PDM_SINC_IN_SHIFT_W::new(self, 20)
     }
     #[doc = "Bits 22:23"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sigmadelta_in_shift(&mut self) -> TX_PDM_SIGMADELTA_IN_SHIFT_W<PDM_CONF_SPEC> {
         TX_PDM_SIGMADELTA_IN_SHIFT_W::new(self, 22)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W<PDM_CONF_SPEC> {
         RX_PDM_SINC_DSR_16_EN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_hp_bypass(&mut self) -> TX_PDM_HP_BYPASS_W<PDM_CONF_SPEC> {
         TX_PDM_HP_BYPASS_W::new(self, 25)
     }
diff --git a/esp32/src/i2s0/pdm_freq_conf.rs b/esp32/src/i2s0/pdm_freq_conf.rs
index 051f1b55cf..4d765aa3a2 100644
--- a/esp32/src/i2s0/pdm_freq_conf.rs
+++ b/esp32/src/i2s0/pdm_freq_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_fs(&mut self) -> TX_PDM_FS_W<PDM_FREQ_CONF_SPEC> {
         TX_PDM_FS_W::new(self, 0)
     }
     #[doc = "Bits 10:19"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_fp(&mut self) -> TX_PDM_FP_W<PDM_FREQ_CONF_SPEC> {
         TX_PDM_FP_W::new(self, 10)
     }
diff --git a/esp32/src/i2s0/plc_conf0.rs b/esp32/src/i2s0/plc_conf0.rs
index 379d1ade7c..2c5598e11f 100644
--- a/esp32/src/i2s0/plc_conf0.rs
+++ b/esp32/src/i2s0/plc_conf0.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn good_pack_max(&mut self) -> GOOD_PACK_MAX_W<PLC_CONF0_SPEC> {
         GOOD_PACK_MAX_W::new(self, 0)
     }
     #[doc = "Bits 6:8"]
     #[inline(always)]
-    #[must_use]
     pub fn n_err_seg(&mut self) -> N_ERR_SEG_W<PLC_CONF0_SPEC> {
         N_ERR_SEG_W::new(self, 6)
     }
     #[doc = "Bits 9:11"]
     #[inline(always)]
-    #[must_use]
     pub fn shift_rate(&mut self) -> SHIFT_RATE_W<PLC_CONF0_SPEC> {
         SHIFT_RATE_W::new(self, 9)
     }
     #[doc = "Bits 12:19"]
     #[inline(always)]
-    #[must_use]
     pub fn max_slide_sample(&mut self) -> MAX_SLIDE_SAMPLE_W<PLC_CONF0_SPEC> {
         MAX_SLIDE_SAMPLE_W::new(self, 12)
     }
     #[doc = "Bits 20:24"]
     #[inline(always)]
-    #[must_use]
     pub fn pack_len_8k(&mut self) -> PACK_LEN_8K_W<PLC_CONF0_SPEC> {
         PACK_LEN_8K_W::new(self, 20)
     }
     #[doc = "Bits 25:27"]
     #[inline(always)]
-    #[must_use]
     pub fn n_min_err(&mut self) -> N_MIN_ERR_W<PLC_CONF0_SPEC> {
         N_MIN_ERR_W::new(self, 25)
     }
diff --git a/esp32/src/i2s0/plc_conf1.rs b/esp32/src/i2s0/plc_conf1.rs
index 3fdfd72c46..36f017de52 100644
--- a/esp32/src/i2s0/plc_conf1.rs
+++ b/esp32/src/i2s0/plc_conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn bad_cef_atten_para(&mut self) -> BAD_CEF_ATTEN_PARA_W<PLC_CONF1_SPEC> {
         BAD_CEF_ATTEN_PARA_W::new(self, 0)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn bad_cef_atten_para_shift(&mut self) -> BAD_CEF_ATTEN_PARA_SHIFT_W<PLC_CONF1_SPEC> {
         BAD_CEF_ATTEN_PARA_SHIFT_W::new(self, 8)
     }
     #[doc = "Bits 12:15"]
     #[inline(always)]
-    #[must_use]
     pub fn bad_ola_win2_para_shift(&mut self) -> BAD_OLA_WIN2_PARA_SHIFT_W<PLC_CONF1_SPEC> {
         BAD_OLA_WIN2_PARA_SHIFT_W::new(self, 12)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn bad_ola_win2_para(&mut self) -> BAD_OLA_WIN2_PARA_W<PLC_CONF1_SPEC> {
         BAD_OLA_WIN2_PARA_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slide_win_len(&mut self) -> SLIDE_WIN_LEN_W<PLC_CONF1_SPEC> {
         SLIDE_WIN_LEN_W::new(self, 24)
     }
diff --git a/esp32/src/i2s0/plc_conf2.rs b/esp32/src/i2s0/plc_conf2.rs
index 89a98b14ad..85809347c6 100644
--- a/esp32/src/i2s0/plc_conf2.rs
+++ b/esp32/src/i2s0/plc_conf2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_seg_mod(&mut self) -> CVSD_SEG_MOD_W<PLC_CONF2_SPEC> {
         CVSD_SEG_MOD_W::new(self, 0)
     }
     #[doc = "Bits 2:6"]
     #[inline(always)]
-    #[must_use]
     pub fn min_period(&mut self) -> MIN_PERIOD_W<PLC_CONF2_SPEC> {
         MIN_PERIOD_W::new(self, 2)
     }
diff --git a/esp32/src/i2s0/rxeof_num.rs b/esp32/src/i2s0/rxeof_num.rs
index ef2eaa4e57..6cdc4ca78c 100644
--- a/esp32/src/i2s0/rxeof_num.rs
+++ b/esp32/src/i2s0/rxeof_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<RXEOF_NUM_SPEC> {
         RX_EOF_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/i2s0/sample_rate_conf.rs b/esp32/src/i2s0/sample_rate_conf.rs
index 4e48aba6a4..2763a66b2b 100644
--- a/esp32/src/i2s0/sample_rate_conf.rs
+++ b/esp32/src/i2s0/sample_rate_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<SAMPLE_RATE_CONF_SPEC> {
         TX_BCK_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 6:11"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<SAMPLE_RATE_CONF_SPEC> {
         RX_BCK_DIV_NUM_W::new(self, 6)
     }
     #[doc = "Bits 12:17"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<SAMPLE_RATE_CONF_SPEC> {
         TX_BITS_MOD_W::new(self, 12)
     }
     #[doc = "Bits 18:23"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<SAMPLE_RATE_CONF_SPEC> {
         RX_BITS_MOD_W::new(self, 18)
     }
diff --git a/esp32/src/i2s0/sco_conf0.rs b/esp32/src/i2s0/sco_conf0.rs
index dd2d1f54c5..9448765f99 100644
--- a/esp32/src/i2s0/sco_conf0.rs
+++ b/esp32/src/i2s0/sco_conf0.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sco_with_i2s_en(&mut self) -> SCO_WITH_I2S_EN_W<SCO_CONF0_SPEC> {
         SCO_WITH_I2S_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sco_no_i2s_en(&mut self) -> SCO_NO_I2S_EN_W<SCO_CONF0_SPEC> {
         SCO_NO_I2S_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_enc_start(&mut self) -> CVSD_ENC_START_W<SCO_CONF0_SPEC> {
         CVSD_ENC_START_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn cvsd_enc_reset(&mut self) -> CVSD_ENC_RESET_W<SCO_CONF0_SPEC> {
         CVSD_ENC_RESET_W::new(self, 3)
     }
diff --git a/esp32/src/i2s0/timing.rs b/esp32/src/i2s0/timing.rs
index 2b0cee1bc0..ca7c0b45f8 100644
--- a/esp32/src/i2s0/timing.rs
+++ b/esp32/src/i2s0/timing.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_delay(&mut self) -> TX_BCK_IN_DELAY_W<TIMING_SPEC> {
         TX_BCK_IN_DELAY_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_in_delay(&mut self) -> TX_WS_IN_DELAY_W<TIMING_SPEC> {
         TX_WS_IN_DELAY_W::new(self, 2)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_in_delay(&mut self) -> RX_BCK_IN_DELAY_W<TIMING_SPEC> {
         RX_BCK_IN_DELAY_W::new(self, 4)
     }
     #[doc = "Bits 6:7"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_in_delay(&mut self) -> RX_WS_IN_DELAY_W<TIMING_SPEC> {
         RX_WS_IN_DELAY_W::new(self, 6)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd_in_delay(&mut self) -> RX_SD_IN_DELAY_W<TIMING_SPEC> {
         RX_SD_IN_DELAY_W::new(self, 8)
     }
     #[doc = "Bits 10:11"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_out_delay(&mut self) -> TX_BCK_OUT_DELAY_W<TIMING_SPEC> {
         TX_BCK_OUT_DELAY_W::new(self, 10)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_out_delay(&mut self) -> TX_WS_OUT_DELAY_W<TIMING_SPEC> {
         TX_WS_OUT_DELAY_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd_out_delay(&mut self) -> TX_SD_OUT_DELAY_W<TIMING_SPEC> {
         TX_SD_OUT_DELAY_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_out_delay(&mut self) -> RX_WS_OUT_DELAY_W<TIMING_SPEC> {
         RX_WS_OUT_DELAY_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_out_delay(&mut self) -> RX_BCK_OUT_DELAY_W<TIMING_SPEC> {
         RX_BCK_OUT_DELAY_W::new(self, 18)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dsync_sw(&mut self) -> TX_DSYNC_SW_W<TIMING_SPEC> {
         TX_DSYNC_SW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dsync_sw(&mut self) -> RX_DSYNC_SW_W<TIMING_SPEC> {
         RX_DSYNC_SW_W::new(self, 21)
     }
     #[doc = "Bits 22:23"]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable_delay(&mut self) -> DATA_ENABLE_DELAY_W<TIMING_SPEC> {
         DATA_ENABLE_DELAY_W::new(self, 22)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_inv(&mut self) -> TX_BCK_IN_INV_W<TIMING_SPEC> {
         TX_BCK_IN_INV_W::new(self, 24)
     }
diff --git a/esp32/src/io_mux/gpio0.rs b/esp32/src/io_mux/gpio0.rs
index 656fe80bb4..234f690253 100644
--- a/esp32/src/io_mux/gpio0.rs
+++ b/esp32/src/io_mux/gpio0.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO0_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO0_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO0_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO0_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO0_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO0_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO0_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO0_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO0_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO0_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO0_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio1.rs b/esp32/src/io_mux/gpio1.rs
index a1d96fcfc2..23978b03ae 100644
--- a/esp32/src/io_mux/gpio1.rs
+++ b/esp32/src/io_mux/gpio1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO1_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO1_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO1_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO1_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO1_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO1_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO1_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO1_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO1_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO1_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO1_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio10.rs b/esp32/src/io_mux/gpio10.rs
index 514fe829f8..1d5bf219ae 100644
--- a/esp32/src/io_mux/gpio10.rs
+++ b/esp32/src/io_mux/gpio10.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO10_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO10_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO10_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO10_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO10_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO10_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO10_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO10_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO10_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO10_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO10_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio11.rs b/esp32/src/io_mux/gpio11.rs
index f0d667d4b5..1617677698 100644
--- a/esp32/src/io_mux/gpio11.rs
+++ b/esp32/src/io_mux/gpio11.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO11_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO11_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO11_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO11_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO11_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO11_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO11_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO11_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO11_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO11_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO11_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio12.rs b/esp32/src/io_mux/gpio12.rs
index 6d05bdcea6..616af3a9c2 100644
--- a/esp32/src/io_mux/gpio12.rs
+++ b/esp32/src/io_mux/gpio12.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO12_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO12_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO12_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO12_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO12_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO12_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO12_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO12_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO12_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO12_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO12_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio13.rs b/esp32/src/io_mux/gpio13.rs
index 47975949e3..484108c420 100644
--- a/esp32/src/io_mux/gpio13.rs
+++ b/esp32/src/io_mux/gpio13.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO13_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO13_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO13_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO13_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO13_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO13_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO13_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO13_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO13_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO13_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO13_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio14.rs b/esp32/src/io_mux/gpio14.rs
index 7506cf5687..e679eb166a 100644
--- a/esp32/src/io_mux/gpio14.rs
+++ b/esp32/src/io_mux/gpio14.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO14_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO14_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO14_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO14_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO14_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO14_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO14_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO14_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO14_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO14_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO14_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio15.rs b/esp32/src/io_mux/gpio15.rs
index 52af870bf9..c874a3502f 100644
--- a/esp32/src/io_mux/gpio15.rs
+++ b/esp32/src/io_mux/gpio15.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO15_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO15_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO15_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO15_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO15_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO15_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO15_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO15_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO15_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO15_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO15_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio16.rs b/esp32/src/io_mux/gpio16.rs
index a9936252c1..f8f85ff9c0 100644
--- a/esp32/src/io_mux/gpio16.rs
+++ b/esp32/src/io_mux/gpio16.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO16_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO16_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO16_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO16_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO16_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO16_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO16_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO16_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO16_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO16_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO16_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio17.rs b/esp32/src/io_mux/gpio17.rs
index 5b3b281b2f..c957cbc12f 100644
--- a/esp32/src/io_mux/gpio17.rs
+++ b/esp32/src/io_mux/gpio17.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO17_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO17_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO17_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO17_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO17_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO17_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO17_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO17_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO17_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO17_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO17_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio18.rs b/esp32/src/io_mux/gpio18.rs
index fa5ddca90c..78f2eaeaa7 100644
--- a/esp32/src/io_mux/gpio18.rs
+++ b/esp32/src/io_mux/gpio18.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO18_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO18_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO18_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO18_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO18_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO18_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO18_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO18_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO18_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO18_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO18_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio19.rs b/esp32/src/io_mux/gpio19.rs
index c848632c75..abb15c9931 100644
--- a/esp32/src/io_mux/gpio19.rs
+++ b/esp32/src/io_mux/gpio19.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO19_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO19_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO19_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO19_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO19_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO19_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO19_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO19_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO19_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO19_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO19_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio2.rs b/esp32/src/io_mux/gpio2.rs
index 61f6a4ea29..ef58481e88 100644
--- a/esp32/src/io_mux/gpio2.rs
+++ b/esp32/src/io_mux/gpio2.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO2_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO2_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO2_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO2_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO2_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO2_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO2_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO2_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO2_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO2_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO2_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio20.rs b/esp32/src/io_mux/gpio20.rs
index 86daf576ea..ce1c8d2773 100644
--- a/esp32/src/io_mux/gpio20.rs
+++ b/esp32/src/io_mux/gpio20.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO20_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO20_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO20_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO20_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO20_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO20_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO20_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO20_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO20_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO20_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO20_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio21.rs b/esp32/src/io_mux/gpio21.rs
index 1d3967ab4f..51f89a5154 100644
--- a/esp32/src/io_mux/gpio21.rs
+++ b/esp32/src/io_mux/gpio21.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO21_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO21_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO21_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO21_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO21_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO21_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO21_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO21_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO21_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO21_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO21_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio22.rs b/esp32/src/io_mux/gpio22.rs
index 3107d103db..d90c56c4d3 100644
--- a/esp32/src/io_mux/gpio22.rs
+++ b/esp32/src/io_mux/gpio22.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO22_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO22_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO22_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO22_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO22_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO22_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO22_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO22_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO22_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO22_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO22_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio23.rs b/esp32/src/io_mux/gpio23.rs
index db7501134f..0f85410073 100644
--- a/esp32/src/io_mux/gpio23.rs
+++ b/esp32/src/io_mux/gpio23.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO23_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO23_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO23_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO23_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO23_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO23_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO23_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO23_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO23_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO23_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO23_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio24.rs b/esp32/src/io_mux/gpio24.rs
index e2a9c505aa..10326660a7 100644
--- a/esp32/src/io_mux/gpio24.rs
+++ b/esp32/src/io_mux/gpio24.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO24_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO24_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO24_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO24_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO24_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO24_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO24_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO24_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO24_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO24_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO24_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio25.rs b/esp32/src/io_mux/gpio25.rs
index 58634f4dc9..bee22c118a 100644
--- a/esp32/src/io_mux/gpio25.rs
+++ b/esp32/src/io_mux/gpio25.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO25_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO25_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO25_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO25_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO25_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO25_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO25_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO25_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO25_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO25_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO25_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio26.rs b/esp32/src/io_mux/gpio26.rs
index 95ecbaa75d..69977e86fe 100644
--- a/esp32/src/io_mux/gpio26.rs
+++ b/esp32/src/io_mux/gpio26.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO26_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO26_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO26_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO26_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO26_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO26_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO26_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO26_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO26_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO26_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO26_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio27.rs b/esp32/src/io_mux/gpio27.rs
index d6352f0eff..400f433619 100644
--- a/esp32/src/io_mux/gpio27.rs
+++ b/esp32/src/io_mux/gpio27.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO27_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO27_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO27_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO27_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO27_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO27_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO27_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO27_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO27_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO27_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO27_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio3.rs b/esp32/src/io_mux/gpio3.rs
index 3ff2e7572f..0dcb313b0d 100644
--- a/esp32/src/io_mux/gpio3.rs
+++ b/esp32/src/io_mux/gpio3.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO3_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO3_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO3_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO3_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO3_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO3_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO3_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO3_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO3_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO3_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO3_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio32.rs b/esp32/src/io_mux/gpio32.rs
index b6b1f7f7e7..8323e81344 100644
--- a/esp32/src/io_mux/gpio32.rs
+++ b/esp32/src/io_mux/gpio32.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO32_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO32_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO32_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO32_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO32_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO32_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO32_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO32_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO32_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO32_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO32_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio33.rs b/esp32/src/io_mux/gpio33.rs
index 298db8b757..5ff9a3266f 100644
--- a/esp32/src/io_mux/gpio33.rs
+++ b/esp32/src/io_mux/gpio33.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO33_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO33_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO33_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO33_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO33_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO33_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO33_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO33_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO33_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO33_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO33_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio34.rs b/esp32/src/io_mux/gpio34.rs
index 3ecb626802..582211c02a 100644
--- a/esp32/src/io_mux/gpio34.rs
+++ b/esp32/src/io_mux/gpio34.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO34_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO34_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO34_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO34_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO34_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO34_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO34_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO34_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO34_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO34_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO34_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio35.rs b/esp32/src/io_mux/gpio35.rs
index 7cf5256673..cb37584fdf 100644
--- a/esp32/src/io_mux/gpio35.rs
+++ b/esp32/src/io_mux/gpio35.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO35_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO35_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO35_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO35_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO35_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO35_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO35_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO35_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO35_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO35_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO35_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio36.rs b/esp32/src/io_mux/gpio36.rs
index eb757a138d..e4d532df97 100644
--- a/esp32/src/io_mux/gpio36.rs
+++ b/esp32/src/io_mux/gpio36.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO36_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO36_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO36_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO36_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO36_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO36_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO36_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO36_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO36_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO36_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO36_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio37.rs b/esp32/src/io_mux/gpio37.rs
index 5edb65370c..88efb2941c 100644
--- a/esp32/src/io_mux/gpio37.rs
+++ b/esp32/src/io_mux/gpio37.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO37_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO37_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO37_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO37_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO37_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO37_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO37_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO37_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO37_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO37_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO37_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio38.rs b/esp32/src/io_mux/gpio38.rs
index bcb397936e..6aa7d272c4 100644
--- a/esp32/src/io_mux/gpio38.rs
+++ b/esp32/src/io_mux/gpio38.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO38_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO38_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO38_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO38_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO38_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO38_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO38_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO38_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO38_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO38_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO38_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio39.rs b/esp32/src/io_mux/gpio39.rs
index dc2f04dc42..1655d666a5 100644
--- a/esp32/src/io_mux/gpio39.rs
+++ b/esp32/src/io_mux/gpio39.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO39_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO39_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO39_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO39_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO39_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO39_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO39_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO39_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO39_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO39_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO39_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio4.rs b/esp32/src/io_mux/gpio4.rs
index f3d03b3763..52abb233a5 100644
--- a/esp32/src/io_mux/gpio4.rs
+++ b/esp32/src/io_mux/gpio4.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO4_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO4_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO4_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO4_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO4_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO4_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO4_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO4_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO4_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO4_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO4_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio5.rs b/esp32/src/io_mux/gpio5.rs
index f666466478..5686351057 100644
--- a/esp32/src/io_mux/gpio5.rs
+++ b/esp32/src/io_mux/gpio5.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO5_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO5_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO5_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO5_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO5_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO5_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO5_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO5_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO5_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO5_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO5_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio6.rs b/esp32/src/io_mux/gpio6.rs
index 9a9df65e9b..4d5928d964 100644
--- a/esp32/src/io_mux/gpio6.rs
+++ b/esp32/src/io_mux/gpio6.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO6_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO6_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO6_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO6_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO6_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO6_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO6_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO6_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO6_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO6_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO6_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio7.rs b/esp32/src/io_mux/gpio7.rs
index 95030389b1..69d0fffb07 100644
--- a/esp32/src/io_mux/gpio7.rs
+++ b/esp32/src/io_mux/gpio7.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO7_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO7_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO7_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO7_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO7_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO7_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO7_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO7_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO7_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO7_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO7_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio8.rs b/esp32/src/io_mux/gpio8.rs
index a2504e6a57..e3b5c5c3d8 100644
--- a/esp32/src/io_mux/gpio8.rs
+++ b/esp32/src/io_mux/gpio8.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO8_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO8_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO8_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO8_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO8_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO8_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO8_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO8_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO8_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO8_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO8_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/gpio9.rs b/esp32/src/io_mux/gpio9.rs
index 26d8b5ae7f..aca7a99340 100644
--- a/esp32/src/io_mux/gpio9.rs
+++ b/esp32/src/io_mux/gpio9.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO9_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO9_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO9_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO9_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO9_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_drv(&mut self) -> MCU_DRV_W<GPIO9_SPEC> {
         MCU_DRV_W::new(self, 5)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO9_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO9_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO9_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO9_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO9_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
diff --git a/esp32/src/io_mux/pin_ctrl.rs b/esp32/src/io_mux/pin_ctrl.rs
index 9c8edeec1a..3aad67ac15 100644
--- a/esp32/src/io_mux/pin_ctrl.rs
+++ b/esp32/src/io_mux/pin_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0x0; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[11:8\\] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0xF; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[11:8\\] = 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn clk1(&mut self) -> CLK1_W<PIN_CTRL_SPEC> {
         CLK1_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0x0; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[11:8\\] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0xF; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[11:8\\] = 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn clk2(&mut self) -> CLK2_W<PIN_CTRL_SPEC> {
         CLK2_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0x0; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[11:8\\] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0xF; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[11:8\\] = 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn clk3(&mut self) -> CLK3_W<PIN_CTRL_SPEC> {
         CLK3_W::new(self, 8)
     }
diff --git a/esp32/src/ledc/conf.rs b/esp32/src/ledc/conf.rs
index 93f1803691..d7f8bd5925 100644
--- a/esp32/src/ledc/conf.rs
+++ b/esp32/src/ledc/conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<CONF_SPEC> {
         APB_CLK_SEL_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/date.rs b/esp32/src/ledc/date.rs
index 0a14ef90f3..bc85de3ddd 100644
--- a/esp32/src/ledc/date.rs
+++ b/esp32/src/ledc/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register represents the version ."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/hsch/conf0.rs b/esp32/src/ledc/hsch/conf0.rs
index e8d7303f6e..12bbb5f779 100644
--- a/esp32/src/ledc/hsch/conf0.rs
+++ b/esp32/src/ledc/hsch/conf0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CONF0_SPEC> {
         TIMER_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - This is the output enable control bit for high speed channel0"]
     #[inline(always)]
-    #[must_use]
     pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<CONF0_SPEC> {
         SIG_OUT_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to control the output value when high speed channel0 is off."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_lv(&mut self) -> IDLE_LV_W<CONF0_SPEC> {
         IDLE_LV_W::new(self, 3)
     }
diff --git a/esp32/src/ledc/hsch/conf1.rs b/esp32/src/ledc/hsch/conf1.rs
index 5d3b5cec3c..0b01453385 100644
--- a/esp32/src/ledc/hsch/conf1.rs
+++ b/esp32/src/ledc/hsch/conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register controls the increase or decrease step scale for high speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_scale(&mut self) -> DUTY_SCALE_W<CONF1_SPEC> {
         DUTY_SCALE_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_cycle(&mut self) -> DUTY_CYCLE_W<CONF1_SPEC> {
         DUTY_CYCLE_W::new(self, 10)
     }
     #[doc = "Bits 20:29 - This register is used to control the num of increased or decreased times for high speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_num(&mut self) -> DUTY_NUM_W<CONF1_SPEC> {
         DUTY_NUM_W::new(self, 20)
     }
     #[doc = "Bit 30 - This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_inc(&mut self) -> DUTY_INC_W<CONF1_SPEC> {
         DUTY_INC_W::new(self, 30)
     }
     #[doc = "Bit 31 - When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_start(&mut self) -> DUTY_START_W<CONF1_SPEC> {
         DUTY_START_W::new(self, 31)
     }
diff --git a/esp32/src/ledc/hsch/duty.rs b/esp32/src/ledc/hsch/duty.rs
index 60060af17e..941e6464e6 100644
--- a/esp32/src/ledc/hsch/duty.rs
+++ b/esp32/src/ledc/hsch/duty.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:24 - This register represents the current duty of the output signal for high speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<DUTY_SPEC> {
         DUTY_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/hsch/hpoint.rs b/esp32/src/ledc/hsch/hpoint.rs
index d4478416df..e538831be8 100644
--- a/esp32/src/ledc/hsch/hpoint.rs
+++ b/esp32/src/ledc/hsch/hpoint.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when htimerx(x=\\[0 3\\]) selected by high speed channel0 has reached reg_hpoint_hsch0\\[19:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn hpoint(&mut self) -> HPOINT_W<HPOINT_SPEC> {
         HPOINT_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/hstimer/conf.rs b/esp32/src/ledc/hstimer/conf.rs
index eeb57be349..4928914d50 100644
--- a/esp32/src/ledc/hstimer/conf.rs
+++ b/esp32/src/ledc/hstimer/conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register controls the range of the counter in high speed timer0. the counter range is \\[0 2**reg_hstimer0_lim\\] the max bit width for counter is 20."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
         DUTY_RES_W::new(self, 0)
     }
     #[doc = "Bits 5:22 - This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part."]
     #[inline(always)]
-    #[must_use]
     pub fn div_num(&mut self) -> DIV_NUM_W<CONF_SPEC> {
         DIV_NUM_W::new(self, 5)
     }
     #[doc = "Bit 23 - This bit is used to pause the counter in high speed timer0"]
     #[inline(always)]
-    #[must_use]
     pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
         PAUSE_W::new(self, 23)
     }
     #[doc = "Bit 24 - This bit is used to reset high speed timer0 the counter will be 0 after reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
         RST_W::new(self, 24)
     }
     #[doc = "Bit 25 - This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
         TICK_SEL_W::new(self, 25)
     }
diff --git a/esp32/src/ledc/int_clr.rs b/esp32/src/ledc/int_clr.rs
index 3a76abe0ff..5c5c2accc9 100644
--- a/esp32/src/ledc/int_clr.rs
+++ b/esp32/src/ledc/int_clr.rs
@@ -19,7 +19,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer_ovf(&mut self, n: u8) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -27,25 +26,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear high speed channel0 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer0_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
         HSTIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear high speed channel1 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer1_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
         HSTIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear high speed channel2 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer2_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
         HSTIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear high speed channel3 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer3_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
         HSTIMER_OVF_W::new(self, 3)
     }
@@ -53,7 +48,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer_ovf(&mut self, n: u8) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -61,25 +55,21 @@ impl W {
     }
     #[doc = "Bit 4 - Set this bit to clear low speed channel0 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer0_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
         LSTIMER_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear low speed channel1 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer1_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
         LSTIMER_OVF_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear low speed channel2 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer2_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
         LSTIMER_OVF_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear low speed channel3 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer3_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
         LSTIMER_OVF_W::new(self, 7)
     }
@@ -87,7 +77,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch(&mut self, n: u8) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -95,49 +84,41 @@ impl W {
     }
     #[doc = "Bit 8 - Set this bit to clear high speed channel 0 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch0(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear high speed channel 1 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch1(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear high speed channel 2 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch2(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear high speed channel 3 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch3(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear high speed channel 4 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch4(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear high speed channel 5 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch5(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear high speed channel 6 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch6(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear high speed channel 7 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch7(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 15)
     }
@@ -145,7 +126,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch(&mut self, n: u8) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -153,49 +133,41 @@ impl W {
     }
     #[doc = "Bit 16 - Set this bit to clear low speed channel 0 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch0(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear low speed channel 1 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch1(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear low speed channel 2 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch2(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear low speed channel 3 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch3(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to clear low speed channel 4 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch4(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to clear low speed channel 5 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch5(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to clear low speed channel 6 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch6(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to clear low speed channel 7 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch7(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 23)
     }
@@ -209,7 +181,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_0111;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32/src/ledc/int_ena.rs b/esp32/src/ledc/int_ena.rs
index c4bcb8d1a9..e9a2214bac 100644
--- a/esp32/src/ledc/int_ena.rs
+++ b/esp32/src/ledc/int_ena.rs
@@ -236,7 +236,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer_ovf(&mut self, n: u8) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -244,25 +243,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for high speed channel0 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer0_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
         HSTIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for high speed channel1 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer1_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
         HSTIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for high speed channel2 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer2_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
         HSTIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for high speed channel3 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer3_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
         HSTIMER_OVF_W::new(self, 3)
     }
@@ -270,7 +265,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer_ovf(&mut self, n: u8) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -278,25 +272,21 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt enable bit for low speed channel0 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer0_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
         LSTIMER_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for low speed channel1 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer1_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
         LSTIMER_OVF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for low speed channel2 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer2_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
         LSTIMER_OVF_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for low speed channel3 counter overflow interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer3_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
         LSTIMER_OVF_W::new(self, 7)
     }
@@ -304,7 +294,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch(&mut self, n: u8) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -312,49 +301,41 @@ impl W {
     }
     #[doc = "Bit 8 - The interrupt enable bit for high speed channel 0 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch0(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for high speed channel 1 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch1(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for high speed channel 2 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch2(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for high speed channel 3 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch3(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 11)
     }
     #[doc = "Bit 12 - The interrupt enable bit for high speed channel 4 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch4(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for high speed channel 5 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch5(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for high speed channel 6 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch6(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for high speed channel 7 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch7(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 15)
     }
@@ -362,7 +343,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch(&mut self, n: u8) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -370,49 +350,41 @@ impl W {
     }
     #[doc = "Bit 16 - The interrupt enable bit for low speed channel 0 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch0(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for low speed channel 1 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch1(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt enable bit for low speed channel 2 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch2(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt enable bit for low speed channel 3 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch3(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 19)
     }
     #[doc = "Bit 20 - The interrupt enable bit for low speed channel 4 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch4(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 20)
     }
     #[doc = "Bit 21 - The interrupt enable bit for low speed channel 5 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch5(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 21)
     }
     #[doc = "Bit 22 - The interrupt enable bit for low speed channel 6 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch6(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 22)
     }
     #[doc = "Bit 23 - The interrupt enable bit for low speed channel 7 duty change done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch7(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 23)
     }
diff --git a/esp32/src/ledc/int_raw.rs b/esp32/src/ledc/int_raw.rs
index 47f7ce9abf..d13dcddc5a 100644
--- a/esp32/src/ledc/int_raw.rs
+++ b/esp32/src/ledc/int_raw.rs
@@ -236,7 +236,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer_ovf(&mut self, n: u8) -> HSTIMER_OVF_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -244,25 +243,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt raw bit for high speed channel0 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer0_ovf(&mut self) -> HSTIMER_OVF_W<INT_RAW_SPEC> {
         HSTIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt raw bit for high speed channel1 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer1_ovf(&mut self) -> HSTIMER_OVF_W<INT_RAW_SPEC> {
         HSTIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt raw bit for high speed channel2 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer2_ovf(&mut self) -> HSTIMER_OVF_W<INT_RAW_SPEC> {
         HSTIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt raw bit for high speed channel3 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn hstimer3_ovf(&mut self) -> HSTIMER_OVF_W<INT_RAW_SPEC> {
         HSTIMER_OVF_W::new(self, 3)
     }
@@ -270,7 +265,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer_ovf(&mut self, n: u8) -> LSTIMER_OVF_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -278,25 +272,21 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt raw bit for low speed channel0 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer0_ovf(&mut self) -> LSTIMER_OVF_W<INT_RAW_SPEC> {
         LSTIMER_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt raw bit for low speed channel1 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer1_ovf(&mut self) -> LSTIMER_OVF_W<INT_RAW_SPEC> {
         LSTIMER_OVF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt raw bit for low speed channel2 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer2_ovf(&mut self) -> LSTIMER_OVF_W<INT_RAW_SPEC> {
         LSTIMER_OVF_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt raw bit for low speed channel3 counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn lstimer3_ovf(&mut self) -> LSTIMER_OVF_W<INT_RAW_SPEC> {
         LSTIMER_OVF_W::new(self, 7)
     }
@@ -304,7 +294,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch(&mut self, n: u8) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -312,49 +301,41 @@ impl W {
     }
     #[doc = "Bit 8 - The interrupt raw bit for high speed channel 0 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch0(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt raw bit for high speed channel 1 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch1(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt raw bit for high speed channel 2 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch2(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt raw bit for high speed channel 3 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch3(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 11)
     }
     #[doc = "Bit 12 - The interrupt raw bit for high speed channel 4 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch4(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt raw bit for high speed channel 5 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch5(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt raw bit for high speed channel 6 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch6(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt raw bit for high speed channel 7 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_hsch7(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_HSCH_W::new(self, 15)
     }
@@ -362,7 +343,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch(&mut self, n: u8) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -370,49 +350,41 @@ impl W {
     }
     #[doc = "Bit 16 - The interrupt raw bit for low speed channel 0 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch0(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt raw bit for low speed channel 1 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch1(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt raw bit for low speed channel 2 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch2(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt raw bit for low speed channel 3 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch3(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 19)
     }
     #[doc = "Bit 20 - The interrupt raw bit for low speed channel 4 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch4(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 20)
     }
     #[doc = "Bit 21 - The interrupt raw bit for low speed channel 5 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch5(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 21)
     }
     #[doc = "Bit 22 - The interrupt raw bit for low speed channel 6 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch6(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 22)
     }
     #[doc = "Bit 23 - The interrupt raw bit for low speed channel 7 duty change done."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_lsch7(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_LSCH_W::new(self, 23)
     }
diff --git a/esp32/src/ledc/lsch/conf0.rs b/esp32/src/ledc/lsch/conf0.rs
index 263a6a7cc3..87109e8158 100644
--- a/esp32/src/ledc/lsch/conf0.rs
+++ b/esp32/src/ledc/lsch/conf0.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CONF0_SPEC> {
         TIMER_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - This is the output enable control bit for low speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<CONF0_SPEC> {
         SIG_OUT_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to control the output value when low speed channel0 is off."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_lv(&mut self) -> IDLE_LV_W<CONF0_SPEC> {
         IDLE_LV_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF0_SPEC> {
         PARA_UP_W::new(self, 4)
     }
diff --git a/esp32/src/ledc/lsch/conf1.rs b/esp32/src/ledc/lsch/conf1.rs
index cb37cd002f..07f275eff0 100644
--- a/esp32/src/ledc/lsch/conf1.rs
+++ b/esp32/src/ledc/lsch/conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register controls the increase or decrease step scale for low speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_scale(&mut self) -> DUTY_SCALE_W<CONF1_SPEC> {
         DUTY_SCALE_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_cycle(&mut self) -> DUTY_CYCLE_W<CONF1_SPEC> {
         DUTY_CYCLE_W::new(self, 10)
     }
     #[doc = "Bits 20:29 - This register is used to control the num of increased or decreased times for low speed channel6."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_num(&mut self) -> DUTY_NUM_W<CONF1_SPEC> {
         DUTY_NUM_W::new(self, 20)
     }
     #[doc = "Bit 30 - This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_inc(&mut self) -> DUTY_INC_W<CONF1_SPEC> {
         DUTY_INC_W::new(self, 30)
     }
     #[doc = "Bit 31 - When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_start(&mut self) -> DUTY_START_W<CONF1_SPEC> {
         DUTY_START_W::new(self, 31)
     }
diff --git a/esp32/src/ledc/lsch/duty.rs b/esp32/src/ledc/lsch/duty.rs
index 5ea1deba76..65e9843671 100644
--- a/esp32/src/ledc/lsch/duty.rs
+++ b/esp32/src/ledc/lsch/duty.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:24 - This register represents the current duty of the output signal for low speed channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<DUTY_SPEC> {
         DUTY_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/lsch/hpoint.rs b/esp32/src/ledc/lsch/hpoint.rs
index 785a8707e0..ad743be91c 100644
--- a/esp32/src/ledc/lsch/hpoint.rs
+++ b/esp32/src/ledc/lsch/hpoint.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when lstimerx(x=\\[0 3\\]) selected by low speed channel0 has reached reg_hpoint_lsch0\\[19:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn hpoint(&mut self) -> HPOINT_W<HPOINT_SPEC> {
         HPOINT_W::new(self, 0)
     }
diff --git a/esp32/src/ledc/lstimer/conf.rs b/esp32/src/ledc/lstimer/conf.rs
index 1eca56a4ff..2065a5fbf7 100644
--- a/esp32/src/ledc/lstimer/conf.rs
+++ b/esp32/src/ledc/lstimer/conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register controls the range of the counter in low speed timer0. the counter range is \\[0 2**reg_lstimer0_lim\\] the max bit width for counter is 20."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
         DUTY_RES_W::new(self, 0)
     }
     #[doc = "Bits 5:22 - This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part."]
     #[inline(always)]
-    #[must_use]
     pub fn div_num(&mut self) -> DIV_NUM_W<CONF_SPEC> {
         DIV_NUM_W::new(self, 5)
     }
     #[doc = "Bit 23 - This bit is used to pause the counter in low speed timer0."]
     #[inline(always)]
-    #[must_use]
     pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
         PAUSE_W::new(self, 23)
     }
     #[doc = "Bit 24 - This bit is used to reset low speed timer0 the counter will be 0 after reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
         RST_W::new(self, 24)
     }
     #[doc = "Bit 25 - This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
         TICK_SEL_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
         PARA_UP_W::new(self, 26)
     }
diff --git a/esp32/src/lib.rs b/esp32/src/lib.rs
index 06f30ebe55..2d7d719719 100644
--- a/esp32/src/lib.rs
+++ b/esp32/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.33.4 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.33.5 (bfe48e2 2024-11-05))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.5/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
@@ -347,13 +347,8 @@ pub enum Interrupt {
     #[doc = "68 - CACHE_IA"]
     CACHE_IA = 68,
 }
-unsafe impl xtensa_lx::interrupt::InterruptNumber for Interrupt {
-    #[inline(always)]
-    fn number(self) -> u16 {
-        self as u16
-    }
-}
 #[doc = r" TryFromInterruptError"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Debug, Copy, Clone)]
 pub struct TryFromInterruptError(());
 impl Interrupt {
diff --git a/esp32/src/mcpwm0/cap_ch_cfg.rs b/esp32/src/mcpwm0/cap_ch_cfg.rs
index ab57cc5635..478d11711a 100644
--- a/esp32/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32/src/mcpwm0/cap_ch_cfg.rs
@@ -56,31 +56,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:2"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
     }
     #[doc = "Bits 3:10"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CAP_CH_CFG_SPEC> {
         PRESCALE_W::new(self, 3)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn in_invert(&mut self) -> IN_INVERT_W<CAP_CH_CFG_SPEC> {
         IN_INVERT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sw(&mut self) -> SW_W<CAP_CH_CFG_SPEC> {
         SW_W::new(self, 12)
     }
diff --git a/esp32/src/mcpwm0/cap_timer_cfg.rs b/esp32/src/mcpwm0/cap_timer_cfg.rs
index af683152d3..4fe630acd1 100644
--- a/esp32/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32/src/mcpwm0/cap_timer_cfg.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<CAP_TIMER_CFG_SPEC> {
         CAP_TIMER_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNCI_EN_W::new(self, 1)
     }
     #[doc = "Bits 2:4"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNCI_SEL_W::new(self, 2)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNC_SW_W::new(self, 5)
     }
diff --git a/esp32/src/mcpwm0/cap_timer_phase.rs b/esp32/src/mcpwm0/cap_timer_phase.rs
index 33495a89b9..e5ab522dbb 100644
--- a/esp32/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32/src/mcpwm0/cap_timer_phase.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_timer_phase(&mut self) -> CAP_TIMER_PHASE_W<CAP_TIMER_PHASE_SPEC> {
         CAP_TIMER_PHASE_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/ch.rs b/esp32/src/mcpwm0/ch.rs
index 1b926c8848..641ca3a164 100644
--- a/esp32/src/mcpwm0/ch.rs
+++ b/esp32/src/mcpwm0/ch.rs
@@ -43,6 +43,8 @@ impl CH {
         &self.gen_force
     }
     #[doc = "0x14..0x1c - Actions triggered by events on PWMx%s"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `GENA` register.</div>"]
     #[inline(always)]
     pub const fn gen(&self, n: usize) -> &GEN {
         &self.gen[n]
diff --git a/esp32/src/mcpwm0/ch/carrier_cfg.rs b/esp32/src/mcpwm0/ch/carrier_cfg.rs
index d1bb60fc66..24b536ce84 100644
--- a/esp32/src/mcpwm0/ch/carrier_cfg.rs
+++ b/esp32/src/mcpwm0/ch/carrier_cfg.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CARRIER_CFG_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:4"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CARRIER_CFG_SPEC> {
         PRESCALE_W::new(self, 1)
     }
     #[doc = "Bits 5:7"]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<CARRIER_CFG_SPEC> {
         DUTY_W::new(self, 5)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn oshtwth(&mut self) -> OSHTWTH_W<CARRIER_CFG_SPEC> {
         OSHTWTH_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn out_invert(&mut self) -> OUT_INVERT_W<CARRIER_CFG_SPEC> {
         OUT_INVERT_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn in_invert(&mut self) -> IN_INVERT_W<CARRIER_CFG_SPEC> {
         IN_INVERT_W::new(self, 13)
     }
diff --git a/esp32/src/mcpwm0/ch/dt_cfg.rs b/esp32/src/mcpwm0/ch/dt_cfg.rs
index cae9050fc2..1394577bc2 100644
--- a/esp32/src/mcpwm0/ch/dt_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_cfg.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W<DT_CFG_SPEC> {
         FED_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W<DT_CFG_SPEC> {
         RED_UPMETHOD_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn deb_mode(&mut self) -> DEB_MODE_W<DT_CFG_SPEC> {
         DEB_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn a_outswap(&mut self) -> A_OUTSWAP_W<DT_CFG_SPEC> {
         A_OUTSWAP_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn b_outswap(&mut self) -> B_OUTSWAP_W<DT_CFG_SPEC> {
         B_OUTSWAP_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn red_insel(&mut self) -> RED_INSEL_W<DT_CFG_SPEC> {
         RED_INSEL_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_insel(&mut self) -> FED_INSEL_W<DT_CFG_SPEC> {
         FED_INSEL_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W<DT_CFG_SPEC> {
         RED_OUTINVERT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W<DT_CFG_SPEC> {
         FED_OUTINVERT_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W<DT_CFG_SPEC> {
         A_OUTBYPASS_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W<DT_CFG_SPEC> {
         B_OUTBYPASS_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<DT_CFG_SPEC> {
         CLK_SEL_W::new(self, 17)
     }
diff --git a/esp32/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
index b70085963f..e873fe4fc8 100644
--- a/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn fed(&mut self) -> FED_W<DT_FED_CFG_SPEC> {
         FED_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/ch/dt_red_cfg.rs b/esp32/src/mcpwm0/ch/dt_red_cfg.rs
index cc8b69b751..ef34bd423d 100644
--- a/esp32/src/mcpwm0/ch/dt_red_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_red_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn red(&mut self) -> RED_W<DT_RED_CFG_SPEC> {
         RED_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/ch/fh_cfg0.rs b/esp32/src/mcpwm0/ch/fh_cfg0.rs
index 19ff2d8dbc..6cf28d1c56 100644
--- a/esp32/src/mcpwm0/ch/fh_cfg0.rs
+++ b/esp32/src/mcpwm0/ch/fh_cfg0.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_cbc(&mut self) -> SW_CBC_W<FH_CFG0_SPEC> {
         SW_CBC_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_cbc(&mut self) -> F2_CBC_W<FH_CFG0_SPEC> {
         F2_CBC_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_cbc(&mut self) -> F1_CBC_W<FH_CFG0_SPEC> {
         F1_CBC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_cbc(&mut self) -> F0_CBC_W<FH_CFG0_SPEC> {
         F0_CBC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_ost(&mut self) -> SW_OST_W<FH_CFG0_SPEC> {
         SW_OST_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_ost(&mut self) -> F2_OST_W<FH_CFG0_SPEC> {
         F2_OST_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_ost(&mut self) -> F1_OST_W<FH_CFG0_SPEC> {
         F1_OST_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_ost(&mut self) -> F0_OST_W<FH_CFG0_SPEC> {
         F0_OST_W::new(self, 7)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cbc_d(&mut self) -> A_CBC_D_W<FH_CFG0_SPEC> {
         A_CBC_D_W::new(self, 8)
     }
     #[doc = "Bits 10:11"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cbc_u(&mut self) -> A_CBC_U_W<FH_CFG0_SPEC> {
         A_CBC_U_W::new(self, 10)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn a_ost_d(&mut self) -> A_OST_D_W<FH_CFG0_SPEC> {
         A_OST_D_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn a_ost_u(&mut self) -> A_OST_U_W<FH_CFG0_SPEC> {
         A_OST_U_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cbc_d(&mut self) -> B_CBC_D_W<FH_CFG0_SPEC> {
         B_CBC_D_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cbc_u(&mut self) -> B_CBC_U_W<FH_CFG0_SPEC> {
         B_CBC_U_W::new(self, 18)
     }
     #[doc = "Bits 20:21"]
     #[inline(always)]
-    #[must_use]
     pub fn b_ost_d(&mut self) -> B_OST_D_W<FH_CFG0_SPEC> {
         B_OST_D_W::new(self, 20)
     }
     #[doc = "Bits 22:23"]
     #[inline(always)]
-    #[must_use]
     pub fn b_ost_u(&mut self) -> B_OST_U_W<FH_CFG0_SPEC> {
         B_OST_U_W::new(self, 22)
     }
diff --git a/esp32/src/mcpwm0/ch/fh_cfg1.rs b/esp32/src/mcpwm0/ch/fh_cfg1.rs
index cabd7dde5b..1d7b833046 100644
--- a/esp32/src/mcpwm0/ch/fh_cfg1.rs
+++ b/esp32/src/mcpwm0/ch/fh_cfg1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clr_ost(&mut self) -> CLR_OST_W<FH_CFG1_SPEC> {
         CLR_OST_W::new(self, 0)
     }
     #[doc = "Bits 1:2"]
     #[inline(always)]
-    #[must_use]
     pub fn cbcpulse(&mut self) -> CBCPULSE_W<FH_CFG1_SPEC> {
         CBCPULSE_W::new(self, 1)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn force_cbc(&mut self) -> FORCE_CBC_W<FH_CFG1_SPEC> {
         FORCE_CBC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn force_ost(&mut self) -> FORCE_OST_W<FH_CFG1_SPEC> {
         FORCE_OST_W::new(self, 4)
     }
diff --git a/esp32/src/mcpwm0/ch/gen.rs b/esp32/src/mcpwm0/ch/gen.rs
index 91ff4f6d32..db6f0794e1 100644
--- a/esp32/src/mcpwm0/ch/gen.rs
+++ b/esp32/src/mcpwm0/ch/gen.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn utez(&mut self) -> UTEZ_W<GEN_SPEC> {
         UTEZ_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn utep(&mut self) -> UTEP_W<GEN_SPEC> {
         UTEP_W::new(self, 2)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn utea(&mut self) -> UTEA_W<GEN_SPEC> {
         UTEA_W::new(self, 4)
     }
     #[doc = "Bits 6:7"]
     #[inline(always)]
-    #[must_use]
     pub fn uteb(&mut self) -> UTEB_W<GEN_SPEC> {
         UTEB_W::new(self, 6)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn ut0(&mut self) -> UT0_W<GEN_SPEC> {
         UT0_W::new(self, 8)
     }
     #[doc = "Bits 10:11"]
     #[inline(always)]
-    #[must_use]
     pub fn ut1(&mut self) -> UT1_W<GEN_SPEC> {
         UT1_W::new(self, 10)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn dtez(&mut self) -> DTEZ_W<GEN_SPEC> {
         DTEZ_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn dtep(&mut self) -> DTEP_W<GEN_SPEC> {
         DTEP_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn dtea(&mut self) -> DTEA_W<GEN_SPEC> {
         DTEA_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn dteb(&mut self) -> DTEB_W<GEN_SPEC> {
         DTEB_W::new(self, 18)
     }
     #[doc = "Bits 20:21"]
     #[inline(always)]
-    #[must_use]
     pub fn dt0(&mut self) -> DT0_W<GEN_SPEC> {
         DT0_W::new(self, 20)
     }
     #[doc = "Bits 22:23"]
     #[inline(always)]
-    #[must_use]
     pub fn dt1(&mut self) -> DT1_W<GEN_SPEC> {
         DT1_W::new(self, 22)
     }
diff --git a/esp32/src/mcpwm0/ch/gen_cfg0.rs b/esp32/src/mcpwm0/ch/gen_cfg0.rs
index 0a51300fa3..c024ab6bab 100644
--- a/esp32/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32/src/mcpwm0/ch/gen_cfg0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn cfg_upmethod(&mut self) -> CFG_UPMETHOD_W<GEN_CFG0_SPEC> {
         CFG_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:6"]
     #[inline(always)]
-    #[must_use]
     pub fn t0_sel(&mut self) -> T0_SEL_W<GEN_CFG0_SPEC> {
         T0_SEL_W::new(self, 4)
     }
     #[doc = "Bits 7:9"]
     #[inline(always)]
-    #[must_use]
     pub fn t1_sel(&mut self) -> T1_SEL_W<GEN_CFG0_SPEC> {
         T1_SEL_W::new(self, 7)
     }
diff --git a/esp32/src/mcpwm0/ch/gen_force.rs b/esp32/src/mcpwm0/ch/gen_force.rs
index 7b654a0f44..0868f77c9a 100644
--- a/esp32/src/mcpwm0/ch/gen_force.rs
+++ b/esp32/src/mcpwm0/ch/gen_force.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn cntuforce_upmethod(&mut self) -> CNTUFORCE_UPMETHOD_W<GEN_FORCE_SPEC> {
         CNTUFORCE_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 6:7"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cntuforce_mode(&mut self) -> A_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
         A_CNTUFORCE_MODE_W::new(self, 6)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cntuforce_mode(&mut self) -> B_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
         B_CNTUFORCE_MODE_W::new(self, 8)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn a_nciforce(&mut self) -> A_NCIFORCE_W<GEN_FORCE_SPEC> {
         A_NCIFORCE_W::new(self, 10)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn a_nciforce_mode(&mut self) -> A_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
         A_NCIFORCE_MODE_W::new(self, 11)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn b_nciforce(&mut self) -> B_NCIFORCE_W<GEN_FORCE_SPEC> {
         B_NCIFORCE_W::new(self, 13)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn b_nciforce_mode(&mut self) -> B_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
         B_NCIFORCE_MODE_W::new(self, 14)
     }
diff --git a/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
index e81288eb3d..ddb55fcceb 100644
--- a/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
+++ b/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn a_upmethod(&mut self) -> A_UPMETHOD_W<GEN_STMP_CFG_SPEC> {
         A_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn b_upmethod(&mut self) -> B_UPMETHOD_W<GEN_STMP_CFG_SPEC> {
         B_UPMETHOD_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W<GEN_STMP_CFG_SPEC> {
         A_SHDW_FULL_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W<GEN_STMP_CFG_SPEC> {
         B_SHDW_FULL_W::new(self, 9)
     }
diff --git a/esp32/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
index be471012a1..24ae887593 100644
--- a/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
+++ b/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn a(&mut self) -> A_W<GEN_TSTMP_A_SPEC> {
         A_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
index 7a0fb69cfd..2c9afcc332 100644
--- a/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
+++ b/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn b(&mut self) -> B_W<GEN_TSTMP_B_SPEC> {
         B_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/clk.rs b/esp32/src/mcpwm0/clk.rs
index 77aaac869a..de30ebc374 100644
--- a/esp32/src/mcpwm0/clk.rs
+++ b/esp32/src/mcpwm0/clk.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CLK_SPEC> {
         EN_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/clk_cfg.rs b/esp32/src/mcpwm0/clk_cfg.rs
index 003ec82f13..4e5cccfcfc 100644
--- a/esp32/src/mcpwm0/clk_cfg.rs
+++ b/esp32/src/mcpwm0/clk_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W<CLK_CFG_SPEC> {
         CLK_PRESCALE_W::new(self, 0)
     }
diff --git a/esp32/src/mcpwm0/fault_detect.rs b/esp32/src/mcpwm0/fault_detect.rs
index ab720fa099..a67db721a2 100644
--- a/esp32/src/mcpwm0/fault_detect.rs
+++ b/esp32/src/mcpwm0/fault_detect.rs
@@ -98,37 +98,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_en(&mut self) -> F0_EN_W<FAULT_DETECT_SPEC> {
         F0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_en(&mut self) -> F1_EN_W<FAULT_DETECT_SPEC> {
         F1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_en(&mut self) -> F2_EN_W<FAULT_DETECT_SPEC> {
         F2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_pole(&mut self) -> F0_POLE_W<FAULT_DETECT_SPEC> {
         F0_POLE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_pole(&mut self) -> F1_POLE_W<FAULT_DETECT_SPEC> {
         F1_POLE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_pole(&mut self) -> F2_POLE_W<FAULT_DETECT_SPEC> {
         F2_POLE_W::new(self, 5)
     }
diff --git a/esp32/src/mcpwm0/int_clr.rs b/esp32/src/mcpwm0/int_clr.rs
index 2bbfc91660..dc2be7ce96 100644
--- a/esp32/src/mcpwm0/int_clr.rs
+++ b/esp32/src/mcpwm0/int_clr.rs
@@ -69,181 +69,151 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_CLR_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_CLR_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_CLR_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_CLR_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_CLR_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_CLR_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_CLR_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_CLR_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_CLR_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_CLR_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_CLR_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_CLR_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_CLR_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_CLR_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_CLR_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_tea(&mut self) -> OP0_TEA_W<INT_CLR_SPEC> {
         OP0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_tea(&mut self) -> OP1_TEA_W<INT_CLR_SPEC> {
         OP1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_tea(&mut self) -> OP2_TEA_W<INT_CLR_SPEC> {
         OP2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_teb(&mut self) -> OP0_TEB_W<INT_CLR_SPEC> {
         OP0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_teb(&mut self) -> OP1_TEB_W<INT_CLR_SPEC> {
         OP1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_teb(&mut self) -> OP2_TEB_W<INT_CLR_SPEC> {
         OP2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_cbc(&mut self) -> FH0_CBC_W<INT_CLR_SPEC> {
         FH0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_cbc(&mut self) -> FH1_CBC_W<INT_CLR_SPEC> {
         FH1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_cbc(&mut self) -> FH2_CBC_W<INT_CLR_SPEC> {
         FH2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_ost(&mut self) -> FH0_OST_W<INT_CLR_SPEC> {
         FH0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_ost(&mut self) -> FH1_OST_W<INT_CLR_SPEC> {
         FH1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_ost(&mut self) -> FH2_OST_W<INT_CLR_SPEC> {
         FH2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_CLR_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_CLR_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_CLR_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32/src/mcpwm0/int_ena.rs b/esp32/src/mcpwm0/int_ena.rs
index 7863b17d2b..cc0044c297 100644
--- a/esp32/src/mcpwm0/int_ena.rs
+++ b/esp32/src/mcpwm0/int_ena.rs
@@ -314,181 +314,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_ENA_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_ENA_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_ENA_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_ENA_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_ENA_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_ENA_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_ENA_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_ENA_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_ENA_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_ENA_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_ENA_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_ENA_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_ENA_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_ENA_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_ENA_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_tea(&mut self) -> OP0_TEA_W<INT_ENA_SPEC> {
         OP0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_tea(&mut self) -> OP1_TEA_W<INT_ENA_SPEC> {
         OP1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_tea(&mut self) -> OP2_TEA_W<INT_ENA_SPEC> {
         OP2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_teb(&mut self) -> OP0_TEB_W<INT_ENA_SPEC> {
         OP0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_teb(&mut self) -> OP1_TEB_W<INT_ENA_SPEC> {
         OP1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_teb(&mut self) -> OP2_TEB_W<INT_ENA_SPEC> {
         OP2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_cbc(&mut self) -> FH0_CBC_W<INT_ENA_SPEC> {
         FH0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_cbc(&mut self) -> FH1_CBC_W<INT_ENA_SPEC> {
         FH1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_cbc(&mut self) -> FH2_CBC_W<INT_ENA_SPEC> {
         FH2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_ost(&mut self) -> FH0_OST_W<INT_ENA_SPEC> {
         FH0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_ost(&mut self) -> FH1_OST_W<INT_ENA_SPEC> {
         FH1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_ost(&mut self) -> FH2_OST_W<INT_ENA_SPEC> {
         FH2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_ENA_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_ENA_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_ENA_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32/src/mcpwm0/int_raw.rs b/esp32/src/mcpwm0/int_raw.rs
index e4ce43b0f0..ec1de184c0 100644
--- a/esp32/src/mcpwm0/int_raw.rs
+++ b/esp32/src/mcpwm0/int_raw.rs
@@ -314,181 +314,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_RAW_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_RAW_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_RAW_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_RAW_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_RAW_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_RAW_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_RAW_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_RAW_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_RAW_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_RAW_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_RAW_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_RAW_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_RAW_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_RAW_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_RAW_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_tea(&mut self) -> OP0_TEA_W<INT_RAW_SPEC> {
         OP0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_tea(&mut self) -> OP1_TEA_W<INT_RAW_SPEC> {
         OP1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_tea(&mut self) -> OP2_TEA_W<INT_RAW_SPEC> {
         OP2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_teb(&mut self) -> OP0_TEB_W<INT_RAW_SPEC> {
         OP0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_teb(&mut self) -> OP1_TEB_W<INT_RAW_SPEC> {
         OP1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_teb(&mut self) -> OP2_TEB_W<INT_RAW_SPEC> {
         OP2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_cbc(&mut self) -> FH0_CBC_W<INT_RAW_SPEC> {
         FH0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_cbc(&mut self) -> FH1_CBC_W<INT_RAW_SPEC> {
         FH1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_cbc(&mut self) -> FH2_CBC_W<INT_RAW_SPEC> {
         FH2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn fh0_ost(&mut self) -> FH0_OST_W<INT_RAW_SPEC> {
         FH0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn fh1_ost(&mut self) -> FH1_OST_W<INT_RAW_SPEC> {
         FH1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn fh2_ost(&mut self) -> FH2_OST_W<INT_RAW_SPEC> {
         FH2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_RAW_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_RAW_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_RAW_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32/src/mcpwm0/operator_timersel.rs b/esp32/src/mcpwm0/operator_timersel.rs
index e2d2381075..6f3772eb76 100644
--- a/esp32/src/mcpwm0/operator_timersel.rs
+++ b/esp32/src/mcpwm0/operator_timersel.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR0_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR1_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR2_TIMERSEL_W::new(self, 4)
     }
diff --git a/esp32/src/mcpwm0/timer/cfg0.rs b/esp32/src/mcpwm0/timer/cfg0.rs
index c4b747b3b2..d2f43b7af6 100644
--- a/esp32/src/mcpwm0/timer/cfg0.rs
+++ b/esp32/src/mcpwm0/timer/cfg0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CFG0_SPEC> {
         PRESCALE_W::new(self, 0)
     }
     #[doc = "Bits 8:23"]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<CFG0_SPEC> {
         PERIOD_W::new(self, 8)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn period_upmethod(&mut self) -> PERIOD_UPMETHOD_W<CFG0_SPEC> {
         PERIOD_UPMETHOD_W::new(self, 24)
     }
diff --git a/esp32/src/mcpwm0/timer/cfg1.rs b/esp32/src/mcpwm0/timer/cfg1.rs
index 849cf4f497..b72cb46489 100644
--- a/esp32/src/mcpwm0/timer/cfg1.rs
+++ b/esp32/src/mcpwm0/timer/cfg1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CFG1_SPEC> {
         START_W::new(self, 0)
     }
     #[doc = "Bits 3:4"]
     #[inline(always)]
-    #[must_use]
     pub fn mod_(&mut self) -> MOD_W<CFG1_SPEC> {
         MOD_W::new(self, 3)
     }
diff --git a/esp32/src/mcpwm0/timer/sync.rs b/esp32/src/mcpwm0/timer/sync.rs
index ff194dcc66..c6c5663d35 100644
--- a/esp32/src/mcpwm0/timer/sync.rs
+++ b/esp32/src/mcpwm0/timer/sync.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn synci_en(&mut self) -> SYNCI_EN_W<SYNC_SPEC> {
         SYNCI_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sw(&mut self) -> SW_W<SYNC_SPEC> {
         SW_W::new(self, 1)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn synco_sel(&mut self) -> SYNCO_SEL_W<SYNC_SPEC> {
         SYNCO_SEL_W::new(self, 2)
     }
     #[doc = "Bits 4:19"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<SYNC_SPEC> {
         PHASE_W::new(self, 4)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn phase_direction(&mut self) -> PHASE_DIRECTION_W<SYNC_SPEC> {
         PHASE_DIRECTION_W::new(self, 20)
     }
diff --git a/esp32/src/mcpwm0/timer_synci_cfg.rs b/esp32/src/mcpwm0/timer_synci_cfg.rs
index 58375e6914..cab7693fc4 100644
--- a/esp32/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32/src/mcpwm0/timer_synci_cfg.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER0_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER1_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER2_SYNCISEL_W::new(self, 6)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
     }
diff --git a/esp32/src/mcpwm0/update_cfg.rs b/esp32/src/mcpwm0/update_cfg.rs
index 3b44a46987..2edba3f2f8 100644
--- a/esp32/src/mcpwm0/update_cfg.rs
+++ b/esp32/src/mcpwm0/update_cfg.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn global_up_en(&mut self) -> GLOBAL_UP_EN_W<UPDATE_CFG_SPEC> {
         GLOBAL_UP_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn global_force_up(&mut self) -> GLOBAL_FORCE_UP_W<UPDATE_CFG_SPEC> {
         GLOBAL_FORCE_UP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_up_en(&mut self) -> OP0_UP_EN_W<UPDATE_CFG_SPEC> {
         OP0_UP_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_force_up(&mut self) -> OP0_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP0_FORCE_UP_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_up_en(&mut self) -> OP1_UP_EN_W<UPDATE_CFG_SPEC> {
         OP1_UP_EN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_force_up(&mut self) -> OP1_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP1_FORCE_UP_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_up_en(&mut self) -> OP2_UP_EN_W<UPDATE_CFG_SPEC> {
         OP2_UP_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_force_up(&mut self) -> OP2_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP2_FORCE_UP_W::new(self, 7)
     }
diff --git a/esp32/src/mcpwm0/version.rs b/esp32/src/mcpwm0/version.rs
index 3e24142419..52c0d300f5 100644
--- a/esp32/src/mcpwm0/version.rs
+++ b/esp32/src/mcpwm0/version.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<VERSION_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/nrx/nrxpd_ctrl.rs b/esp32/src/nrx/nrxpd_ctrl.rs
index 43b5959bea..2254fe2e6d 100644
--- a/esp32/src/nrx/nrxpd_ctrl.rs
+++ b/esp32/src/nrx/nrxpd_ctrl.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn demap_force_pd(&mut self) -> DEMAP_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         DEMAP_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn demap_force_pu(&mut self) -> DEMAP_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         DEMAP_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn vit_force_pd(&mut self) -> VIT_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         VIT_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn vit_force_pu(&mut self) -> VIT_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         VIT_FORCE_PU_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rot_force_pd(&mut self) -> RX_ROT_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         RX_ROT_FORCE_PD_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rot_force_pu(&mut self) -> RX_ROT_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         RX_ROT_FORCE_PU_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn chan_est_force_pd(&mut self) -> CHAN_EST_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         CHAN_EST_FORCE_PD_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn chan_est_force_pu(&mut self) -> CHAN_EST_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         CHAN_EST_FORCE_PU_W::new(self, 7)
     }
diff --git a/esp32/src/pcnt/ctrl.rs b/esp32/src/pcnt/ctrl.rs
index 16e9d06c41..5cbe1be7d5 100644
--- a/esp32/src/pcnt/ctrl.rs
+++ b/esp32/src/pcnt/ctrl.rs
@@ -160,7 +160,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_RST_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u(&mut self, n: u8) -> CNT_RST_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -168,49 +167,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u0(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 0)
     }
     #[doc = "Bit 2 - Set this bit to clear unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u1(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 2)
     }
     #[doc = "Bit 4 - Set this bit to clear unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u2(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 4)
     }
     #[doc = "Bit 6 - Set this bit to clear unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u3(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 6)
     }
     #[doc = "Bit 8 - Set this bit to clear unit4's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u4(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 8)
     }
     #[doc = "Bit 10 - Set this bit to clear unit5's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u5(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 10)
     }
     #[doc = "Bit 12 - Set this bit to clear unit6's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u6(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 12)
     }
     #[doc = "Bit 14 - Set this bit to clear unit7's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u7(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 14)
     }
@@ -218,7 +209,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_PAUSE_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u(&mut self, n: u8) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -226,55 +216,46 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to pause unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 1)
     }
     #[doc = "Bit 3 - Set this bit to pause unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to pause unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 5)
     }
     #[doc = "Bit 7 - Set this bit to pause unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 7)
     }
     #[doc = "Bit 9 - Set this bit to pause unit4's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u4(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 9)
     }
     #[doc = "Bit 11 - Set this bit to pause unit5's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u5(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 11)
     }
     #[doc = "Bit 13 - Set this bit to pause unit6's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u6(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 13)
     }
     #[doc = "Bit 15 - Set this bit to pause unit7's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u7(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
         CLK_EN_W::new(self, 16)
     }
diff --git a/esp32/src/pcnt/date.rs b/esp32/src/pcnt/date.rs
index 9b8f9a14fa..291efa991d 100644
--- a/esp32/src/pcnt/date.rs
+++ b/esp32/src/pcnt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/pcnt/int_clr.rs b/esp32/src/pcnt/int_clr.rs
index 4138dd3cb4..2965ed9217 100644
--- a/esp32/src/pcnt/int_clr.rs
+++ b/esp32/src/pcnt/int_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -21,49 +20,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear channel0 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear channel1 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear channel2 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear channel3 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear channel4 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u4(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear channel5 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u5(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear channel6 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u6(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear channel7 event interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u7(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 7)
     }
diff --git a/esp32/src/pcnt/int_ena.rs b/esp32/src/pcnt/int_ena.rs
index 94ea93319c..80c9ef85bb 100644
--- a/esp32/src/pcnt/int_ena.rs
+++ b/esp32/src/pcnt/int_ena.rs
@@ -83,7 +83,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -91,49 +90,41 @@ impl W {
     }
     #[doc = "Bit 0 - This is the interrupt enable bit for channel0 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the interrupt enable bit for channel1 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the interrupt enable bit for channel2 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the interrupt enable bit for channel3 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the interrupt enable bit for channel4 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u4(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the interrupt enable bit for channel5 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u5(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the interrupt enable bit for channel6 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u6(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the interrupt enable bit for channel7 event."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u7(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 7)
     }
diff --git a/esp32/src/pcnt/u_status.rs b/esp32/src/pcnt/u_status.rs
index 359137992e..3542a0cfc1 100644
--- a/esp32/src/pcnt/u_status.rs
+++ b/esp32/src/pcnt/u_status.rs
@@ -82,37 +82,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn zero_mode(&mut self) -> ZERO_MODE_W<U_STATUS_SPEC> {
         ZERO_MODE_W::new(self, 0)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1(&mut self) -> THRES1_W<U_STATUS_SPEC> {
         THRES1_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0(&mut self) -> THRES0_W<U_STATUS_SPEC> {
         THRES0_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn l_lim(&mut self) -> L_LIM_W<U_STATUS_SPEC> {
         L_LIM_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn h_lim(&mut self) -> H_LIM_W<U_STATUS_SPEC> {
         H_LIM_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn zero(&mut self) -> ZERO_W<U_STATUS_SPEC> {
         ZERO_W::new(self, 6)
     }
diff --git a/esp32/src/pcnt/unit/conf0.rs b/esp32/src/pcnt/unit/conf0.rs
index 1498ff1a54..0e0b1d3222 100644
--- a/esp32/src/pcnt/unit/conf0.rs
+++ b/esp32/src/pcnt/unit/conf0.rs
@@ -346,43 +346,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to filter pluse whose width is smaller than this value for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_thres(&mut self) -> FILTER_THRES_W<CONF0_SPEC> {
         FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 10 - This is the enable bit for filtering input signals for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<CONF0_SPEC> {
         FILTER_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for comparing unit0's count with 0 value."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_zero_en(&mut self) -> THR_ZERO_EN_W<CONF0_SPEC> {
         THR_ZERO_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for comparing unit0's count with thr_h_lim value."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_h_lim_en(&mut self) -> THR_H_LIM_EN_W<CONF0_SPEC> {
         THR_H_LIM_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for comparing unit0's count with thr_l_lim value."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_l_lim_en(&mut self) -> THR_L_LIM_EN_W<CONF0_SPEC> {
         THR_L_LIM_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for comparing unit0's count with thres0 value."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres0_en(&mut self) -> THR_THRES0_EN_W<CONF0_SPEC> {
         THR_THRES0_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for comparing unit0's count with thres1 value ."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres1_en(&mut self) -> THR_THRES1_EN_W<CONF0_SPEC> {
         THR_THRES1_EN_W::new(self, 15)
     }
@@ -390,7 +383,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_neg_mode(&mut self, n: u8) -> CH_NEG_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -398,13 +390,11 @@ impl W {
     }
     #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 16)
     }
     #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 24)
     }
@@ -412,7 +402,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_pos_mode(&mut self, n: u8) -> CH_POS_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -420,13 +409,11 @@ impl W {
     }
     #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 18)
     }
     #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 26)
     }
@@ -434,7 +421,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_hctrl_mode(&mut self, n: u8) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -442,13 +428,11 @@ impl W {
     }
     #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 20)
     }
     #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 28)
     }
@@ -456,7 +440,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_lctrl_mode(&mut self, n: u8) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -464,13 +447,11 @@ impl W {
     }
     #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 22)
     }
     #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 30)
     }
diff --git a/esp32/src/pcnt/unit/conf1.rs b/esp32/src/pcnt/unit/conf1.rs
index 9ef384eede..626be7f64d 100644
--- a/esp32/src/pcnt/unit/conf1.rs
+++ b/esp32/src/pcnt/unit/conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure thres0 value for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres0(&mut self) -> CNT_THRES0_W<CONF1_SPEC> {
         CNT_THRES0_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure thres1 value for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres1(&mut self) -> CNT_THRES1_W<CONF1_SPEC> {
         CNT_THRES1_W::new(self, 16)
     }
diff --git a/esp32/src/pcnt/unit/conf2.rs b/esp32/src/pcnt/unit/conf2.rs
index 41a97b2fa4..de787b3cbe 100644
--- a/esp32/src/pcnt/unit/conf2.rs
+++ b/esp32/src/pcnt/unit/conf2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure thr_h_lim value for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_h_lim(&mut self) -> CNT_H_LIM_W<CONF2_SPEC> {
         CNT_H_LIM_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to confiugre thr_l_lim value for unit0."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_l_lim(&mut self) -> CNT_L_LIM_W<CONF2_SPEC> {
         CNT_L_LIM_W::new(self, 16)
     }
diff --git a/esp32/src/rmt.rs b/esp32/src/rmt.rs
index 43be64084f..309be40471 100644
--- a/esp32/src/rmt.rs
+++ b/esp32/src/rmt.rs
@@ -76,14 +76,25 @@ impl RegisterBlock {
     pub const fn chconf0(&self, n: usize) -> &CHCONF0 {
         #[allow(clippy::no_effect)]
         [(); 8][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(32).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(32)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x20..0x40 - "]
     #[inline(always)]
     pub fn chconf0_iter(&self) -> impl Iterator<Item = &CHCONF0> {
-        (0..8)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(32).add(8 * n).cast() })
+        (0..8).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(32)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x20 - CH0CONF0"]
     #[inline(always)]
@@ -130,14 +141,25 @@ impl RegisterBlock {
     pub const fn chconf1(&self, n: usize) -> &CHCONF1 {
         #[allow(clippy::no_effect)]
         [(); 8][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(36).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(36)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x24..0x44 - "]
     #[inline(always)]
     pub fn chconf1_iter(&self) -> impl Iterator<Item = &CHCONF1> {
-        (0..8)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(36).add(8 * n).cast() })
+        (0..8).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(36)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x24 - CH0CONF1"]
     #[inline(always)]
diff --git a/esp32/src/rmt/apb_conf.rs b/esp32/src/rmt/apb_conf.rs
index 75df5108cb..b1c9ca78f2 100644
--- a/esp32/src/rmt/apb_conf.rs
+++ b/esp32/src/rmt/apb_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to disable apb fifo access"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<APB_CONF_SPEC> {
         APB_FIFO_MASK_W::new(self, 0)
     }
     #[doc = "Bit 1 - when datas need to be send is more than channel's mem can store then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<APB_CONF_SPEC> {
         MEM_TX_WRAP_EN_W::new(self, 1)
     }
diff --git a/esp32/src/rmt/ch_tx_lim.rs b/esp32/src/rmt/ch_tx_lim.rs
index de2e337de7..939ae2edef 100644
--- a/esp32/src/rmt/ch_tx_lim.rs
+++ b/esp32/src/rmt/ch_tx_lim.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lim(&mut self) -> TX_LIM_W<CH_TX_LIM_SPEC> {
         TX_LIM_W::new(self, 0)
     }
diff --git a/esp32/src/rmt/chcarrier_duty.rs b/esp32/src/rmt/chcarrier_duty.rs
index a77cf3ca47..3578a8618c 100644
--- a/esp32/src/rmt/chcarrier_duty.rs
+++ b/esp32/src/rmt/chcarrier_duty.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave's low level value for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_low(&mut self) -> CARRIER_LOW_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_LOW_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure carrier wave's high level value for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_high(&mut self) -> CARRIER_HIGH_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_HIGH_W::new(self, 16)
     }
diff --git a/esp32/src/rmt/chconf0.rs b/esp32/src/rmt/chconf0.rs
index 27a9d13be8..727b995b1f 100644
--- a/esp32/src/rmt/chconf0.rs
+++ b/esp32/src/rmt/chconf0.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the frequency divider's factor in channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn div_cnt(&mut self) -> DIV_CNT_W<CHCONF0_SPEC> {
         DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bits 8:23 - In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_thres(&mut self) -> IDLE_THRES_W<CHCONF0_SPEC> {
         IDLE_THRES_W::new(self, 8)
     }
     #[doc = "Bits 24:27 - This register is used to configure the the amount of memory blocks allocated to channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_size(&mut self) -> MEM_SIZE_W<CHCONF0_SPEC> {
         MEM_SIZE_W::new(self, 24)
     }
     #[doc = "Bit 28 - This is the carrier modulation enable control bit for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_en(&mut self) -> CARRIER_EN_W<CHCONF0_SPEC> {
         CARRIER_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit is used to configure the way carrier wave is modulated for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<CHCONF0_SPEC> {
         CARRIER_OUT_LV_W::new(self, 29)
     }
     #[doc = "Bit 30 - This bit is used to reduce power consumed by mem. 1:mem is in low power state."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_pd(&mut self) -> MEM_PD_W<CHCONF0_SPEC> {
         MEM_PD_W::new(self, 30)
     }
     #[doc = "Bit 31 - This bit is used to control clock.when software config RMT internal registers it controls the register clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CHCONF0_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32/src/rmt/chconf1.rs b/esp32/src/rmt/chconf1.rs
index 7fb2ce9d5f..98d568047f 100644
--- a/esp32/src/rmt/chconf1.rs
+++ b/esp32/src/rmt/chconf1.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<CHCONF1_SPEC> {
         TX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enbale receving data for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_en(&mut self) -> RX_EN_W<CHCONF1_SPEC> {
         RX_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset write ram address for channel0 by receiver access."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_wr_rst(&mut self) -> MEM_WR_RST_W<CHCONF1_SPEC> {
         MEM_WR_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset read ram address for channel0 by transmitter access."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_rd_rst(&mut self) -> MEM_RD_RST_W<CHCONF1_SPEC> {
         MEM_RD_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to reset W/R ram address for channel0 by apb fifo access"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<CHCONF1_SPEC> {
         APB_MEM_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_owner(&mut self) -> MEM_OWNER_W<CHCONF1_SPEC> {
         MEM_OWNER_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to continue sending from the first data to the last data in channel0 again and again."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_conti_mode(&mut self) -> TX_CONTI_MODE_W<CHCONF1_SPEC> {
         TX_CONTI_MODE_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the receive filter enable bit for channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_en(&mut self) -> RX_FILTER_EN_W<CHCONF1_SPEC> {
         RX_FILTER_EN_W::new(self, 7)
     }
     #[doc = "Bits 8:15 - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_thres(&mut self) -> RX_FILTER_THRES_W<CHCONF1_SPEC> {
         RX_FILTER_THRES_W::new(self, 8)
     }
     #[doc = "Bit 16 - This bit is used to reset divider in channel0."]
     #[inline(always)]
-    #[must_use]
     pub fn ref_cnt_rst(&mut self) -> REF_CNT_RST_W<CHCONF1_SPEC> {
         REF_CNT_RST_W::new(self, 16)
     }
     #[doc = "Bit 17 - This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref"]
     #[inline(always)]
-    #[must_use]
     pub fn ref_always_on(&mut self) -> REF_ALWAYS_ON_W<CHCONF1_SPEC> {
         REF_ALWAYS_ON_W::new(self, 17)
     }
     #[doc = "Bit 18 - This bit configures the output signal's level for channel0 in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_lv(&mut self) -> IDLE_OUT_LV_W<CHCONF1_SPEC> {
         IDLE_OUT_LV_W::new(self, 18)
     }
     #[doc = "Bit 19 - This is the output enable control bit for channel0 in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_en(&mut self) -> IDLE_OUT_EN_W<CHCONF1_SPEC> {
         IDLE_OUT_EN_W::new(self, 19)
     }
diff --git a/esp32/src/rmt/date.rs b/esp32/src/rmt/date.rs
index 2d0a9e956c..9d239b066e 100644
--- a/esp32/src/rmt/date.rs
+++ b/esp32/src/rmt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/rmt/int_clr.rs b/esp32/src/rmt/int_clr.rs
index 7fb0bc90f7..e8f1b14bfb 100644
--- a/esp32/src/rmt/int_clr.rs
+++ b/esp32/src/rmt/int_clr.rs
@@ -19,7 +19,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -27,49 +26,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the rmt_ch0_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to clear the rmt_ch1_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
     #[doc = "Bit 6 - Set this bit to clear the rmt_ch2_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 6)
     }
     #[doc = "Bit 9 - Set this bit to clear the rmt_ch3_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 9)
     }
     #[doc = "Bit 12 - Set this bit to clear the rmt_ch4_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 12)
     }
     #[doc = "Bit 15 - Set this bit to clear the rmt_ch5_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 15)
     }
     #[doc = "Bit 18 - Set this bit to clear the rmt_ch6_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 18)
     }
     #[doc = "Bit 21 - Set this bit to clear the rmt_ch7_rx_end_int_raw.."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 21)
     }
@@ -77,7 +68,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -85,49 +75,41 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to clear the rmt_ch0_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 1)
     }
     #[doc = "Bit 4 - Set this bit to clear the rmt_ch1_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to clear the rmt_ch2_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 7)
     }
     #[doc = "Bit 10 - Set this bit to clear the rmt_ch3_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 10)
     }
     #[doc = "Bit 13 - Set this bit to clear the rmt_ch4_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 13)
     }
     #[doc = "Bit 16 - Set this bit to clear the rmt_ch5_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 16)
     }
     #[doc = "Bit 19 - Set this bit to clear the rmt_ch6_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 19)
     }
     #[doc = "Bit 22 - Set this bit to clear the rmt_ch7_tx_end_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 22)
     }
@@ -135,7 +117,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -143,49 +124,41 @@ impl W {
     }
     #[doc = "Bit 2 - Set this bit to clear the rmt_ch0_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 2)
     }
     #[doc = "Bit 5 - Set this bit to clear the rmt_ch1_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 5)
     }
     #[doc = "Bit 8 - Set this bit to clear the rmt_ch2_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 8)
     }
     #[doc = "Bit 11 - Set this bit to clear the rmt_ch3_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 11)
     }
     #[doc = "Bit 14 - Set this bit to clear the rmt_ch4_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 14)
     }
     #[doc = "Bit 17 - Set this bit to clear the rmt_ch5_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 17)
     }
     #[doc = "Bit 20 - Set this bit to clear the rmt_ch6_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 20)
     }
     #[doc = "Bit 23 - Set this bit to clear the rmt_ch7_err_int_raw."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 23)
     }
@@ -193,7 +166,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -201,49 +173,41 @@ impl W {
     }
     #[doc = "Bit 24 - Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 31)
     }
diff --git a/esp32/src/rmt/int_ena.rs b/esp32/src/rmt/int_ena.rs
index 6195b8ed4c..07904877a8 100644
--- a/esp32/src/rmt/int_ena.rs
+++ b/esp32/src/rmt/int_ena.rs
@@ -284,7 +284,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -292,49 +291,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to enable rmt_ch0_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to enable rmt_ch1_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
     #[doc = "Bit 6 - Set this bit to enable rmt_ch2_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 6)
     }
     #[doc = "Bit 9 - Set this bit to enable rmt_ch3_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 9)
     }
     #[doc = "Bit 12 - Set this bit to enable rmt_ch4_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 12)
     }
     #[doc = "Bit 15 - Set this bit to enable rmt_ch5_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 15)
     }
     #[doc = "Bit 18 - Set this bit to enable rmt_ch6_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 18)
     }
     #[doc = "Bit 21 - Set this bit to enable rmt_ch7_tx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 21)
     }
@@ -342,7 +333,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -350,49 +340,41 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to enable rmt_ch0_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 1)
     }
     #[doc = "Bit 4 - Set this bit to enable rmt_ch1_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to enable rmt_ch2_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 7)
     }
     #[doc = "Bit 10 - Set this bit to enable rmt_ch3_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 10)
     }
     #[doc = "Bit 13 - Set this bit to enable rmt_ch4_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 13)
     }
     #[doc = "Bit 16 - Set this bit to enable rmt_ch5_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 16)
     }
     #[doc = "Bit 19 - Set this bit to enable rmt_ch6_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 19)
     }
     #[doc = "Bit 22 - Set this bit to enable rmt_ch7_rx_end_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 22)
     }
@@ -400,7 +382,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -408,49 +389,41 @@ impl W {
     }
     #[doc = "Bit 2 - Set this bit to enable rmt_ch0_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 2)
     }
     #[doc = "Bit 5 - Set this bit to enable rmt_ch1_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 5)
     }
     #[doc = "Bit 8 - Set this bit to enable rmt_ch2_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 8)
     }
     #[doc = "Bit 11 - Set this bit to enable rmt_ch3_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 11)
     }
     #[doc = "Bit 14 - Set this bit to enable rmt_ch4_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 14)
     }
     #[doc = "Bit 17 - Set this bit to enable rmt_ch5_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 17)
     }
     #[doc = "Bit 20 - Set this bit to enable rmt_ch6_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 20)
     }
     #[doc = "Bit 23 - Set this bit to enable rmt_ch7_err_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 23)
     }
@@ -458,7 +431,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -466,49 +438,41 @@ impl W {
     }
     #[doc = "Bit 24 - Set this bit to enable rmt_ch0_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable rmt_ch1_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable rmt_ch2_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable rmt_ch3_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to enable rmt_ch4_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable rmt_ch5_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable rmt_ch6_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable rmt_ch7_tx_thr_event_int_st."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 31)
     }
diff --git a/esp32/src/rsa/interrupt.rs b/esp32/src/rsa/interrupt.rs
index 0afff10a22..6effb34647 100644
--- a/esp32/src/rsa/interrupt.rs
+++ b/esp32/src/rsa/interrupt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - RSA interrupt status register. Will read 1 once an operation has completed."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt(&mut self) -> INTERRUPT_W<INTERRUPT_SPEC> {
         INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32/src/rsa/m_prime.rs b/esp32/src/rsa/m_prime.rs
index e7efc49a80..2d9c243ee5 100644
--- a/esp32/src/rsa/m_prime.rs
+++ b/esp32/src/rsa/m_prime.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register contains M’."]
     #[inline(always)]
-    #[must_use]
     pub fn m_prime(&mut self) -> M_PRIME_W<M_PRIME_SPEC> {
         M_PRIME_W::new(self, 0)
     }
diff --git a/esp32/src/rsa/modexp_mode.rs b/esp32/src/rsa/modexp_mode.rs
index 844c718457..9155a05422 100644
--- a/esp32/src/rsa/modexp_mode.rs
+++ b/esp32/src/rsa/modexp_mode.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - This register contains the mode of modular exponentiation."]
     #[inline(always)]
-    #[must_use]
     pub fn modexp_mode(&mut self) -> MODEXP_MODE_W<MODEXP_MODE_SPEC> {
         MODEXP_MODE_W::new(self, 0)
     }
diff --git a/esp32/src/rsa/modexp_start.rs b/esp32/src/rsa/modexp_start.rs
index 0354439324..d28ab61ff4 100644
--- a/esp32/src/rsa/modexp_start.rs
+++ b/esp32/src/rsa/modexp_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MODEXP_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start modular exponentiation."]
     #[inline(always)]
-    #[must_use]
     pub fn modexp_start(&mut self) -> MODEXP_START_W<MODEXP_START_SPEC> {
         MODEXP_START_W::new(self, 0)
     }
diff --git a/esp32/src/rsa/mult_mode.rs b/esp32/src/rsa/mult_mode.rs
index 637b277170..fa71efb0c9 100644
--- a/esp32/src/rsa/mult_mode.rs
+++ b/esp32/src/rsa/mult_mode.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - This register contains the mode of modular multiplication and multiplication."]
     #[inline(always)]
-    #[must_use]
     pub fn mult_mode(&mut self) -> MULT_MODE_W<MULT_MODE_SPEC> {
         MULT_MODE_W::new(self, 0)
     }
diff --git a/esp32/src/rsa/mult_start.rs b/esp32/src/rsa/mult_start.rs
index 9258fd98f8..83d6bb2e03 100644
--- a/esp32/src/rsa/mult_start.rs
+++ b/esp32/src/rsa/mult_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MULT_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start modular multiplication or multiplication."]
     #[inline(always)]
-    #[must_use]
     pub fn mult_start(&mut self) -> MULT_START_W<MULT_START_SPEC> {
         MULT_START_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/ana_conf.rs b/esp32/src/rtc_cntl/ana_conf.rs
index dfe4abdba2..874d07ade2 100644
--- a/esp32/src/rtc_cntl/ana_conf.rs
+++ b/esp32/src/rtc_cntl/ana_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 23 - PLLA force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn plla_force_pd(&mut self) -> PLLA_FORCE_PD_W<ANA_CONF_SPEC> {
         PLLA_FORCE_PD_W::new(self, 23)
     }
     #[doc = "Bit 24 - PLLA force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn plla_force_pu(&mut self) -> PLLA_FORCE_PU_W<ANA_CONF_SPEC> {
         PLLA_FORCE_PU_W::new(self, 24)
     }
     #[doc = "Bit 25 - start BBPLL calibration during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<ANA_CONF_SPEC> {
         BBPLL_CAL_SLP_START_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: PVTMON power up otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<ANA_CONF_SPEC> {
         PVTMON_PU_W::new(self, 26)
     }
     #[doc = "Bit 27 - 1: TXRF_I2C power up otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<ANA_CONF_SPEC> {
         TXRF_I2C_PU_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: RFRX_PBUS power up otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<ANA_CONF_SPEC> {
         RFRX_PBUS_PU_W::new(self, 28)
     }
     #[doc = "Bit 30 - 1: CKGEN_I2C power up otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<ANA_CONF_SPEC> {
         CKGEN_I2C_PU_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: PLL_I2C power up otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<ANA_CONF_SPEC> {
         PLL_I2C_PU_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/bias_conf.rs b/esp32/src/rtc_cntl/bias_conf.rs
index 5836eb2961..afc674fd43 100644
--- a/esp32/src/rtc_cntl/bias_conf.rs
+++ b/esp32/src/rtc_cntl/bias_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 24:25 - DBG_ATTEN"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten(&mut self) -> DBG_ATTEN_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_W::new(self, 24)
     }
     #[doc = "Bit 26 - ENB_SCK_XTAL"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_sck_xtal(&mut self) -> ENB_SCK_XTAL_W<BIAS_CONF_SPEC> {
         ENB_SCK_XTAL_W::new(self, 26)
     }
     #[doc = "Bit 27 - INC_HEARTBEAT_REFRESH"]
     #[inline(always)]
-    #[must_use]
     pub fn inc_heartbeat_refresh(&mut self) -> INC_HEARTBEAT_REFRESH_W<BIAS_CONF_SPEC> {
         INC_HEARTBEAT_REFRESH_W::new(self, 27)
     }
     #[doc = "Bit 28 - DEC_HEARTBEAT_PERIOD"]
     #[inline(always)]
-    #[must_use]
     pub fn dec_heartbeat_period(&mut self) -> DEC_HEARTBEAT_PERIOD_W<BIAS_CONF_SPEC> {
         DEC_HEARTBEAT_PERIOD_W::new(self, 28)
     }
     #[doc = "Bit 29 - INC_HEARTBEAT_PERIOD"]
     #[inline(always)]
-    #[must_use]
     pub fn inc_heartbeat_period(&mut self) -> INC_HEARTBEAT_PERIOD_W<BIAS_CONF_SPEC> {
         INC_HEARTBEAT_PERIOD_W::new(self, 29)
     }
     #[doc = "Bit 30 - DEC_HEARTBEAT_WIDTH"]
     #[inline(always)]
-    #[must_use]
     pub fn dec_heartbeat_width(&mut self) -> DEC_HEARTBEAT_WIDTH_W<BIAS_CONF_SPEC> {
         DEC_HEARTBEAT_WIDTH_W::new(self, 30)
     }
     #[doc = "Bit 31 - RST_BIAS_I2C"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_bias_i2c(&mut self) -> RST_BIAS_I2C_W<BIAS_CONF_SPEC> {
         RST_BIAS_I2C_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/brown_out.rs b/esp32/src/rtc_cntl/brown_out.rs
index ed2c8335fa..2472adeafa 100644
--- a/esp32/src/rtc_cntl/brown_out.rs
+++ b/esp32/src/rtc_cntl/brown_out.rs
@@ -132,67 +132,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_pid_conf(&mut self) -> RTC_MEM_PID_CONF_W<BROWN_OUT_SPEC> {
         RTC_MEM_PID_CONF_W::new(self, 0)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_start(&mut self) -> RTC_MEM_CRC_START_W<BROWN_OUT_SPEC> {
         RTC_MEM_CRC_START_W::new(self, 8)
     }
     #[doc = "Bits 9:19"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_addr(&mut self) -> RTC_MEM_CRC_ADDR_W<BROWN_OUT_SPEC> {
         RTC_MEM_CRC_ADDR_W::new(self, 9)
     }
     #[doc = "Bit 14 - enable close flash when brown out happens"]
     #[inline(always)]
-    #[must_use]
     pub fn close_flash_ena(&mut self) -> CLOSE_FLASH_ENA_W<BROWN_OUT_SPEC> {
         CLOSE_FLASH_ENA_W::new(self, 14)
     }
     #[doc = "Bit 15 - enable power down RF when brown out happens"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_rf_ena(&mut self) -> PD_RF_ENA_W<BROWN_OUT_SPEC> {
         PD_RF_ENA_W::new(self, 15)
     }
     #[doc = "Bits 16:25 - brown out reset wait cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_wait(&mut self) -> RST_WAIT_W<BROWN_OUT_SPEC> {
         RST_WAIT_W::new(self, 16)
     }
     #[doc = "Bits 20:30"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_len(&mut self) -> RTC_MEM_CRC_LEN_W<BROWN_OUT_SPEC> {
         RTC_MEM_CRC_LEN_W::new(self, 20)
     }
     #[doc = "Bit 26 - enable brown out reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_ena(&mut self) -> RST_ENA_W<BROWN_OUT_SPEC> {
         RST_ENA_W::new(self, 26)
     }
     #[doc = "Bits 27:29 - brown out threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn dbrown_out_thres(&mut self) -> DBROWN_OUT_THRES_W<BROWN_OUT_SPEC> {
         DBROWN_OUT_THRES_W::new(self, 27)
     }
     #[doc = "Bit 30 - enable brown out"]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<BROWN_OUT_SPEC> {
         ENA_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_finish(&mut self) -> RTC_MEM_CRC_FINISH_W<BROWN_OUT_SPEC> {
         RTC_MEM_CRC_FINISH_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/clk_conf.rs b/esp32/src/rtc_cntl/clk_conf.rs
index 4a0d5db2ad..1055ac860c 100644
--- a/esp32/src/rtc_cntl/clk_conf.rs
+++ b/esp32/src/rtc_cntl/clk_conf.rs
@@ -510,97 +510,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
         CK8M_DIV_W::new(self, 4)
     }
     #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
         ENB_CK8M_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
         ENB_CK8M_DIV_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
         DIG_XTAL32K_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_D256_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_dfreq_force(&mut self) -> CK8M_DFREQ_FORCE_W<CLK_CONF_SPEC> {
         CK8M_DFREQ_FORCE_W::new(self, 11)
     }
     #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
         CK8M_DIV_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - XTAL force no gating during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         XTAL_FORCE_NOGATING_W::new(self, 15)
     }
     #[doc = "Bit 16 - CK8M force no gating during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         CK8M_FORCE_NOGATING_W::new(self, 16)
     }
     #[doc = "Bits 17:24 - CK8M_DFREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
         CK8M_DFREQ_W::new(self, 17)
     }
     #[doc = "Bit 25 - CK8M force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PD_W::new(self, 25)
     }
     #[doc = "Bit 26 - CK8M force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PU_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL"]
     #[inline(always)]
-    #[must_use]
     pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<CLK_CONF_SPEC> {
         SOC_CLK_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4 1: CK8M"]
     #[inline(always)]
-    #[must_use]
     pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         FAST_CLK_RTC_SEL_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT"]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         ANA_CLK_RTC_SEL_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_cntl/cpu_period_conf.rs b/esp32/src/rtc_cntl/cpu_period_conf.rs
index ef6a67157e..e2b08cc8e3 100644
--- a/esp32/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32/src/rtc_cntl/cpu_period_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
-    #[must_use]
     pub fn cpusel_conf(&mut self) -> CPUSEL_CONF_W<CPU_PERIOD_CONF_SPEC> {
         CPUSEL_CONF_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - CPU period sel"]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PERIOD_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_cntl/date.rs b/esp32/src/rtc_cntl/date.rs
index deda0a530e..49ac56b6be 100644
--- a/esp32/src/rtc_cntl/date.rs
+++ b/esp32/src/rtc_cntl/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn cntl_date(&mut self) -> CNTL_DATE_W<DATE_SPEC> {
         CNTL_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/dig_iso.rs b/esp32/src/rtc_cntl/dig_iso.rs
index 76d553fbb3..632d979800 100644
--- a/esp32/src/rtc_cntl/dig_iso.rs
+++ b/esp32/src/rtc_cntl/dig_iso.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn force_off(&mut self) -> FORCE_OFF_W<DIG_ISO_SPEC> {
         FORCE_OFF_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn force_on(&mut self) -> FORCE_ON_W<DIG_ISO_SPEC> {
         FORCE_ON_W::new(self, 8)
     }
     #[doc = "Bit 10 - wtite only register to clear digital pad auto-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn clr_dg_pad_autohold(&mut self) -> CLR_DG_PAD_AUTOHOLD_W<DIG_ISO_SPEC> {
         CLR_DG_PAD_AUTOHOLD_W::new(self, 10)
     }
     #[doc = "Bit 11 - digital pad enable auto-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_autohold_en(&mut self) -> DG_PAD_AUTOHOLD_EN_W<DIG_ISO_SPEC> {
         DG_PAD_AUTOHOLD_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - digital pad force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_noiso(&mut self) -> DG_PAD_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_NOISO_W::new(self, 12)
     }
     #[doc = "Bit 13 - digital pad force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_iso(&mut self) -> DG_PAD_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_ISO_W::new(self, 13)
     }
     #[doc = "Bit 14 - digital pad force un-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_unhold(&mut self) -> DG_PAD_FORCE_UNHOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_UNHOLD_W::new(self, 14)
     }
     #[doc = "Bit 15 - digital pad force hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_hold(&mut self) -> DG_PAD_FORCE_HOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_HOLD_W::new(self, 15)
     }
     #[doc = "Bit 16 - ROM force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_iso(&mut self) -> ROM0_FORCE_ISO_W<DIG_ISO_SPEC> {
         ROM0_FORCE_ISO_W::new(self, 16)
     }
     #[doc = "Bit 17 - ROM force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_noiso(&mut self) -> ROM0_FORCE_NOISO_W<DIG_ISO_SPEC> {
         ROM0_FORCE_NOISO_W::new(self, 17)
     }
     #[doc = "Bit 18 - internal SRAM 0 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_iso(&mut self) -> INTER_RAM0_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM0_FORCE_ISO_W::new(self, 18)
     }
     #[doc = "Bit 19 - internal SRAM 0 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_noiso(&mut self) -> INTER_RAM0_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM0_FORCE_NOISO_W::new(self, 19)
     }
     #[doc = "Bit 20 - internal SRAM 1 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_iso(&mut self) -> INTER_RAM1_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM1_FORCE_ISO_W::new(self, 20)
     }
     #[doc = "Bit 21 - internal SRAM 1 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_noiso(&mut self) -> INTER_RAM1_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM1_FORCE_NOISO_W::new(self, 21)
     }
     #[doc = "Bit 22 - internal SRAM 2 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_iso(&mut self) -> INTER_RAM2_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM2_FORCE_ISO_W::new(self, 22)
     }
     #[doc = "Bit 23 - internal SRAM 2 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_noiso(&mut self) -> INTER_RAM2_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM2_FORCE_NOISO_W::new(self, 23)
     }
     #[doc = "Bit 24 - internal SRAM 3 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_iso(&mut self) -> INTER_RAM3_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM3_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25 - internal SRAM 3 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_noiso(&mut self) -> INTER_RAM3_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM3_FORCE_NOISO_W::new(self, 25)
     }
     #[doc = "Bit 26 - internal SRAM 4 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_iso(&mut self) -> INTER_RAM4_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM4_FORCE_ISO_W::new(self, 26)
     }
     #[doc = "Bit 27 - internal SRAM 4 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_noiso(&mut self) -> INTER_RAM4_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM4_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28 - wifi force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_iso(&mut self) -> WIFI_FORCE_ISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_ISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - wifi force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_noiso(&mut self) -> WIFI_FORCE_NOISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_NOISO_W::new(self, 29)
     }
     #[doc = "Bit 30 - digital core force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_iso(&mut self) -> DG_WRAP_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_ISO_W::new(self, 30)
     }
     #[doc = "Bit 31 - digital core force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_noiso(&mut self) -> DG_WRAP_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_NOISO_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/dig_pwc.rs b/esp32/src/rtc_cntl/dig_pwc.rs
index ac9dea5919..169fa91d6e 100644
--- a/esp32/src/rtc_cntl/dig_pwc.rs
+++ b/esp32/src/rtc_cntl/dig_pwc.rs
@@ -274,157 +274,131 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - memories in digital core force PD in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - memories in digital core force no PD in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 5 - ROM force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_pd(&mut self) -> ROM0_FORCE_PD_W<DIG_PWC_SPEC> {
         ROM0_FORCE_PD_W::new(self, 5)
     }
     #[doc = "Bit 6 - ROM force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_pu(&mut self) -> ROM0_FORCE_PU_W<DIG_PWC_SPEC> {
         ROM0_FORCE_PU_W::new(self, 6)
     }
     #[doc = "Bit 7 - internal SRAM 0 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_pd(&mut self) -> INTER_RAM0_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM0_FORCE_PD_W::new(self, 7)
     }
     #[doc = "Bit 8 - internal SRAM 0 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_pu(&mut self) -> INTER_RAM0_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM0_FORCE_PU_W::new(self, 8)
     }
     #[doc = "Bit 9 - internal SRAM 1 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_pd(&mut self) -> INTER_RAM1_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM1_FORCE_PD_W::new(self, 9)
     }
     #[doc = "Bit 10 - internal SRAM 1 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_pu(&mut self) -> INTER_RAM1_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM1_FORCE_PU_W::new(self, 10)
     }
     #[doc = "Bit 11 - internal SRAM 2 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_pd(&mut self) -> INTER_RAM2_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM2_FORCE_PD_W::new(self, 11)
     }
     #[doc = "Bit 12 - internal SRAM 2 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_pu(&mut self) -> INTER_RAM2_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM2_FORCE_PU_W::new(self, 12)
     }
     #[doc = "Bit 13 - internal SRAM 3 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_pd(&mut self) -> INTER_RAM3_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM3_FORCE_PD_W::new(self, 13)
     }
     #[doc = "Bit 14 - internal SRAM 3 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_pu(&mut self) -> INTER_RAM3_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM3_FORCE_PU_W::new(self, 14)
     }
     #[doc = "Bit 15 - internal SRAM 4 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_pd(&mut self) -> INTER_RAM4_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM4_FORCE_PD_W::new(self, 15)
     }
     #[doc = "Bit 16 - internal SRAM 4 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_pu(&mut self) -> INTER_RAM4_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM4_FORCE_PU_W::new(self, 16)
     }
     #[doc = "Bit 17 - wifi force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pd(&mut self) -> WIFI_FORCE_PD_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PD_W::new(self, 17)
     }
     #[doc = "Bit 18 - wifi force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pu(&mut self) -> WIFI_FORCE_PU_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PU_W::new(self, 18)
     }
     #[doc = "Bit 19 - digital core force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PD_W::new(self, 19)
     }
     #[doc = "Bit 20 - digital core force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PU_W::new(self, 20)
     }
     #[doc = "Bit 24 - enable power down ROM in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_pd_en(&mut self) -> ROM0_PD_EN_W<DIG_PWC_SPEC> {
         ROM0_PD_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - enable power down internal SRAM 0 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_pd_en(&mut self) -> INTER_RAM0_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM0_PD_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - enable power down internal SRAM 1 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_pd_en(&mut self) -> INTER_RAM1_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM1_PD_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - enable power down internal SRAM 2 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_pd_en(&mut self) -> INTER_RAM2_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM2_PD_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - enable power down internal SRAM 3 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_pd_en(&mut self) -> INTER_RAM3_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM3_PD_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - enable power down internal SRAM 4 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_pd_en(&mut self) -> INTER_RAM4_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM4_PD_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable power down wifi in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_pd_en(&mut self) -> WIFI_PD_EN_W<DIG_PWC_SPEC> {
         WIFI_PD_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable power down digital core in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<DIG_PWC_SPEC> {
         DG_WRAP_PD_EN_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/ext_wakeup1.rs b/esp32/src/rtc_cntl/ext_wakeup1.rs
index 5c1a91f4d7..6d3f426050 100644
--- a/esp32/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32/src/rtc_cntl/ext_wakeup1.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Bitmap to select RTC pads for ext wakeup1"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP1_SPEC> {
         SEL_W::new(self, 0)
     }
     #[doc = "Bit 18 - clear ext wakeup1 status"]
     #[inline(always)]
-    #[must_use]
     pub fn status_clr(&mut self) -> STATUS_CLR_W<EXT_WAKEUP1_SPEC> {
         STATUS_CLR_W::new(self, 18)
     }
diff --git a/esp32/src/rtc_cntl/ext_wakeup_conf.rs b/esp32/src/rtc_cntl/ext_wakeup_conf.rs
index 31a7e6fd77..76afa7e2de 100644
--- a/esp32/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32/src/rtc_cntl/ext_wakeup_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - 0: external wakeup at low level 1: external wakeup at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup0_lv(&mut self) -> EXT_WAKEUP0_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP0_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - 0: external wakeup at low level 1: external wakeup at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup1_lv(&mut self) -> EXT_WAKEUP1_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP1_LV_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/ext_xtl_conf.rs b/esp32/src/rtc_cntl/ext_xtl_conf.rs
index b1f9ac8cec..8b8d1a8e9d 100644
--- a/esp32/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32/src/rtc_cntl/ext_xtl_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - 0: power down XTAL at high level 1: power down XTAL at low level"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_lv(&mut self) -> XTL_EXT_CTR_LV_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable control XTAL by external pads"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_en(&mut self) -> XTL_EXT_CTR_EN_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_EN_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/hold_force.rs b/esp32/src/rtc_cntl/hold_force.rs
index 9d1df062ae..f772eb64a2 100644
--- a/esp32/src/rtc_cntl/hold_force.rs
+++ b/esp32/src/rtc_cntl/hold_force.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_hold_force(&mut self) -> ADC1_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         ADC1_HOLD_FORCE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_hold_force(&mut self) -> ADC2_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         ADC2_HOLD_FORCE_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_hold_force(&mut self) -> PDAC1_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         PDAC1_HOLD_FORCE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_hold_force(&mut self) -> PDAC2_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         PDAC2_HOLD_FORCE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_hold_force(&mut self) -> SENSE1_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         SENSE1_HOLD_FORCE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_hold_force(&mut self) -> SENSE2_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         SENSE2_HOLD_FORCE_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_hold_force(&mut self) -> SENSE3_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         SENSE3_HOLD_FORCE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_hold_force(&mut self) -> SENSE4_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         SENSE4_HOLD_FORCE_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad0_hold_force(&mut self) -> TOUCH_PAD0_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD0_HOLD_FORCE_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad1_hold_force(&mut self) -> TOUCH_PAD1_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD1_HOLD_FORCE_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad2_hold_force(&mut self) -> TOUCH_PAD2_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD2_HOLD_FORCE_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad3_hold_force(&mut self) -> TOUCH_PAD3_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD3_HOLD_FORCE_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad4_hold_force(&mut self) -> TOUCH_PAD4_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD4_HOLD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad5_hold_force(&mut self) -> TOUCH_PAD5_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD5_HOLD_FORCE_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad6_hold_force(&mut self) -> TOUCH_PAD6_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD6_HOLD_FORCE_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad7_hold_force(&mut self) -> TOUCH_PAD7_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         TOUCH_PAD7_HOLD_FORCE_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_hold_force(&mut self) -> X32P_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         X32P_HOLD_FORCE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_hold_force(&mut self) -> X32N_HOLD_FORCE_W<HOLD_FORCE_SPEC> {
         X32N_HOLD_FORCE_W::new(self, 17)
     }
diff --git a/esp32/src/rtc_cntl/int_clr.rs b/esp32/src/rtc_cntl/int_clr.rs
index 29821aba5c..fa01f780cf 100644
--- a/esp32/src/rtc_cntl/int_clr.rs
+++ b/esp32/src/rtc_cntl/int_clr.rs
@@ -27,55 +27,46 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Clear sleep reject interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Clear SDIO idle interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Clear RTC time valid interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn time_valid(&mut self) -> TIME_VALID_W<INT_CLR_SPEC> {
         TIME_VALID_W::new(self, 4)
     }
     #[doc = "Bit 5 - Clear ULP-coprocessor interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn sar(&mut self) -> SAR_W<INT_CLR_SPEC> {
         SAR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Clear touch interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch(&mut self) -> TOUCH_W<INT_CLR_SPEC> {
         TOUCH_W::new(self, 6)
     }
     #[doc = "Bit 7 - Clear brown out interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
         BROWN_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8 - Clear RTC main timer interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
         MAIN_TIMER_W::new(self, 8)
     }
diff --git a/esp32/src/rtc_cntl/int_ena.rs b/esp32/src/rtc_cntl/int_ena.rs
index 400b76bfa0..0f36ce29a8 100644
--- a/esp32/src/rtc_cntl/int_ena.rs
+++ b/esp32/src/rtc_cntl/int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - enable sleep reject interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - enable SDIO idle interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable RTC WDT interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - enable RTC time valid interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn time_valid(&mut self) -> TIME_VALID_W<INT_ENA_SPEC> {
         TIME_VALID_W::new(self, 4)
     }
     #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable touch interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch(&mut self) -> TOUCH_W<INT_ENA_SPEC> {
         TOUCH_W::new(self, 6)
     }
     #[doc = "Bit 7 - enable brown out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
         BROWN_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable RTC main timer interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_SPEC> {
         MAIN_TIMER_W::new(self, 8)
     }
diff --git a/esp32/src/rtc_cntl/options0.rs b/esp32/src/rtc_cntl/options0.rs
index f1692f2729..5ffb60f5c0 100644
--- a/esp32/src/rtc_cntl/options0.rs
+++ b/esp32/src/rtc_cntl/options0.rs
@@ -290,181 +290,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c0(&mut self) -> SW_STALL_APPCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_APPCPU_C0_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - {reg_sw_stall_procpu_c1\\[5:0\\] reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c0(&mut self) -> SW_STALL_PROCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_PROCPU_C0_W::new(self, 2)
     }
     #[doc = "Bit 4 - APP CPU SW reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_appcpu_rst(&mut self) -> SW_APPCPU_RST_W<OPTIONS0_SPEC> {
         SW_APPCPU_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - PRO CPU SW reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_procpu_rst(&mut self) -> SW_PROCPU_RST_W<OPTIONS0_SPEC> {
         SW_PROCPU_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - BB_I2C force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pd(&mut self) -> BB_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PD_W::new(self, 6)
     }
     #[doc = "Bit 7 - BB_I2C force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pu(&mut self) -> BB_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PU_W::new(self, 7)
     }
     #[doc = "Bit 8 - BB_PLL _I2C force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pd(&mut self) -> BBPLL_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PD_W::new(self, 8)
     }
     #[doc = "Bit 9 - BB_PLL_I2C force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pu(&mut self) -> BBPLL_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PU_W::new(self, 9)
     }
     #[doc = "Bit 10 - BB_PLL force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pd(&mut self) -> BBPLL_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PD_W::new(self, 10)
     }
     #[doc = "Bit 11 - BB_PLL force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pu(&mut self) -> BBPLL_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PU_W::new(self, 11)
     }
     #[doc = "Bit 12 - crystall force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pd(&mut self) -> XTL_FORCE_PD_W<OPTIONS0_SPEC> {
         XTL_FORCE_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - crystall force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pu(&mut self) -> XTL_FORCE_PU_W<OPTIONS0_SPEC> {
         XTL_FORCE_PU_W::new(self, 13)
     }
     #[doc = "Bit 14 - BIAS_SLEEP follow CK8M"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_sleep_folw_8m(&mut self) -> BIAS_SLEEP_FOLW_8M_W<OPTIONS0_SPEC> {
         BIAS_SLEEP_FOLW_8M_W::new(self, 14)
     }
     #[doc = "Bit 15 - BIAS_SLEEP force sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_force_sleep(&mut self) -> BIAS_FORCE_SLEEP_W<OPTIONS0_SPEC> {
         BIAS_FORCE_SLEEP_W::new(self, 15)
     }
     #[doc = "Bit 16 - BIAS_SLEEP force no sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_force_nosleep(&mut self) -> BIAS_FORCE_NOSLEEP_W<OPTIONS0_SPEC> {
         BIAS_FORCE_NOSLEEP_W::new(self, 16)
     }
     #[doc = "Bit 17 - BIAS_I2C follow CK8M"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_i2c_folw_8m(&mut self) -> BIAS_I2C_FOLW_8M_W<OPTIONS0_SPEC> {
         BIAS_I2C_FOLW_8M_W::new(self, 17)
     }
     #[doc = "Bit 18 - BIAS_I2C force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_i2c_force_pd(&mut self) -> BIAS_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BIAS_I2C_FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - BIAS_I2C force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_i2c_force_pu(&mut self) -> BIAS_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BIAS_I2C_FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - BIAS_CORE follow CK8M"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_core_folw_8m(&mut self) -> BIAS_CORE_FOLW_8M_W<OPTIONS0_SPEC> {
         BIAS_CORE_FOLW_8M_W::new(self, 20)
     }
     #[doc = "Bit 21 - BIAS_CORE force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_core_force_pd(&mut self) -> BIAS_CORE_FORCE_PD_W<OPTIONS0_SPEC> {
         BIAS_CORE_FORCE_PD_W::new(self, 21)
     }
     #[doc = "Bit 22 - BIAS_CORE force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_core_force_pu(&mut self) -> BIAS_CORE_FORCE_PU_W<OPTIONS0_SPEC> {
         BIAS_CORE_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_iso(&mut self) -> XTL_FORCE_ISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_ISO_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_iso(&mut self) -> PLL_FORCE_ISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_iso(&mut self) -> ANALOG_FORCE_ISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_ISO_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_noiso(&mut self) -> XTL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_NOISO_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_noiso(&mut self) -> PLL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_noiso(&mut self) -> ANALOG_FORCE_NOISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_NOISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - digital wrap force reset in deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_rst(&mut self) -> DG_WRAP_FORCE_RST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - digital core force no reset in deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_norst(&mut self) -> DG_WRAP_FORCE_NORST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_NORST_W::new(self, 30)
     }
     #[doc = "Bit 31 - SW system reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_sys_rst(&mut self) -> SW_SYS_RST_W<OPTIONS0_SPEC> {
         SW_SYS_RST_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/pwc.rs b/esp32/src/rtc_cntl/pwc.rs
index be20e6d6e5..b6c0451c51 100644
--- a/esp32/src/rtc_cntl/pwc.rs
+++ b/esp32/src/rtc_cntl/pwc.rs
@@ -224,127 +224,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Fast RTC memory force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_noiso(&mut self) -> FASTMEM_FORCE_NOISO_W<PWC_SPEC> {
         FASTMEM_FORCE_NOISO_W::new(self, 0)
     }
     #[doc = "Bit 1 - Fast RTC memory force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_iso(&mut self) -> FASTMEM_FORCE_ISO_W<PWC_SPEC> {
         FASTMEM_FORCE_ISO_W::new(self, 1)
     }
     #[doc = "Bit 2 - RTC memory force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_noiso(&mut self) -> SLOWMEM_FORCE_NOISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_NOISO_W::new(self, 2)
     }
     #[doc = "Bit 3 - RTC memory force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_iso(&mut self) -> SLOWMEM_FORCE_ISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_ISO_W::new(self, 3)
     }
     #[doc = "Bit 4 - rtc_peri force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn force_iso(&mut self) -> FORCE_ISO_W<PWC_SPEC> {
         FORCE_ISO_W::new(self, 4)
     }
     #[doc = "Bit 5 - rtc_peri force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn force_noiso(&mut self) -> FORCE_NOISO_W<PWC_SPEC> {
         FORCE_NOISO_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_folw_cpu(&mut self) -> FASTMEM_FOLW_CPU_W<PWC_SPEC> {
         FASTMEM_FOLW_CPU_W::new(self, 6)
     }
     #[doc = "Bit 7 - Fast RTC memory force PD"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpd(&mut self) -> FASTMEM_FORCE_LPD_W<PWC_SPEC> {
         FASTMEM_FORCE_LPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Fast RTC memory force no PD"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpu(&mut self) -> FASTMEM_FORCE_LPU_W<PWC_SPEC> {
         FASTMEM_FORCE_LPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_folw_cpu(&mut self) -> SLOWMEM_FOLW_CPU_W<PWC_SPEC> {
         SLOWMEM_FOLW_CPU_W::new(self, 9)
     }
     #[doc = "Bit 10 - RTC memory force PD"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpd(&mut self) -> SLOWMEM_FORCE_LPD_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPD_W::new(self, 10)
     }
     #[doc = "Bit 11 - RTC memory force no PD"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpu(&mut self) -> SLOWMEM_FORCE_LPU_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPU_W::new(self, 11)
     }
     #[doc = "Bit 12 - Fast RTC memory force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_pd(&mut self) -> FASTMEM_FORCE_PD_W<PWC_SPEC> {
         FASTMEM_FORCE_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - Fast RTC memory force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_pu(&mut self) -> FASTMEM_FORCE_PU_W<PWC_SPEC> {
         FASTMEM_FORCE_PU_W::new(self, 13)
     }
     #[doc = "Bit 14 - enable power down fast RTC memory in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_pd_en(&mut self) -> FASTMEM_PD_EN_W<PWC_SPEC> {
         FASTMEM_PD_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - RTC memory force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_pd(&mut self) -> SLOWMEM_FORCE_PD_W<PWC_SPEC> {
         SLOWMEM_FORCE_PD_W::new(self, 15)
     }
     #[doc = "Bit 16 - RTC memory force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_pu(&mut self) -> SLOWMEM_FORCE_PU_W<PWC_SPEC> {
         SLOWMEM_FORCE_PU_W::new(self, 16)
     }
     #[doc = "Bit 17 - enable power down RTC memory in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_pd_en(&mut self) -> SLOWMEM_PD_EN_W<PWC_SPEC> {
         SLOWMEM_PD_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - rtc_peri force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pd(&mut self) -> FORCE_PD_W<PWC_SPEC> {
         FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - rtc_peri force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pu(&mut self) -> FORCE_PU_W<PWC_SPEC> {
         FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - enable power down rtc_peri in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_en(&mut self) -> PD_EN_W<PWC_SPEC> {
         PD_EN_W::new(self, 20)
     }
diff --git a/esp32/src/rtc_cntl/reg.rs b/esp32/src/rtc_cntl/reg.rs
index 7fc6b8f0cf..0b18af2a45 100644
--- a/esp32/src/rtc_cntl/reg.rs
+++ b/esp32/src/rtc_cntl/reg.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - N/A"]
     #[inline(always)]
-    #[must_use]
     pub fn sck_dcap_force(&mut self) -> SCK_DCAP_FORCE_W<REG_SPEC> {
         SCK_DCAP_FORCE_W::new(self, 7)
     }
     #[doc = "Bits 8:10 - DIG_REG_DBIAS during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_dbias_slp(&mut self) -> DIG_DBIAS_SLP_W<REG_SPEC> {
         DIG_DBIAS_SLP_W::new(self, 8)
     }
     #[doc = "Bits 11:13 - DIG_REG_DBIAS during wakeup"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_dbias_wak(&mut self) -> DIG_DBIAS_WAK_W<REG_SPEC> {
         DIG_DBIAS_WAK_W::new(self, 11)
     }
     #[doc = "Bits 14:21 - SCK_DCAP"]
     #[inline(always)]
-    #[must_use]
     pub fn sck_dcap(&mut self) -> SCK_DCAP_W<REG_SPEC> {
         SCK_DCAP_W::new(self, 14)
     }
     #[doc = "Bits 22:24 - RTC_DBIAS during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dbias_slp(&mut self) -> DBIAS_SLP_W<REG_SPEC> {
         DBIAS_SLP_W::new(self, 22)
     }
     #[doc = "Bits 25:27 - RTC_DBIAS during wakeup"]
     #[inline(always)]
-    #[must_use]
     pub fn dbias_wak(&mut self) -> DBIAS_WAK_W<REG_SPEC> {
         DBIAS_WAK_W::new(self, 25)
     }
     #[doc = "Bit 28 - RTC_DBOOST force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pd(&mut self) -> DBOOST_FORCE_PD_W<REG_SPEC> {
         DBOOST_FORCE_PD_W::new(self, 28)
     }
     #[doc = "Bit 29 - RTC_DBOOST force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pu(&mut self) -> DBOOST_FORCE_PU_W<REG_SPEC> {
         DBOOST_FORCE_PU_W::new(self, 29)
     }
     #[doc = "Bit 30 - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pd(&mut self) -> FORCE_PD_W<REG_SPEC> {
         FORCE_PD_W::new(self, 30)
     }
     #[doc = "Bit 31 - RTC_REG force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pu(&mut self) -> FORCE_PU_W<REG_SPEC> {
         FORCE_PU_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/reset_state.rs b/esp32/src/rtc_cntl/reset_state.rs
index b51ca4e17b..17dfcac87d 100644
--- a/esp32/src/rtc_cntl/reset_state.rs
+++ b/esp32/src/rtc_cntl/reset_state.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_stat_vector_sel(&mut self) -> APPCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         APPCPU_STAT_VECTOR_SEL_W::new(self, 12)
     }
     #[doc = "Bit 13 - PRO CPU state vector sel"]
     #[inline(always)]
-    #[must_use]
     pub fn procpu_stat_vector_sel(&mut self) -> PROCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         PROCPU_STAT_VECTOR_SEL_W::new(self, 13)
     }
diff --git a/esp32/src/rtc_cntl/sdio_act_conf.rs b/esp32/src/rtc_cntl/sdio_act_conf.rs
index b4eb0aa248..195a713f84 100644
--- a/esp32/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32/src/rtc_cntl/sdio_act_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 22:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W<SDIO_ACT_CONF_SPEC> {
         SDIO_ACT_DNUM_W::new(self, 22)
     }
diff --git a/esp32/src/rtc_cntl/sdio_conf.rs b/esp32/src/rtc_cntl/sdio_conf.rs
index 01aa3dbc09..38c2b59fe6 100644
--- a/esp32/src/rtc_cntl/sdio_conf.rs
+++ b/esp32/src/rtc_cntl/sdio_conf.rs
@@ -92,43 +92,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_pd_en(&mut self) -> SDIO_PD_EN_W<SDIO_CONF_SPEC> {
         SDIO_PD_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: use SW option to control SDIO_REG 0: use state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_force(&mut self) -> SDIO_FORCE_W<SDIO_CONF_SPEC> {
         SDIO_FORCE_W::new(self, 22)
     }
     #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<SDIO_CONF_SPEC> {
         SDIO_TIEH_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<SDIO_CONF_SPEC> {
         DREFL_SDIO_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<SDIO_CONF_SPEC> {
         DREFM_SDIO_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<SDIO_CONF_SPEC> {
         DREFH_SDIO_W::new(self, 29)
     }
     #[doc = "Bit 31 - SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sdio(&mut self) -> XPD_SDIO_W<SDIO_CONF_SPEC> {
         XPD_SDIO_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/slp_reject_conf.rs b/esp32/src/rtc_cntl/slp_reject_conf.rs
index de38b889ba..58fdc163c1 100644
--- a/esp32/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32/src/rtc_cntl/slp_reject_conf.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 24 - enable GPIO reject"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_reject_en(&mut self) -> GPIO_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         GPIO_REJECT_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - enable SDIO reject"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_reject_en(&mut self) -> SDIO_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         SDIO_REJECT_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - enable reject for light sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn light_slp_reject_en(&mut self) -> LIGHT_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         LIGHT_SLP_REJECT_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - enable reject for deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn deep_slp_reject_en(&mut self) -> DEEP_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         DEEP_SLP_REJECT_EN_W::new(self, 27)
     }
diff --git a/esp32/src/rtc_cntl/slp_timer0.rs b/esp32/src/rtc_cntl/slp_timer0.rs
index 96fbc6ecbb..aa2d471ecf 100644
--- a/esp32/src/rtc_cntl/slp_timer0.rs
+++ b/esp32/src/rtc_cntl/slp_timer0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_lo(&mut self) -> SLP_VAL_LO_W<SLP_TIMER0_SPEC> {
         SLP_VAL_LO_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/slp_timer1.rs b/esp32/src/rtc_cntl/slp_timer1.rs
index 85b78b7810..72c5fc6528 100644
--- a/esp32/src/rtc_cntl/slp_timer1.rs
+++ b/esp32/src/rtc_cntl/slp_timer1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<SLP_TIMER1_SPEC> {
         SLP_VAL_HI_W::new(self, 0)
     }
     #[doc = "Bit 16 - timer alarm enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<SLP_TIMER1_SPEC> {
         MAIN_TIMER_ALARM_EN_W::new(self, 16)
     }
diff --git a/esp32/src/rtc_cntl/state0.rs b/esp32/src/rtc_cntl/state0.rs
index 8b70233cab..8f31422364 100644
--- a/esp32/src/rtc_cntl/state0.rs
+++ b/esp32/src/rtc_cntl/state0.rs
@@ -102,49 +102,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20 - touch controller force wake up"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_wakeup_force_en(&mut self) -> TOUCH_WAKEUP_FORCE_EN_W<STATE0_SPEC> {
         TOUCH_WAKEUP_FORCE_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - ULP-coprocessor force wake up"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_wakeup_force_en(&mut self) -> ULP_CP_WAKEUP_FORCE_EN_W<STATE0_SPEC> {
         ULP_CP_WAKEUP_FORCE_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: APB to RTC using bridge 0: APB to RTC using sync"]
     #[inline(always)]
-    #[must_use]
     pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<STATE0_SPEC> {
         APB2RTC_BRIDGE_SEL_W::new(self, 22)
     }
     #[doc = "Bit 23 - touch timer enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_timer_en(&mut self) -> TOUCH_SLP_TIMER_EN_W<STATE0_SPEC> {
         TOUCH_SLP_TIMER_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - ULP-coprocessor timer enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<STATE0_SPEC> {
         ULP_CP_SLP_TIMER_EN_W::new(self, 24)
     }
     #[doc = "Bit 29 - sleep wakeup bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<STATE0_SPEC> {
         SLP_WAKEUP_W::new(self, 29)
     }
     #[doc = "Bit 30 - sleep reject bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<STATE0_SPEC> {
         SLP_REJECT_W::new(self, 30)
     }
     #[doc = "Bit 31 - sleep enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_en(&mut self) -> SLEEP_EN_W<STATE0_SPEC> {
         SLEEP_EN_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/store0.rs b/esp32/src/rtc_cntl/store0.rs
index b8510c385f..2ce81f5fa8 100644
--- a/esp32/src/rtc_cntl/store0.rs
+++ b/esp32/src/rtc_cntl/store0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch0(&mut self) -> SCRATCH0_W<STORE0_SPEC> {
         SCRATCH0_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store1.rs b/esp32/src/rtc_cntl/store1.rs
index 04febd071e..631442449e 100644
--- a/esp32/src/rtc_cntl/store1.rs
+++ b/esp32/src/rtc_cntl/store1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch1(&mut self) -> SCRATCH1_W<STORE1_SPEC> {
         SCRATCH1_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store2.rs b/esp32/src/rtc_cntl/store2.rs
index 9c35a60d35..f89e95c740 100644
--- a/esp32/src/rtc_cntl/store2.rs
+++ b/esp32/src/rtc_cntl/store2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch2(&mut self) -> SCRATCH2_W<STORE2_SPEC> {
         SCRATCH2_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store3.rs b/esp32/src/rtc_cntl/store3.rs
index 79723e38c0..43e1375a03 100644
--- a/esp32/src/rtc_cntl/store3.rs
+++ b/esp32/src/rtc_cntl/store3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch3(&mut self) -> SCRATCH3_W<STORE3_SPEC> {
         SCRATCH3_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store4.rs b/esp32/src/rtc_cntl/store4.rs
index 8432c64eeb..b87c7266e6 100644
--- a/esp32/src/rtc_cntl/store4.rs
+++ b/esp32/src/rtc_cntl/store4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch4(&mut self) -> SCRATCH4_W<STORE4_SPEC> {
         SCRATCH4_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store5.rs b/esp32/src/rtc_cntl/store5.rs
index 8b1fd29c9d..68684a6337 100644
--- a/esp32/src/rtc_cntl/store5.rs
+++ b/esp32/src/rtc_cntl/store5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch5(&mut self) -> SCRATCH5_W<STORE5_SPEC> {
         SCRATCH5_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store6.rs b/esp32/src/rtc_cntl/store6.rs
index 5046782723..a89e32cb01 100644
--- a/esp32/src/rtc_cntl/store6.rs
+++ b/esp32/src/rtc_cntl/store6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch6(&mut self) -> SCRATCH6_W<STORE6_SPEC> {
         SCRATCH6_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/store7.rs b/esp32/src/rtc_cntl/store7.rs
index b796a05990..02950cb377 100644
--- a/esp32/src/rtc_cntl/store7.rs
+++ b/esp32/src/rtc_cntl/store7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch7(&mut self) -> SCRATCH7_W<STORE7_SPEC> {
         SCRATCH7_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/sw_cpu_stall.rs b/esp32/src/rtc_cntl/sw_cpu_stall.rs
index ae2be351a8..d46ee7df3c 100644
--- a/esp32/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32/src/rtc_cntl/sw_cpu_stall.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c1(&mut self) -> SW_STALL_APPCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_APPCPU_C1_W::new(self, 20)
     }
     #[doc = "Bits 26:31 - {reg_sw_stall_procpu_c1\\[5:0\\] reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c1(&mut self) -> SW_STALL_PROCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_PROCPU_C1_W::new(self, 26)
     }
diff --git a/esp32/src/rtc_cntl/test_mux.rs b/esp32/src/rtc_cntl/test_mux.rs
index cd515ee358..cf52cc0462 100644
--- a/esp32/src/rtc_cntl/test_mux.rs
+++ b/esp32/src/rtc_cntl/test_mux.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - ENT_RTC"]
     #[inline(always)]
-    #[must_use]
     pub fn ent_rtc(&mut self) -> ENT_RTC_W<TEST_MUX_SPEC> {
         ENT_RTC_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - DTEST_RTC"]
     #[inline(always)]
-    #[must_use]
     pub fn dtest_rtc(&mut self) -> DTEST_RTC_W<TEST_MUX_SPEC> {
         DTEST_RTC_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_cntl/time_update.rs b/esp32/src/rtc_cntl/time_update.rs
index b675b8dcde..8c8a29993f 100644
--- a/esp32/src/rtc_cntl/time_update.rs
+++ b/esp32/src/rtc_cntl/time_update.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Set 1: to update register with RTC timer"]
     #[inline(always)]
-    #[must_use]
     pub fn time_update(&mut self) -> TIME_UPDATE_W<TIME_UPDATE_SPEC> {
         TIME_UPDATE_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/timer1.rs b/esp32/src/rtc_cntl/timer1.rs
index 804dda8abf..b6c21e9202 100644
--- a/esp32/src/rtc_cntl/timer1.rs
+++ b/esp32/src/rtc_cntl/timer1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<TIMER1_SPEC> {
         CPU_STALL_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<TIMER1_SPEC> {
         CPU_STALL_WAIT_W::new(self, 1)
     }
     #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<TIMER1_SPEC> {
         CK8M_WAIT_W::new(self, 6)
     }
     #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<TIMER1_SPEC> {
         XTL_BUF_WAIT_W::new(self, 14)
     }
     #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<TIMER1_SPEC> {
         PLL_BUF_WAIT_W::new(self, 24)
     }
diff --git a/esp32/src/rtc_cntl/timer2.rs b/esp32/src/rtc_cntl/timer2.rs
index f89909059b..3a9e0241c7 100644
--- a/esp32/src/rtc_cntl/timer2.rs
+++ b/esp32/src/rtc_cntl/timer2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
     #[inline(always)]
-    #[must_use]
     pub fn ulpcp_touch_start_wait(&mut self) -> ULPCP_TOUCH_START_WAIT_W<TIMER2_SPEC> {
         ULPCP_TOUCH_START_WAIT_W::new(self, 15)
     }
     #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
     #[inline(always)]
-    #[must_use]
     pub fn min_time_ck8m_off(&mut self) -> MIN_TIME_CK8M_OFF_W<TIMER2_SPEC> {
         MIN_TIME_CK8M_OFF_W::new(self, 24)
     }
diff --git a/esp32/src/rtc_cntl/timer3.rs b/esp32/src/rtc_cntl/timer3.rs
index ba2b6ec3b4..5be62166c8 100644
--- a/esp32/src/rtc_cntl/timer3.rs
+++ b/esp32/src/rtc_cntl/timer3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_wait_timer(&mut self) -> WIFI_WAIT_TIMER_W<TIMER3_SPEC> {
         WIFI_WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_powerup_timer(&mut self) -> WIFI_POWERUP_TIMER_W<TIMER3_SPEC> {
         WIFI_POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_ram_wait_timer(&mut self) -> ROM_RAM_WAIT_TIMER_W<TIMER3_SPEC> {
         ROM_RAM_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_ram_powerup_timer(&mut self) -> ROM_RAM_POWERUP_TIMER_W<TIMER3_SPEC> {
         ROM_RAM_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32/src/rtc_cntl/timer4.rs b/esp32/src/rtc_cntl/timer4.rs
index 7f3ccf88c5..d6801c4001 100644
--- a/esp32/src/rtc_cntl/timer4.rs
+++ b/esp32/src/rtc_cntl/timer4.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn wait_timer(&mut self) -> WAIT_TIMER_W<TIMER4_SPEC> {
         WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15"]
     #[inline(always)]
-    #[must_use]
     pub fn powerup_timer(&mut self) -> POWERUP_TIMER_W<TIMER4_SPEC> {
         POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_wait_timer(&mut self) -> DG_WRAP_WAIT_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_powerup_timer(&mut self) -> DG_WRAP_POWERUP_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32/src/rtc_cntl/timer5.rs b/esp32/src/rtc_cntl/timer5.rs
index 223a77bb06..0fe9d33ecb 100644
--- a/esp32/src/rtc_cntl/timer5.rs
+++ b/esp32/src/rtc_cntl/timer5.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_subtimer_prediv(&mut self) -> ULP_CP_SUBTIMER_PREDIV_W<TIMER5_SPEC> {
         ULP_CP_SUBTIMER_PREDIV_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<TIMER5_SPEC> {
         MIN_SLP_VAL_W::new(self, 8)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn rtcmem_wait_timer(&mut self) -> RTCMEM_WAIT_TIMER_W<TIMER5_SPEC> {
         RTCMEM_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rtcmem_powerup_timer(&mut self) -> RTCMEM_POWERUP_TIMER_W<TIMER5_SPEC> {
         RTCMEM_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32/src/rtc_cntl/wakeup_state.rs b/esp32/src/rtc_cntl/wakeup_state.rs
index 993d3f4ed7..1af41b318a 100644
--- a/esp32/src/rtc_cntl/wakeup_state.rs
+++ b/esp32/src/rtc_cntl/wakeup_state.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 11:21 - wakeup enable bitmap"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W<WAKEUP_STATE_SPEC> {
         WAKEUP_ENA_W::new(self, 11)
     }
     #[doc = "Bit 22 - enable filter for gpio wakeup event"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_wakeup_filter(&mut self) -> GPIO_WAKEUP_FILTER_W<WAKEUP_STATE_SPEC> {
         GPIO_WAKEUP_FILTER_W::new(self, 22)
     }
diff --git a/esp32/src/rtc_cntl/wdtconfig0.rs b/esp32/src/rtc_cntl/wdtconfig0.rs
index 34bc4e6c1a..766d191b83 100644
--- a/esp32/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32/src/rtc_cntl/wdtconfig0.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - pause WDT in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<WDTCONFIG0_SPEC> {
         WDT_PAUSE_IN_SLP_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable WDT reset APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_APPCPU_RESET_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable WDT reset PRO CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_PROCPU_RESET_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable WDT in flash boot"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 10)
     }
     #[doc = "Bits 11:13 - system reset counter length"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 11)
     }
     #[doc = "Bits 14:16 - CPU reset counter length"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 14)
     }
     #[doc = "Bit 17 - N/A"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_LEVEL_INT_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - N/A"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EDGE_INT_EN_W::new(self, 18)
     }
     #[doc = "Bits 19:21 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 19)
     }
     #[doc = "Bits 22:24 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 22)
     }
     #[doc = "Bits 25:27 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 28)
     }
     #[doc = "Bit 31 - enable RTC WDT"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/wdtconfig1.rs b/esp32/src/rtc_cntl/wdtconfig1.rs
index ef41da26e5..dc1c1e8312 100644
--- a/esp32/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32/src/rtc_cntl/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG1_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/wdtconfig2.rs b/esp32/src/rtc_cntl/wdtconfig2.rs
index 6528769dfb..0d38c5c461 100644
--- a/esp32/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32/src/rtc_cntl/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/wdtconfig3.rs b/esp32/src/rtc_cntl/wdtconfig3.rs
index e62c11a620..3c7391e88f 100644
--- a/esp32/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32/src/rtc_cntl/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/wdtconfig4.rs b/esp32/src/rtc_cntl/wdtconfig4.rs
index 73fb5c4b47..62fb7fb500 100644
--- a/esp32/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32/src/rtc_cntl/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_cntl/wdtfeed.rs b/esp32/src/rtc_cntl/wdtfeed.rs
index 8405420ed7..4b687c22d0 100644
--- a/esp32/src/rtc_cntl/wdtfeed.rs
+++ b/esp32/src/rtc_cntl/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_cntl/wdtwprotect.rs b/esp32/src/rtc_cntl/wdtwprotect.rs
index 54b8a891e7..94d4e973e8 100644
--- a/esp32/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32/src/rtc_cntl/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/cmd.rs b/esp32/src/rtc_i2c/cmd.rs
index 0860abcbe0..647245d981 100644
--- a/esp32/src/rtc_i2c/cmd.rs
+++ b/esp32/src/rtc_i2c/cmd.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - Command content"]
     #[inline(always)]
-    #[must_use]
     pub fn val(&mut self) -> VAL_W<CMD_SPEC> {
         VAL_W::new(self, 0)
     }
     #[doc = "Bit 31 - Bit is set by HW when command is done"]
     #[inline(always)]
-    #[must_use]
     pub fn done(&mut self) -> DONE_W<CMD_SPEC> {
         DONE_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_i2c/ctrl.rs b/esp32/src/rtc_i2c/ctrl.rs
index edf037c028..55ac671591 100644
--- a/esp32/src/rtc_i2c/ctrl.rs
+++ b/esp32/src/rtc_i2c/ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - SDA is push-pull (1) or open-drain (0)"]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - SCL is push-pull (1) or open-drain (0)"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 4 - Master (1) or slave (0)"]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
         MS_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Force to generate start condition"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
         TRANS_START_W::new(self, 5)
     }
     #[doc = "Bit 6 - Send LSB first"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
         TX_LSB_FIRST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Receive LSB first"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
         RX_LSB_FIRST_W::new(self, 7)
     }
diff --git a/esp32/src/rtc_i2c/debug_status.rs b/esp32/src/rtc_i2c/debug_status.rs
index 7e4c23ab26..ef76cae0e3 100644
--- a/esp32/src/rtc_i2c/debug_status.rs
+++ b/esp32/src/rtc_i2c/debug_status.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The value of an acknowledge signal on the bus"]
     #[inline(always)]
-    #[must_use]
     pub fn ack_val(&mut self) -> ACK_VAL_W<DEBUG_STATUS_SPEC> {
         ACK_VAL_W::new(self, 0)
     }
     #[doc = "Bit 1 - When working as a slave, the value of R/W bit received"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_rw(&mut self) -> SLAVE_RW_W<DEBUG_STATUS_SPEC> {
         SLAVE_RW_W::new(self, 1)
     }
     #[doc = "Bit 2 - Transfer has timed out"]
     #[inline(always)]
-    #[must_use]
     pub fn timed_out(&mut self) -> TIMED_OUT_W<DEBUG_STATUS_SPEC> {
         TIMED_OUT_W::new(self, 2)
     }
     #[doc = "Bit 3 - When working as a master, lost control of I2C bus"]
     #[inline(always)]
-    #[must_use]
     pub fn arb_lost(&mut self) -> ARB_LOST_W<DEBUG_STATUS_SPEC> {
         ARB_LOST_W::new(self, 3)
     }
     #[doc = "Bit 4 - operation is in progress"]
     #[inline(always)]
-    #[must_use]
     pub fn bus_busy(&mut self) -> BUS_BUSY_W<DEBUG_STATUS_SPEC> {
         BUS_BUSY_W::new(self, 4)
     }
     #[doc = "Bit 5 - When working as a slave, whether address was matched"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr_match(&mut self) -> SLAVE_ADDR_MATCH_W<DEBUG_STATUS_SPEC> {
         SLAVE_ADDR_MATCH_W::new(self, 5)
     }
     #[doc = "Bit 6 - 8 bit transmit done"]
     #[inline(always)]
-    #[must_use]
     pub fn byte_trans(&mut self) -> BYTE_TRANS_W<DEBUG_STATUS_SPEC> {
         BYTE_TRANS_W::new(self, 6)
     }
     #[doc = "Bits 25:27 - state of the main state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn main_state(&mut self) -> MAIN_STATE_W<DEBUG_STATUS_SPEC> {
         MAIN_STATE_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - state of SCL state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_state(&mut self) -> SCL_STATE_W<DEBUG_STATUS_SPEC> {
         SCL_STATE_W::new(self, 28)
     }
diff --git a/esp32/src/rtc_i2c/int_clr.rs b/esp32/src/rtc_i2c/int_clr.rs
index c83d13f34c..65d07f0fab 100644
--- a/esp32/src/rtc_i2c/int_clr.rs
+++ b/esp32/src/rtc_i2c/int_clr.rs
@@ -56,31 +56,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_trans_complete(&mut self) -> SLAVE_TRANS_COMPLETE_W<INT_CLR_SPEC> {
         SLAVE_TRANS_COMPLETE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn master_trans_complete(&mut self) -> MASTER_TRANS_COMPLETE_W<INT_CLR_SPEC> {
         MASTER_TRANS_COMPLETE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
diff --git a/esp32/src/rtc_i2c/int_raw.rs b/esp32/src/rtc_i2c/int_raw.rs
index cbb26bf484..2ced2eba4b 100644
--- a/esp32/src/rtc_i2c/int_raw.rs
+++ b/esp32/src/rtc_i2c/int_raw.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - Slave accepted 1 byte and address matched"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_trans_complete(&mut self) -> SLAVE_TRANS_COMPLETE_W<INT_RAW_SPEC> {
         SLAVE_TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Master lost arbitration"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_RAW_SPEC> {
         ARBITRATION_LOST_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn master_trans_complete(&mut self) -> MASTER_TRANS_COMPLETE_W<INT_RAW_SPEC> {
         MASTER_TRANS_COMPLETE_W::new(self, 5)
     }
     #[doc = "Bit 6 - Stop condition has been detected interrupt raw status"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_RAW_SPEC> {
         TRANS_COMPLETE_W::new(self, 6)
     }
diff --git a/esp32/src/rtc_i2c/scl_high_period.rs b/esp32/src/rtc_i2c/scl_high_period.rs
index 16b39bcf43..a17e9af1c6 100644
--- a/esp32/src/rtc_i2c/scl_high_period.rs
+++ b/esp32/src/rtc_i2c/scl_high_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles for SCL to be high"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_HIGH_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/scl_low_period.rs b/esp32/src/rtc_i2c/scl_low_period.rs
index 9538fe1b6e..df3c65c0c9 100644
--- a/esp32/src/rtc_i2c/scl_low_period.rs
+++ b/esp32/src/rtc_i2c/scl_low_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:24 - number of cycles that scl == 0"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<SCL_LOW_PERIOD_SPEC> {
         SCL_LOW_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/scl_start_period.rs b/esp32/src/rtc_i2c/scl_start_period.rs
index fb4b2321f9..8817c9448e 100644
--- a/esp32/src/rtc_i2c/scl_start_period.rs
+++ b/esp32/src/rtc_i2c/scl_start_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles to wait before generating start condition"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_start_period(&mut self) -> SCL_START_PERIOD_W<SCL_START_PERIOD_SPEC> {
         SCL_START_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/scl_stop_period.rs b/esp32/src/rtc_i2c/scl_stop_period.rs
index 2c5b9b9a4d..b70fb6015c 100644
--- a/esp32/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32/src/rtc_i2c/scl_stop_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles to wait before generating stop condition"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_stop_period(&mut self) -> SCL_STOP_PERIOD_W<SCL_STOP_PERIOD_SPEC> {
         SCL_STOP_PERIOD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/sda_duty.rs b/esp32/src/rtc_i2c/sda_duty.rs
index a3070df62f..aafdce8a42 100644
--- a/esp32/src/rtc_i2c/sda_duty.rs
+++ b/esp32/src/rtc_i2c/sda_duty.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles SDA will switch after falling edge of SCL"]
     #[inline(always)]
-    #[must_use]
     pub fn sda_duty(&mut self) -> SDA_DUTY_W<SDA_DUTY_SPEC> {
         SDA_DUTY_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_i2c/slave_addr.rs b/esp32/src/rtc_i2c/slave_addr.rs
index 1d0323a546..8ba09a6783 100644
--- a/esp32/src/rtc_i2c/slave_addr.rs
+++ b/esp32/src/rtc_i2c/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - local slave address"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - Set if local slave address is 10-bit"]
     #[inline(always)]
-    #[must_use]
     pub fn _10bit(&mut self) -> _10BIT_W<SLAVE_ADDR_SPEC> {
         _10BIT_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_i2c/timeout.rs b/esp32/src/rtc_i2c/timeout.rs
index 0548e3e2f8..3595ed440a 100644
--- a/esp32/src/rtc_i2c/timeout.rs
+++ b/esp32/src/rtc_i2c/timeout.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Maximum number of FAST_CLK cycles that the transmission can take"]
     #[inline(always)]
-    #[must_use]
     pub fn timeout(&mut self) -> TIMEOUT_W<TIMEOUT_SPEC> {
         TIMEOUT_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_io.rs b/esp32/src/rtc_io.rs
index 737610b658..c40e0dd6d1 100644
--- a/esp32/src/rtc_io.rs
+++ b/esp32/src/rtc_io.rs
@@ -124,6 +124,8 @@ impl RegisterBlock {
         &self.adc_pad
     }
     #[doc = "0x84..0x8c - "]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `PAD_DAC1` register.</div>"]
     #[inline(always)]
     pub const fn pad_dac(&self, n: usize) -> &PAD_DAC {
         &self.pad_dac[n]
diff --git a/esp32/src/rtc_io/adc_pad.rs b/esp32/src/rtc_io/adc_pad.rs
index af2a538916..a8d35cf46e 100644
--- a/esp32/src/rtc_io/adc_pad.rs
+++ b/esp32/src/rtc_io/adc_pad.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 18 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_fun_ie(&mut self) -> ADC2_FUN_IE_W<ADC_PAD_SPEC> {
         ADC2_FUN_IE_W::new(self, 18)
     }
     #[doc = "Bit 19 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_slp_ie(&mut self) -> ADC2_SLP_IE_W<ADC_PAD_SPEC> {
         ADC2_SLP_IE_W::new(self, 19)
     }
     #[doc = "Bit 20 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_slp_sel(&mut self) -> ADC2_SLP_SEL_W<ADC_PAD_SPEC> {
         ADC2_SLP_SEL_W::new(self, 20)
     }
     #[doc = "Bits 21:22 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_fun_sel(&mut self) -> ADC2_FUN_SEL_W<ADC_PAD_SPEC> {
         ADC2_FUN_SEL_W::new(self, 21)
     }
     #[doc = "Bit 23 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_fun_ie(&mut self) -> ADC1_FUN_IE_W<ADC_PAD_SPEC> {
         ADC1_FUN_IE_W::new(self, 23)
     }
     #[doc = "Bit 24 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_slp_ie(&mut self) -> ADC1_SLP_IE_W<ADC_PAD_SPEC> {
         ADC1_SLP_IE_W::new(self, 24)
     }
     #[doc = "Bit 25 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_slp_sel(&mut self) -> ADC1_SLP_SEL_W<ADC_PAD_SPEC> {
         ADC1_SLP_SEL_W::new(self, 25)
     }
     #[doc = "Bits 26:27 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_fun_sel(&mut self) -> ADC1_FUN_SEL_W<ADC_PAD_SPEC> {
         ADC1_FUN_SEL_W::new(self, 26)
     }
     #[doc = "Bit 28 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_mux_sel(&mut self) -> ADC2_MUX_SEL_W<ADC_PAD_SPEC> {
         ADC2_MUX_SEL_W::new(self, 28)
     }
     #[doc = "Bit 29 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_mux_sel(&mut self) -> ADC1_MUX_SEL_W<ADC_PAD_SPEC> {
         ADC1_MUX_SEL_W::new(self, 29)
     }
     #[doc = "Bit 30 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_hold(&mut self) -> ADC2_HOLD_W<ADC_PAD_SPEC> {
         ADC2_HOLD_W::new(self, 30)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_hold(&mut self) -> ADC1_HOLD_W<ADC_PAD_SPEC> {
         ADC1_HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/date.rs b/esp32/src/rtc_io/date.rs
index 423472f5fa..51c470b95a 100644
--- a/esp32/src/rtc_io/date.rs
+++ b/esp32/src/rtc_io/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - date"]
     #[inline(always)]
-    #[must_use]
     pub fn io_date(&mut self) -> IO_DATE_W<DATE_SPEC> {
         IO_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_io/dig_pad_hold.rs b/esp32/src/rtc_io/dig_pad_hold.rs
index 5186f2d14f..e6c03c3e68 100644
--- a/esp32/src/rtc_io/dig_pad_hold.rs
+++ b/esp32/src/rtc_io/dig_pad_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - select the digital pad hold value."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_pad_hold(&mut self) -> DIG_PAD_HOLD_W<DIG_PAD_HOLD_SPEC> {
         DIG_PAD_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/rtc_io/enable.rs b/esp32/src/rtc_io/enable.rs
index b69b17e3f8..14f6214bfa 100644
--- a/esp32/src/rtc_io/enable.rs
+++ b/esp32/src/rtc_io/enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output enable"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<ENABLE_SPEC> {
         ENABLE_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/enable_w1tc.rs b/esp32/src/rtc_io/enable_w1tc.rs
index 4a6ca20b09..8ad82dce67 100644
--- a/esp32/src/rtc_io/enable_w1tc.rs
+++ b/esp32/src/rtc_io/enable_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output enable write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_W1TC_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/enable_w1ts.rs b/esp32/src/rtc_io/enable_w1ts.rs
index 117ca2db4e..fe1def7b95 100644
--- a/esp32/src/rtc_io/enable_w1ts.rs
+++ b/esp32/src/rtc_io/enable_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output enable write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1ts(&mut self) -> ENABLE_W1TS_W<ENABLE_W1TS_SPEC> {
         ENABLE_W1TS_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/ext_wakeup0.rs b/esp32/src/rtc_io/ext_wakeup0.rs
index 08fa37abc9..64fe93c7a0 100644
--- a/esp32/src/rtc_io/ext_wakeup0.rs
+++ b/esp32/src/rtc_io/ext_wakeup0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP0_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32/src/rtc_io/hall_sens.rs b/esp32/src/rtc_io/hall_sens.rs
index 4928740c53..1a60e64c3e 100644
--- a/esp32/src/rtc_io/hall_sens.rs
+++ b/esp32/src/rtc_io/hall_sens.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - Reverse phase of hall sensor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase(&mut self) -> HALL_PHASE_W<HALL_SENS_SPEC> {
         HALL_PHASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Power on hall sensor and connect to VP and VN"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall(&mut self) -> XPD_HALL_W<HALL_SENS_SPEC> {
         XPD_HALL_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/out.rs b/esp32/src/rtc_io/out.rs
index ddc9219acc..d50f6fb6d1 100644
--- a/esp32/src/rtc_io/out.rs
+++ b/esp32/src/rtc_io/out.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output value"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<OUT_SPEC> {
         DATA_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/out_w1tc.rs b/esp32/src/rtc_io/out_w1tc.rs
index 83c3956a7b..b99d2f5b9c 100644
--- a/esp32/src/rtc_io/out_w1tc.rs
+++ b/esp32/src/rtc_io/out_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output value write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_w1tc(&mut self) -> OUT_DATA_W1TC_W<OUT_W1TC_SPEC> {
         OUT_DATA_W1TC_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/out_w1ts.rs b/esp32/src/rtc_io/out_w1ts.rs
index 8524051778..222f728252 100644
--- a/esp32/src/rtc_io/out_w1ts.rs
+++ b/esp32/src/rtc_io/out_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output value write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_w1ts(&mut self) -> OUT_DATA_W1TS_W<OUT_W1TS_SPEC> {
         OUT_DATA_W1TS_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/pad_dac.rs b/esp32/src/rtc_io/pad_dac.rs
index 6fa689ba1a..9e903cd42b 100644
--- a/esp32/src/rtc_io/pad_dac.rs
+++ b/esp32/src/rtc_io/pad_dac.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_xpd_force(&mut self) -> DAC_XPD_FORCE_W<PAD_DAC_SPEC> {
         DAC_XPD_FORCE_W::new(self, 10)
     }
     #[doc = "Bit 11 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<PAD_DAC_SPEC> {
         FUN_IE_W::new(self, 11)
     }
     #[doc = "Bit 12 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<PAD_DAC_SPEC> {
         SLP_OE_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<PAD_DAC_SPEC> {
         SLP_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<PAD_DAC_SPEC> {
         SLP_SEL_W::new(self, 14)
     }
     #[doc = "Bits 15:16 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<PAD_DAC_SPEC> {
         FUN_SEL_W::new(self, 15)
     }
     #[doc = "Bit 17 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<PAD_DAC_SPEC> {
         MUX_SEL_W::new(self, 17)
     }
     #[doc = "Bit 18 - Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_dac(&mut self) -> XPD_DAC_W<PAD_DAC_SPEC> {
         XPD_DAC_W::new(self, 18)
     }
     #[doc = "Bits 19:26 - PAD DAC1 control code."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<PAD_DAC_SPEC> {
         DAC_W::new(self, 19)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<PAD_DAC_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<PAD_DAC_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bit 29 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<PAD_DAC_SPEC> {
         HOLD_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<PAD_DAC_SPEC> {
         DRV_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_io/pin.rs b/esp32/src/rtc_io/pin.rs
index 0fd06acf32..18958d3128 100644
--- a/esp32/src/rtc_io/pin.rs
+++ b/esp32/src/rtc_io/pin.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
         INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - GPIO wake up enable only available in light sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
         WAKEUP_ENABLE_W::new(self, 10)
     }
diff --git a/esp32/src/rtc_io/rtc_debug_sel.rs b/esp32/src/rtc_io/rtc_debug_sel.rs
index 84e4df0d52..65edd16a49 100644
--- a/esp32/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32/src/rtc_io/rtc_debug_sel.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_sel0(&mut self) -> DEBUG_SEL0_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_SEL0_W::new(self, 0)
     }
     #[doc = "Bits 5:9"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_sel1(&mut self) -> DEBUG_SEL1_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_SEL1_W::new(self, 5)
     }
     #[doc = "Bits 10:14"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_sel2(&mut self) -> DEBUG_SEL2_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_SEL2_W::new(self, 10)
     }
     #[doc = "Bits 15:19"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_sel3(&mut self) -> DEBUG_SEL3_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_SEL3_W::new(self, 15)
     }
     #[doc = "Bits 20:24"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_sel4(&mut self) -> DEBUG_SEL4_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_SEL4_W::new(self, 20)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_12m_no_gating(&mut self) -> DEBUG_12M_NO_GATING_W<RTC_DEBUG_SEL_SPEC> {
         DEBUG_12M_NO_GATING_W::new(self, 25)
     }
diff --git a/esp32/src/rtc_io/sar_i2c_io.rs b/esp32/src/rtc_io/sar_i2c_io.rs
index fa79748608..1ce7346e0d 100644
--- a/esp32/src/rtc_io/sar_i2c_io.rs
+++ b/esp32/src/rtc_io/sar_i2c_io.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 23:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_DEBUG_BIT_SEL_W::new(self, 23)
     }
     #[doc = "Bits 28:29 - Ò0Ó using TOUCH_PAD\\[0\\] as i2c clk Ò1Ó using TOUCH_PAD\\[2\\] as i2c clk"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SCL_SEL_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - Ò0Ó using TOUCH_PAD\\[1\\] as i2c sda Ò1Ó using TOUCH_PAD\\[3\\] as i2c sda"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SDA_SEL_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_io/sensor_pads.rs b/esp32/src/rtc_io/sensor_pads.rs
index b1c37246e7..1f4a0e1496 100644
--- a/esp32/src/rtc_io/sensor_pads.rs
+++ b/esp32/src/rtc_io/sensor_pads.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 4 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_fun_ie(&mut self) -> SENSE4_FUN_IE_W<SENSOR_PADS_SPEC> {
         SENSE4_FUN_IE_W::new(self, 4)
     }
     #[doc = "Bit 5 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_slp_ie(&mut self) -> SENSE4_SLP_IE_W<SENSOR_PADS_SPEC> {
         SENSE4_SLP_IE_W::new(self, 5)
     }
     #[doc = "Bit 6 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_slp_sel(&mut self) -> SENSE4_SLP_SEL_W<SENSOR_PADS_SPEC> {
         SENSE4_SLP_SEL_W::new(self, 6)
     }
     #[doc = "Bits 7:8 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_fun_sel(&mut self) -> SENSE4_FUN_SEL_W<SENSOR_PADS_SPEC> {
         SENSE4_FUN_SEL_W::new(self, 7)
     }
     #[doc = "Bit 9 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_fun_ie(&mut self) -> SENSE3_FUN_IE_W<SENSOR_PADS_SPEC> {
         SENSE3_FUN_IE_W::new(self, 9)
     }
     #[doc = "Bit 10 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_slp_ie(&mut self) -> SENSE3_SLP_IE_W<SENSOR_PADS_SPEC> {
         SENSE3_SLP_IE_W::new(self, 10)
     }
     #[doc = "Bit 11 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_slp_sel(&mut self) -> SENSE3_SLP_SEL_W<SENSOR_PADS_SPEC> {
         SENSE3_SLP_SEL_W::new(self, 11)
     }
     #[doc = "Bits 12:13 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_fun_sel(&mut self) -> SENSE3_FUN_SEL_W<SENSOR_PADS_SPEC> {
         SENSE3_FUN_SEL_W::new(self, 12)
     }
     #[doc = "Bit 14 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_fun_ie(&mut self) -> SENSE2_FUN_IE_W<SENSOR_PADS_SPEC> {
         SENSE2_FUN_IE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_slp_ie(&mut self) -> SENSE2_SLP_IE_W<SENSOR_PADS_SPEC> {
         SENSE2_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_slp_sel(&mut self) -> SENSE2_SLP_SEL_W<SENSOR_PADS_SPEC> {
         SENSE2_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_fun_sel(&mut self) -> SENSE2_FUN_SEL_W<SENSOR_PADS_SPEC> {
         SENSE2_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_fun_ie(&mut self) -> SENSE1_FUN_IE_W<SENSOR_PADS_SPEC> {
         SENSE1_FUN_IE_W::new(self, 19)
     }
     #[doc = "Bit 20 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_slp_ie(&mut self) -> SENSE1_SLP_IE_W<SENSOR_PADS_SPEC> {
         SENSE1_SLP_IE_W::new(self, 20)
     }
     #[doc = "Bit 21 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_slp_sel(&mut self) -> SENSE1_SLP_SEL_W<SENSOR_PADS_SPEC> {
         SENSE1_SLP_SEL_W::new(self, 21)
     }
     #[doc = "Bits 22:23 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_fun_sel(&mut self) -> SENSE1_FUN_SEL_W<SENSOR_PADS_SPEC> {
         SENSE1_FUN_SEL_W::new(self, 22)
     }
     #[doc = "Bit 24 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_mux_sel(&mut self) -> SENSE4_MUX_SEL_W<SENSOR_PADS_SPEC> {
         SENSE4_MUX_SEL_W::new(self, 24)
     }
     #[doc = "Bit 25 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_mux_sel(&mut self) -> SENSE3_MUX_SEL_W<SENSOR_PADS_SPEC> {
         SENSE3_MUX_SEL_W::new(self, 25)
     }
     #[doc = "Bit 26 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_mux_sel(&mut self) -> SENSE2_MUX_SEL_W<SENSOR_PADS_SPEC> {
         SENSE2_MUX_SEL_W::new(self, 26)
     }
     #[doc = "Bit 27 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_mux_sel(&mut self) -> SENSE1_MUX_SEL_W<SENSOR_PADS_SPEC> {
         SENSE1_MUX_SEL_W::new(self, 27)
     }
     #[doc = "Bit 28 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn sense4_hold(&mut self) -> SENSE4_HOLD_W<SENSOR_PADS_SPEC> {
         SENSE4_HOLD_W::new(self, 28)
     }
     #[doc = "Bit 29 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn sense3_hold(&mut self) -> SENSE3_HOLD_W<SENSOR_PADS_SPEC> {
         SENSE3_HOLD_W::new(self, 29)
     }
     #[doc = "Bit 30 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn sense2_hold(&mut self) -> SENSE2_HOLD_W<SENSOR_PADS_SPEC> {
         SENSE2_HOLD_W::new(self, 30)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn sense1_hold(&mut self) -> SENSE1_HOLD_W<SENSOR_PADS_SPEC> {
         SENSE1_HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/status.rs b/esp32/src/rtc_io/status.rs
index 548ffca081..3edb6da92b 100644
--- a/esp32/src/rtc_io/status.rs
+++ b/esp32/src/rtc_io/status.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 interrupt status"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<STATUS_SPEC> {
         INT_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/status_w1tc.rs b/esp32/src/rtc_io/status_w1tc.rs
index 8652b1702c..b4ccf70bdc 100644
--- a/esp32/src/rtc_io/status_w1tc.rs
+++ b/esp32/src/rtc_io/status_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 interrupt status write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn status_int_w1tc(&mut self) -> STATUS_INT_W1TC_W<STATUS_W1TC_SPEC> {
         STATUS_INT_W1TC_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/status_w1ts.rs b/esp32/src/rtc_io/status_w1ts.rs
index adfd2786de..cf93196c13 100644
--- a/esp32/src/rtc_io/status_w1ts.rs
+++ b/esp32/src/rtc_io/status_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 interrupt status write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn status_int_w1ts(&mut self) -> STATUS_INT_W1TS_W<STATUS_W1TS_SPEC> {
         STATUS_INT_W1TS_W::new(self, 14)
     }
diff --git a/esp32/src/rtc_io/touch_cfg.rs b/esp32/src/rtc_io/touch_cfg.rs
index 5b8cf2eccd..c788f1df6e 100644
--- a/esp32/src/rtc_io/touch_cfg.rs
+++ b/esp32/src/rtc_io/touch_cfg.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 23:24 - touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_dcur(&mut self) -> TOUCH_DCUR_W<TOUCH_CFG_SPEC> {
         TOUCH_DCUR_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - touch sensor saw wave voltage range."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drange(&mut self) -> TOUCH_DRANGE_W<TOUCH_CFG_SPEC> {
         TOUCH_DRANGE_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - touch sensor saw wave bottom voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefl(&mut self) -> TOUCH_DREFL_W<TOUCH_CFG_SPEC> {
         TOUCH_DREFL_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - touch sensor saw wave top voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefh(&mut self) -> TOUCH_DREFH_W<TOUCH_CFG_SPEC> {
         TOUCH_DREFH_W::new(self, 29)
     }
     #[doc = "Bit 31 - touch sensor bias power on."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_bias(&mut self) -> TOUCH_XPD_BIAS_W<TOUCH_CFG_SPEC> {
         TOUCH_XPD_BIAS_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad0.rs b/esp32/src/rtc_io/touch_pad0.rs
index 3e174b106c..2ddb2a8ee1 100644
--- a/esp32/src/rtc_io/touch_pad0.rs
+++ b/esp32/src/rtc_io/touch_pad0.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD0_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD0_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD0_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD0_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD0_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD0_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD0_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD0_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD0_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD0_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD0_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD0_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD0_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD0_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD0_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad1.rs b/esp32/src/rtc_io/touch_pad1.rs
index 956972e64c..8b75add873 100644
--- a/esp32/src/rtc_io/touch_pad1.rs
+++ b/esp32/src/rtc_io/touch_pad1.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD1_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD1_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD1_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD1_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD1_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD1_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD1_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD1_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD1_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD1_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD1_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD1_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD1_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD1_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD1_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad2.rs b/esp32/src/rtc_io/touch_pad2.rs
index 8a0cb10bd8..76a6e3820b 100644
--- a/esp32/src/rtc_io/touch_pad2.rs
+++ b/esp32/src/rtc_io/touch_pad2.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD2_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD2_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD2_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD2_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD2_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD2_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD2_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD2_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD2_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD2_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD2_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD2_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD2_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD2_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD2_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad3.rs b/esp32/src/rtc_io/touch_pad3.rs
index 4a1ab35171..e2670394c6 100644
--- a/esp32/src/rtc_io/touch_pad3.rs
+++ b/esp32/src/rtc_io/touch_pad3.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD3_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD3_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD3_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD3_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD3_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD3_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD3_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD3_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD3_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD3_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD3_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD3_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD3_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD3_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD3_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad4.rs b/esp32/src/rtc_io/touch_pad4.rs
index d5d4edbed6..b43ebe5e3b 100644
--- a/esp32/src/rtc_io/touch_pad4.rs
+++ b/esp32/src/rtc_io/touch_pad4.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD4_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD4_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD4_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD4_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD4_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD4_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD4_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD4_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD4_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD4_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD4_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD4_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD4_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD4_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD4_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad5.rs b/esp32/src/rtc_io/touch_pad5.rs
index afeaf48287..886a0011f8 100644
--- a/esp32/src/rtc_io/touch_pad5.rs
+++ b/esp32/src/rtc_io/touch_pad5.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD5_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD5_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD5_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD5_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD5_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD5_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD5_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD5_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD5_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD5_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD5_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD5_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD5_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD5_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD5_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad6.rs b/esp32/src/rtc_io/touch_pad6.rs
index 3697bd1da1..13fa9ebe3d 100644
--- a/esp32/src/rtc_io/touch_pad6.rs
+++ b/esp32/src/rtc_io/touch_pad6.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD6_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD6_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD6_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD6_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD6_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD6_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD6_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD6_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD6_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD6_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD6_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD6_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD6_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD6_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD6_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad7.rs b/esp32/src/rtc_io/touch_pad7.rs
index 9c1f7afd16..850a2babea 100644
--- a/esp32/src/rtc_io/touch_pad7.rs
+++ b/esp32/src/rtc_io/touch_pad7.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD7_SPEC> {
         TO_GPIO_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD7_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD7_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD7_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD7_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD7_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD7_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD7_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD7_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD7_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD7_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD7_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD7_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD7_SPEC> {
         DRV_W::new(self, 29)
     }
     #[doc = "Bit 31 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn hold(&mut self) -> HOLD_W<TOUCH_PAD7_SPEC> {
         HOLD_W::new(self, 31)
     }
diff --git a/esp32/src/rtc_io/touch_pad8.rs b/esp32/src/rtc_io/touch_pad8.rs
index 1e050fe630..cea987a062 100644
--- a/esp32/src/rtc_io/touch_pad8.rs
+++ b/esp32/src/rtc_io/touch_pad8.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 19 - connect the rtc pad input to digital pad input Ó0Ó is availbale"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD8_SPEC> {
         TO_GPIO_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD8_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD8_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD8_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD8_SPEC> {
         DAC_W::new(self, 23)
     }
diff --git a/esp32/src/rtc_io/touch_pad9.rs b/esp32/src/rtc_io/touch_pad9.rs
index 60faa1e482..61f4869502 100644
--- a/esp32/src/rtc_io/touch_pad9.rs
+++ b/esp32/src/rtc_io/touch_pad9.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 19 - connect the rtc pad input to digital pad input Ó0Ó is availbale"]
     #[inline(always)]
-    #[must_use]
     pub fn to_gpio(&mut self) -> TO_GPIO_W<TOUCH_PAD9_SPEC> {
         TO_GPIO_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD9_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - default touch sensor tie option. 0: tie low 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD9_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD9_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - touch sensor slope control. 3-bit for each touch panel default 100."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD9_SPEC> {
         DAC_W::new(self, 23)
     }
diff --git a/esp32/src/rtc_io/xtal_32k_pad.rs b/esp32/src/rtc_io/xtal_32k_pad.rs
index cf35292646..40bf6c225b 100644
--- a/esp32/src/rtc_io/xtal_32k_pad.rs
+++ b/esp32/src/rtc_io/xtal_32k_pad.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:2 - 32K XTAL self-bias reference control."]
     #[inline(always)]
-    #[must_use]
     pub fn dbias_xtal_32k(&mut self) -> DBIAS_XTAL_32K_W<XTAL_32K_PAD_SPEC> {
         DBIAS_XTAL_32K_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - 32K XTAL resistor bias control."]
     #[inline(always)]
-    #[must_use]
     pub fn dres_xtal_32k(&mut self) -> DRES_XTAL_32K_W<XTAL_32K_PAD_SPEC> {
         DRES_XTAL_32K_W::new(self, 3)
     }
     #[doc = "Bit 5 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_ie(&mut self) -> X32P_FUN_IE_W<XTAL_32K_PAD_SPEC> {
         X32P_FUN_IE_W::new(self, 5)
     }
     #[doc = "Bit 6 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_oe(&mut self) -> X32P_SLP_OE_W<XTAL_32K_PAD_SPEC> {
         X32P_SLP_OE_W::new(self, 6)
     }
     #[doc = "Bit 7 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_ie(&mut self) -> X32P_SLP_IE_W<XTAL_32K_PAD_SPEC> {
         X32P_SLP_IE_W::new(self, 7)
     }
     #[doc = "Bit 8 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_sel(&mut self) -> X32P_SLP_SEL_W<XTAL_32K_PAD_SPEC> {
         X32P_SLP_SEL_W::new(self, 8)
     }
     #[doc = "Bits 9:10 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_sel(&mut self) -> X32P_FUN_SEL_W<XTAL_32K_PAD_SPEC> {
         X32P_FUN_SEL_W::new(self, 9)
     }
     #[doc = "Bit 11 - the input enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_ie(&mut self) -> X32N_FUN_IE_W<XTAL_32K_PAD_SPEC> {
         X32N_FUN_IE_W::new(self, 11)
     }
     #[doc = "Bit 12 - the output enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_oe(&mut self) -> X32N_SLP_OE_W<XTAL_32K_PAD_SPEC> {
         X32N_SLP_OE_W::new(self, 12)
     }
     #[doc = "Bit 13 - the input enable of the pad in sleep status"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_ie(&mut self) -> X32N_SLP_IE_W<XTAL_32K_PAD_SPEC> {
         X32N_SLP_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - the sleep status selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_sel(&mut self) -> X32N_SLP_SEL_W<XTAL_32K_PAD_SPEC> {
         X32N_SLP_SEL_W::new(self, 14)
     }
     #[doc = "Bits 15:16 - the functional selection signal of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_sel(&mut self) -> X32N_FUN_SEL_W<XTAL_32K_PAD_SPEC> {
         X32N_FUN_SEL_W::new(self, 15)
     }
     #[doc = "Bit 17 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_mux_sel(&mut self) -> X32P_MUX_SEL_W<XTAL_32K_PAD_SPEC> {
         X32P_MUX_SEL_W::new(self, 17)
     }
     #[doc = "Bit 18 - Ò1Ó select the digital function Ó0Óslection the rtc function"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_mux_sel(&mut self) -> X32N_MUX_SEL_W<XTAL_32K_PAD_SPEC> {
         X32N_MUX_SEL_W::new(self, 18)
     }
     #[doc = "Bit 19 - Power up 32kHz crystal oscillator"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_xtal_32k(&mut self) -> XPD_XTAL_32K_W<XTAL_32K_PAD_SPEC> {
         XPD_XTAL_32K_W::new(self, 19)
     }
     #[doc = "Bits 20:21 - 32K XTAL bias current DAC."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_xtal_32k(&mut self) -> DAC_XTAL_32K_W<XTAL_32K_PAD_SPEC> {
         DAC_XTAL_32K_W::new(self, 20)
     }
     #[doc = "Bit 22 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rue(&mut self) -> X32P_RUE_W<XTAL_32K_PAD_SPEC> {
         X32P_RUE_W::new(self, 22)
     }
     #[doc = "Bit 23 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rde(&mut self) -> X32P_RDE_W<XTAL_32K_PAD_SPEC> {
         X32P_RDE_W::new(self, 23)
     }
     #[doc = "Bit 24 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_hold(&mut self) -> X32P_HOLD_W<XTAL_32K_PAD_SPEC> {
         X32P_HOLD_W::new(self, 24)
     }
     #[doc = "Bits 25:26 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_drv(&mut self) -> X32P_DRV_W<XTAL_32K_PAD_SPEC> {
         X32P_DRV_W::new(self, 25)
     }
     #[doc = "Bit 27 - the pull up enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rue(&mut self) -> X32N_RUE_W<XTAL_32K_PAD_SPEC> {
         X32N_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - the pull down enable of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rde(&mut self) -> X32N_RDE_W<XTAL_32K_PAD_SPEC> {
         X32N_RDE_W::new(self, 28)
     }
     #[doc = "Bit 29 - hold the current value of the output when setting the hold to Ò1Ó"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_hold(&mut self) -> X32N_HOLD_W<XTAL_32K_PAD_SPEC> {
         X32N_HOLD_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - the driver strength of the pad"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_drv(&mut self) -> X32N_DRV_W<XTAL_32K_PAD_SPEC> {
         X32N_DRV_W::new(self, 30)
     }
diff --git a/esp32/src/rtc_io/xtl_ext_ctr.rs b/esp32/src/rtc_io/xtl_ext_ctr.rs
index 2371634c95..5f781de06e 100644
--- a/esp32/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32/src/rtc_io/xtl_ext_ctr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<XTL_EXT_CTR_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32/src/sdhost/blksiz.rs b/esp32/src/sdhost/blksiz.rs
index 7ac50857b9..97a552eab9 100644
--- a/esp32/src/sdhost/blksiz.rs
+++ b/esp32/src/sdhost/blksiz.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Block size."]
     #[inline(always)]
-    #[must_use]
     pub fn block_size(&mut self) -> BLOCK_SIZE_W<BLKSIZ_SPEC> {
         BLOCK_SIZE_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/bmod.rs b/esp32/src/sdhost/bmod.rs
index e2aff690f5..75568d4b2e 100644
--- a/esp32/src/sdhost/bmod.rs
+++ b/esp32/src/sdhost/bmod.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn swr(&mut self) -> SWR_W<BMOD_SPEC> {
         SWR_W::new(self, 0)
     }
     #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
     #[inline(always)]
-    #[must_use]
     pub fn fb(&mut self) -> FB_W<BMOD_SPEC> {
         FB_W::new(self, 1)
     }
     #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn de(&mut self) -> DE_W<BMOD_SPEC> {
         DE_W::new(self, 7)
     }
     #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
     #[inline(always)]
-    #[must_use]
     pub fn pbl(&mut self) -> PBL_W<BMOD_SPEC> {
         PBL_W::new(self, 8)
     }
diff --git a/esp32/src/sdhost/buffifo.rs b/esp32/src/sdhost/buffifo.rs
index 5886f135ca..6ff254e646 100644
--- a/esp32/src/sdhost/buffifo.rs
+++ b/esp32/src/sdhost/buffifo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
     #[inline(always)]
-    #[must_use]
     pub fn buffifo(&mut self) -> BUFFIFO_W<BUFFIFO_SPEC> {
         BUFFIFO_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/bytcnt.rs b/esp32/src/sdhost/bytcnt.rs
index 95bbb226ce..52246a239f 100644
--- a/esp32/src/sdhost/bytcnt.rs
+++ b/esp32/src/sdhost/bytcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_count(&mut self) -> BYTE_COUNT_W<BYTCNT_SPEC> {
         BYTE_COUNT_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/cardthrctl.rs b/esp32/src/sdhost/cardthrctl.rs
index a3a12f56ea..29187b55f5 100644
--- a/esp32/src/sdhost/cardthrctl.rs
+++ b/esp32/src/sdhost/cardthrctl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardrdthren(&mut self) -> CARDRDTHREN_W<CARDTHRCTL_SPEC> {
         CARDRDTHREN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardclrinten(&mut self) -> CARDCLRINTEN_W<CARDTHRCTL_SPEC> {
         CARDCLRINTEN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardwrthren(&mut self) -> CARDWRTHREN_W<CARDTHRCTL_SPEC> {
         CARDWRTHREN_W::new(self, 2)
     }
     #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cardthreshold(&mut self) -> CARDTHRESHOLD_W<CARDTHRCTL_SPEC> {
         CARDTHRESHOLD_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/clk_edge_sel.rs b/esp32/src/sdhost/clk_edge_sel.rs
index 48f2f17cf9..4e0073dbc5 100644
--- a/esp32/src/sdhost/clk_edge_sel.rs
+++ b/esp32/src/sdhost/clk_edge_sel.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_DRV_SEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_SAM_SEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_SLF_SEL_W::new(self, 6)
     }
     #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_H_W::new(self, 9)
     }
     #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_L_W::new(self, 13)
     }
     #[doc = "Bits 17:20 - The value should be equal to CCLKIN_EDGE_L."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_N_W::new(self, 17)
     }
     #[doc = "Bit 21 - Enable esdio mode."]
     #[inline(always)]
-    #[must_use]
     pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<CLK_EDGE_SEL_SPEC> {
         ESDIO_MODE_W::new(self, 21)
     }
     #[doc = "Bit 22 - Enable esd mode."]
     #[inline(always)]
-    #[must_use]
     pub fn esd_mode(&mut self) -> ESD_MODE_W<CLK_EDGE_SEL_SPEC> {
         ESD_MODE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Sdio clock enable"]
     #[inline(always)]
-    #[must_use]
     pub fn cclk_en(&mut self) -> CCLK_EN_W<CLK_EDGE_SEL_SPEC> {
         CCLK_EN_W::new(self, 23)
     }
diff --git a/esp32/src/sdhost/clkdiv.rs b/esp32/src/sdhost/clkdiv.rs
index 6d43304da9..4e556096c2 100644
--- a/esp32/src/sdhost/clkdiv.rs
+++ b/esp32/src/sdhost/clkdiv.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W<CLKDIV_SPEC> {
         CLK_DIVIDER0_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider1(&mut self) -> CLK_DIVIDER1_W<CLKDIV_SPEC> {
         CLK_DIVIDER1_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider2(&mut self) -> CLK_DIVIDER2_W<CLKDIV_SPEC> {
         CLK_DIVIDER2_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider3(&mut self) -> CLK_DIVIDER3_W<CLKDIV_SPEC> {
         CLK_DIVIDER3_W::new(self, 24)
     }
diff --git a/esp32/src/sdhost/clkena.rs b/esp32/src/sdhost/clkena.rs
index 8ea549e305..38637db020 100644
--- a/esp32/src/sdhost/clkena.rs
+++ b/esp32/src/sdhost/clkena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cclk_enable(&mut self) -> CCLK_ENABLE_W<CLKENA_SPEC> {
         CCLK_ENABLE_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn lp_enable(&mut self) -> LP_ENABLE_W<CLKENA_SPEC> {
         LP_ENABLE_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/clksrc.rs b/esp32/src/sdhost/clksrc.rs
index 291b8b4cce..6065175aa7 100644
--- a/esp32/src/sdhost/clksrc.rs
+++ b/esp32/src/sdhost/clksrc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
     #[inline(always)]
-    #[must_use]
     pub fn clksrc(&mut self) -> CLKSRC_W<CLKSRC_SPEC> {
         CLKSRC_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/cmd.rs b/esp32/src/sdhost/cmd.rs
index fde61df83d..5fee890900 100644
--- a/esp32/src/sdhost/cmd.rs
+++ b/esp32/src/sdhost/cmd.rs
@@ -34,9 +34,9 @@ pub type TRANSFER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type SEND_AUTO_STOP_R = crate::BitReader;
 #[doc = "Field `SEND_AUTO_STOP` writer - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
 pub type SEND_AUTO_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
 pub type WAIT_PRVDATA_COMPLETE_R = crate::BitReader;
-#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
 pub type WAIT_PRVDATA_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `STOP_ABORT_CMD` reader - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
 pub type STOP_ABORT_CMD_R = crate::BitReader;
@@ -111,7 +111,7 @@ impl R {
     pub fn send_auto_stop(&self) -> SEND_AUTO_STOP_R {
         SEND_AUTO_STOP_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
     #[inline(always)]
     pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETE_R {
         WAIT_PRVDATA_COMPLETE_R::new(((self.bits >> 13) & 1) != 0)
@@ -187,103 +187,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Command index."]
     #[inline(always)]
-    #[must_use]
     pub fn index(&mut self) -> INDEX_W<CMD_SPEC> {
         INDEX_W::new(self, 0)
     }
     #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W<CMD_SPEC> {
         RESPONSE_EXPECT_W::new(self, 6)
     }
     #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn response_length(&mut self) -> RESPONSE_LENGTH_W<CMD_SPEC> {
         RESPONSE_LENGTH_W::new(self, 7)
     }
     #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
     #[inline(always)]
-    #[must_use]
     pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W<CMD_SPEC> {
         CHECK_RESPONSE_CRC_W::new(self, 8)
     }
     #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
     #[inline(always)]
-    #[must_use]
     pub fn data_expected(&mut self) -> DATA_EXPECTED_W<CMD_SPEC> {
         DATA_EXPECTED_W::new(self, 9)
     }
     #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn read_write(&mut self) -> READ_WRITE_W<CMD_SPEC> {
         READ_WRITE_W::new(self, 10)
     }
     #[doc = "Bit 11 - Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
     #[inline(always)]
-    #[must_use]
     pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W<CMD_SPEC> {
         TRANSFER_MODE_W::new(self, 11)
     }
     #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W<CMD_SPEC> {
         SEND_AUTO_STOP_W::new(self, 12)
     }
-    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W<CMD_SPEC> {
         WAIT_PRVDATA_COMPLETE_W::new(self, 13)
     }
     #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W<CMD_SPEC> {
         STOP_ABORT_CMD_W::new(self, 14)
     }
     #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
     #[inline(always)]
-    #[must_use]
     pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W<CMD_SPEC> {
         SEND_INITIALIZATION_W::new(self, 15)
     }
     #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn card_number(&mut self) -> CARD_NUMBER_W<CMD_SPEC> {
         CARD_NUMBER_W::new(self, 16)
     }
     #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
     #[inline(always)]
-    #[must_use]
     pub fn update_clock_registers_only(&mut self) -> UPDATE_CLOCK_REGISTERS_ONLY_W<CMD_SPEC> {
         UPDATE_CLOCK_REGISTERS_ONLY_W::new(self, 21)
     }
     #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
     #[inline(always)]
-    #[must_use]
     pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W<CMD_SPEC> {
         READ_CEATA_DEVICE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W<CMD_SPEC> {
         CCS_EXPECTED_W::new(self, 23)
     }
     #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
     #[inline(always)]
-    #[must_use]
     pub fn use_hole(&mut self) -> USE_HOLE_W<CMD_SPEC> {
         USE_HOLE_W::new(self, 29)
     }
     #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
     #[inline(always)]
-    #[must_use]
     pub fn start_cmd(&mut self) -> START_CMD_W<CMD_SPEC> {
         START_CMD_W::new(self, 31)
     }
diff --git a/esp32/src/sdhost/cmdarg.rs b/esp32/src/sdhost/cmdarg.rs
index 9b54253c45..16efa0eb23 100644
--- a/esp32/src/sdhost/cmdarg.rs
+++ b/esp32/src/sdhost/cmdarg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
     #[inline(always)]
-    #[must_use]
     pub fn cmdarg(&mut self) -> CMDARG_W<CMDARG_SPEC> {
         CMDARG_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/ctrl.rs b/esp32/src/sdhost/ctrl.rs
index 188695044f..bdeba0dd0d 100644
--- a/esp32/src/sdhost/ctrl.rs
+++ b/esp32/src/sdhost/ctrl.rs
@@ -117,61 +117,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W<CTRL_SPEC> {
         CONTROLLER_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_reset(&mut self) -> FIFO_RESET_W<CTRL_SPEC> {
         FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_reset(&mut self) -> DMA_RESET_W<CTRL_SPEC> {
         DMA_RESET_W::new(self, 2)
     }
     #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
     #[inline(always)]
-    #[must_use]
     pub fn int_enable(&mut self) -> INT_ENABLE_W<CTRL_SPEC> {
         INT_ENABLE_W::new(self, 4)
     }
     #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
     #[inline(always)]
-    #[must_use]
     pub fn read_wait(&mut self) -> READ_WAIT_W<CTRL_SPEC> {
         READ_WAIT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W<CTRL_SPEC> {
         SEND_IRQ_RESPONSE_W::new(self, 7)
     }
     #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W<CTRL_SPEC> {
         ABORT_READ_DATA_W::new(self, 8)
     }
     #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
     #[inline(always)]
-    #[must_use]
     pub fn send_ccsd(&mut self) -> SEND_CCSD_W<CTRL_SPEC> {
         SEND_CCSD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
     #[inline(always)]
-    #[must_use]
     pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W<CTRL_SPEC> {
         SEND_AUTO_STOP_CCSD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ceata_device_interrupt_status(&mut self) -> CEATA_DEVICE_INTERRUPT_STATUS_W<CTRL_SPEC> {
         CEATA_DEVICE_INTERRUPT_STATUS_W::new(self, 11)
     }
diff --git a/esp32/src/sdhost/ctype.rs b/esp32/src/sdhost/ctype.rs
index 87fd7264c1..626c966262 100644
--- a/esp32/src/sdhost/ctype.rs
+++ b/esp32/src/sdhost/ctype.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn card_width4(&mut self) -> CARD_WIDTH4_W<CTYPE_SPEC> {
         CARD_WIDTH4_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn card_width8(&mut self) -> CARD_WIDTH8_W<CTYPE_SPEC> {
         CARD_WIDTH8_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/dbaddr.rs b/esp32/src/sdhost/dbaddr.rs
index aaf52a61c5..d3c712d63a 100644
--- a/esp32/src/sdhost/dbaddr.rs
+++ b/esp32/src/sdhost/dbaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
     #[inline(always)]
-    #[must_use]
     pub fn dbaddr(&mut self) -> DBADDR_W<DBADDR_SPEC> {
         DBADDR_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/debnce.rs b/esp32/src/sdhost/debnce.rs
index f5664a5673..06e70e3dcd 100644
--- a/esp32/src/sdhost/debnce.rs
+++ b/esp32/src/sdhost/debnce.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
     #[inline(always)]
-    #[must_use]
     pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W<DEBNCE_SPEC> {
         DEBOUNCE_COUNT_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/emmcddr.rs b/esp32/src/sdhost/emmcddr.rs
index 405b5d2739..31ada02122 100644
--- a/esp32/src/sdhost/emmcddr.rs
+++ b/esp32/src/sdhost/emmcddr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn halfstartbit(&mut self) -> HALFSTARTBIT_W<EMMCDDR_SPEC> {
         HALFSTARTBIT_W::new(self, 0)
     }
     #[doc = "Bit 31 - Set 1 to enable HS400 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn hs400_mode(&mut self) -> HS400_MODE_W<EMMCDDR_SPEC> {
         HS400_MODE_W::new(self, 31)
     }
diff --git a/esp32/src/sdhost/enshift.rs b/esp32/src/sdhost/enshift.rs
index bd77802532..3d441e55f7 100644
--- a/esp32/src/sdhost/enshift.rs
+++ b/esp32/src/sdhost/enshift.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_shift(&mut self) -> ENABLE_SHIFT_W<ENSHIFT_SPEC> {
         ENABLE_SHIFT_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/fifoth.rs b/esp32/src/sdhost/fifoth.rs
index 841b6ce6d7..557b69a335 100644
--- a/esp32/src/sdhost/fifoth.rs
+++ b/esp32/src/sdhost/fifoth.rs
@@ -47,19 +47,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wmark(&mut self) -> TX_WMARK_W<FIFOTH_SPEC> {
         TX_WMARK_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wmark(&mut self) -> RX_WMARK_W<FIFOTH_SPEC> {
         RX_WMARK_W::new(self, 16)
     }
     #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_multiple_transaction_size(
         &mut self,
     ) -> DMA_MULTIPLE_TRANSACTION_SIZE_W<FIFOTH_SPEC> {
diff --git a/esp32/src/sdhost/idinten.rs b/esp32/src/sdhost/idinten.rs
index 730c7c8bd1..5c9d873d90 100644
--- a/esp32/src/sdhost/idinten.rs
+++ b/esp32/src/sdhost/idinten.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn ti(&mut self) -> TI_W<IDINTEN_SPEC> {
         TI_W::new(self, 0)
     }
     #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn ri(&mut self) -> RI_W<IDINTEN_SPEC> {
         RI_W::new(self, 1)
     }
     #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe(&mut self) -> FBE_W<IDINTEN_SPEC> {
         FBE_W::new(self, 2)
     }
     #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn du(&mut self) -> DU_W<IDINTEN_SPEC> {
         DU_W::new(self, 4)
     }
     #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
     #[inline(always)]
-    #[must_use]
     pub fn ces(&mut self) -> CES_W<IDINTEN_SPEC> {
         CES_W::new(self, 5)
     }
     #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ni(&mut self) -> NI_W<IDINTEN_SPEC> {
         NI_W::new(self, 8)
     }
     #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ai(&mut self) -> AI_W<IDINTEN_SPEC> {
         AI_W::new(self, 9)
     }
diff --git a/esp32/src/sdhost/idsts.rs b/esp32/src/sdhost/idsts.rs
index fbf3d95fb4..b9ded110b9 100644
--- a/esp32/src/sdhost/idsts.rs
+++ b/esp32/src/sdhost/idsts.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ti(&mut self) -> TI_W<IDSTS_SPEC> {
         TI_W::new(self, 0)
     }
     #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ri(&mut self) -> RI_W<IDSTS_SPEC> {
         RI_W::new(self, 1)
     }
     #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe(&mut self) -> FBE_W<IDSTS_SPEC> {
         FBE_W::new(self, 2)
     }
     #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn du(&mut self) -> DU_W<IDSTS_SPEC> {
         DU_W::new(self, 4)
     }
     #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
     #[inline(always)]
-    #[must_use]
     pub fn ces(&mut self) -> CES_W<IDSTS_SPEC> {
         CES_W::new(self, 5)
     }
     #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn nis(&mut self) -> NIS_W<IDSTS_SPEC> {
         NIS_W::new(self, 8)
     }
     #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ais(&mut self) -> AIS_W<IDSTS_SPEC> {
         AIS_W::new(self, 9)
     }
     #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe_code(&mut self) -> FBE_CODE_W<IDSTS_SPEC> {
         FBE_CODE_W::new(self, 10)
     }
     #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
     #[inline(always)]
-    #[must_use]
     pub fn fsm(&mut self) -> FSM_W<IDSTS_SPEC> {
         FSM_W::new(self, 13)
     }
diff --git a/esp32/src/sdhost/intmask.rs b/esp32/src/sdhost/intmask.rs
index d8f06f1b7b..04af2f6725 100644
--- a/esp32/src/sdhost/intmask.rs
+++ b/esp32/src/sdhost/intmask.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
-    #[must_use]
     pub fn int_mask(&mut self) -> INT_MASK_W<INTMASK_SPEC> {
         INT_MASK_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<INTMASK_SPEC> {
         SDIO_INT_MASK_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/pldmnd.rs b/esp32/src/sdhost/pldmnd.rs
index feb2236b6a..593156e368 100644
--- a/esp32/src/sdhost/pldmnd.rs
+++ b/esp32/src/sdhost/pldmnd.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<PLDMND_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."]
     #[inline(always)]
-    #[must_use]
     pub fn pd(&mut self) -> PD_W<PLDMND_SPEC> {
         PD_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/rintsts.rs b/esp32/src/sdhost/rintsts.rs
index 9bc56751d6..5d6e6f419f 100644
--- a/esp32/src/sdhost/rintsts.rs
+++ b/esp32/src/sdhost/rintsts.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
-    #[must_use]
     pub fn int_status_raw(&mut self) -> INT_STATUS_RAW_W<RINTSTS_SPEC> {
         INT_STATUS_RAW_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_interrupt_raw(&mut self) -> SDIO_INTERRUPT_RAW_W<RINTSTS_SPEC> {
         SDIO_INTERRUPT_RAW_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/rst_n.rs b/esp32/src/sdhost/rst_n.rs
index c9aee83112..b7bcd3f632 100644
--- a/esp32/src/sdhost/rst_n.rs
+++ b/esp32/src/sdhost/rst_n.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
     #[inline(always)]
-    #[must_use]
     pub fn card_reset(&mut self) -> CARD_RESET_W<RST_N_SPEC> {
         CARD_RESET_W::new(self, 0)
     }
diff --git a/esp32/src/sdhost/tmout.rs b/esp32/src/sdhost/tmout.rs
index e8c4de9106..8c443976e0 100644
--- a/esp32/src/sdhost/tmout.rs
+++ b/esp32/src/sdhost/tmout.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
     #[inline(always)]
-    #[must_use]
     pub fn response_timeout(&mut self) -> RESPONSE_TIMEOUT_W<TMOUT_SPEC> {
         RESPONSE_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn data_timeout(&mut self) -> DATA_TIMEOUT_W<TMOUT_SPEC> {
         DATA_TIMEOUT_W::new(self, 8)
     }
diff --git a/esp32/src/sdhost/uhs.rs b/esp32/src/sdhost/uhs.rs
index 7ab87510f3..92f0b1c227 100644
--- a/esp32/src/sdhost/uhs.rs
+++ b/esp32/src/sdhost/uhs.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
     #[inline(always)]
-    #[must_use]
     pub fn ddr(&mut self) -> DDR_W<UHS_SPEC> {
         DDR_W::new(self, 16)
     }
diff --git a/esp32/src/sdhost/usrid.rs b/esp32/src/sdhost/usrid.rs
index 7a0013604a..ca2811794d 100644
--- a/esp32/src/sdhost/usrid.rs
+++ b/esp32/src/sdhost/usrid.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
     #[inline(always)]
-    #[must_use]
     pub fn usrid(&mut self) -> USRID_W<USRID_SPEC> {
         USRID_W::new(self, 0)
     }
diff --git a/esp32/src/sens/sar_atten1.rs b/esp32/src/sens/sar_atten1.rs
index 4ec55683bd..f4a56e0d0b 100644
--- a/esp32/src/sens/sar_atten1.rs
+++ b/esp32/src/sens/sar_atten1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W<SAR_ATTEN1_SPEC> {
         SAR1_ATTEN_W::new(self, 0)
     }
diff --git a/esp32/src/sens/sar_atten2.rs b/esp32/src/sens/sar_atten2.rs
index ac2ea06971..33fdfc3dc9 100644
--- a/esp32/src/sens/sar_atten2.rs
+++ b/esp32/src/sens/sar_atten2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W<SAR_ATTEN2_SPEC> {
         SAR2_ATTEN_W::new(self, 0)
     }
diff --git a/esp32/src/sens/sar_dac_ctrl1.rs b/esp32/src/sens/sar_dac_ctrl1.rs
index 9b4179fdfe..627e3c7756 100644
--- a/esp32/src/sens/sar_dac_ctrl1.rs
+++ b/esp32/src/sens/sar_dac_ctrl1.rs
@@ -14,9 +14,9 @@ pub type SW_TONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type DEBUG_BIT_SEL_R = crate::FieldReader;
 #[doc = "Field `DEBUG_BIT_SEL` writer - "]
 pub type DEBUG_BIT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
-#[doc = "Field `DAC_DIG_FORCE` reader - 1: DAC1 &amp; DAC2 use DMA 0: DAC1 &amp; DAC2 do not use DMA"]
+#[doc = "Field `DAC_DIG_FORCE` reader - 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA"]
 pub type DAC_DIG_FORCE_R = crate::BitReader;
-#[doc = "Field `DAC_DIG_FORCE` writer - 1: DAC1 &amp; DAC2 use DMA 0: DAC1 &amp; DAC2 do not use DMA"]
+#[doc = "Field `DAC_DIG_FORCE` writer - 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA"]
 pub type DAC_DIG_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `DAC_CLK_FORCE_LOW` reader - 1: force PDAC_CLK to low"]
 pub type DAC_CLK_FORCE_LOW_R = crate::BitReader;
@@ -46,7 +46,7 @@ impl R {
     pub fn debug_bit_sel(&self) -> DEBUG_BIT_SEL_R {
         DEBUG_BIT_SEL_R::new(((self.bits >> 17) & 0x1f) as u8)
     }
-    #[doc = "Bit 22 - 1: DAC1 &amp; DAC2 use DMA 0: DAC1 &amp; DAC2 do not use DMA"]
+    #[doc = "Bit 22 - 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA"]
     #[inline(always)]
     pub fn dac_dig_force(&self) -> DAC_DIG_FORCE_R {
         DAC_DIG_FORCE_R::new(((self.bits >> 22) & 1) != 0)
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - frequency step for CW generator can be used to adjust the frequency"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_fstep(&mut self) -> SW_FSTEP_W<SAR_DAC_CTRL1_SPEC> {
         SW_FSTEP_W::new(self, 0)
     }
     #[doc = "Bit 16 - 1: enable CW generator 0: disable CW generator"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_tone_en(&mut self) -> SW_TONE_EN_W<SAR_DAC_CTRL1_SPEC> {
         SW_TONE_EN_W::new(self, 16)
     }
     #[doc = "Bits 17:21"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_bit_sel(&mut self) -> DEBUG_BIT_SEL_W<SAR_DAC_CTRL1_SPEC> {
         DEBUG_BIT_SEL_W::new(self, 17)
     }
-    #[doc = "Bit 22 - 1: DAC1 &amp; DAC2 use DMA 0: DAC1 &amp; DAC2 do not use DMA"]
+    #[doc = "Bit 22 - 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dig_force(&mut self) -> DAC_DIG_FORCE_W<SAR_DAC_CTRL1_SPEC> {
         DAC_DIG_FORCE_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: force PDAC_CLK to low"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_force_low(&mut self) -> DAC_CLK_FORCE_LOW_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_FORCE_LOW_W::new(self, 23)
     }
     #[doc = "Bit 24 - 1: force PDAC_CLK to high"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_force_high(&mut self) -> DAC_CLK_FORCE_HIGH_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_FORCE_HIGH_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: invert PDAC_CLK"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_inv(&mut self) -> DAC_CLK_INV_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_INV_W::new(self, 25)
     }
diff --git a/esp32/src/sens/sar_dac_ctrl2.rs b/esp32/src/sens/sar_dac_ctrl2.rs
index 5a78149b3a..50c4c00d86 100644
--- a/esp32/src/sens/sar_dac_ctrl2.rs
+++ b/esp32/src/sens/sar_dac_ctrl2.rs
@@ -140,7 +140,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_DC1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc(&mut self, n: u8) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -148,13 +147,11 @@ impl W {
     }
     #[doc = "Bits 0:7 - DC offset for DAC1 CW generator"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc1(&mut self) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         DAC_DC_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - DC offset for DAC2 CW generator"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc2(&mut self) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         DAC_DC_W::new(self, 8)
     }
@@ -162,7 +159,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_SCALE1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale(&mut self, n: u8) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -170,13 +166,11 @@ impl W {
     }
     #[doc = "Bits 16:17 - 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale1(&mut self) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         DAC_SCALE_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale2(&mut self) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         DAC_SCALE_W::new(self, 18)
     }
@@ -184,7 +178,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_INV1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv(&mut self, n: u8) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -192,13 +185,11 @@ impl W {
     }
     #[doc = "Bits 20:21 - 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv1(&mut self) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         DAC_INV_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv2(&mut self) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         DAC_INV_W::new(self, 22)
     }
@@ -206,7 +197,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_CW_EN1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en(&mut self, n: u8) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -214,13 +204,11 @@ impl W {
     }
     #[doc = "Bit 24 - 1: to select CW generator as source to PDAC1_DAC\\[7:0\\] 0: to select register reg_pdac1_dac\\[7:0\\] as source to PDAC1_DAC\\[7:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en1(&mut self) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         DAC_CW_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: to select CW generator as source to PDAC2_DAC\\[7:0\\] 0: to select register reg_pdac2_dac\\[7:0\\] as source to PDAC2_DAC\\[7:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en2(&mut self) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         DAC_CW_EN_W::new(self, 25)
     }
diff --git a/esp32/src/sens/sar_i2c_ctrl.rs b/esp32/src/sens/sar_i2c_ctrl.rs
index 99fe68daab..292e9b2df9 100644
--- a/esp32/src/sens/sar_i2c_ctrl.rs
+++ b/esp32/src/sens/sar_i2c_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_CTRL_W::new(self, 0)
     }
     #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_W::new(self, 28)
     }
     #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_FORCE_W::new(self, 29)
     }
diff --git a/esp32/src/sens/sar_meas_ctrl.rs b/esp32/src/sens/sar_meas_ctrl.rs
index 55e66457be..054ce2b333 100644
--- a/esp32/src/sens/sar_meas_ctrl.rs
+++ b/esp32/src/sens/sar_meas_ctrl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W<SAR_MEAS_CTRL_SPEC> {
         XPD_SAR_AMP_FSM_W::new(self, 0)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W<SAR_MEAS_CTRL_SPEC> {
         AMP_RST_FB_FSM_W::new(self, 4)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W<SAR_MEAS_CTRL_SPEC> {
         AMP_SHORT_REF_FSM_W::new(self, 8)
     }
     #[doc = "Bits 12:15"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W<SAR_MEAS_CTRL_SPEC> {
         AMP_SHORT_REF_GND_FSM_W::new(self, 12)
     }
     #[doc = "Bits 16:19"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W<SAR_MEAS_CTRL_SPEC> {
         XPD_SAR_FSM_W::new(self, 16)
     }
     #[doc = "Bits 20:23"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rstb_fsm(&mut self) -> SAR_RSTB_FSM_W<SAR_MEAS_CTRL_SPEC> {
         SAR_RSTB_FSM_W::new(self, 20)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_xpd_wait(&mut self) -> SAR2_XPD_WAIT_W<SAR_MEAS_CTRL_SPEC> {
         SAR2_XPD_WAIT_W::new(self, 24)
     }
diff --git a/esp32/src/sens/sar_meas_ctrl2.rs b/esp32/src/sens/sar_meas_ctrl2.rs
index 1698076558..a262fc313e 100644
--- a/esp32/src/sens/sar_meas_ctrl2.rs
+++ b/esp32/src/sens/sar_meas_ctrl2.rs
@@ -137,37 +137,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W<SAR_MEAS_CTRL2_SPEC> {
         SAR1_DAC_XPD_FSM_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dac_xpd_fsm_idle(&mut self) -> SAR1_DAC_XPD_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         SAR1_DAC_XPD_FSM_IDLE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_amp_fsm_idle(&mut self) -> XPD_SAR_AMP_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         XPD_SAR_AMP_FSM_IDLE_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_fsm_idle(&mut self) -> AMP_RST_FB_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         AMP_RST_FB_FSM_IDLE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_fsm_idle(&mut self) -> AMP_SHORT_REF_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         AMP_SHORT_REF_FSM_IDLE_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_fsm_idle(
         &mut self,
     ) -> AMP_SHORT_REF_GND_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
@@ -175,37 +169,31 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_fsm_idle(&mut self) -> XPD_SAR_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         XPD_SAR_FSM_IDLE_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W<SAR_MEAS_CTRL2_SPEC> {
         SAR_RSTB_FSM_IDLE_W::new(self, 10)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rstb_force(&mut self) -> SAR2_RSTB_FORCE_W<SAR_MEAS_CTRL2_SPEC> {
         SAR2_RSTB_FORCE_W::new(self, 11)
     }
     #[doc = "Bits 13:14"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W<SAR_MEAS_CTRL2_SPEC> {
         AMP_RST_FB_FORCE_W::new(self, 13)
     }
     #[doc = "Bits 15:16"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W<SAR_MEAS_CTRL2_SPEC> {
         AMP_SHORT_REF_FORCE_W::new(self, 15)
     }
     #[doc = "Bits 17:18"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W<SAR_MEAS_CTRL2_SPEC> {
         AMP_SHORT_REF_GND_FORCE_W::new(self, 17)
     }
diff --git a/esp32/src/sens/sar_meas_start1.rs b/esp32/src/sens/sar_meas_start1.rs
index cd94f4bd81..ccd900535f 100644
--- a/esp32/src/sens/sar_meas_start1.rs
+++ b/esp32/src/sens/sar_meas_start1.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W<SAR_MEAS_START1_SPEC> {
         MEAS1_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W<SAR_MEAS_START1_SPEC> {
         MEAS1_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W<SAR_MEAS_START1_SPEC> {
         SAR1_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W<SAR_MEAS_START1_SPEC> {
         SAR1_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32/src/sens/sar_meas_start2.rs b/esp32/src/sens/sar_meas_start2.rs
index cfc115d772..94781bba03 100644
--- a/esp32/src/sens/sar_meas_start2.rs
+++ b/esp32/src/sens/sar_meas_start2.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W<SAR_MEAS_START2_SPEC> {
         MEAS2_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W<SAR_MEAS_START2_SPEC> {
         MEAS2_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W<SAR_MEAS_START2_SPEC> {
         SAR2_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W<SAR_MEAS_START2_SPEC> {
         SAR2_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32/src/sens/sar_meas_wait1.rs b/esp32/src/sens/sar_meas_wait1.rs
index 22b06be1ad..1abe323684 100644
--- a/esp32/src/sens/sar_meas_wait1.rs
+++ b/esp32/src/sens/sar_meas_wait1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W<SAR_MEAS_WAIT1_SPEC> {
         SAR_AMP_WAIT1_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W<SAR_MEAS_WAIT1_SPEC> {
         SAR_AMP_WAIT2_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_meas_wait2.rs b/esp32/src/sens/sar_meas_wait2.rs
index c0f011cc60..717df43c1e 100644
--- a/esp32/src/sens/sar_meas_wait2.rs
+++ b/esp32/src/sens/sar_meas_wait2.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_sar_sw(&mut self) -> FORCE_XPD_SAR_SW_W<SAR_MEAS_WAIT2_SPEC> {
         FORCE_XPD_SAR_SW_W::new(self, 0)
     }
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W<SAR_MEAS_WAIT2_SPEC> {
         SAR_AMP_WAIT3_W::new(self, 0)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W<SAR_MEAS_WAIT2_SPEC> {
         FORCE_XPD_AMP_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_sar(&mut self) -> FORCE_XPD_SAR_W<SAR_MEAS_WAIT2_SPEC> {
         FORCE_XPD_SAR_W::new(self, 18)
     }
     #[doc = "Bits 20:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rstb_wait(&mut self) -> SAR2_RSTB_WAIT_W<SAR_MEAS_WAIT2_SPEC> {
         SAR2_RSTB_WAIT_W::new(self, 20)
     }
diff --git a/esp32/src/sens/sar_mem_wr_ctrl.rs b/esp32/src/sens/sar_mem_wr_ctrl.rs
index 25bef08c19..9ea60f131a 100644
--- a/esp32/src/sens/sar_mem_wr_ctrl.rs
+++ b/esp32/src/sens/sar_mem_wr_ctrl.rs
@@ -36,19 +36,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_wr_addr_init(&mut self) -> MEM_WR_ADDR_INIT_W<SAR_MEM_WR_CTRL_SPEC> {
         MEM_WR_ADDR_INIT_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_wr_addr_size(&mut self) -> MEM_WR_ADDR_SIZE_W<SAR_MEM_WR_CTRL_SPEC> {
         MEM_WR_ADDR_SIZE_W::new(self, 11)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_wr_offst_clr(&mut self) -> RTC_MEM_WR_OFFST_CLR_W<SAR_MEM_WR_CTRL_SPEC> {
         RTC_MEM_WR_OFFST_CLR_W::new(self, 22)
     }
diff --git a/esp32/src/sens/sar_nouse.rs b/esp32/src/sens/sar_nouse.rs
index d10e4a24f1..acce7f4c80 100644
--- a/esp32/src/sens/sar_nouse.rs
+++ b/esp32/src/sens/sar_nouse.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_nouse(&mut self) -> SAR_NOUSE_W<SAR_NOUSE_SPEC> {
         SAR_NOUSE_W::new(self, 0)
     }
diff --git a/esp32/src/sens/sar_read_ctrl.rs b/esp32/src/sens/sar_read_ctrl.rs
index a635774396..a40e1cf521 100644
--- a/esp32/src/sens/sar_read_ctrl.rs
+++ b/esp32/src/sens/sar_read_ctrl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_clk_div(&mut self) -> SAR1_CLK_DIV_W<SAR_READ_CTRL_SPEC> {
         SAR1_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - sample cycles for SAR ADC1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_sample_cycle(&mut self) -> SAR1_SAMPLE_CYCLE_W<SAR_READ_CTRL_SPEC> {
         SAR1_SAMPLE_CYCLE_W::new(self, 8)
     }
     #[doc = "Bits 16:17 - 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_sample_bit(&mut self) -> SAR1_SAMPLE_BIT_W<SAR_READ_CTRL_SPEC> {
         SAR1_SAMPLE_BIT_W::new(self, 16)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_clk_gated(&mut self) -> SAR1_CLK_GATED_W<SAR_READ_CTRL_SPEC> {
         SAR1_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_sample_num(&mut self) -> SAR1_SAMPLE_NUM_W<SAR_READ_CTRL_SPEC> {
         SAR1_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 27 - 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W<SAR_READ_CTRL_SPEC> {
         SAR1_DIG_FORCE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Invert SAR ADC1 data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_data_inv(&mut self) -> SAR1_DATA_INV_W<SAR_READ_CTRL_SPEC> {
         SAR1_DATA_INV_W::new(self, 28)
     }
diff --git a/esp32/src/sens/sar_read_ctrl2.rs b/esp32/src/sens/sar_read_ctrl2.rs
index 5f1244a559..e678ed68a8 100644
--- a/esp32/src/sens/sar_read_ctrl2.rs
+++ b/esp32/src/sens/sar_read_ctrl2.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_clk_div(&mut self) -> SAR2_CLK_DIV_W<SAR_READ_CTRL2_SPEC> {
         SAR2_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - sample cycles for SAR ADC2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_sample_cycle(&mut self) -> SAR2_SAMPLE_CYCLE_W<SAR_READ_CTRL2_SPEC> {
         SAR2_SAMPLE_CYCLE_W::new(self, 8)
     }
     #[doc = "Bits 16:17 - 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_sample_bit(&mut self) -> SAR2_SAMPLE_BIT_W<SAR_READ_CTRL2_SPEC> {
         SAR2_SAMPLE_BIT_W::new(self, 16)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_clk_gated(&mut self) -> SAR2_CLK_GATED_W<SAR_READ_CTRL2_SPEC> {
         SAR2_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_sample_num(&mut self) -> SAR2_SAMPLE_NUM_W<SAR_READ_CTRL2_SPEC> {
         SAR2_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_force(&mut self) -> SAR2_PWDET_FORCE_W<SAR_READ_CTRL2_SPEC> {
         SAR2_PWDET_FORCE_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_dig_force(&mut self) -> SAR2_DIG_FORCE_W<SAR_READ_CTRL2_SPEC> {
         SAR2_DIG_FORCE_W::new(self, 28)
     }
     #[doc = "Bit 29 - Invert SAR ADC2 data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_data_inv(&mut self) -> SAR2_DATA_INV_W<SAR_READ_CTRL2_SPEC> {
         SAR2_DATA_INV_W::new(self, 29)
     }
diff --git a/esp32/src/sens/sar_slave_addr1.rs b/esp32/src/sens/sar_slave_addr1.rs
index 0625e4de48..e2c0fc06a1 100644
--- a/esp32/src/sens/sar_slave_addr1.rs
+++ b/esp32/src/sens/sar_slave_addr1.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr1(&mut self) -> I2C_SLAVE_ADDR1_W<SAR_SLAVE_ADDR1_SPEC> {
         I2C_SLAVE_ADDR1_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr0(&mut self) -> I2C_SLAVE_ADDR0_W<SAR_SLAVE_ADDR1_SPEC> {
         I2C_SLAVE_ADDR0_W::new(self, 11)
     }
diff --git a/esp32/src/sens/sar_slave_addr2.rs b/esp32/src/sens/sar_slave_addr2.rs
index d9bc0bda1f..ccb924f77c 100644
--- a/esp32/src/sens/sar_slave_addr2.rs
+++ b/esp32/src/sens/sar_slave_addr2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr3(&mut self) -> I2C_SLAVE_ADDR3_W<SAR_SLAVE_ADDR2_SPEC> {
         I2C_SLAVE_ADDR3_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr2(&mut self) -> I2C_SLAVE_ADDR2_W<SAR_SLAVE_ADDR2_SPEC> {
         I2C_SLAVE_ADDR2_W::new(self, 11)
     }
diff --git a/esp32/src/sens/sar_slave_addr3.rs b/esp32/src/sens/sar_slave_addr3.rs
index 72cf436527..327d0ac750 100644
--- a/esp32/src/sens/sar_slave_addr3.rs
+++ b/esp32/src/sens/sar_slave_addr3.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr5(&mut self) -> I2C_SLAVE_ADDR5_W<SAR_SLAVE_ADDR3_SPEC> {
         I2C_SLAVE_ADDR5_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr4(&mut self) -> I2C_SLAVE_ADDR4_W<SAR_SLAVE_ADDR3_SPEC> {
         I2C_SLAVE_ADDR4_W::new(self, 11)
     }
diff --git a/esp32/src/sens/sar_slave_addr4.rs b/esp32/src/sens/sar_slave_addr4.rs
index 4291ad3ddc..384d356e5d 100644
--- a/esp32/src/sens/sar_slave_addr4.rs
+++ b/esp32/src/sens/sar_slave_addr4.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr7(&mut self) -> I2C_SLAVE_ADDR7_W<SAR_SLAVE_ADDR4_SPEC> {
         I2C_SLAVE_ADDR7_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr6(&mut self) -> I2C_SLAVE_ADDR6_W<SAR_SLAVE_ADDR4_SPEC> {
         I2C_SLAVE_ADDR6_W::new(self, 11)
     }
diff --git a/esp32/src/sens/sar_start_force.rs b/esp32/src/sens/sar_start_force.rs
index 1254c80810..b74088d2a4 100644
--- a/esp32/src/sens/sar_start_force.rs
+++ b/esp32/src/sens/sar_start_force.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_bit_width(&mut self) -> SAR1_BIT_WIDTH_W<SAR_START_FORCE_SPEC> {
         SAR1_BIT_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_bit_width(&mut self) -> SAR2_BIT_WIDTH_W<SAR_START_FORCE_SPEC> {
         SAR2_BIT_WIDTH_W::new(self, 2)
     }
     #[doc = "Bit 4 - SAR2_EN_TEST only active when reg_sar2_dig_force = 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_test(&mut self) -> SAR2_EN_TEST_W<SAR_START_FORCE_SPEC> {
         SAR2_EN_TEST_W::new(self, 4)
     }
     #[doc = "Bits 5:7 - SAR2_PWDET_CCT PA power detector capacitance tuning."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<SAR_START_FORCE_SPEC> {
         SAR2_PWDET_CCT_W::new(self, 5)
     }
     #[doc = "Bit 8 - 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_force_start_top(&mut self) -> ULP_CP_FORCE_START_TOP_W<SAR_START_FORCE_SPEC> {
         ULP_CP_FORCE_START_TOP_W::new(self, 8)
     }
     #[doc = "Bit 9 - Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_start_top(&mut self) -> ULP_CP_START_TOP_W<SAR_START_FORCE_SPEC> {
         ULP_CP_START_TOP_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sarclk_en(&mut self) -> SARCLK_EN_W<SAR_START_FORCE_SPEC> {
         SARCLK_EN_W::new(self, 10)
     }
     #[doc = "Bits 11:21 - initialized PC for ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn pc_init(&mut self) -> PC_INIT_W<SAR_START_FORCE_SPEC> {
         PC_INIT_W::new(self, 11)
     }
     #[doc = "Bit 22 - stop SAR ADC2 conversion"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_stop(&mut self) -> SAR2_STOP_W<SAR_START_FORCE_SPEC> {
         SAR2_STOP_W::new(self, 22)
     }
     #[doc = "Bit 23 - stop SAR ADC1 conversion"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_stop(&mut self) -> SAR1_STOP_W<SAR_START_FORCE_SPEC> {
         SAR1_STOP_W::new(self, 23)
     }
     #[doc = "Bit 24 - N/A"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_en(&mut self) -> SAR2_PWDET_EN_W<SAR_START_FORCE_SPEC> {
         SAR2_PWDET_EN_W::new(self, 24)
     }
diff --git a/esp32/src/sens/sar_touch_ctrl1.rs b/esp32/src/sens/sar_touch_ctrl1.rs
index ddefc40851..d1f46d77c3 100644
--- a/esp32/src/sens/sar_touch_ctrl1.rs
+++ b/esp32/src/sens/sar_touch_ctrl1.rs
@@ -14,9 +14,9 @@ pub type TOUCH_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 pub type TOUCH_OUT_SEL_R = crate::BitReader;
 #[doc = "Field `TOUCH_OUT_SEL` writer - 1: when the counter is greater then the threshold the touch pad is considered as \"touched\" 0: when the counter is less than the threshold the touch pad is considered as \"touched\""]
 pub type TOUCH_OUT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TOUCH_OUT_1EN` reader - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 &amp; SET2 is both \"touched\""]
+#[doc = "Field `TOUCH_OUT_1EN` reader - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 & SET2 is both \"touched\""]
 pub type TOUCH_OUT_1EN_R = crate::BitReader;
-#[doc = "Field `TOUCH_OUT_1EN` writer - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 &amp; SET2 is both \"touched\""]
+#[doc = "Field `TOUCH_OUT_1EN` writer - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 & SET2 is both \"touched\""]
 pub type TOUCH_OUT_1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `XPD_HALL_FORCE` reader - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
 pub type XPD_HALL_FORCE_R = crate::BitReader;
@@ -42,7 +42,7 @@ impl R {
     pub fn touch_out_sel(&self) -> TOUCH_OUT_SEL_R {
         TOUCH_OUT_SEL_R::new(((self.bits >> 24) & 1) != 0)
     }
-    #[doc = "Bit 25 - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 &amp; SET2 is both \"touched\""]
+    #[doc = "Bit 25 - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 & SET2 is both \"touched\""]
     #[inline(always)]
     pub fn touch_out_1en(&self) -> TOUCH_OUT_1EN_R {
         TOUCH_OUT_1EN_R::new(((self.bits >> 25) & 1) != 0)
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the meas length (in 8MHz)"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_meas_delay(&mut self) -> TOUCH_MEAS_DELAY_W<SAR_TOUCH_CTRL1_SPEC> {
         TOUCH_MEAS_DELAY_W::new(self, 0)
     }
     #[doc = "Bits 16:23 - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_wait(&mut self) -> TOUCH_XPD_WAIT_W<SAR_TOUCH_CTRL1_SPEC> {
         TOUCH_XPD_WAIT_W::new(self, 16)
     }
     #[doc = "Bit 24 - 1: when the counter is greater then the threshold the touch pad is considered as \"touched\" 0: when the counter is less than the threshold the touch pad is considered as \"touched\""]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_sel(&mut self) -> TOUCH_OUT_SEL_W<SAR_TOUCH_CTRL1_SPEC> {
         TOUCH_OUT_SEL_W::new(self, 24)
     }
-    #[doc = "Bit 25 - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 &amp; SET2 is both \"touched\""]
+    #[doc = "Bit 25 - 1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 & SET2 is both \"touched\""]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_1en(&mut self) -> TOUCH_OUT_1EN_W<SAR_TOUCH_CTRL1_SPEC> {
         TOUCH_OUT_1EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall_force(&mut self) -> XPD_HALL_FORCE_W<SAR_TOUCH_CTRL1_SPEC> {
         XPD_HALL_FORCE_W::new(self, 26)
     }
     #[doc = "Bit 27 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase_force(&mut self) -> HALL_PHASE_FORCE_W<SAR_TOUCH_CTRL1_SPEC> {
         HALL_PHASE_FORCE_W::new(self, 27)
     }
diff --git a/esp32/src/sens/sar_touch_ctrl2.rs b/esp32/src/sens/sar_touch_ctrl2.rs
index 4579854c0e..c54c9af822 100644
--- a/esp32/src/sens/sar_touch_ctrl2.rs
+++ b/esp32/src/sens/sar_touch_ctrl2.rs
@@ -6,9 +6,9 @@ pub type W = crate::W<SAR_TOUCH_CTRL2_SPEC>;
 pub type TOUCH_MEAS_EN_R = crate::FieldReader<u16>;
 #[doc = "Field `TOUCH_MEAS_DONE` reader - fsm set 1 to indicate touch touch meas is done"]
 pub type TOUCH_MEAS_DONE_R = crate::BitReader;
-#[doc = "Field `TOUCH_START_FSM_EN` reader - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &amp; TOUCH_XPD is controlled by registers"]
+#[doc = "Field `TOUCH_START_FSM_EN` reader - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers"]
 pub type TOUCH_START_FSM_EN_R = crate::BitReader;
-#[doc = "Field `TOUCH_START_FSM_EN` writer - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &amp; TOUCH_XPD is controlled by registers"]
+#[doc = "Field `TOUCH_START_FSM_EN` writer - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers"]
 pub type TOUCH_START_FSM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `TOUCH_START_EN` reader - 1: start touch fsm valid when reg_touch_start_force is set"]
 pub type TOUCH_START_EN_R = crate::BitReader;
@@ -35,7 +35,7 @@ impl R {
     pub fn touch_meas_done(&self) -> TOUCH_MEAS_DONE_R {
         TOUCH_MEAS_DONE_R::new(((self.bits >> 10) & 1) != 0)
     }
-    #[doc = "Bit 11 - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &amp; TOUCH_XPD is controlled by registers"]
+    #[doc = "Bit 11 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers"]
     #[inline(always)]
     pub fn touch_start_fsm_en(&self) -> TOUCH_START_FSM_EN_R {
         TOUCH_START_FSM_EN_R::new(((self.bits >> 11) & 1) != 0)
@@ -70,33 +70,28 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bit 11 - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &amp; TOUCH_XPD is controlled by registers"]
+    #[doc = "Bit 11 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_fsm_en(&mut self) -> TOUCH_START_FSM_EN_W<SAR_TOUCH_CTRL2_SPEC> {
         TOUCH_START_FSM_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: start touch fsm valid when reg_touch_start_force is set"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_en(&mut self) -> TOUCH_START_EN_W<SAR_TOUCH_CTRL2_SPEC> {
         TOUCH_START_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: to start touch fsm by SW 0: to start touch fsm by timer"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_force(&mut self) -> TOUCH_START_FORCE_W<SAR_TOUCH_CTRL2_SPEC> {
         TOUCH_START_FORCE_W::new(self, 13)
     }
     #[doc = "Bits 14:29 - sleep cycles for timer"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W<SAR_TOUCH_CTRL2_SPEC> {
         TOUCH_SLEEP_CYCLES_W::new(self, 14)
     }
     #[doc = "Bit 30 - to clear reg_touch_meas_en"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_meas_en_clr(&mut self) -> TOUCH_MEAS_EN_CLR_W<SAR_TOUCH_CTRL2_SPEC> {
         TOUCH_MEAS_EN_CLR_W::new(self, 30)
     }
diff --git a/esp32/src/sens/sar_touch_enable.rs b/esp32/src/sens/sar_touch_enable.rs
index 94e19d95f2..28a955ebb2 100644
--- a/esp32/src/sens/sar_touch_enable.rs
+++ b/esp32/src/sens/sar_touch_enable.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - Bitmap defining the working set during the measurement."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad_worken(&mut self) -> TOUCH_PAD_WORKEN_W<SAR_TOUCH_ENABLE_SPEC> {
         TOUCH_PAD_WORKEN_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - Bitmap defining SET2 for generating wakeup interrupt. SET2 is \"touched\" only if at least one of touch pad in SET2 is \"touched\"."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad_outen2(&mut self) -> TOUCH_PAD_OUTEN2_W<SAR_TOUCH_ENABLE_SPEC> {
         TOUCH_PAD_OUTEN2_W::new(self, 10)
     }
     #[doc = "Bits 20:29 - Bitmap defining SET1 for generating wakeup interrupt. SET1 is \"touched\" only if at least one of touch pad in SET1 is \"touched\"."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad_outen1(&mut self) -> TOUCH_PAD_OUTEN1_W<SAR_TOUCH_ENABLE_SPEC> {
         TOUCH_PAD_OUTEN1_W::new(self, 20)
     }
diff --git a/esp32/src/sens/sar_touch_thres1.rs b/esp32/src/sens/sar_touch_thres1.rs
index befd2264b1..015187485e 100644
--- a/esp32/src/sens/sar_touch_thres1.rs
+++ b/esp32/src/sens/sar_touch_thres1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 1"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th1(&mut self) -> TOUCH_OUT_TH1_W<SAR_TOUCH_THRES1_SPEC> {
         TOUCH_OUT_TH1_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the threshold for touch pad 0"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th0(&mut self) -> TOUCH_OUT_TH0_W<SAR_TOUCH_THRES1_SPEC> {
         TOUCH_OUT_TH0_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_touch_thres2.rs b/esp32/src/sens/sar_touch_thres2.rs
index 0f36714266..5596582999 100644
--- a/esp32/src/sens/sar_touch_thres2.rs
+++ b/esp32/src/sens/sar_touch_thres2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 3"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th3(&mut self) -> TOUCH_OUT_TH3_W<SAR_TOUCH_THRES2_SPEC> {
         TOUCH_OUT_TH3_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the threshold for touch pad 2"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th2(&mut self) -> TOUCH_OUT_TH2_W<SAR_TOUCH_THRES2_SPEC> {
         TOUCH_OUT_TH2_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_touch_thres3.rs b/esp32/src/sens/sar_touch_thres3.rs
index d58cf24a07..7f91ec8c76 100644
--- a/esp32/src/sens/sar_touch_thres3.rs
+++ b/esp32/src/sens/sar_touch_thres3.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 5"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th5(&mut self) -> TOUCH_OUT_TH5_W<SAR_TOUCH_THRES3_SPEC> {
         TOUCH_OUT_TH5_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the threshold for touch pad 4"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th4(&mut self) -> TOUCH_OUT_TH4_W<SAR_TOUCH_THRES3_SPEC> {
         TOUCH_OUT_TH4_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_touch_thres4.rs b/esp32/src/sens/sar_touch_thres4.rs
index 4457723b4b..79d4d67fc5 100644
--- a/esp32/src/sens/sar_touch_thres4.rs
+++ b/esp32/src/sens/sar_touch_thres4.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 7"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th7(&mut self) -> TOUCH_OUT_TH7_W<SAR_TOUCH_THRES4_SPEC> {
         TOUCH_OUT_TH7_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the threshold for touch pad 6"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th6(&mut self) -> TOUCH_OUT_TH6_W<SAR_TOUCH_THRES4_SPEC> {
         TOUCH_OUT_TH6_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_touch_thres5.rs b/esp32/src/sens/sar_touch_thres5.rs
index 529aab0089..b4e3ba7cb6 100644
--- a/esp32/src/sens/sar_touch_thres5.rs
+++ b/esp32/src/sens/sar_touch_thres5.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 9"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th9(&mut self) -> TOUCH_OUT_TH9_W<SAR_TOUCH_THRES5_SPEC> {
         TOUCH_OUT_TH9_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the threshold for touch pad 8"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th8(&mut self) -> TOUCH_OUT_TH8_W<SAR_TOUCH_THRES5_SPEC> {
         TOUCH_OUT_TH8_W::new(self, 16)
     }
diff --git a/esp32/src/sens/sar_tsens_ctrl.rs b/esp32/src/sens/sar_tsens_ctrl.rs
index 49742b5c1b..478ee23da1 100644
--- a/esp32/src/sens/sar_tsens_ctrl.rs
+++ b/esp32/src/sens/sar_tsens_ctrl.rs
@@ -30,9 +30,9 @@ pub type TSENS_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 pub type TSENS_POWER_UP_R = crate::BitReader;
 #[doc = "Field `TSENS_POWER_UP` writer - temperature sensor power up"]
 pub type TSENS_POWER_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TSENS_POWER_UP_FORCE` reader - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+#[doc = "Field `TSENS_POWER_UP_FORCE` reader - 1: dump out & power up controlled by SW 0: by FSM"]
 pub type TSENS_POWER_UP_FORCE_R = crate::BitReader;
-#[doc = "Field `TSENS_POWER_UP_FORCE` writer - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+#[doc = "Field `TSENS_POWER_UP_FORCE` writer - 1: dump out & power up controlled by SW 0: by FSM"]
 pub type TSENS_POWER_UP_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `TSENS_DUMP_OUT` reader - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
 pub type TSENS_DUMP_OUT_R = crate::BitReader;
@@ -74,7 +74,7 @@ impl R {
     pub fn tsens_power_up(&self) -> TSENS_POWER_UP_R {
         TSENS_POWER_UP_R::new(((self.bits >> 24) & 1) != 0)
     }
-    #[doc = "Bit 25 - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+    #[doc = "Bit 25 - 1: dump out & power up controlled by SW 0: by FSM"]
     #[inline(always)]
     pub fn tsens_power_up_force(&self) -> TSENS_POWER_UP_FORCE_R {
         TSENS_POWER_UP_FORCE_R::new(((self.bits >> 25) & 1) != 0)
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_xpd_wait(&mut self) -> TSENS_XPD_WAIT_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_XPD_WAIT_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_xpd_force(&mut self) -> TSENS_XPD_FORCE_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_inv(&mut self) -> TSENS_CLK_INV_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_CLK_INV_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_gated(&mut self) -> TSENS_CLK_GATED_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_CLK_GATED_W::new(self, 14)
     }
     #[doc = "Bit 15 - invert temperature sensor data"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_in_inv(&mut self) -> TSENS_IN_INV_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_IN_INV_W::new(self, 15)
     }
     #[doc = "Bits 16:23 - temperature sensor clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_div(&mut self) -> TSENS_CLK_DIV_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_CLK_DIV_W::new(self, 16)
     }
     #[doc = "Bit 24 - temperature sensor power up"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_power_up(&mut self) -> TSENS_POWER_UP_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_POWER_UP_W::new(self, 24)
     }
-    #[doc = "Bit 25 - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+    #[doc = "Bit 25 - 1: dump out & power up controlled by SW 0: by FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_power_up_force(&mut self) -> TSENS_POWER_UP_FORCE_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_POWER_UP_FORCE_W::new(self, 25)
     }
     #[doc = "Bit 26 - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_dump_out(&mut self) -> TSENS_DUMP_OUT_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_DUMP_OUT_W::new(self, 26)
     }
diff --git a/esp32/src/sens/sardate.rs b/esp32/src/sens/sardate.rs
index 3993392d88..741de76804 100644
--- a/esp32/src/sens/sardate.rs
+++ b/esp32/src/sens/sardate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_date(&mut self) -> SAR_DATE_W<SARDATE_SPEC> {
         SAR_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc0.rs b/esp32/src/sens/ulp_cp_sleep_cyc0.rs
index 708f032f85..db5754611f 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc0.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_cycles_s0(&mut self) -> SLEEP_CYCLES_S0_W<ULP_CP_SLEEP_CYC0_SPEC> {
         SLEEP_CYCLES_S0_W::new(self, 0)
     }
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc1.rs b/esp32/src/sens/ulp_cp_sleep_cyc1.rs
index 3ac0602a23..d55bda0b31 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc1.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_cycles_s1(&mut self) -> SLEEP_CYCLES_S1_W<ULP_CP_SLEEP_CYC1_SPEC> {
         SLEEP_CYCLES_S1_W::new(self, 0)
     }
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc2.rs b/esp32/src/sens/ulp_cp_sleep_cyc2.rs
index 502465b3a0..d5e6f920ce 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc2.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_cycles_s2(&mut self) -> SLEEP_CYCLES_S2_W<ULP_CP_SLEEP_CYC2_SPEC> {
         SLEEP_CYCLES_S2_W::new(self, 0)
     }
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc3.rs b/esp32/src/sens/ulp_cp_sleep_cyc3.rs
index 4a27f1ff36..1d2c921be6 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc3.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_cycles_s3(&mut self) -> SLEEP_CYCLES_S3_W<ULP_CP_SLEEP_CYC3_SPEC> {
         SLEEP_CYCLES_S3_W::new(self, 0)
     }
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc4.rs b/esp32/src/sens/ulp_cp_sleep_cyc4.rs
index cd60fdb811..44cfd4e9dc 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc4.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_cycles_s4(&mut self) -> SLEEP_CYCLES_S4_W<ULP_CP_SLEEP_CYC4_SPEC> {
         SLEEP_CYCLES_S4_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha1_continue.rs b/esp32/src/sha/sha1_continue.rs
index b518cbdabc..59604d8fea 100644
--- a/esp32/src/sha/sha1_continue.rs
+++ b/esp32/src/sha/sha1_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA1_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue the SHA-1 operation with subsequent blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn sha1_continue(&mut self) -> SHA1_CONTINUE_W<SHA1_CONTINUE_SPEC> {
         SHA1_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha1_load.rs b/esp32/src/sha/sha1_load.rs
index de960a7a25..de57f513a5 100644
--- a/esp32/src/sha/sha1_load.rs
+++ b/esp32/src/sha/sha1_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA1_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to finish the SHA-1 operation to calculate the final message hash."]
     #[inline(always)]
-    #[must_use]
     pub fn sha1_load(&mut self) -> SHA1_LOAD_W<SHA1_LOAD_SPEC> {
         SHA1_LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha1_start.rs b/esp32/src/sha/sha1_start.rs
index 9488c280b6..1116c57db1 100644
--- a/esp32/src/sha/sha1_start.rs
+++ b/esp32/src/sha/sha1_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA1_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start an SHA-1 operation on the first message block."]
     #[inline(always)]
-    #[must_use]
     pub fn sha1_start(&mut self) -> SHA1_START_W<SHA1_START_SPEC> {
         SHA1_START_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha256_continue.rs b/esp32/src/sha/sha256_continue.rs
index 6812234e47..58fd83e8ef 100644
--- a/esp32/src/sha/sha256_continue.rs
+++ b/esp32/src/sha/sha256_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA256_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue the SHA-256 operation with subsequent blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn sha256_continue(&mut self) -> SHA256_CONTINUE_W<SHA256_CONTINUE_SPEC> {
         SHA256_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha256_load.rs b/esp32/src/sha/sha256_load.rs
index 66f3b0f1a4..fbef9cdc1b 100644
--- a/esp32/src/sha/sha256_load.rs
+++ b/esp32/src/sha/sha256_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA256_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to finish the SHA-256 operation to calculate the final message hash."]
     #[inline(always)]
-    #[must_use]
     pub fn sha256_load(&mut self) -> SHA256_LOAD_W<SHA256_LOAD_SPEC> {
         SHA256_LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha256_start.rs b/esp32/src/sha/sha256_start.rs
index a31951f101..b42347a677 100644
--- a/esp32/src/sha/sha256_start.rs
+++ b/esp32/src/sha/sha256_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA256_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start an SHA-256 operation on the first message block."]
     #[inline(always)]
-    #[must_use]
     pub fn sha256_start(&mut self) -> SHA256_START_W<SHA256_START_SPEC> {
         SHA256_START_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha384_continue.rs b/esp32/src/sha/sha384_continue.rs
index e3cded8ac1..d009f9babf 100644
--- a/esp32/src/sha/sha384_continue.rs
+++ b/esp32/src/sha/sha384_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA384_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue the SHA-384 operation with subsequent blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn sha384_continue(&mut self) -> SHA384_CONTINUE_W<SHA384_CONTINUE_SPEC> {
         SHA384_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha384_load.rs b/esp32/src/sha/sha384_load.rs
index 112098f96b..75804a09d4 100644
--- a/esp32/src/sha/sha384_load.rs
+++ b/esp32/src/sha/sha384_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA384_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to finish the SHA-384 operation to calculate the final message hash."]
     #[inline(always)]
-    #[must_use]
     pub fn sha384_load(&mut self) -> SHA384_LOAD_W<SHA384_LOAD_SPEC> {
         SHA384_LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha384_start.rs b/esp32/src/sha/sha384_start.rs
index 8536411631..6cb4e92e09 100644
--- a/esp32/src/sha/sha384_start.rs
+++ b/esp32/src/sha/sha384_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA384_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start an SHA-384 operation on the first message block."]
     #[inline(always)]
-    #[must_use]
     pub fn sha384_start(&mut self) -> SHA384_START_W<SHA384_START_SPEC> {
         SHA384_START_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha512_continue.rs b/esp32/src/sha/sha512_continue.rs
index eb998f09d3..26db062a03 100644
--- a/esp32/src/sha/sha512_continue.rs
+++ b/esp32/src/sha/sha512_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA512_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue the SHA-512 operation with subsequent blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn sha512_continue(&mut self) -> SHA512_CONTINUE_W<SHA512_CONTINUE_SPEC> {
         SHA512_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha512_load.rs b/esp32/src/sha/sha512_load.rs
index 719311a84b..dcc015f4f6 100644
--- a/esp32/src/sha/sha512_load.rs
+++ b/esp32/src/sha/sha512_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA512_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to finish the SHA-512 operation to calculate the final message hash."]
     #[inline(always)]
-    #[must_use]
     pub fn sha512_load(&mut self) -> SHA512_LOAD_W<SHA512_LOAD_SPEC> {
         SHA512_LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/sha/sha512_start.rs b/esp32/src/sha/sha512_start.rs
index 5a9c0da307..4a2042d29b 100644
--- a/esp32/src/sha/sha512_start.rs
+++ b/esp32/src/sha/sha512_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SHA512_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start an SHA-512 operation on the first message block."]
     #[inline(always)]
-    #[must_use]
     pub fn sha512_start(&mut self) -> SHA512_START_W<SHA512_START_SPEC> {
         SHA512_START_W::new(self, 0)
     }
diff --git a/esp32/src/sha/text.rs b/esp32/src/sha/text.rs
index 7b5db8bf97..f0c7bfcc17 100644
--- a/esp32/src/sha/text.rs
+++ b/esp32/src/sha/text.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - SHA Message block and hash result register."]
     #[inline(always)]
-    #[must_use]
     pub fn text(&mut self) -> TEXT_W<TEXT_SPEC> {
         TEXT_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_dscr_rec_conf.rs b/esp32/src/slc/_0_dscr_rec_conf.rs
index 1be8d426f1..68b61475a2 100644
--- a/esp32/src/slc/_0_dscr_rec_conf.rs
+++ b/esp32/src/slc/_0_dscr_rec_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_dscr_rec_lim(&mut self) -> SLC0_RX_DSCR_REC_LIM_W<_0_DSCR_REC_CONF_SPEC> {
         SLC0_RX_DSCR_REC_LIM_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_len_conf.rs b/esp32/src/slc/_0_len_conf.rs
index a419b4dd21..05a433634e 100644
--- a/esp32/src/slc/_0_len_conf.rs
+++ b/esp32/src/slc/_0_len_conf.rs
@@ -62,49 +62,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_wdata(&mut self) -> SLC0_LEN_WDATA_W<_0_LEN_CONF_SPEC> {
         SLC0_LEN_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_wr(&mut self) -> SLC0_LEN_WR_W<_0_LEN_CONF_SPEC> {
         SLC0_LEN_WR_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_inc(&mut self) -> SLC0_LEN_INC_W<_0_LEN_CONF_SPEC> {
         SLC0_LEN_INC_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_inc_more(&mut self) -> SLC0_LEN_INC_MORE_W<_0_LEN_CONF_SPEC> {
         SLC0_LEN_INC_MORE_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_packet_load_en(&mut self) -> SLC0_RX_PACKET_LOAD_EN_W<_0_LEN_CONF_SPEC> {
         SLC0_RX_PACKET_LOAD_EN_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_packet_load_en(&mut self) -> SLC0_TX_PACKET_LOAD_EN_W<_0_LEN_CONF_SPEC> {
         SLC0_TX_PACKET_LOAD_EN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_get_used_dscr(&mut self) -> SLC0_RX_GET_USED_DSCR_W<_0_LEN_CONF_SPEC> {
         SLC0_RX_GET_USED_DSCR_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_get_used_dscr(&mut self) -> SLC0_TX_GET_USED_DSCR_W<_0_LEN_CONF_SPEC> {
         SLC0_TX_GET_USED_DSCR_W::new(self, 26)
     }
diff --git a/esp32/src/slc/_0_len_lim_conf.rs b/esp32/src/slc/_0_len_lim_conf.rs
index 474addbd26..088ce87c57 100644
--- a/esp32/src/slc/_0_len_lim_conf.rs
+++ b/esp32/src/slc/_0_len_lim_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_lim(&mut self) -> SLC0_LEN_LIM_W<_0_LEN_LIM_CONF_SPEC> {
         SLC0_LEN_LIM_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_rxpkt_e_dscr.rs b/esp32/src/slc/_0_rxpkt_e_dscr.rs
index ba44fb6521..c32adf19ea 100644
--- a/esp32/src/slc/_0_rxpkt_e_dscr.rs
+++ b/esp32/src/slc/_0_rxpkt_e_dscr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_pkt_e_dscr_addr(&mut self) -> SLC0_RX_PKT_E_DSCR_ADDR_W<_0_RXPKT_E_DSCR_SPEC> {
         SLC0_RX_PKT_E_DSCR_ADDR_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_rxpkt_h_dscr.rs b/esp32/src/slc/_0_rxpkt_h_dscr.rs
index 22716b6b04..ca60689c00 100644
--- a/esp32/src/slc/_0_rxpkt_h_dscr.rs
+++ b/esp32/src/slc/_0_rxpkt_h_dscr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_pkt_h_dscr_addr(&mut self) -> SLC0_RX_PKT_H_DSCR_ADDR_W<_0_RXPKT_H_DSCR_SPEC> {
         SLC0_RX_PKT_H_DSCR_ADDR_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_txpkt_e_dscr.rs b/esp32/src/slc/_0_txpkt_e_dscr.rs
index c33eb60a69..7175428b9a 100644
--- a/esp32/src/slc/_0_txpkt_e_dscr.rs
+++ b/esp32/src/slc/_0_txpkt_e_dscr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_pkt_e_dscr_addr(&mut self) -> SLC0_TX_PKT_E_DSCR_ADDR_W<_0_TXPKT_E_DSCR_SPEC> {
         SLC0_TX_PKT_E_DSCR_ADDR_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0_txpkt_h_dscr.rs b/esp32/src/slc/_0_txpkt_h_dscr.rs
index 15054ae90f..8e38ff0281 100644
--- a/esp32/src/slc/_0_txpkt_h_dscr.rs
+++ b/esp32/src/slc/_0_txpkt_h_dscr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_pkt_h_dscr_addr(&mut self) -> SLC0_TX_PKT_H_DSCR_ADDR_W<_0_TXPKT_H_DSCR_SPEC> {
         SLC0_TX_PKT_H_DSCR_ADDR_W::new(self, 0)
     }
diff --git a/esp32/src/slc/_0int_clr.rs b/esp32/src/slc/_0int_clr.rs
index 6c9523655d..46991c9b7e 100644
--- a/esp32/src/slc/_0int_clr.rs
+++ b/esp32/src/slc/_0int_clr.rs
@@ -63,163 +63,136 @@ impl core::fmt::Debug for crate::generic::Reg<_0INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit0_int_clr(&mut self) -> FRHOST_BIT0_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT0_INT_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit1_int_clr(&mut self) -> FRHOST_BIT1_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT1_INT_CLR_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit2_int_clr(&mut self) -> FRHOST_BIT2_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT2_INT_CLR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit3_int_clr(&mut self) -> FRHOST_BIT3_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT3_INT_CLR_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit4_int_clr(&mut self) -> FRHOST_BIT4_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT4_INT_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit5_int_clr(&mut self) -> FRHOST_BIT5_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT5_INT_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit6_int_clr(&mut self) -> FRHOST_BIT6_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT6_INT_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit7_int_clr(&mut self) -> FRHOST_BIT7_INT_CLR_W<_0INT_CLR_SPEC> {
         FRHOST_BIT7_INT_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_start_int_clr(&mut self) -> SLC0_RX_START_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_START_INT_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_start_int_clr(&mut self) -> SLC0_TX_START_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_START_INT_CLR_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_udf_int_clr(&mut self) -> SLC0_RX_UDF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_UDF_INT_CLR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_ovf_int_clr(&mut self) -> SLC0_TX_OVF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_OVF_INT_CLR_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_1to0_int_clr(&mut self) -> SLC0_TOKEN0_1TO0_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TOKEN0_1TO0_INT_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_1to0_int_clr(&mut self) -> SLC0_TOKEN1_1TO0_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TOKEN1_1TO0_INT_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_done_int_clr(&mut self) -> SLC0_TX_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_DONE_INT_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_suc_eof_int_clr(&mut self) -> SLC0_TX_SUC_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_SUC_EOF_INT_CLR_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_done_int_clr(&mut self) -> SLC0_RX_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_DONE_INT_CLR_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_eof_int_clr(&mut self) -> SLC0_RX_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_EOF_INT_CLR_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tohost_int_clr(&mut self) -> SLC0_TOHOST_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TOHOST_INT_CLR_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_err_int_clr(&mut self) -> SLC0_TX_DSCR_ERR_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_DSCR_ERR_INT_CLR_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_dscr_err_int_clr(&mut self) -> SLC0_RX_DSCR_ERR_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_DSCR_ERR_INT_CLR_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_empty_int_clr(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_DSCR_EMPTY_INT_CLR_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_host_rd_ack_int_clr(&mut self) -> SLC0_HOST_RD_ACK_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_HOST_RD_ACK_INT_CLR_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_wr_retry_done_int_clr(&mut self) -> SLC0_WR_RETRY_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_WR_RETRY_DONE_INT_CLR_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_err_eof_int_clr(&mut self) -> SLC0_TX_ERR_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_TX_ERR_EOF_INT_CLR_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dtc_int_clr(&mut self) -> CMD_DTC_INT_CLR_W<_0INT_CLR_SPEC> {
         CMD_DTC_INT_CLR_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_quick_eof_int_clr(&mut self) -> SLC0_RX_QUICK_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
         SLC0_RX_QUICK_EOF_INT_CLR_W::new(self, 26)
     }
diff --git a/esp32/src/slc/_0int_ena.rs b/esp32/src/slc/_0int_ena.rs
index d3929a9207..0617f36d38 100644
--- a/esp32/src/slc/_0int_ena.rs
+++ b/esp32/src/slc/_0int_ena.rs
@@ -293,163 +293,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit0_int_ena(&mut self) -> FRHOST_BIT0_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT0_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit1_int_ena(&mut self) -> FRHOST_BIT1_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT1_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit2_int_ena(&mut self) -> FRHOST_BIT2_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT2_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit3_int_ena(&mut self) -> FRHOST_BIT3_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT3_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit4_int_ena(&mut self) -> FRHOST_BIT4_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT4_INT_ENA_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit5_int_ena(&mut self) -> FRHOST_BIT5_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT5_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit6_int_ena(&mut self) -> FRHOST_BIT6_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT6_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit7_int_ena(&mut self) -> FRHOST_BIT7_INT_ENA_W<_0INT_ENA_SPEC> {
         FRHOST_BIT7_INT_ENA_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_start_int_ena(&mut self) -> SLC0_RX_START_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_START_INT_ENA_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_start_int_ena(&mut self) -> SLC0_TX_START_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_START_INT_ENA_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_udf_int_ena(&mut self) -> SLC0_RX_UDF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_UDF_INT_ENA_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_ovf_int_ena(&mut self) -> SLC0_TX_OVF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_OVF_INT_ENA_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_1to0_int_ena(&mut self) -> SLC0_TOKEN0_1TO0_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TOKEN0_1TO0_INT_ENA_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_1to0_int_ena(&mut self) -> SLC0_TOKEN1_1TO0_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TOKEN1_1TO0_INT_ENA_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_done_int_ena(&mut self) -> SLC0_TX_DONE_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_DONE_INT_ENA_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_suc_eof_int_ena(&mut self) -> SLC0_TX_SUC_EOF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_SUC_EOF_INT_ENA_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_done_int_ena(&mut self) -> SLC0_RX_DONE_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_DONE_INT_ENA_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_eof_int_ena(&mut self) -> SLC0_RX_EOF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_EOF_INT_ENA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tohost_int_ena(&mut self) -> SLC0_TOHOST_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TOHOST_INT_ENA_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_err_int_ena(&mut self) -> SLC0_TX_DSCR_ERR_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_DSCR_ERR_INT_ENA_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_dscr_err_int_ena(&mut self) -> SLC0_RX_DSCR_ERR_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_DSCR_ERR_INT_ENA_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_empty_int_ena(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_DSCR_EMPTY_INT_ENA_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_host_rd_ack_int_ena(&mut self) -> SLC0_HOST_RD_ACK_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_HOST_RD_ACK_INT_ENA_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_wr_retry_done_int_ena(&mut self) -> SLC0_WR_RETRY_DONE_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_WR_RETRY_DONE_INT_ENA_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_err_eof_int_ena(&mut self) -> SLC0_TX_ERR_EOF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_TX_ERR_EOF_INT_ENA_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dtc_int_ena(&mut self) -> CMD_DTC_INT_ENA_W<_0INT_ENA_SPEC> {
         CMD_DTC_INT_ENA_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_quick_eof_int_ena(&mut self) -> SLC0_RX_QUICK_EOF_INT_ENA_W<_0INT_ENA_SPEC> {
         SLC0_RX_QUICK_EOF_INT_ENA_W::new(self, 26)
     }
diff --git a/esp32/src/slc/_0int_ena1.rs b/esp32/src/slc/_0int_ena1.rs
index cedbf9b1ba..a73d837bf2 100644
--- a/esp32/src/slc/_0int_ena1.rs
+++ b/esp32/src/slc/_0int_ena1.rs
@@ -308,133 +308,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit0_int_ena1(&mut self) -> FRHOST_BIT0_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT0_INT_ENA1_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit1_int_ena1(&mut self) -> FRHOST_BIT1_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT1_INT_ENA1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit2_int_ena1(&mut self) -> FRHOST_BIT2_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT2_INT_ENA1_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit3_int_ena1(&mut self) -> FRHOST_BIT3_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT3_INT_ENA1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit4_int_ena1(&mut self) -> FRHOST_BIT4_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT4_INT_ENA1_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit5_int_ena1(&mut self) -> FRHOST_BIT5_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT5_INT_ENA1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit6_int_ena1(&mut self) -> FRHOST_BIT6_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT6_INT_ENA1_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit7_int_ena1(&mut self) -> FRHOST_BIT7_INT_ENA1_W<_0INT_ENA1_SPEC> {
         FRHOST_BIT7_INT_ENA1_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_start_int_ena1(&mut self) -> SLC0_RX_START_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_START_INT_ENA1_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_start_int_ena1(&mut self) -> SLC0_TX_START_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_START_INT_ENA1_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_udf_int_ena1(&mut self) -> SLC0_RX_UDF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_UDF_INT_ENA1_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_ovf_int_ena1(&mut self) -> SLC0_TX_OVF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_OVF_INT_ENA1_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_1to0_int_ena1(&mut self) -> SLC0_TOKEN0_1TO0_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TOKEN0_1TO0_INT_ENA1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_1to0_int_ena1(&mut self) -> SLC0_TOKEN1_1TO0_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TOKEN1_1TO0_INT_ENA1_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_done_int_ena1(&mut self) -> SLC0_TX_DONE_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_DONE_INT_ENA1_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_suc_eof_int_ena1(&mut self) -> SLC0_TX_SUC_EOF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_SUC_EOF_INT_ENA1_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_done_int_ena1(&mut self) -> SLC0_RX_DONE_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_DONE_INT_ENA1_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_eof_int_ena1(&mut self) -> SLC0_RX_EOF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_EOF_INT_ENA1_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tohost_int_ena1(&mut self) -> SLC0_TOHOST_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TOHOST_INT_ENA1_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_err_int_ena1(&mut self) -> SLC0_TX_DSCR_ERR_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_DSCR_ERR_INT_ENA1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_dscr_err_int_ena1(&mut self) -> SLC0_RX_DSCR_ERR_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_DSCR_ERR_INT_ENA1_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dscr_empty_int_ena1(
         &mut self,
     ) -> SLC0_TX_DSCR_EMPTY_INT_ENA1_W<_0INT_ENA1_SPEC> {
@@ -442,13 +420,11 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_host_rd_ack_int_ena1(&mut self) -> SLC0_HOST_RD_ACK_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_HOST_RD_ACK_INT_ENA1_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_wr_retry_done_int_ena1(
         &mut self,
     ) -> SLC0_WR_RETRY_DONE_INT_ENA1_W<_0INT_ENA1_SPEC> {
@@ -456,19 +432,16 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_err_eof_int_ena1(&mut self) -> SLC0_TX_ERR_EOF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_TX_ERR_EOF_INT_ENA1_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dtc_int_ena1(&mut self) -> CMD_DTC_INT_ENA1_W<_0INT_ENA1_SPEC> {
         CMD_DTC_INT_ENA1_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_quick_eof_int_ena1(&mut self) -> SLC0_RX_QUICK_EOF_INT_ENA1_W<_0INT_ENA1_SPEC> {
         SLC0_RX_QUICK_EOF_INT_ENA1_W::new(self, 26)
     }
diff --git a/esp32/src/slc/_0rx_link.rs b/esp32/src/slc/_0rx_link.rs
index 63446bd7a8..2be82c7b9f 100644
--- a/esp32/src/slc/_0rx_link.rs
+++ b/esp32/src/slc/_0rx_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxlink_addr(&mut self) -> SLC0_RXLINK_ADDR_W<_0RX_LINK_SPEC> {
         SLC0_RXLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxlink_stop(&mut self) -> SLC0_RXLINK_STOP_W<_0RX_LINK_SPEC> {
         SLC0_RXLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxlink_start(&mut self) -> SLC0_RXLINK_START_W<_0RX_LINK_SPEC> {
         SLC0_RXLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxlink_restart(&mut self) -> SLC0_RXLINK_RESTART_W<_0RX_LINK_SPEC> {
         SLC0_RXLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/slc/_0rxfifo_push.rs b/esp32/src/slc/_0rxfifo_push.rs
index 7a86e2f0fc..a48f234a88 100644
--- a/esp32/src/slc/_0rxfifo_push.rs
+++ b/esp32/src/slc/_0rxfifo_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxfifo_wdata(&mut self) -> SLC0_RXFIFO_WDATA_W<_0RXFIFO_PUSH_SPEC> {
         SLC0_RXFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxfifo_push(&mut self) -> SLC0_RXFIFO_PUSH_W<_0RXFIFO_PUSH_SPEC> {
         SLC0_RXFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32/src/slc/_0token0.rs b/esp32/src/slc/_0token0.rs
index 171ad26489..3012ca72a2 100644
--- a/esp32/src/slc/_0token0.rs
+++ b/esp32/src/slc/_0token0.rs
@@ -30,25 +30,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_wdata(&mut self) -> SLC0_TOKEN0_WDATA_W<_0TOKEN0_SPEC> {
         SLC0_TOKEN0_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_wr(&mut self) -> SLC0_TOKEN0_WR_W<_0TOKEN0_SPEC> {
         SLC0_TOKEN0_WR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_inc(&mut self) -> SLC0_TOKEN0_INC_W<_0TOKEN0_SPEC> {
         SLC0_TOKEN0_INC_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token0_inc_more(&mut self) -> SLC0_TOKEN0_INC_MORE_W<_0TOKEN0_SPEC> {
         SLC0_TOKEN0_INC_MORE_W::new(self, 14)
     }
diff --git a/esp32/src/slc/_0token1.rs b/esp32/src/slc/_0token1.rs
index df081035cf..00f6e5fbb6 100644
--- a/esp32/src/slc/_0token1.rs
+++ b/esp32/src/slc/_0token1.rs
@@ -30,25 +30,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_wdata(&mut self) -> SLC0_TOKEN1_WDATA_W<_0TOKEN1_SPEC> {
         SLC0_TOKEN1_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_wr(&mut self) -> SLC0_TOKEN1_WR_W<_0TOKEN1_SPEC> {
         SLC0_TOKEN1_WR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_inc(&mut self) -> SLC0_TOKEN1_INC_W<_0TOKEN1_SPEC> {
         SLC0_TOKEN1_INC_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token1_inc_more(&mut self) -> SLC0_TOKEN1_INC_MORE_W<_0TOKEN1_SPEC> {
         SLC0_TOKEN1_INC_MORE_W::new(self, 14)
     }
diff --git a/esp32/src/slc/_0tx_link.rs b/esp32/src/slc/_0tx_link.rs
index 1fdfc20f43..e02bce39fd 100644
--- a/esp32/src/slc/_0tx_link.rs
+++ b/esp32/src/slc/_0tx_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txlink_addr(&mut self) -> SLC0_TXLINK_ADDR_W<_0TX_LINK_SPEC> {
         SLC0_TXLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txlink_stop(&mut self) -> SLC0_TXLINK_STOP_W<_0TX_LINK_SPEC> {
         SLC0_TXLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txlink_start(&mut self) -> SLC0_TXLINK_START_W<_0TX_LINK_SPEC> {
         SLC0_TXLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txlink_restart(&mut self) -> SLC0_TXLINK_RESTART_W<_0TX_LINK_SPEC> {
         SLC0_TXLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/slc/_0txfifo_pop.rs b/esp32/src/slc/_0txfifo_pop.rs
index 7eafe87f88..ae480ce35d 100644
--- a/esp32/src/slc/_0txfifo_pop.rs
+++ b/esp32/src/slc/_0txfifo_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txfifo_pop(&mut self) -> SLC0_TXFIFO_POP_W<_0TXFIFO_POP_SPEC> {
         SLC0_TXFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32/src/slc/_1int_clr.rs b/esp32/src/slc/_1int_clr.rs
index 8a0e39456b..b95c87e6b9 100644
--- a/esp32/src/slc/_1int_clr.rs
+++ b/esp32/src/slc/_1int_clr.rs
@@ -59,151 +59,126 @@ impl core::fmt::Debug for crate::generic::Reg<_1INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit8_int_clr(&mut self) -> FRHOST_BIT8_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT8_INT_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit9_int_clr(&mut self) -> FRHOST_BIT9_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT9_INT_CLR_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit10_int_clr(&mut self) -> FRHOST_BIT10_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT10_INT_CLR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit11_int_clr(&mut self) -> FRHOST_BIT11_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT11_INT_CLR_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit12_int_clr(&mut self) -> FRHOST_BIT12_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT12_INT_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit13_int_clr(&mut self) -> FRHOST_BIT13_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT13_INT_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit14_int_clr(&mut self) -> FRHOST_BIT14_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT14_INT_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit15_int_clr(&mut self) -> FRHOST_BIT15_INT_CLR_W<_1INT_CLR_SPEC> {
         FRHOST_BIT15_INT_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_start_int_clr(&mut self) -> SLC1_RX_START_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_RX_START_INT_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_start_int_clr(&mut self) -> SLC1_TX_START_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_START_INT_CLR_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_udf_int_clr(&mut self) -> SLC1_RX_UDF_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_RX_UDF_INT_CLR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_ovf_int_clr(&mut self) -> SLC1_TX_OVF_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_OVF_INT_CLR_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_1to0_int_clr(&mut self) -> SLC1_TOKEN0_1TO0_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TOKEN0_1TO0_INT_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_1to0_int_clr(&mut self) -> SLC1_TOKEN1_1TO0_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TOKEN1_1TO0_INT_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_done_int_clr(&mut self) -> SLC1_TX_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_DONE_INT_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_suc_eof_int_clr(&mut self) -> SLC1_TX_SUC_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_SUC_EOF_INT_CLR_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_done_int_clr(&mut self) -> SLC1_RX_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_RX_DONE_INT_CLR_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_eof_int_clr(&mut self) -> SLC1_RX_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_RX_EOF_INT_CLR_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tohost_int_clr(&mut self) -> SLC1_TOHOST_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TOHOST_INT_CLR_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_err_int_clr(&mut self) -> SLC1_TX_DSCR_ERR_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_DSCR_ERR_INT_CLR_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_dscr_err_int_clr(&mut self) -> SLC1_RX_DSCR_ERR_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_RX_DSCR_ERR_INT_CLR_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_empty_int_clr(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_DSCR_EMPTY_INT_CLR_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_host_rd_ack_int_clr(&mut self) -> SLC1_HOST_RD_ACK_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_HOST_RD_ACK_INT_CLR_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_wr_retry_done_int_clr(&mut self) -> SLC1_WR_RETRY_DONE_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_WR_RETRY_DONE_INT_CLR_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_err_eof_int_clr(&mut self) -> SLC1_TX_ERR_EOF_INT_CLR_W<_1INT_CLR_SPEC> {
         SLC1_TX_ERR_EOF_INT_CLR_W::new(self, 24)
     }
diff --git a/esp32/src/slc/_1int_ena.rs b/esp32/src/slc/_1int_ena.rs
index 997e1fd0b7..9243946f13 100644
--- a/esp32/src/slc/_1int_ena.rs
+++ b/esp32/src/slc/_1int_ena.rs
@@ -270,151 +270,126 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit8_int_ena(&mut self) -> FRHOST_BIT8_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT8_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit9_int_ena(&mut self) -> FRHOST_BIT9_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT9_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit10_int_ena(&mut self) -> FRHOST_BIT10_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT10_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit11_int_ena(&mut self) -> FRHOST_BIT11_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT11_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit12_int_ena(&mut self) -> FRHOST_BIT12_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT12_INT_ENA_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit13_int_ena(&mut self) -> FRHOST_BIT13_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT13_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit14_int_ena(&mut self) -> FRHOST_BIT14_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT14_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit15_int_ena(&mut self) -> FRHOST_BIT15_INT_ENA_W<_1INT_ENA_SPEC> {
         FRHOST_BIT15_INT_ENA_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_start_int_ena(&mut self) -> SLC1_RX_START_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_RX_START_INT_ENA_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_start_int_ena(&mut self) -> SLC1_TX_START_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_START_INT_ENA_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_udf_int_ena(&mut self) -> SLC1_RX_UDF_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_RX_UDF_INT_ENA_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_ovf_int_ena(&mut self) -> SLC1_TX_OVF_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_OVF_INT_ENA_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_1to0_int_ena(&mut self) -> SLC1_TOKEN0_1TO0_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TOKEN0_1TO0_INT_ENA_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_1to0_int_ena(&mut self) -> SLC1_TOKEN1_1TO0_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TOKEN1_1TO0_INT_ENA_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_done_int_ena(&mut self) -> SLC1_TX_DONE_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_DONE_INT_ENA_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_suc_eof_int_ena(&mut self) -> SLC1_TX_SUC_EOF_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_SUC_EOF_INT_ENA_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_done_int_ena(&mut self) -> SLC1_RX_DONE_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_RX_DONE_INT_ENA_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_eof_int_ena(&mut self) -> SLC1_RX_EOF_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_RX_EOF_INT_ENA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tohost_int_ena(&mut self) -> SLC1_TOHOST_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TOHOST_INT_ENA_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_err_int_ena(&mut self) -> SLC1_TX_DSCR_ERR_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_DSCR_ERR_INT_ENA_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_dscr_err_int_ena(&mut self) -> SLC1_RX_DSCR_ERR_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_RX_DSCR_ERR_INT_ENA_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_empty_int_ena(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_DSCR_EMPTY_INT_ENA_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_host_rd_ack_int_ena(&mut self) -> SLC1_HOST_RD_ACK_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_HOST_RD_ACK_INT_ENA_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_wr_retry_done_int_ena(&mut self) -> SLC1_WR_RETRY_DONE_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_WR_RETRY_DONE_INT_ENA_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_err_eof_int_ena(&mut self) -> SLC1_TX_ERR_EOF_INT_ENA_W<_1INT_ENA_SPEC> {
         SLC1_TX_ERR_EOF_INT_ENA_W::new(self, 24)
     }
diff --git a/esp32/src/slc/_1int_ena1.rs b/esp32/src/slc/_1int_ena1.rs
index e0d601d4b9..61fad62093 100644
--- a/esp32/src/slc/_1int_ena1.rs
+++ b/esp32/src/slc/_1int_ena1.rs
@@ -285,133 +285,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit8_int_ena1(&mut self) -> FRHOST_BIT8_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT8_INT_ENA1_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit9_int_ena1(&mut self) -> FRHOST_BIT9_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT9_INT_ENA1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit10_int_ena1(&mut self) -> FRHOST_BIT10_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT10_INT_ENA1_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit11_int_ena1(&mut self) -> FRHOST_BIT11_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT11_INT_ENA1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit12_int_ena1(&mut self) -> FRHOST_BIT12_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT12_INT_ENA1_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit13_int_ena1(&mut self) -> FRHOST_BIT13_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT13_INT_ENA1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit14_int_ena1(&mut self) -> FRHOST_BIT14_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT14_INT_ENA1_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn frhost_bit15_int_ena1(&mut self) -> FRHOST_BIT15_INT_ENA1_W<_1INT_ENA1_SPEC> {
         FRHOST_BIT15_INT_ENA1_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_start_int_ena1(&mut self) -> SLC1_RX_START_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_RX_START_INT_ENA1_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_start_int_ena1(&mut self) -> SLC1_TX_START_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_START_INT_ENA1_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_udf_int_ena1(&mut self) -> SLC1_RX_UDF_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_RX_UDF_INT_ENA1_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_ovf_int_ena1(&mut self) -> SLC1_TX_OVF_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_OVF_INT_ENA1_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_1to0_int_ena1(&mut self) -> SLC1_TOKEN0_1TO0_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TOKEN0_1TO0_INT_ENA1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_1to0_int_ena1(&mut self) -> SLC1_TOKEN1_1TO0_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TOKEN1_1TO0_INT_ENA1_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_done_int_ena1(&mut self) -> SLC1_TX_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_DONE_INT_ENA1_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_suc_eof_int_ena1(&mut self) -> SLC1_TX_SUC_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_SUC_EOF_INT_ENA1_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_done_int_ena1(&mut self) -> SLC1_RX_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_RX_DONE_INT_ENA1_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_eof_int_ena1(&mut self) -> SLC1_RX_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_RX_EOF_INT_ENA1_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tohost_int_ena1(&mut self) -> SLC1_TOHOST_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TOHOST_INT_ENA1_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_err_int_ena1(&mut self) -> SLC1_TX_DSCR_ERR_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_DSCR_ERR_INT_ENA1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_dscr_err_int_ena1(&mut self) -> SLC1_RX_DSCR_ERR_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_RX_DSCR_ERR_INT_ENA1_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dscr_empty_int_ena1(
         &mut self,
     ) -> SLC1_TX_DSCR_EMPTY_INT_ENA1_W<_1INT_ENA1_SPEC> {
@@ -419,13 +397,11 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_host_rd_ack_int_ena1(&mut self) -> SLC1_HOST_RD_ACK_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_HOST_RD_ACK_INT_ENA1_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_wr_retry_done_int_ena1(
         &mut self,
     ) -> SLC1_WR_RETRY_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
@@ -433,7 +409,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_err_eof_int_ena1(&mut self) -> SLC1_TX_ERR_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
         SLC1_TX_ERR_EOF_INT_ENA1_W::new(self, 24)
     }
diff --git a/esp32/src/slc/_1rx_link.rs b/esp32/src/slc/_1rx_link.rs
index 60e3d2c58e..d22c4d42ec 100644
--- a/esp32/src/slc/_1rx_link.rs
+++ b/esp32/src/slc/_1rx_link.rs
@@ -72,31 +72,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxlink_addr(&mut self) -> SLC1_RXLINK_ADDR_W<_1RX_LINK_SPEC> {
         SLC1_RXLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_bt_packet(&mut self) -> SLC1_BT_PACKET_W<_1RX_LINK_SPEC> {
         SLC1_BT_PACKET_W::new(self, 20)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxlink_stop(&mut self) -> SLC1_RXLINK_STOP_W<_1RX_LINK_SPEC> {
         SLC1_RXLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxlink_start(&mut self) -> SLC1_RXLINK_START_W<_1RX_LINK_SPEC> {
         SLC1_RXLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxlink_restart(&mut self) -> SLC1_RXLINK_RESTART_W<_1RX_LINK_SPEC> {
         SLC1_RXLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/slc/_1rxfifo_push.rs b/esp32/src/slc/_1rxfifo_push.rs
index 7987e8375f..fcca718c2c 100644
--- a/esp32/src/slc/_1rxfifo_push.rs
+++ b/esp32/src/slc/_1rxfifo_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxfifo_wdata(&mut self) -> SLC1_RXFIFO_WDATA_W<_1RXFIFO_PUSH_SPEC> {
         SLC1_RXFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxfifo_push(&mut self) -> SLC1_RXFIFO_PUSH_W<_1RXFIFO_PUSH_SPEC> {
         SLC1_RXFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32/src/slc/_1token0.rs b/esp32/src/slc/_1token0.rs
index ed08f5c859..ca2e136299 100644
--- a/esp32/src/slc/_1token0.rs
+++ b/esp32/src/slc/_1token0.rs
@@ -30,25 +30,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_wdata(&mut self) -> SLC1_TOKEN0_WDATA_W<_1TOKEN0_SPEC> {
         SLC1_TOKEN0_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_wr(&mut self) -> SLC1_TOKEN0_WR_W<_1TOKEN0_SPEC> {
         SLC1_TOKEN0_WR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_inc(&mut self) -> SLC1_TOKEN0_INC_W<_1TOKEN0_SPEC> {
         SLC1_TOKEN0_INC_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token0_inc_more(&mut self) -> SLC1_TOKEN0_INC_MORE_W<_1TOKEN0_SPEC> {
         SLC1_TOKEN0_INC_MORE_W::new(self, 14)
     }
diff --git a/esp32/src/slc/_1token1.rs b/esp32/src/slc/_1token1.rs
index 6ed4c6f41e..2b114a4a4f 100644
--- a/esp32/src/slc/_1token1.rs
+++ b/esp32/src/slc/_1token1.rs
@@ -30,25 +30,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_wdata(&mut self) -> SLC1_TOKEN1_WDATA_W<_1TOKEN1_SPEC> {
         SLC1_TOKEN1_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_wr(&mut self) -> SLC1_TOKEN1_WR_W<_1TOKEN1_SPEC> {
         SLC1_TOKEN1_WR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_inc(&mut self) -> SLC1_TOKEN1_INC_W<_1TOKEN1_SPEC> {
         SLC1_TOKEN1_INC_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token1_inc_more(&mut self) -> SLC1_TOKEN1_INC_MORE_W<_1TOKEN1_SPEC> {
         SLC1_TOKEN1_INC_MORE_W::new(self, 14)
     }
diff --git a/esp32/src/slc/_1tx_link.rs b/esp32/src/slc/_1tx_link.rs
index 5771a315bb..41c42efc8e 100644
--- a/esp32/src/slc/_1tx_link.rs
+++ b/esp32/src/slc/_1tx_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txlink_addr(&mut self) -> SLC1_TXLINK_ADDR_W<_1TX_LINK_SPEC> {
         SLC1_TXLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txlink_stop(&mut self) -> SLC1_TXLINK_STOP_W<_1TX_LINK_SPEC> {
         SLC1_TXLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txlink_start(&mut self) -> SLC1_TXLINK_START_W<_1TX_LINK_SPEC> {
         SLC1_TXLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txlink_restart(&mut self) -> SLC1_TXLINK_RESTART_W<_1TX_LINK_SPEC> {
         SLC1_TXLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/slc/_1txfifo_pop.rs b/esp32/src/slc/_1txfifo_pop.rs
index a622b82f44..3103749757 100644
--- a/esp32/src/slc/_1txfifo_pop.rs
+++ b/esp32/src/slc/_1txfifo_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txfifo_pop(&mut self) -> SLC1_TXFIFO_POP_W<_1TXFIFO_POP_SPEC> {
         SLC1_TXFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32/src/slc/ahb_test.rs b/esp32/src/slc/ahb_test.rs
index f08e85fc77..6556bb57fa 100644
--- a/esp32/src/slc/ahb_test.rs
+++ b/esp32/src/slc/ahb_test.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
         AHB_TESTMODE_W::new(self, 0)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
         AHB_TESTADDR_W::new(self, 4)
     }
diff --git a/esp32/src/slc/bridge_conf.rs b/esp32/src/slc/bridge_conf.rs
index 5d07b794fb..39d3045c47 100644
--- a/esp32/src/slc/bridge_conf.rs
+++ b/esp32/src/slc/bridge_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn txeof_ena(&mut self) -> TXEOF_ENA_W<BRIDGE_CONF_SPEC> {
         TXEOF_ENA_W::new(self, 0)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_map_ena(&mut self) -> FIFO_MAP_ENA_W<BRIDGE_CONF_SPEC> {
         FIFO_MAP_ENA_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_dummy_mode(&mut self) -> SLC0_TX_DUMMY_MODE_W<BRIDGE_CONF_SPEC> {
         SLC0_TX_DUMMY_MODE_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn hda_map_128k(&mut self) -> HDA_MAP_128K_W<BRIDGE_CONF_SPEC> {
         HDA_MAP_128K_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_dummy_mode(&mut self) -> SLC1_TX_DUMMY_MODE_W<BRIDGE_CONF_SPEC> {
         SLC1_TX_DUMMY_MODE_W::new(self, 14)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_push_idle_num(&mut self) -> TX_PUSH_IDLE_NUM_W<BRIDGE_CONF_SPEC> {
         TX_PUSH_IDLE_NUM_W::new(self, 16)
     }
diff --git a/esp32/src/slc/conf0.rs b/esp32/src/slc/conf0.rs
index 40a3b3c4e8..39807b7470 100644
--- a/esp32/src/slc/conf0.rs
+++ b/esp32/src/slc/conf0.rs
@@ -334,193 +334,161 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_rst(&mut self) -> SLC0_TX_RST_W<CONF0_SPEC> {
         SLC0_TX_RST_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_rst(&mut self) -> SLC0_RX_RST_W<CONF0_SPEC> {
         SLC0_RX_RST_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<CONF0_SPEC> {
         AHBM_FIFO_RST_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<CONF0_SPEC> {
         AHBM_RST_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_loop_test(&mut self) -> SLC0_TX_LOOP_TEST_W<CONF0_SPEC> {
         SLC0_TX_LOOP_TEST_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_loop_test(&mut self) -> SLC0_RX_LOOP_TEST_W<CONF0_SPEC> {
         SLC0_RX_LOOP_TEST_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_auto_wrback(&mut self) -> SLC0_RX_AUTO_WRBACK_W<CONF0_SPEC> {
         SLC0_RX_AUTO_WRBACK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_no_restart_clr(&mut self) -> SLC0_RX_NO_RESTART_CLR_W<CONF0_SPEC> {
         SLC0_RX_NO_RESTART_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxdscr_burst_en(&mut self) -> SLC0_RXDSCR_BURST_EN_W<CONF0_SPEC> {
         SLC0_RXDSCR_BURST_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxdata_burst_en(&mut self) -> SLC0_RXDATA_BURST_EN_W<CONF0_SPEC> {
         SLC0_RXDATA_BURST_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rxlink_auto_ret(&mut self) -> SLC0_RXLINK_AUTO_RET_W<CONF0_SPEC> {
         SLC0_RXLINK_AUTO_RET_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txlink_auto_ret(&mut self) -> SLC0_TXLINK_AUTO_RET_W<CONF0_SPEC> {
         SLC0_TXLINK_AUTO_RET_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txdscr_burst_en(&mut self) -> SLC0_TXDSCR_BURST_EN_W<CONF0_SPEC> {
         SLC0_TXDSCR_BURST_EN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_txdata_burst_en(&mut self) -> SLC0_TXDATA_BURST_EN_W<CONF0_SPEC> {
         SLC0_TXDATA_BURST_EN_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token_auto_clr(&mut self) -> SLC0_TOKEN_AUTO_CLR_W<CONF0_SPEC> {
         SLC0_TOKEN_AUTO_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token_sel(&mut self) -> SLC0_TOKEN_SEL_W<CONF0_SPEC> {
         SLC0_TOKEN_SEL_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_rst(&mut self) -> SLC1_TX_RST_W<CONF0_SPEC> {
         SLC1_TX_RST_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_rst(&mut self) -> SLC1_RX_RST_W<CONF0_SPEC> {
         SLC1_RX_RST_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_wr_retry_mask_en(&mut self) -> SLC0_WR_RETRY_MASK_EN_W<CONF0_SPEC> {
         SLC0_WR_RETRY_MASK_EN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_wr_retry_mask_en(&mut self) -> SLC1_WR_RETRY_MASK_EN_W<CONF0_SPEC> {
         SLC1_WR_RETRY_MASK_EN_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_loop_test(&mut self) -> SLC1_TX_LOOP_TEST_W<CONF0_SPEC> {
         SLC1_TX_LOOP_TEST_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_loop_test(&mut self) -> SLC1_RX_LOOP_TEST_W<CONF0_SPEC> {
         SLC1_RX_LOOP_TEST_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_auto_wrback(&mut self) -> SLC1_RX_AUTO_WRBACK_W<CONF0_SPEC> {
         SLC1_RX_AUTO_WRBACK_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_no_restart_clr(&mut self) -> SLC1_RX_NO_RESTART_CLR_W<CONF0_SPEC> {
         SLC1_RX_NO_RESTART_CLR_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxdscr_burst_en(&mut self) -> SLC1_RXDSCR_BURST_EN_W<CONF0_SPEC> {
         SLC1_RXDSCR_BURST_EN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxdata_burst_en(&mut self) -> SLC1_RXDATA_BURST_EN_W<CONF0_SPEC> {
         SLC1_RXDATA_BURST_EN_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rxlink_auto_ret(&mut self) -> SLC1_RXLINK_AUTO_RET_W<CONF0_SPEC> {
         SLC1_RXLINK_AUTO_RET_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txlink_auto_ret(&mut self) -> SLC1_TXLINK_AUTO_RET_W<CONF0_SPEC> {
         SLC1_TXLINK_AUTO_RET_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txdscr_burst_en(&mut self) -> SLC1_TXDSCR_BURST_EN_W<CONF0_SPEC> {
         SLC1_TXDSCR_BURST_EN_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_txdata_burst_en(&mut self) -> SLC1_TXDATA_BURST_EN_W<CONF0_SPEC> {
         SLC1_TXDATA_BURST_EN_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token_auto_clr(&mut self) -> SLC1_TOKEN_AUTO_CLR_W<CONF0_SPEC> {
         SLC1_TOKEN_AUTO_CLR_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token_sel(&mut self) -> SLC1_TOKEN_SEL_W<CONF0_SPEC> {
         SLC1_TOKEN_SEL_W::new(self, 31)
     }
diff --git a/esp32/src/slc/conf1.rs b/esp32/src/slc/conf1.rs
index 98879cff64..1974eef12e 100644
--- a/esp32/src/slc/conf1.rs
+++ b/esp32/src/slc/conf1.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_check_owner(&mut self) -> SLC0_CHECK_OWNER_W<CONF1_SPEC> {
         SLC0_CHECK_OWNER_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_check_sum_en(&mut self) -> SLC0_TX_CHECK_SUM_EN_W<CONF1_SPEC> {
         SLC0_TX_CHECK_SUM_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_check_sum_en(&mut self) -> SLC0_RX_CHECK_SUM_EN_W<CONF1_SPEC> {
         SLC0_RX_CHECK_SUM_EN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_hold_en(&mut self) -> CMD_HOLD_EN_W<CONF1_SPEC> {
         CMD_HOLD_EN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_len_auto_clr(&mut self) -> SLC0_LEN_AUTO_CLR_W<CONF1_SPEC> {
         SLC0_LEN_AUTO_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tx_stitch_en(&mut self) -> SLC0_TX_STITCH_EN_W<CONF1_SPEC> {
         SLC0_TX_STITCH_EN_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_stitch_en(&mut self) -> SLC0_RX_STITCH_EN_W<CONF1_SPEC> {
         SLC0_RX_STITCH_EN_W::new(self, 6)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_check_owner(&mut self) -> SLC1_CHECK_OWNER_W<CONF1_SPEC> {
         SLC1_CHECK_OWNER_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_check_sum_en(&mut self) -> SLC1_TX_CHECK_SUM_EN_W<CONF1_SPEC> {
         SLC1_TX_CHECK_SUM_EN_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_check_sum_en(&mut self) -> SLC1_RX_CHECK_SUM_EN_W<CONF1_SPEC> {
         SLC1_RX_CHECK_SUM_EN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_int_level_sel(&mut self) -> HOST_INT_LEVEL_SEL_W<CONF1_SPEC> {
         HOST_INT_LEVEL_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tx_stitch_en(&mut self) -> SLC1_TX_STITCH_EN_W<CONF1_SPEC> {
         SLC1_TX_STITCH_EN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_stitch_en(&mut self) -> SLC1_RX_STITCH_EN_W<CONF1_SPEC> {
         SLC1_RX_STITCH_EN_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF1_SPEC> {
         CLK_EN_W::new(self, 22)
     }
diff --git a/esp32/src/slc/date.rs b/esp32/src/slc/date.rs
index 36d5cde3e3..772beba346 100644
--- a/esp32/src/slc/date.rs
+++ b/esp32/src/slc/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/slc/id.rs b/esp32/src/slc/id.rs
index 712ee7ae62..a07140cd13 100644
--- a/esp32/src/slc/id.rs
+++ b/esp32/src/slc/id.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn id(&mut self) -> ID_W<ID_SPEC> {
         ID_W::new(self, 0)
     }
diff --git a/esp32/src/slc/intvec_tohost.rs b/esp32/src/slc/intvec_tohost.rs
index 04c75d6932..165825fff5 100644
--- a/esp32/src/slc/intvec_tohost.rs
+++ b/esp32/src/slc/intvec_tohost.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INTVEC_TOHOST_SPEC> {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_tohost_intvec(&mut self) -> SLC0_TOHOST_INTVEC_W<INTVEC_TOHOST_SPEC> {
         SLC0_TOHOST_INTVEC_W::new(self, 0)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_tohost_intvec(&mut self) -> SLC1_TOHOST_INTVEC_W<INTVEC_TOHOST_SPEC> {
         SLC1_TOHOST_INTVEC_W::new(self, 16)
     }
diff --git a/esp32/src/slc/rx_dscr_conf.rs b/esp32/src/slc/rx_dscr_conf.rs
index fc2deb90af..9e4234b428 100644
--- a/esp32/src/slc/rx_dscr_conf.rs
+++ b/esp32/src/slc/rx_dscr_conf.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_token_no_replace(&mut self) -> SLC0_TOKEN_NO_REPLACE_W<RX_DSCR_CONF_SPEC> {
         SLC0_TOKEN_NO_REPLACE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_infor_no_replace(&mut self) -> SLC0_INFOR_NO_REPLACE_W<RX_DSCR_CONF_SPEC> {
         SLC0_INFOR_NO_REPLACE_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_fill_mode(&mut self) -> SLC0_RX_FILL_MODE_W<RX_DSCR_CONF_SPEC> {
         SLC0_RX_FILL_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_eof_mode(&mut self) -> SLC0_RX_EOF_MODE_W<RX_DSCR_CONF_SPEC> {
         SLC0_RX_EOF_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rx_fill_en(&mut self) -> SLC0_RX_FILL_EN_W<RX_DSCR_CONF_SPEC> {
         SLC0_RX_FILL_EN_W::new(self, 4)
     }
     #[doc = "Bits 5:15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_rd_retry_threshold(&mut self) -> SLC0_RD_RETRY_THRESHOLD_W<RX_DSCR_CONF_SPEC> {
         SLC0_RD_RETRY_THRESHOLD_W::new(self, 5)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_token_no_replace(&mut self) -> SLC1_TOKEN_NO_REPLACE_W<RX_DSCR_CONF_SPEC> {
         SLC1_TOKEN_NO_REPLACE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_infor_no_replace(&mut self) -> SLC1_INFOR_NO_REPLACE_W<RX_DSCR_CONF_SPEC> {
         SLC1_INFOR_NO_REPLACE_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_fill_mode(&mut self) -> SLC1_RX_FILL_MODE_W<RX_DSCR_CONF_SPEC> {
         SLC1_RX_FILL_MODE_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_eof_mode(&mut self) -> SLC1_RX_EOF_MODE_W<RX_DSCR_CONF_SPEC> {
         SLC1_RX_EOF_MODE_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rx_fill_en(&mut self) -> SLC1_RX_FILL_EN_W<RX_DSCR_CONF_SPEC> {
         SLC1_RX_FILL_EN_W::new(self, 20)
     }
     #[doc = "Bits 21:31"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_rd_retry_threshold(&mut self) -> SLC1_RD_RETRY_THRESHOLD_W<RX_DSCR_CONF_SPEC> {
         SLC1_RD_RETRY_THRESHOLD_W::new(self, 21)
     }
diff --git a/esp32/src/slc/sdio_crc_st1.rs b/esp32/src/slc/sdio_crc_st1.rs
index 03e09b7725..7d4d695975 100644
--- a/esp32/src/slc/sdio_crc_st1.rs
+++ b/esp32/src/slc/sdio_crc_st1.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn err_cnt_clr(&mut self) -> ERR_CNT_CLR_W<SDIO_CRC_ST1_SPEC> {
         ERR_CNT_CLR_W::new(self, 31)
     }
diff --git a/esp32/src/slc/seq_position.rs b/esp32/src/slc/seq_position.rs
index b676119340..069974e9ee 100644
--- a/esp32/src/slc/seq_position.rs
+++ b/esp32/src/slc/seq_position.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_seq_position(&mut self) -> SLC0_SEQ_POSITION_W<SEQ_POSITION_SPEC> {
         SLC0_SEQ_POSITION_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_seq_position(&mut self) -> SLC1_SEQ_POSITION_W<SEQ_POSITION_SPEC> {
         SLC1_SEQ_POSITION_W::new(self, 8)
     }
diff --git a/esp32/src/slc/tx_dscr_conf.rs b/esp32/src/slc/tx_dscr_conf.rs
index fe4a0d47e8..80a1d539bd 100644
--- a/esp32/src/slc/tx_dscr_conf.rs
+++ b/esp32/src/slc/tx_dscr_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn wr_retry_threshold(&mut self) -> WR_RETRY_THRESHOLD_W<TX_DSCR_CONF_SPEC> {
         WR_RETRY_THRESHOLD_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slc0host_func1_int_ena.rs b/esp32/src/slchost/host_slc0host_func1_int_ena.rs
index a3752e13f6..8b8a6fc5e5 100644
--- a/esp32/src/slchost/host_slc0host_func1_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_func1_int_ena.rs
@@ -352,7 +352,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -360,7 +359,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -368,7 +366,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -376,7 +373,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -384,7 +380,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -392,7 +387,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -400,7 +394,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -408,7 +401,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -416,7 +408,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -424,7 +415,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -432,7 +422,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -440,7 +429,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -448,7 +436,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -456,7 +443,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -464,7 +450,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0host_rx_start_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0HOST_RX_START_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -472,7 +457,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0host_tx_start_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0HOST_TX_START_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -480,7 +464,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_rx_udf_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_RX_UDF_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -488,7 +471,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_TX_OVF_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -496,7 +478,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -504,7 +485,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_EXT_BIT0_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -512,7 +492,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_EXT_BIT1_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -520,7 +499,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_EXT_BIT2_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -528,7 +506,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_EXT_BIT3_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -536,7 +513,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -544,7 +520,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc0_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
@@ -552,7 +527,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_gpio_sdio_int_ena(
         &mut self,
     ) -> HOST_FN1_GPIO_SDIO_INT_ENA_W<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_func2_int_ena.rs b/esp32/src/slchost/host_slc0host_func2_int_ena.rs
index 39f9993aac..b067a4c35e 100644
--- a/esp32/src/slchost/host_slc0host_func2_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_func2_int_ena.rs
@@ -352,7 +352,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -360,7 +359,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -368,7 +366,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -376,7 +373,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -384,7 +380,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -392,7 +387,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -400,7 +394,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -408,7 +401,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -416,7 +408,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -424,7 +415,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -432,7 +422,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -440,7 +429,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -448,7 +436,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -456,7 +443,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -464,7 +450,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0host_rx_start_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0HOST_RX_START_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -472,7 +457,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0host_tx_start_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0HOST_TX_START_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -480,7 +464,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_rx_udf_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_RX_UDF_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -488,7 +471,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_TX_OVF_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -496,7 +478,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -504,7 +485,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_EXT_BIT0_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -512,7 +492,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_EXT_BIT1_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -520,7 +499,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_EXT_BIT2_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -528,7 +506,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_EXT_BIT3_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -536,7 +513,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -544,7 +520,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc0_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
@@ -552,7 +527,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_gpio_sdio_int_ena(
         &mut self,
     ) -> HOST_FN2_GPIO_SDIO_INT_ENA_W<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_int_clr.rs b/esp32/src/slchost/host_slc0host_int_clr.rs
index b4c4f2132a..a02f751581 100644
--- a/esp32/src/slchost/host_slc0host_int_clr.rs
+++ b/esp32/src/slchost/host_slc0host_int_clr.rs
@@ -61,7 +61,6 @@ impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit0_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT0_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -69,7 +68,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit1_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT1_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -77,7 +75,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit2_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT2_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -85,7 +82,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit3_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT3_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -93,7 +89,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit4_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT4_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -101,7 +96,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit5_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT5_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -109,7 +103,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit6_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT6_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -117,7 +110,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit7_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT7_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -125,7 +117,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_1to0_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_1TO0_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -133,7 +124,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_1to0_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_1TO0_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -141,7 +131,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_0to1_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_0TO1_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -149,7 +138,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_0to1_int_clr(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_0TO1_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -157,7 +145,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_sof_int_clr(
         &mut self,
     ) -> HOST_SLC0HOST_RX_SOF_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -165,7 +152,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_eof_int_clr(
         &mut self,
     ) -> HOST_SLC0HOST_RX_EOF_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -173,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_start_int_clr(
         &mut self,
     ) -> HOST_SLC0HOST_RX_START_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -181,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_tx_start_int_clr(
         &mut self,
     ) -> HOST_SLC0HOST_TX_START_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -189,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_udf_int_clr(
         &mut self,
     ) -> HOST_SLC0_RX_UDF_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -197,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tx_ovf_int_clr(
         &mut self,
     ) -> HOST_SLC0_TX_OVF_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -205,7 +187,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_pf_valid_int_clr(
         &mut self,
     ) -> HOST_SLC0_RX_PF_VALID_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -213,7 +194,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit0_int_clr(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT0_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -221,7 +201,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit1_int_clr(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT1_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -229,7 +208,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit2_int_clr(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT2_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -237,7 +215,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit3_int_clr(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT3_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -245,7 +222,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_new_packet_int_clr(
         &mut self,
     ) -> HOST_SLC0_RX_NEW_PACKET_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -253,7 +229,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_host_rd_retry_int_clr(
         &mut self,
     ) -> HOST_SLC0_HOST_RD_RETRY_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
@@ -261,7 +236,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_gpio_sdio_int_clr(
         &mut self,
     ) -> HOST_GPIO_SDIO_INT_CLR_W<HOST_SLC0HOST_INT_CLR_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_int_ena.rs b/esp32/src/slchost/host_slc0host_int_ena.rs
index c7d19dcef1..9808e4fddb 100644
--- a/esp32/src/slchost/host_slc0host_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_int_ena.rs
@@ -343,7 +343,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT0_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -351,7 +350,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT1_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -359,7 +357,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT2_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -367,7 +364,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT3_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -375,7 +371,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT4_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -383,7 +378,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT5_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -391,7 +385,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT6_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -399,7 +392,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT7_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -407,7 +399,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -415,7 +406,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -423,7 +413,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -431,7 +420,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -439,7 +427,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_SLC0HOST_RX_SOF_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -447,7 +434,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_SLC0HOST_RX_EOF_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -455,7 +441,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_start_int_ena(
         &mut self,
     ) -> HOST_SLC0HOST_RX_START_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -463,7 +448,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_tx_start_int_ena(
         &mut self,
     ) -> HOST_SLC0HOST_TX_START_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -471,7 +455,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_udf_int_ena(
         &mut self,
     ) -> HOST_SLC0_RX_UDF_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -479,7 +462,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_SLC0_TX_OVF_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -487,7 +469,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_SLC0_RX_PF_VALID_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -495,7 +476,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT0_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -503,7 +483,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT1_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -511,7 +490,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT2_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -519,7 +497,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT3_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -527,7 +504,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -535,7 +511,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
@@ -543,7 +518,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_gpio_sdio_int_ena(
         &mut self,
     ) -> HOST_GPIO_SDIO_INT_ENA_W<HOST_SLC0HOST_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_int_ena1.rs b/esp32/src/slchost/host_slc0host_int_ena1.rs
index 4179503eca..f3cf1622cb 100644
--- a/esp32/src/slchost/host_slc0host_int_ena1.rs
+++ b/esp32/src/slchost/host_slc0host_int_ena1.rs
@@ -349,7 +349,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit0_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT0_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -357,7 +356,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit1_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT1_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -365,7 +363,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit2_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT2_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -373,7 +370,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit3_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT3_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -381,7 +377,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit4_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT4_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -389,7 +384,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit5_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT5_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -397,7 +391,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit6_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT6_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -405,7 +398,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tohost_bit7_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOHOST_BIT7_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -413,7 +405,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_1to0_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -421,7 +412,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_1to0_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -429,7 +419,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token0_0to1_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -437,7 +426,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_token1_0to1_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -445,7 +433,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_sof_int_ena1(
         &mut self,
     ) -> HOST_SLC0HOST_RX_SOF_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -453,7 +440,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_eof_int_ena1(
         &mut self,
     ) -> HOST_SLC0HOST_RX_EOF_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -461,7 +447,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_start_int_ena1(
         &mut self,
     ) -> HOST_SLC0HOST_RX_START_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -469,7 +454,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_tx_start_int_ena1(
         &mut self,
     ) -> HOST_SLC0HOST_TX_START_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -477,7 +461,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_udf_int_ena1(
         &mut self,
     ) -> HOST_SLC0_RX_UDF_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -485,7 +468,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_tx_ovf_int_ena1(
         &mut self,
     ) -> HOST_SLC0_TX_OVF_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -493,7 +475,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_pf_valid_int_ena1(
         &mut self,
     ) -> HOST_SLC0_RX_PF_VALID_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -501,7 +482,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit0_int_ena1(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT0_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -509,7 +489,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit1_int_ena1(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT1_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -517,7 +496,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit2_int_ena1(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT2_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -525,7 +503,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_ext_bit3_int_ena1(
         &mut self,
     ) -> HOST_SLC0_EXT_BIT3_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -533,7 +510,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_rx_new_packet_int_ena1(
         &mut self,
     ) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -541,7 +517,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0_host_rd_retry_int_ena1(
         &mut self,
     ) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
@@ -549,7 +524,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_gpio_sdio_int_ena1(
         &mut self,
     ) -> HOST_GPIO_SDIO_INT_ENA1_W<HOST_SLC0HOST_INT_ENA1_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_len_wd.rs b/esp32/src/slchost/host_slc0host_len_wd.rs
index 85c684a0a9..e9213147a1 100644
--- a/esp32/src/slchost/host_slc0host_len_wd.rs
+++ b/esp32/src/slchost/host_slc0host_len_wd.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_len_wd(&mut self) -> HOST_SLC0HOST_LEN_WD_W<HOST_SLC0HOST_LEN_WD_SPEC> {
         HOST_SLC0HOST_LEN_WD_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slc0host_rx_infor.rs b/esp32/src/slchost/host_slc0host_rx_infor.rs
index 4261cb7e2e..326a4b1cdc 100644
--- a/esp32/src/slchost/host_slc0host_rx_infor.rs
+++ b/esp32/src/slchost/host_slc0host_rx_infor.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_rx_infor(
         &mut self,
     ) -> HOST_SLC0HOST_RX_INFOR_W<HOST_SLC0HOST_RX_INFOR_SPEC> {
diff --git a/esp32/src/slchost/host_slc0host_token_wdata.rs b/esp32/src/slchost/host_slc0host_token_wdata.rs
index 1c9c9fb052..c3ba01731d 100644
--- a/esp32/src/slchost/host_slc0host_token_wdata.rs
+++ b/esp32/src/slchost/host_slc0host_token_wdata.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token0_wd(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN0_WD_W<HOST_SLC0HOST_TOKEN_WDATA_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bits 16:27"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token1_wd(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN1_WD_W<HOST_SLC0HOST_TOKEN_WDATA_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_func1_int_ena.rs b/esp32/src/slchost/host_slc1host_func1_int_ena.rs
index af507300df..2bdb5919b6 100644
--- a/esp32/src/slchost/host_slc1host_func1_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_func1_int_ena.rs
@@ -356,7 +356,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -364,7 +363,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -372,7 +370,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -380,7 +377,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -388,7 +384,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -396,7 +391,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -404,7 +398,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -412,7 +405,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -420,7 +412,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -428,7 +419,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -436,7 +426,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -444,7 +433,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -452,7 +440,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -460,7 +447,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -468,7 +454,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1host_rx_start_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1HOST_RX_START_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -476,7 +461,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1host_tx_start_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1HOST_TX_START_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -484,7 +468,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_rx_udf_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_RX_UDF_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -492,7 +475,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_TX_OVF_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -500,7 +482,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -508,7 +489,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_EXT_BIT0_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -516,7 +496,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_EXT_BIT1_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -524,7 +503,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_EXT_BIT2_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -532,7 +510,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_EXT_BIT3_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -540,7 +517,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_wifi_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -548,7 +524,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
@@ -556,7 +531,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn1_slc1_bt_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_func2_int_ena.rs b/esp32/src/slchost/host_slc1host_func2_int_ena.rs
index 62d78141df..ba64041cdb 100644
--- a/esp32/src/slchost/host_slc1host_func2_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_func2_int_ena.rs
@@ -356,7 +356,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -364,7 +363,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -372,7 +370,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -380,7 +377,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -388,7 +384,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -396,7 +391,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -404,7 +398,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -412,7 +405,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -420,7 +412,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -428,7 +419,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -436,7 +426,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -444,7 +433,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -452,7 +440,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -460,7 +447,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -468,7 +454,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1host_rx_start_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1HOST_RX_START_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -476,7 +461,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1host_tx_start_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1HOST_TX_START_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -484,7 +468,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_rx_udf_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_RX_UDF_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -492,7 +475,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_TX_OVF_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -500,7 +482,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -508,7 +489,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_EXT_BIT0_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -516,7 +496,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_EXT_BIT1_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -524,7 +503,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_EXT_BIT2_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -532,7 +510,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_EXT_BIT3_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -540,7 +517,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_wifi_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -548,7 +524,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
@@ -556,7 +531,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_fn2_slc1_bt_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_int_clr.rs b/esp32/src/slchost/host_slc1host_int_clr.rs
index 828e26498d..e0a5ebe16c 100644
--- a/esp32/src/slchost/host_slc1host_int_clr.rs
+++ b/esp32/src/slchost/host_slc1host_int_clr.rs
@@ -61,7 +61,6 @@ impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit0_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT0_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -69,7 +68,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit1_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT1_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -77,7 +75,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit2_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT2_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -85,7 +82,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit3_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT3_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -93,7 +89,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit4_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT4_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -101,7 +96,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit5_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT5_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -109,7 +103,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit6_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT6_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -117,7 +110,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit7_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT7_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -125,7 +117,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_1to0_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_1TO0_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -133,7 +124,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_1to0_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_1TO0_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -141,7 +131,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_0to1_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_0TO1_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -149,7 +138,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_0to1_int_clr(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_0TO1_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -157,7 +145,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_sof_int_clr(
         &mut self,
     ) -> HOST_SLC1HOST_RX_SOF_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -165,7 +152,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_eof_int_clr(
         &mut self,
     ) -> HOST_SLC1HOST_RX_EOF_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -173,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_start_int_clr(
         &mut self,
     ) -> HOST_SLC1HOST_RX_START_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -181,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_tx_start_int_clr(
         &mut self,
     ) -> HOST_SLC1HOST_TX_START_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -189,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_udf_int_clr(
         &mut self,
     ) -> HOST_SLC1_RX_UDF_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -197,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tx_ovf_int_clr(
         &mut self,
     ) -> HOST_SLC1_TX_OVF_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -205,7 +187,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_pf_valid_int_clr(
         &mut self,
     ) -> HOST_SLC1_RX_PF_VALID_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -213,7 +194,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit0_int_clr(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT0_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -221,7 +201,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit1_int_clr(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT1_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -229,7 +208,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit2_int_clr(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT2_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -237,7 +215,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit3_int_clr(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT3_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -245,7 +222,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_wifi_rx_new_packet_int_clr(
         &mut self,
     ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -253,7 +229,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_host_rd_retry_int_clr(
         &mut self,
     ) -> HOST_SLC1_HOST_RD_RETRY_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
@@ -261,7 +236,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_bt_rx_new_packet_int_clr(
         &mut self,
     ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_W<HOST_SLC1HOST_INT_CLR_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_int_ena.rs b/esp32/src/slchost/host_slc1host_int_ena.rs
index ad697a0ed2..8f68a7adbb 100644
--- a/esp32/src/slchost/host_slc1host_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_int_ena.rs
@@ -346,7 +346,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit0_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT0_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -354,7 +353,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit1_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT1_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -362,7 +360,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit2_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT2_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -370,7 +367,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit3_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT3_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -378,7 +374,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit4_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT4_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -386,7 +381,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit5_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT5_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -394,7 +388,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit6_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT6_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -402,7 +395,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit7_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT7_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -410,7 +402,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_1to0_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -418,7 +409,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_1to0_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -426,7 +416,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_0to1_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -434,7 +423,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_0to1_int_ena(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -442,7 +430,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_sof_int_ena(
         &mut self,
     ) -> HOST_SLC1HOST_RX_SOF_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -450,7 +437,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_eof_int_ena(
         &mut self,
     ) -> HOST_SLC1HOST_RX_EOF_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -458,7 +444,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_start_int_ena(
         &mut self,
     ) -> HOST_SLC1HOST_RX_START_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -466,7 +451,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_tx_start_int_ena(
         &mut self,
     ) -> HOST_SLC1HOST_TX_START_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -474,7 +458,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_udf_int_ena(
         &mut self,
     ) -> HOST_SLC1_RX_UDF_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -482,7 +465,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tx_ovf_int_ena(
         &mut self,
     ) -> HOST_SLC1_TX_OVF_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -490,7 +472,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_pf_valid_int_ena(
         &mut self,
     ) -> HOST_SLC1_RX_PF_VALID_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -498,7 +479,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit0_int_ena(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT0_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -506,7 +486,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit1_int_ena(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT1_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -514,7 +493,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit2_int_ena(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT2_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -522,7 +500,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit3_int_ena(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT3_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -530,7 +507,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_wifi_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -538,7 +514,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_host_rd_retry_int_ena(
         &mut self,
     ) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
@@ -546,7 +521,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_bt_rx_new_packet_int_ena(
         &mut self,
     ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<HOST_SLC1HOST_INT_ENA_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_int_ena1.rs b/esp32/src/slchost/host_slc1host_int_ena1.rs
index b41f9b0311..d3cabe2fc8 100644
--- a/esp32/src/slchost/host_slc1host_int_ena1.rs
+++ b/esp32/src/slchost/host_slc1host_int_ena1.rs
@@ -352,7 +352,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit0_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT0_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -360,7 +359,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit1_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT1_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -368,7 +366,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit2_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT2_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -376,7 +373,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit3_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT3_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -384,7 +380,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit4_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT4_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -392,7 +387,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit5_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT5_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -400,7 +394,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit6_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT6_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -408,7 +401,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tohost_bit7_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOHOST_BIT7_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -416,7 +408,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_1to0_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -424,7 +415,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_1to0_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -432,7 +422,6 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token0_0to1_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -440,7 +429,6 @@ impl W {
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_token1_0to1_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -448,7 +436,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_sof_int_ena1(
         &mut self,
     ) -> HOST_SLC1HOST_RX_SOF_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -456,7 +443,6 @@ impl W {
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_eof_int_ena1(
         &mut self,
     ) -> HOST_SLC1HOST_RX_EOF_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -464,7 +450,6 @@ impl W {
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_start_int_ena1(
         &mut self,
     ) -> HOST_SLC1HOST_RX_START_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -472,7 +457,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_tx_start_int_ena1(
         &mut self,
     ) -> HOST_SLC1HOST_TX_START_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -480,7 +464,6 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_udf_int_ena1(
         &mut self,
     ) -> HOST_SLC1_RX_UDF_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -488,7 +471,6 @@ impl W {
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_tx_ovf_int_ena1(
         &mut self,
     ) -> HOST_SLC1_TX_OVF_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -496,7 +478,6 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_rx_pf_valid_int_ena1(
         &mut self,
     ) -> HOST_SLC1_RX_PF_VALID_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -504,7 +485,6 @@ impl W {
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit0_int_ena1(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT0_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -512,7 +492,6 @@ impl W {
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit1_int_ena1(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT1_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -520,7 +499,6 @@ impl W {
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit2_int_ena1(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT2_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -528,7 +506,6 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_ext_bit3_int_ena1(
         &mut self,
     ) -> HOST_SLC1_EXT_BIT3_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -536,7 +513,6 @@ impl W {
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_wifi_rx_new_packet_int_ena1(
         &mut self,
     ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -544,7 +520,6 @@ impl W {
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_host_rd_retry_int_ena1(
         &mut self,
     ) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
@@ -552,7 +527,6 @@ impl W {
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1_bt_rx_new_packet_int_ena1(
         &mut self,
     ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_W<HOST_SLC1HOST_INT_ENA1_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_rx_infor.rs b/esp32/src/slchost/host_slc1host_rx_infor.rs
index 28a698e851..05439e9a32 100644
--- a/esp32/src/slchost/host_slc1host_rx_infor.rs
+++ b/esp32/src/slchost/host_slc1host_rx_infor.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_rx_infor(
         &mut self,
     ) -> HOST_SLC1HOST_RX_INFOR_W<HOST_SLC1HOST_RX_INFOR_SPEC> {
diff --git a/esp32/src/slchost/host_slc1host_token_wdata.rs b/esp32/src/slchost/host_slc1host_token_wdata.rs
index a555aa8e24..15555aebc4 100644
--- a/esp32/src/slchost/host_slc1host_token_wdata.rs
+++ b/esp32/src/slchost/host_slc1host_token_wdata.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token0_wd(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN0_WD_W<HOST_SLC1HOST_TOKEN_WDATA_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bits 16:27"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token1_wd(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN1_WD_W<HOST_SLC1HOST_TOKEN_WDATA_SPEC> {
diff --git a/esp32/src/slchost/host_slc_apbwin_conf.rs b/esp32/src/slchost/host_slc_apbwin_conf.rs
index 79433e4120..f41a03555b 100644
--- a/esp32/src/slchost/host_slc_apbwin_conf.rs
+++ b/esp32/src/slchost/host_slc_apbwin_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_apbwin_addr(&mut self) -> HOST_SLC_APBWIN_ADDR_W<HOST_SLC_APBWIN_CONF_SPEC> {
         HOST_SLC_APBWIN_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_apbwin_wr(&mut self) -> HOST_SLC_APBWIN_WR_W<HOST_SLC_APBWIN_CONF_SPEC> {
         HOST_SLC_APBWIN_WR_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_apbwin_start(&mut self) -> HOST_SLC_APBWIN_START_W<HOST_SLC_APBWIN_CONF_SPEC> {
         HOST_SLC_APBWIN_START_W::new(self, 29)
     }
diff --git a/esp32/src/slchost/host_slc_apbwin_wdata.rs b/esp32/src/slchost/host_slc_apbwin_wdata.rs
index 8b30e21885..6b4fb890fd 100644
--- a/esp32/src/slchost/host_slc_apbwin_wdata.rs
+++ b/esp32/src/slchost/host_slc_apbwin_wdata.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_apbwin_wdata(&mut self) -> HOST_SLC_APBWIN_WDATA_W<HOST_SLC_APBWIN_WDATA_SPEC> {
         HOST_SLC_APBWIN_WDATA_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slchost_conf.rs b/esp32/src/slchost/host_slchost_conf.rs
index 7a0d7672bf..a5b20451d7 100644
--- a/esp32/src/slchost/host_slchost_conf.rs
+++ b/esp32/src/slchost/host_slchost_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_frc_sdio11(&mut self) -> HOST_FRC_SDIO11_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_FRC_SDIO11_W::new(self, 0)
     }
     #[doc = "Bits 5:9"]
     #[inline(always)]
-    #[must_use]
     pub fn host_frc_sdio20(&mut self) -> HOST_FRC_SDIO20_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_FRC_SDIO20_W::new(self, 5)
     }
     #[doc = "Bits 10:14"]
     #[inline(always)]
-    #[must_use]
     pub fn host_frc_neg_samp(&mut self) -> HOST_FRC_NEG_SAMP_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_FRC_NEG_SAMP_W::new(self, 10)
     }
     #[doc = "Bits 15:19"]
     #[inline(always)]
-    #[must_use]
     pub fn host_frc_pos_samp(&mut self) -> HOST_FRC_POS_SAMP_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_FRC_POS_SAMP_W::new(self, 15)
     }
     #[doc = "Bits 20:24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_frc_quick_in(&mut self) -> HOST_FRC_QUICK_IN_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_FRC_QUICK_IN_W::new(self, 20)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn host_sdio20_int_delay(&mut self) -> HOST_SDIO20_INT_DELAY_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_SDIO20_INT_DELAY_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn host_sdio_pad_pullup(&mut self) -> HOST_SDIO_PAD_PULLUP_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_SDIO_PAD_PULLUP_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn host_hspeed_con_en(&mut self) -> HOST_HSPEED_CON_EN_W<HOST_SLCHOST_CONF_SPEC> {
         HOST_HSPEED_CON_EN_W::new(self, 27)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w0.rs b/esp32/src/slchost/host_slchost_conf_w0.rs
index 7c777fe086..d56950defe 100644
--- a/esp32/src/slchost/host_slchost_conf_w0.rs
+++ b/esp32/src/slchost/host_slchost_conf_w0.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf0(&mut self) -> HOST_SLCHOST_CONF0_W<HOST_SLCHOST_CONF_W0_SPEC> {
         HOST_SLCHOST_CONF0_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf1(&mut self) -> HOST_SLCHOST_CONF1_W<HOST_SLCHOST_CONF_W0_SPEC> {
         HOST_SLCHOST_CONF1_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf2(&mut self) -> HOST_SLCHOST_CONF2_W<HOST_SLCHOST_CONF_W0_SPEC> {
         HOST_SLCHOST_CONF2_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf3(&mut self) -> HOST_SLCHOST_CONF3_W<HOST_SLCHOST_CONF_W0_SPEC> {
         HOST_SLCHOST_CONF3_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w1.rs b/esp32/src/slchost/host_slchost_conf_w1.rs
index 94755c78aa..0cebcdad8b 100644
--- a/esp32/src/slchost/host_slchost_conf_w1.rs
+++ b/esp32/src/slchost/host_slchost_conf_w1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf4(&mut self) -> HOST_SLCHOST_CONF4_W<HOST_SLCHOST_CONF_W1_SPEC> {
         HOST_SLCHOST_CONF4_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf5(&mut self) -> HOST_SLCHOST_CONF5_W<HOST_SLCHOST_CONF_W1_SPEC> {
         HOST_SLCHOST_CONF5_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf6(&mut self) -> HOST_SLCHOST_CONF6_W<HOST_SLCHOST_CONF_W1_SPEC> {
         HOST_SLCHOST_CONF6_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf7(&mut self) -> HOST_SLCHOST_CONF7_W<HOST_SLCHOST_CONF_W1_SPEC> {
         HOST_SLCHOST_CONF7_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w10.rs b/esp32/src/slchost/host_slchost_conf_w10.rs
index 6736f69404..e1e19115e0 100644
--- a/esp32/src/slchost/host_slchost_conf_w10.rs
+++ b/esp32/src/slchost/host_slchost_conf_w10.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf40(&mut self) -> HOST_SLCHOST_CONF40_W<HOST_SLCHOST_CONF_W10_SPEC> {
         HOST_SLCHOST_CONF40_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf41(&mut self) -> HOST_SLCHOST_CONF41_W<HOST_SLCHOST_CONF_W10_SPEC> {
         HOST_SLCHOST_CONF41_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf42(&mut self) -> HOST_SLCHOST_CONF42_W<HOST_SLCHOST_CONF_W10_SPEC> {
         HOST_SLCHOST_CONF42_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf43(&mut self) -> HOST_SLCHOST_CONF43_W<HOST_SLCHOST_CONF_W10_SPEC> {
         HOST_SLCHOST_CONF43_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w11.rs b/esp32/src/slchost/host_slchost_conf_w11.rs
index ab3db6767d..18c63c45e5 100644
--- a/esp32/src/slchost/host_slchost_conf_w11.rs
+++ b/esp32/src/slchost/host_slchost_conf_w11.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf44(&mut self) -> HOST_SLCHOST_CONF44_W<HOST_SLCHOST_CONF_W11_SPEC> {
         HOST_SLCHOST_CONF44_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf45(&mut self) -> HOST_SLCHOST_CONF45_W<HOST_SLCHOST_CONF_W11_SPEC> {
         HOST_SLCHOST_CONF45_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf46(&mut self) -> HOST_SLCHOST_CONF46_W<HOST_SLCHOST_CONF_W11_SPEC> {
         HOST_SLCHOST_CONF46_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf47(&mut self) -> HOST_SLCHOST_CONF47_W<HOST_SLCHOST_CONF_W11_SPEC> {
         HOST_SLCHOST_CONF47_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w12.rs b/esp32/src/slchost/host_slchost_conf_w12.rs
index 4c651bbfd4..98ac8bd5e5 100644
--- a/esp32/src/slchost/host_slchost_conf_w12.rs
+++ b/esp32/src/slchost/host_slchost_conf_w12.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf48(&mut self) -> HOST_SLCHOST_CONF48_W<HOST_SLCHOST_CONF_W12_SPEC> {
         HOST_SLCHOST_CONF48_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf49(&mut self) -> HOST_SLCHOST_CONF49_W<HOST_SLCHOST_CONF_W12_SPEC> {
         HOST_SLCHOST_CONF49_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf50(&mut self) -> HOST_SLCHOST_CONF50_W<HOST_SLCHOST_CONF_W12_SPEC> {
         HOST_SLCHOST_CONF50_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf51(&mut self) -> HOST_SLCHOST_CONF51_W<HOST_SLCHOST_CONF_W12_SPEC> {
         HOST_SLCHOST_CONF51_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w13.rs b/esp32/src/slchost/host_slchost_conf_w13.rs
index 2ede77517a..39ed285563 100644
--- a/esp32/src/slchost/host_slchost_conf_w13.rs
+++ b/esp32/src/slchost/host_slchost_conf_w13.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf52(&mut self) -> HOST_SLCHOST_CONF52_W<HOST_SLCHOST_CONF_W13_SPEC> {
         HOST_SLCHOST_CONF52_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf53(&mut self) -> HOST_SLCHOST_CONF53_W<HOST_SLCHOST_CONF_W13_SPEC> {
         HOST_SLCHOST_CONF53_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf54(&mut self) -> HOST_SLCHOST_CONF54_W<HOST_SLCHOST_CONF_W13_SPEC> {
         HOST_SLCHOST_CONF54_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf55(&mut self) -> HOST_SLCHOST_CONF55_W<HOST_SLCHOST_CONF_W13_SPEC> {
         HOST_SLCHOST_CONF55_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w14.rs b/esp32/src/slchost/host_slchost_conf_w14.rs
index 4731ce8e34..6ba0a3b57a 100644
--- a/esp32/src/slchost/host_slchost_conf_w14.rs
+++ b/esp32/src/slchost/host_slchost_conf_w14.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf56(&mut self) -> HOST_SLCHOST_CONF56_W<HOST_SLCHOST_CONF_W14_SPEC> {
         HOST_SLCHOST_CONF56_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf57(&mut self) -> HOST_SLCHOST_CONF57_W<HOST_SLCHOST_CONF_W14_SPEC> {
         HOST_SLCHOST_CONF57_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf58(&mut self) -> HOST_SLCHOST_CONF58_W<HOST_SLCHOST_CONF_W14_SPEC> {
         HOST_SLCHOST_CONF58_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf59(&mut self) -> HOST_SLCHOST_CONF59_W<HOST_SLCHOST_CONF_W14_SPEC> {
         HOST_SLCHOST_CONF59_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w15.rs b/esp32/src/slchost/host_slchost_conf_w15.rs
index d11107833f..2f859b4e08 100644
--- a/esp32/src/slchost/host_slchost_conf_w15.rs
+++ b/esp32/src/slchost/host_slchost_conf_w15.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf60(&mut self) -> HOST_SLCHOST_CONF60_W<HOST_SLCHOST_CONF_W15_SPEC> {
         HOST_SLCHOST_CONF60_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf61(&mut self) -> HOST_SLCHOST_CONF61_W<HOST_SLCHOST_CONF_W15_SPEC> {
         HOST_SLCHOST_CONF61_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf62(&mut self) -> HOST_SLCHOST_CONF62_W<HOST_SLCHOST_CONF_W15_SPEC> {
         HOST_SLCHOST_CONF62_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf63(&mut self) -> HOST_SLCHOST_CONF63_W<HOST_SLCHOST_CONF_W15_SPEC> {
         HOST_SLCHOST_CONF63_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w2.rs b/esp32/src/slchost/host_slchost_conf_w2.rs
index 6a2032fd2f..040371e133 100644
--- a/esp32/src/slchost/host_slchost_conf_w2.rs
+++ b/esp32/src/slchost/host_slchost_conf_w2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf8(&mut self) -> HOST_SLCHOST_CONF8_W<HOST_SLCHOST_CONF_W2_SPEC> {
         HOST_SLCHOST_CONF8_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf9(&mut self) -> HOST_SLCHOST_CONF9_W<HOST_SLCHOST_CONF_W2_SPEC> {
         HOST_SLCHOST_CONF9_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf10(&mut self) -> HOST_SLCHOST_CONF10_W<HOST_SLCHOST_CONF_W2_SPEC> {
         HOST_SLCHOST_CONF10_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf11(&mut self) -> HOST_SLCHOST_CONF11_W<HOST_SLCHOST_CONF_W2_SPEC> {
         HOST_SLCHOST_CONF11_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w3.rs b/esp32/src/slchost/host_slchost_conf_w3.rs
index 9877471931..4d0d95dea5 100644
--- a/esp32/src/slchost/host_slchost_conf_w3.rs
+++ b/esp32/src/slchost/host_slchost_conf_w3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf12(&mut self) -> HOST_SLCHOST_CONF12_W<HOST_SLCHOST_CONF_W3_SPEC> {
         HOST_SLCHOST_CONF12_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf13(&mut self) -> HOST_SLCHOST_CONF13_W<HOST_SLCHOST_CONF_W3_SPEC> {
         HOST_SLCHOST_CONF13_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf14(&mut self) -> HOST_SLCHOST_CONF14_W<HOST_SLCHOST_CONF_W3_SPEC> {
         HOST_SLCHOST_CONF14_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf15(&mut self) -> HOST_SLCHOST_CONF15_W<HOST_SLCHOST_CONF_W3_SPEC> {
         HOST_SLCHOST_CONF15_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w4.rs b/esp32/src/slchost/host_slchost_conf_w4.rs
index ae3857922a..39fe08b40f 100644
--- a/esp32/src/slchost/host_slchost_conf_w4.rs
+++ b/esp32/src/slchost/host_slchost_conf_w4.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - SLC timeout value"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf16(&mut self) -> HOST_SLCHOST_CONF16_W<HOST_SLCHOST_CONF_W4_SPEC> {
         HOST_SLCHOST_CONF16_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - SLC timeout enable"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf17(&mut self) -> HOST_SLCHOST_CONF17_W<HOST_SLCHOST_CONF_W4_SPEC> {
         HOST_SLCHOST_CONF17_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf18(&mut self) -> HOST_SLCHOST_CONF18_W<HOST_SLCHOST_CONF_W4_SPEC> {
         HOST_SLCHOST_CONF18_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Interrupt to target CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf19(&mut self) -> HOST_SLCHOST_CONF19_W<HOST_SLCHOST_CONF_W4_SPEC> {
         HOST_SLCHOST_CONF19_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w5.rs b/esp32/src/slchost/host_slchost_conf_w5.rs
index bac07d9e10..b98ef7af85 100644
--- a/esp32/src/slchost/host_slchost_conf_w5.rs
+++ b/esp32/src/slchost/host_slchost_conf_w5.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf20(&mut self) -> HOST_SLCHOST_CONF20_W<HOST_SLCHOST_CONF_W5_SPEC> {
         HOST_SLCHOST_CONF20_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf21(&mut self) -> HOST_SLCHOST_CONF21_W<HOST_SLCHOST_CONF_W5_SPEC> {
         HOST_SLCHOST_CONF21_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf22(&mut self) -> HOST_SLCHOST_CONF22_W<HOST_SLCHOST_CONF_W5_SPEC> {
         HOST_SLCHOST_CONF22_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf23(&mut self) -> HOST_SLCHOST_CONF23_W<HOST_SLCHOST_CONF_W5_SPEC> {
         HOST_SLCHOST_CONF23_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w6.rs b/esp32/src/slchost/host_slchost_conf_w6.rs
index 1e7c219184..f5010e704d 100644
--- a/esp32/src/slchost/host_slchost_conf_w6.rs
+++ b/esp32/src/slchost/host_slchost_conf_w6.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf24(&mut self) -> HOST_SLCHOST_CONF24_W<HOST_SLCHOST_CONF_W6_SPEC> {
         HOST_SLCHOST_CONF24_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf25(&mut self) -> HOST_SLCHOST_CONF25_W<HOST_SLCHOST_CONF_W6_SPEC> {
         HOST_SLCHOST_CONF25_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf26(&mut self) -> HOST_SLCHOST_CONF26_W<HOST_SLCHOST_CONF_W6_SPEC> {
         HOST_SLCHOST_CONF26_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf27(&mut self) -> HOST_SLCHOST_CONF27_W<HOST_SLCHOST_CONF_W6_SPEC> {
         HOST_SLCHOST_CONF27_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w7.rs b/esp32/src/slchost/host_slchost_conf_w7.rs
index 2411c1f26d..e33fb3f713 100644
--- a/esp32/src/slchost/host_slchost_conf_w7.rs
+++ b/esp32/src/slchost/host_slchost_conf_w7.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf28(&mut self) -> HOST_SLCHOST_CONF28_W<HOST_SLCHOST_CONF_W7_SPEC> {
         HOST_SLCHOST_CONF28_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf29(&mut self) -> HOST_SLCHOST_CONF29_W<HOST_SLCHOST_CONF_W7_SPEC> {
         HOST_SLCHOST_CONF29_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf30(&mut self) -> HOST_SLCHOST_CONF30_W<HOST_SLCHOST_CONF_W7_SPEC> {
         HOST_SLCHOST_CONF30_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf31(&mut self) -> HOST_SLCHOST_CONF31_W<HOST_SLCHOST_CONF_W7_SPEC> {
         HOST_SLCHOST_CONF31_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w8.rs b/esp32/src/slchost/host_slchost_conf_w8.rs
index a7147098aa..7cf4179f77 100644
--- a/esp32/src/slchost/host_slchost_conf_w8.rs
+++ b/esp32/src/slchost/host_slchost_conf_w8.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf32(&mut self) -> HOST_SLCHOST_CONF32_W<HOST_SLCHOST_CONF_W8_SPEC> {
         HOST_SLCHOST_CONF32_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf33(&mut self) -> HOST_SLCHOST_CONF33_W<HOST_SLCHOST_CONF_W8_SPEC> {
         HOST_SLCHOST_CONF33_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf34(&mut self) -> HOST_SLCHOST_CONF34_W<HOST_SLCHOST_CONF_W8_SPEC> {
         HOST_SLCHOST_CONF34_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf35(&mut self) -> HOST_SLCHOST_CONF35_W<HOST_SLCHOST_CONF_W8_SPEC> {
         HOST_SLCHOST_CONF35_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_conf_w9.rs b/esp32/src/slchost/host_slchost_conf_w9.rs
index e4e8ccd352..49166b2e1c 100644
--- a/esp32/src/slchost/host_slchost_conf_w9.rs
+++ b/esp32/src/slchost/host_slchost_conf_w9.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf36(&mut self) -> HOST_SLCHOST_CONF36_W<HOST_SLCHOST_CONF_W9_SPEC> {
         HOST_SLCHOST_CONF36_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf37(&mut self) -> HOST_SLCHOST_CONF37_W<HOST_SLCHOST_CONF_W9_SPEC> {
         HOST_SLCHOST_CONF37_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf38(&mut self) -> HOST_SLCHOST_CONF38_W<HOST_SLCHOST_CONF_W9_SPEC> {
         HOST_SLCHOST_CONF38_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_conf39(&mut self) -> HOST_SLCHOST_CONF39_W<HOST_SLCHOST_CONF_W9_SPEC> {
         HOST_SLCHOST_CONF39_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_func2_0.rs b/esp32/src/slchost/host_slchost_func2_0.rs
index 412caafdb9..509ffa33e0 100644
--- a/esp32/src/slchost/host_slchost_func2_0.rs
+++ b/esp32/src/slchost/host_slchost_func2_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_func2_int(&mut self) -> HOST_SLC_FUNC2_INT_W<HOST_SLCHOST_FUNC2_0_SPEC> {
         HOST_SLC_FUNC2_INT_W::new(self, 24)
     }
diff --git a/esp32/src/slchost/host_slchost_func2_1.rs b/esp32/src/slchost/host_slchost_func2_1.rs
index b6f7be3410..ac46223834 100644
--- a/esp32/src/slchost/host_slchost_func2_1.rs
+++ b/esp32/src/slchost/host_slchost_func2_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_func2_int_en(&mut self) -> HOST_SLC_FUNC2_INT_EN_W<HOST_SLCHOST_FUNC2_1_SPEC> {
         HOST_SLC_FUNC2_INT_EN_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slchost_func2_2.rs b/esp32/src/slchost/host_slchost_func2_2.rs
index 9d938a2ba4..ec730e96d1 100644
--- a/esp32/src/slchost/host_slchost_func2_2.rs
+++ b/esp32/src/slchost/host_slchost_func2_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc_func1_mdstat(&mut self) -> HOST_SLC_FUNC1_MDSTAT_W<HOST_SLCHOST_FUNC2_2_SPEC> {
         HOST_SLC_FUNC1_MDSTAT_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slchost_rdclr0.rs b/esp32/src/slchost/host_slchost_rdclr0.rs
index cd9ff69774..849a8201f4 100644
--- a/esp32/src/slchost/host_slchost_rdclr0.rs
+++ b/esp32/src/slchost/host_slchost_rdclr0.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_slc0_bit7_clraddr(
         &mut self,
     ) -> HOST_SLCHOST_SLC0_BIT7_CLRADDR_W<HOST_SLCHOST_RDCLR0_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 9:17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_slc0_bit6_clraddr(
         &mut self,
     ) -> HOST_SLCHOST_SLC0_BIT6_CLRADDR_W<HOST_SLCHOST_RDCLR0_SPEC> {
diff --git a/esp32/src/slchost/host_slchost_rdclr1.rs b/esp32/src/slchost/host_slchost_rdclr1.rs
index 3adbd91210..ebff758970 100644
--- a/esp32/src/slchost/host_slchost_rdclr1.rs
+++ b/esp32/src/slchost/host_slchost_rdclr1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_slc1_bit7_clraddr(
         &mut self,
     ) -> HOST_SLCHOST_SLC1_BIT7_CLRADDR_W<HOST_SLCHOST_RDCLR1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 9:17"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_slc1_bit6_clraddr(
         &mut self,
     ) -> HOST_SLCHOST_SLC1_BIT6_CLRADDR_W<HOST_SLCHOST_RDCLR1_SPEC> {
diff --git a/esp32/src/slchost/host_slchost_token_con.rs b/esp32/src/slchost/host_slchost_token_con.rs
index cb6b0069ef..75f20b6a75 100644
--- a/esp32/src/slchost/host_slchost_token_con.rs
+++ b/esp32/src/slchost/host_slchost_token_con.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_TOKEN_CON_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token0_dec(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN0_DEC_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -35,7 +34,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token1_dec(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN1_DEC_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -43,7 +41,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token0_wr(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN0_WR_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -51,7 +48,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_token1_wr(
         &mut self,
     ) -> HOST_SLC0HOST_TOKEN1_WR_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -59,7 +55,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token0_dec(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN0_DEC_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -67,7 +62,6 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token1_dec(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN1_DEC_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -75,7 +69,6 @@ impl W {
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token0_wr(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN0_WR_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -83,7 +76,6 @@ impl W {
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc1host_token1_wr(
         &mut self,
     ) -> HOST_SLC1HOST_TOKEN1_WR_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
@@ -91,7 +83,6 @@ impl W {
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slc0host_len_wr(&mut self) -> HOST_SLC0HOST_LEN_WR_W<HOST_SLCHOST_TOKEN_CON_SPEC> {
         HOST_SLC0HOST_LEN_WR_W::new(self, 8)
     }
diff --git a/esp32/src/slchost/host_slchostdate.rs b/esp32/src/slchost/host_slchostdate.rs
index 271a80bb21..b47474ba21 100644
--- a/esp32/src/slchost/host_slchostdate.rs
+++ b/esp32/src/slchost/host_slchostdate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_date(&mut self) -> HOST_SLCHOST_DATE_W<HOST_SLCHOSTDATE_SPEC> {
         HOST_SLCHOST_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/slchost/host_slchostid.rs b/esp32/src/slchost/host_slchostid.rs
index 31dc2e103f..451c9a5fa4 100644
--- a/esp32/src/slchost/host_slchostid.rs
+++ b/esp32/src/slchost/host_slchostid.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn host_slchost_id(&mut self) -> HOST_SLCHOST_ID_W<HOST_SLCHOSTID_SPEC> {
         HOST_SLCHOST_ID_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/cache_fctrl.rs b/esp32/src/spi0/cache_fctrl.rs
index faa2f9ec84..6ed0037980 100644
--- a/esp32/src/spi0/cache_fctrl.rs
+++ b/esp32/src/spi0/cache_fctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - For SPI0 Cache access enable 1: enable 0:disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<CACHE_FCTRL_SPEC> {
         CACHE_REQ_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<CACHE_FCTRL_SPEC> {
         CACHE_USR_CMD_4BYTE_W::new(self, 1)
     }
     #[doc = "Bit 2 - For SPI0 cache read flash for user define command 1: enable 0:disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<CACHE_FCTRL_SPEC> {
         CACHE_FLASH_USR_CMD_W::new(self, 2)
     }
     #[doc = "Bit 3 - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_flash_pes_en(&mut self) -> CACHE_FLASH_PES_EN_W<CACHE_FCTRL_SPEC> {
         CACHE_FLASH_PES_EN_W::new(self, 3)
     }
diff --git a/esp32/src/spi0/cache_sctrl.rs b/esp32/src/spi0/cache_sctrl.rs
index 2187b1abff..271884f715 100644
--- a/esp32/src/spi0/cache_sctrl.rs
+++ b/esp32/src/spi0/cache_sctrl.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_DIO_W::new(self, 1)
     }
     #[doc = "Bit 2 - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_QIO_W::new(self, 2)
     }
     #[doc = "Bit 3 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_WR_SRAM_DUMMY_W::new(self, 3)
     }
     #[doc = "Bit 4 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_RD_SRAM_DUMMY_W::new(self, 4)
     }
     #[doc = "Bit 5 - For SPI0 In the spi sram mode cache read sram for user define command."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_RCMD_W::new(self, 5)
     }
     #[doc = "Bits 6:13 - For SPI0 In the sram mode it is the byte length of spi read sram data."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_bytes_len(&mut self) -> SRAM_BYTES_LEN_W<CACHE_SCTRL_SPEC> {
         SRAM_BYTES_LEN_W::new(self, 6)
     }
     #[doc = "Bits 14:21 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_dummy_cyclelen(&mut self) -> SRAM_DUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
         SRAM_DUMMY_CYCLELEN_W::new(self, 14)
     }
     #[doc = "Bits 22:27 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<CACHE_SCTRL_SPEC> {
         SRAM_ADDR_BITLEN_W::new(self, 22)
     }
     #[doc = "Bit 28 - For SPI0 In the spi sram mode cache write sram for user define command"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_WCMD_W::new(self, 28)
     }
diff --git a/esp32/src/spi0/clock.rs b/esp32/src/spi0/clock.rs
index edeb80b01a..cd9e547af7 100644
--- a/esp32/src/spi0/clock.rs
+++ b/esp32/src/spi0/clock.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
         CLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
         CLKCNT_H_W::new(self, 6)
     }
     #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
         CLKCNT_N_W::new(self, 12)
     }
     #[doc = "Bits 18:30 - In the master mode it is pre-divider of spi_clk."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<CLOCK_SPEC> {
         CLKDIV_PRE_W::new(self, 18)
     }
     #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
         CLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/cmd.rs b/esp32/src/spi0/cmd.rs
index afdb71895d..938a8b4cd5 100644
--- a/esp32/src/spi0/cmd.rs
+++ b/esp32/src/spi0/cmd.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16 - program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_per(&mut self) -> FLASH_PER_W<CMD_SPEC> {
         FLASH_PER_W::new(self, 16)
     }
     #[doc = "Bit 17 - program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes(&mut self) -> FLASH_PES_W<CMD_SPEC> {
         FLASH_PES_W::new(self, 17)
     }
     #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
         USR_W::new(self, 18)
     }
     #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_hpm(&mut self) -> FLASH_HPM_W<CMD_SPEC> {
         FLASH_HPM_W::new(self, 19)
     }
     #[doc = "Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_res(&mut self) -> FLASH_RES_W<CMD_SPEC> {
         FLASH_RES_W::new(self, 20)
     }
     #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_dp(&mut self) -> FLASH_DP_W<CMD_SPEC> {
         FLASH_DP_W::new(self, 21)
     }
     #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ce(&mut self) -> FLASH_CE_W<CMD_SPEC> {
         FLASH_CE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_be(&mut self) -> FLASH_BE_W<CMD_SPEC> {
         FLASH_BE_W::new(self, 23)
     }
     #[doc = "Bit 24 - Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_se(&mut self) -> FLASH_SE_W<CMD_SPEC> {
         FLASH_SE_W::new(self, 24)
     }
     #[doc = "Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pp(&mut self) -> FLASH_PP_W<CMD_SPEC> {
         FLASH_PP_W::new(self, 25)
     }
     #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wrsr(&mut self) -> FLASH_WRSR_W<CMD_SPEC> {
         FLASH_WRSR_W::new(self, 26)
     }
     #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_rdsr(&mut self) -> FLASH_RDSR_W<CMD_SPEC> {
         FLASH_RDSR_W::new(self, 27)
     }
     #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_rdid(&mut self) -> FLASH_RDID_W<CMD_SPEC> {
         FLASH_RDID_W::new(self, 28)
     }
     #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wrdi(&mut self) -> FLASH_WRDI_W<CMD_SPEC> {
         FLASH_WRDI_W::new(self, 29)
     }
     #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wren(&mut self) -> FLASH_WREN_W<CMD_SPEC> {
         FLASH_WREN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_read(&mut self) -> FLASH_READ_W<CMD_SPEC> {
         FLASH_READ_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/ctrl.rs b/esp32/src/spi0/ctrl.rs
index 3f276b6a9c..9a808f30fe 100644
--- a/esp32/src/spi0/ctrl.rs
+++ b/esp32/src/spi0/ctrl.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
     #[inline(always)]
-    #[must_use]
     pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
         FCS_CRC_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
         TX_CRC_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - wait flash idle when program flash or erase flash. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_flash_idle_en(&mut self) -> WAIT_FLASH_IDLE_EN_W<CTRL_SPEC> {
         WAIT_FLASH_IDLE_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
         FASTRD_MODE_W::new(self, 13)
     }
     #[doc = "Bit 14 - In the read operations read-data phase apply 2 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
         FREAD_DUAL_W::new(self, 14)
     }
     #[doc = "Bit 15 - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
         RESANDRES_W::new(self, 15)
     }
     #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
         FREAD_QUAD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high 0: output low."]
     #[inline(always)]
-    #[must_use]
     pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
         WP_W::new(self, 21)
     }
     #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
         WRSR_2B_W::new(self, 22)
     }
     #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
         FREAD_DIO_W::new(self, 23)
     }
     #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
         FREAD_QIO_W::new(self, 24)
     }
     #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
         RD_BIT_ORDER_W::new(self, 25)
     }
     #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first"]
     #[inline(always)]
-    #[must_use]
     pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
         WR_BIT_ORDER_W::new(self, 26)
     }
diff --git a/esp32/src/spi0/ctrl1.rs b/esp32/src/spi0/ctrl1.rs
index 5f2df403fa..f6adc49a85 100644
--- a/esp32/src/spi0/ctrl1.rs
+++ b/esp32/src/spi0/ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:27 - Delay cycles of resume Flash when resume Flash is enable by spi clock."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_delay_res(&mut self) -> CS_HOLD_DELAY_RES_W<CTRL1_SPEC> {
         CS_HOLD_DELAY_RES_W::new(self, 16)
     }
     #[doc = "Bits 28:31 - SPI cs signal is delayed by spi clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<CTRL1_SPEC> {
         CS_HOLD_DELAY_W::new(self, 28)
     }
diff --git a/esp32/src/spi0/ctrl2.rs b/esp32/src/spi0/ctrl2.rs
index 5158f0c18d..9331afcc19 100644
--- a/esp32/src/spi0/ctrl2.rs
+++ b/esp32/src/spi0/ctrl2.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
     #[inline(always)]
-    #[must_use]
     pub fn setup_time(&mut self) -> SETUP_TIME_W<CTRL2_SPEC> {
         SETUP_TIME_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
     #[inline(always)]
-    #[must_use]
     pub fn hold_time(&mut self) -> HOLD_TIME_W<CTRL2_SPEC> {
         HOLD_TIME_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_low_mode(&mut self) -> CK_OUT_LOW_MODE_W<CTRL2_SPEC> {
         CK_OUT_LOW_MODE_W::new(self, 8)
     }
     #[doc = "Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_high_mode(&mut self) -> CK_OUT_HIGH_MODE_W<CTRL2_SPEC> {
         CK_OUT_HIGH_MODE_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn miso_delay_mode(&mut self) -> MISO_DELAY_MODE_W<CTRL2_SPEC> {
         MISO_DELAY_MODE_W::new(self, 16)
     }
     #[doc = "Bits 18:20 - MISO signals are delayed by system clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn miso_delay_num(&mut self) -> MISO_DELAY_NUM_W<CTRL2_SPEC> {
         MISO_DELAY_NUM_W::new(self, 18)
     }
     #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn mosi_delay_mode(&mut self) -> MOSI_DELAY_MODE_W<CTRL2_SPEC> {
         MOSI_DELAY_MODE_W::new(self, 21)
     }
     #[doc = "Bits 23:25 - MOSI signals are delayed by system clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn mosi_delay_num(&mut self) -> MOSI_DELAY_NUM_W<CTRL2_SPEC> {
         MOSI_DELAY_NUM_W::new(self, 23)
     }
     #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<CTRL2_SPEC> {
         CS_DELAY_MODE_W::new(self, 26)
     }
     #[doc = "Bits 28:31 - spi_cs signal is delayed by system clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<CTRL2_SPEC> {
         CS_DELAY_NUM_W::new(self, 28)
     }
diff --git a/esp32/src/spi0/dma_conf.rs b/esp32/src/spi0/dma_conf.rs
index 4381b72d74..6858bfccf5 100644
--- a/esp32/src/spi0/dma_conf.rs
+++ b/esp32/src/spi0/dma_conf.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - The bit is used to reset in dma fsm and in data fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<DMA_CONF_SPEC> {
         IN_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to reset out dma fsm and out data fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<DMA_CONF_SPEC> {
         OUT_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - reset spi dma ahb master fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<DMA_CONF_SPEC> {
         AHBM_FIFO_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - reset spi dma ahb master."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<DMA_CONF_SPEC> {
         AHBM_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set bit to test in link."]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<DMA_CONF_SPEC> {
         IN_LOOP_TEST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set bit to test out link."]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<DMA_CONF_SPEC> {
         OUT_LOOP_TEST_W::new(self, 7)
     }
     #[doc = "Bit 8 - when the link is empty jump to next automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<DMA_CONF_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 8)
     }
     #[doc = "Bit 9 - out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<DMA_CONF_SPEC> {
         OUT_EOF_MODE_W::new(self, 9)
     }
     #[doc = "Bit 10 - read descriptor use burst mode when read data for memory."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<DMA_CONF_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - read descriptor use burst mode when write data to memory."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<DMA_CONF_SPEC> {
         INDSCR_BURST_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - spi dma read data from memory in burst mode."]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<DMA_CONF_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 12)
     }
     #[doc = "Bit 14 - spi dma read data stop when in continue tx/rx mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_stop(&mut self) -> DMA_RX_STOP_W<DMA_CONF_SPEC> {
         DMA_RX_STOP_W::new(self, 14)
     }
     #[doc = "Bit 15 - spi dma write data stop when in continue tx/rx mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_stop(&mut self) -> DMA_TX_STOP_W<DMA_CONF_SPEC> {
         DMA_TX_STOP_W::new(self, 15)
     }
     #[doc = "Bit 16 - spi dma continue tx/rx data."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<DMA_CONF_SPEC> {
         DMA_CONTINUE_W::new(self, 16)
     }
diff --git a/esp32/src/spi0/dma_in_link.rs b/esp32/src/spi0/dma_in_link.rs
index 2bc973c8ef..f62a70f1d2 100644
--- a/esp32/src/spi0/dma_in_link.rs
+++ b/esp32/src/spi0/dma_in_link.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of the first inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<DMA_IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<DMA_IN_LINK_SPEC> {
         INLINK_AUTO_RET_W::new(self, 20)
     }
     #[doc = "Bit 28 - Set the bit to stop to use inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<DMA_IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set the bit to start to use inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<DMA_IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set the bit to mount on new inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<DMA_IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/spi0/dma_int_clr.rs b/esp32/src/spi0/dma_int_clr.rs
index a67eb3b900..82f192527a 100644
--- a/esp32/src/spi0/dma_int_clr.rs
+++ b/esp32/src/spi0/dma_int_clr.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear bit for lack of enough inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_empty(&mut self) -> INLINK_DSCR_EMPTY_W<DMA_INT_CLR_SPEC> {
         INLINK_DSCR_EMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear bit for outlink descriptor error."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_dscr_error(&mut self) -> OUTLINK_DSCR_ERROR_W<DMA_INT_CLR_SPEC> {
         OUTLINK_DSCR_ERROR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The clear bit for inlink descriptor error."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_error(&mut self) -> INLINK_DSCR_ERROR_W<DMA_INT_CLR_SPEC> {
         INLINK_DSCR_ERROR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The clear bit for completing usage of a inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<DMA_INT_CLR_SPEC> {
         IN_DONE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The clear bit for receiving error."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<DMA_INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The clear bit for completing receiving all the packets from host."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<DMA_INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The clear bit for completing usage of a outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<DMA_INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - The clear bit for sending a packet to host done."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<DMA_INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The clear bit for sending all the packets to host done."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<DMA_INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 8)
     }
diff --git a/esp32/src/spi0/dma_int_ena.rs b/esp32/src/spi0/dma_int_ena.rs
index 2a574894e0..98e2e0e527 100644
--- a/esp32/src/spi0/dma_int_ena.rs
+++ b/esp32/src/spi0/dma_int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for lack of enough inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_empty(&mut self) -> INLINK_DSCR_EMPTY_W<DMA_INT_ENA_SPEC> {
         INLINK_DSCR_EMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for outlink descriptor error."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_dscr_error(&mut self) -> OUTLINK_DSCR_ERROR_W<DMA_INT_ENA_SPEC> {
         OUTLINK_DSCR_ERROR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for inlink descriptor error."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_error(&mut self) -> INLINK_DSCR_ERROR_W<DMA_INT_ENA_SPEC> {
         INLINK_DSCR_ERROR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for completing usage of a inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<DMA_INT_ENA_SPEC> {
         IN_DONE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for receiving error."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<DMA_INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for completing receiving all the packets from host."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<DMA_INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for completing usage of a outlink descriptor ."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<DMA_INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for sending a packet to host done."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<DMA_INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The enable bit for sending all the packets to host done."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<DMA_INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 8)
     }
diff --git a/esp32/src/spi0/dma_out_link.rs b/esp32/src/spi0/dma_out_link.rs
index ffa034d597..71fc62fe20 100644
--- a/esp32/src/spi0/dma_out_link.rs
+++ b/esp32/src/spi0/dma_out_link.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of the first outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set the bit to stop to use outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set the bit to start to use outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set the bit to mount on new outlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/spi0/ext0.rs b/esp32/src/spi0/ext0.rs
index 77bfcdca3c..4698ebf144 100644
--- a/esp32/src/spi0/ext0.rs
+++ b/esp32/src/spi0/ext0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - page program delay time by system clock."]
     #[inline(always)]
-    #[must_use]
     pub fn t_pp_time(&mut self) -> T_PP_TIME_W<EXT0_SPEC> {
         T_PP_TIME_W::new(self, 0)
     }
     #[doc = "Bits 16:19 - page program delay time shift ."]
     #[inline(always)]
-    #[must_use]
     pub fn t_pp_shift(&mut self) -> T_PP_SHIFT_W<EXT0_SPEC> {
         T_PP_SHIFT_W::new(self, 16)
     }
     #[doc = "Bit 31 - page program delay enable."]
     #[inline(always)]
-    #[must_use]
     pub fn t_pp_ena(&mut self) -> T_PP_ENA_W<EXT0_SPEC> {
         T_PP_ENA_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/ext1.rs b/esp32/src/spi0/ext1.rs
index bfe1fa5787..bd842e9dae 100644
--- a/esp32/src/spi0/ext1.rs
+++ b/esp32/src/spi0/ext1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - erase flash delay time by system clock."]
     #[inline(always)]
-    #[must_use]
     pub fn t_erase_time(&mut self) -> T_ERASE_TIME_W<EXT1_SPEC> {
         T_ERASE_TIME_W::new(self, 0)
     }
     #[doc = "Bits 16:19 - erase flash delay time shift."]
     #[inline(always)]
-    #[must_use]
     pub fn t_erase_shift(&mut self) -> T_ERASE_SHIFT_W<EXT1_SPEC> {
         T_ERASE_SHIFT_W::new(self, 16)
     }
     #[doc = "Bit 31 - erase flash delay enable."]
     #[inline(always)]
-    #[must_use]
     pub fn t_erase_ena(&mut self) -> T_ERASE_ENA_W<EXT1_SPEC> {
         T_ERASE_ENA_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/ext3.rs b/esp32/src/spi0/ext3.rs
index e58ab9794b..a78fa68eb4 100644
--- a/esp32/src/spi0/ext3.rs
+++ b/esp32/src/spi0/ext3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase."]
     #[inline(always)]
-    #[must_use]
     pub fn int_hold_ena(&mut self) -> INT_HOLD_ENA_W<EXT3_SPEC> {
         INT_HOLD_ENA_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/miso_dlen.rs b/esp32/src/spi0/miso_dlen.rs
index cd516a9ad8..59b496e335 100644
--- a/esp32/src/spi0/miso_dlen.rs
+++ b/esp32/src/spi0/miso_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_dbitlen(&mut self) -> USR_MISO_DBITLEN_W<MISO_DLEN_SPEC> {
         USR_MISO_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/mosi_dlen.rs b/esp32/src/spi0/mosi_dlen.rs
index 06b68e65e7..d9fea551d3 100644
--- a/esp32/src/spi0/mosi_dlen.rs
+++ b/esp32/src/spi0/mosi_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_dbitlen(&mut self) -> USR_MOSI_DBITLEN_W<MOSI_DLEN_SPEC> {
         USR_MOSI_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/pin.rs b/esp32/src/spi0/pin.rs
index 726449cb4c..5e533030a7 100644
--- a/esp32/src/spi0/pin.rs
+++ b/esp32/src/spi0/pin.rs
@@ -103,7 +103,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<PIN_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -111,49 +110,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs0_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
         CS_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs1_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
         CS_DIS_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs2_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
         CS_DIS_W::new(self, 2)
     }
     #[doc = "Bit 5 - 1: spi clk out disable 0: spi clk out enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ck_dis(&mut self) -> CK_DIS_W<PIN_SPEC> {
         CK_DIS_W::new(self, 5)
     }
     #[doc = "Bits 6:8 - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol."]
     #[inline(always)]
-    #[must_use]
     pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<PIN_SPEC> {
         MASTER_CS_POL_W::new(self, 6)
     }
     #[doc = "Bits 11:13 - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis."]
     #[inline(always)]
-    #[must_use]
     pub fn master_ck_sel(&mut self) -> MASTER_CK_SEL_W<PIN_SPEC> {
         MASTER_CK_SEL_W::new(self, 11)
     }
     #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
     #[inline(always)]
-    #[must_use]
     pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<PIN_SPEC> {
         CK_IDLE_EDGE_W::new(self, 29)
     }
     #[doc = "Bit 30 - spi cs line keep low when the bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<PIN_SPEC> {
         CS_KEEP_ACTIVE_W::new(self, 30)
     }
diff --git a/esp32/src/spi0/rd_status.rs b/esp32/src/spi0/rd_status.rs
index c2cf114c7e..0cb38fcf93 100644
--- a/esp32/src/spi0/rd_status.rs
+++ b/esp32/src/spi0/rd_status.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<RD_STATUS_SPEC> {
         STATUS_W::new(self, 0)
     }
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."]
     #[inline(always)]
-    #[must_use]
     pub fn wb_mode(&mut self) -> WB_MODE_W<RD_STATUS_SPEC> {
         WB_MODE_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - In the slave mode,it is the status for master to read out."]
     #[inline(always)]
-    #[must_use]
     pub fn status_ext(&mut self) -> STATUS_EXT_W<RD_STATUS_SPEC> {
         STATUS_EXT_W::new(self, 24)
     }
diff --git a/esp32/src/spi0/slave.rs b/esp32/src/spi0/slave.rs
index 7bfdd2942e..f3f83e9235 100644
--- a/esp32/src/spi0/slave.rs
+++ b/esp32/src/spi0/slave.rs
@@ -158,73 +158,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<SLAVE_SPEC> {
         SLV_RD_BUF_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt raw bit for the completion of write-buffer operation in the slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<SLAVE_SPEC> {
         SLV_WR_BUF_DONE_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt raw bit for the completion of read-status operation in the slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_sta_done(&mut self) -> SLV_RD_STA_DONE_W<SLAVE_SPEC> {
         SLV_RD_STA_DONE_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt raw bit for the completion of write-status operation in the slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_sta_done(&mut self) -> SLV_WR_STA_DONE_W<SLAVE_SPEC> {
         SLV_WR_STA_DONE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done(&mut self) -> TRANS_DONE_W<SLAVE_SPEC> {
         TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bits 5:9 - Interrupt enable bits for the below 5 sources"]
     #[inline(always)]
-    #[must_use]
     pub fn int_en(&mut self) -> INT_EN_W<SLAVE_SPEC> {
         INT_EN_W::new(self, 5)
     }
     #[doc = "Bits 10:11 - In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_i_mode(&mut self) -> CS_I_MODE_W<SLAVE_SPEC> {
         CS_I_MODE_W::new(self, 10)
     }
     #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_define(&mut self) -> SLV_CMD_DEFINE_W<SLAVE_SPEC> {
         SLV_CMD_DEFINE_W::new(self, 27)
     }
     #[doc = "Bit 28 - write and read status enable in the slave mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_rd_sta_en(&mut self) -> SLV_WR_RD_STA_EN_W<SLAVE_SPEC> {
         SLV_WR_RD_STA_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - write and read buffer enable in the slave mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_rd_buf_en(&mut self) -> SLV_WR_RD_BUF_EN_W<SLAVE_SPEC> {
         SLV_WR_RD_BUF_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - 1: slave mode 0: master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
         MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_reset(&mut self) -> SYNC_RESET_W<SLAVE_SPEC> {
         SYNC_RESET_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/slave1.rs b/esp32/src/spi0/slave1.rs
index 3b55ea16e1..341dc15078 100644
--- a/esp32/src/spi0/slave1.rs
+++ b/esp32/src/spi0/slave1.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - In the slave mode it is the enable bit of dummy phase for read-buffer operations."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_dummy_en(&mut self) -> SLV_RDBUF_DUMMY_EN_W<SLAVE1_SPEC> {
         SLV_RDBUF_DUMMY_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - In the slave mode it is the enable bit of dummy phase for write-buffer operations."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_dummy_en(&mut self) -> SLV_WRBUF_DUMMY_EN_W<SLAVE1_SPEC> {
         SLV_WRBUF_DUMMY_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - In the slave mode it is the enable bit of dummy phase for read-status operations."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdsta_dummy_en(&mut self) -> SLV_RDSTA_DUMMY_EN_W<SLAVE1_SPEC> {
         SLV_RDSTA_DUMMY_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - In the slave mode it is the enable bit of dummy phase for write-status operations."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrsta_dummy_en(&mut self) -> SLV_WRSTA_DUMMY_EN_W<SLAVE1_SPEC> {
         SLV_WRSTA_DUMMY_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:9 - In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_addr_bitlen(&mut self) -> SLV_WR_ADDR_BITLEN_W<SLAVE1_SPEC> {
         SLV_WR_ADDR_BITLEN_W::new(self, 4)
     }
     #[doc = "Bits 10:15 - In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_addr_bitlen(&mut self) -> SLV_RD_ADDR_BITLEN_W<SLAVE1_SPEC> {
         SLV_RD_ADDR_BITLEN_W::new(self, 10)
     }
     #[doc = "Bit 25 - In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_status_readback(&mut self) -> SLV_STATUS_READBACK_W<SLAVE1_SPEC> {
         SLV_STATUS_READBACK_W::new(self, 25)
     }
     #[doc = "Bit 26 - In the slave mode enable fast read status."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_status_fast_en(&mut self) -> SLV_STATUS_FAST_EN_W<SLAVE1_SPEC> {
         SLV_STATUS_FAST_EN_W::new(self, 26)
     }
     #[doc = "Bits 27:31 - In the slave mode it is the length of status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_status_bitlen(&mut self) -> SLV_STATUS_BITLEN_W<SLAVE1_SPEC> {
         SLV_STATUS_BITLEN_W::new(self, 27)
     }
diff --git a/esp32/src/spi0/slave2.rs b/esp32/src/spi0/slave2.rs
index 8aebb47b51..f8ea6f408a 100644
--- a/esp32/src/spi0/slave2.rs
+++ b/esp32/src/spi0/slave2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdsta_dummy_cyclelen(&mut self) -> SLV_RDSTA_DUMMY_CYCLELEN_W<SLAVE2_SPEC> {
         SLV_RDSTA_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrsta_dummy_cyclelen(&mut self) -> SLV_WRSTA_DUMMY_CYCLELEN_W<SLAVE2_SPEC> {
         SLV_WRSTA_DUMMY_CYCLELEN_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_dummy_cyclelen(&mut self) -> SLV_RDBUF_DUMMY_CYCLELEN_W<SLAVE2_SPEC> {
         SLV_RDBUF_DUMMY_CYCLELEN_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_dummy_cyclelen(&mut self) -> SLV_WRBUF_DUMMY_CYCLELEN_W<SLAVE2_SPEC> {
         SLV_WRBUF_DUMMY_CYCLELEN_W::new(self, 24)
     }
diff --git a/esp32/src/spi0/slave3.rs b/esp32/src/spi0/slave3.rs
index 6af0e00d3b..dcb161a27e 100644
--- a/esp32/src/spi0/slave3.rs
+++ b/esp32/src/spi0/slave3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In the slave mode it is the value of read-buffer command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_cmd_value(&mut self) -> SLV_RDBUF_CMD_VALUE_W<SLAVE3_SPEC> {
         SLV_RDBUF_CMD_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - In the slave mode it is the value of write-buffer command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_cmd_value(&mut self) -> SLV_WRBUF_CMD_VALUE_W<SLAVE3_SPEC> {
         SLV_WRBUF_CMD_VALUE_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - In the slave mode it is the value of read-status command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdsta_cmd_value(&mut self) -> SLV_RDSTA_CMD_VALUE_W<SLAVE3_SPEC> {
         SLV_RDSTA_CMD_VALUE_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - In the slave mode it is the value of write-status command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrsta_cmd_value(&mut self) -> SLV_WRSTA_CMD_VALUE_W<SLAVE3_SPEC> {
         SLV_WRSTA_CMD_VALUE_W::new(self, 24)
     }
diff --git a/esp32/src/spi0/slv_rd_bit.rs b/esp32/src/spi0/slv_rd_bit.rs
index 9e8f84ff6a..fb3e924bfd 100644
--- a/esp32/src/spi0/slv_rd_bit.rs
+++ b/esp32/src/spi0/slv_rd_bit.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the bit length of read data. The value is the length - 1."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdata_bit(&mut self) -> SLV_RDATA_BIT_W<SLV_RD_BIT_SPEC> {
         SLV_RDATA_BIT_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/slv_rdbuf_dlen.rs b/esp32/src/spi0/slv_rdbuf_dlen.rs
index e0403ce27c..4850fbca8b 100644
--- a/esp32/src/spi0/slv_rdbuf_dlen.rs
+++ b/esp32/src/spi0/slv_rdbuf_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_dbitlen(&mut self) -> SLV_RDBUF_DBITLEN_W<SLV_RDBUF_DLEN_SPEC> {
         SLV_RDBUF_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/slv_wr_status.rs b/esp32/src/spi0/slv_wr_status.rs
index 0239ba1a60..d252d2e850 100644
--- a/esp32/src/spi0/slv_wr_status.rs
+++ b/esp32/src/spi0/slv_wr_status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_st(&mut self) -> SLV_WR_ST_W<SLV_WR_STATUS_SPEC> {
         SLV_WR_ST_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/slv_wrbuf_dlen.rs b/esp32/src/spi0/slv_wrbuf_dlen.rs
index d3377e310c..ea08030c2f 100644
--- a/esp32/src/spi0/slv_wrbuf_dlen.rs
+++ b/esp32/src/spi0/slv_wrbuf_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_dbitlen(&mut self) -> SLV_WRBUF_DBITLEN_W<SLV_WRBUF_DLEN_SPEC> {
         SLV_WRBUF_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/sram_cmd.rs b/esp32/src/spi0/sram_cmd.rs
index f37647f706..213ad45790 100644
--- a/esp32/src/spi0/sram_cmd.rs
+++ b/esp32/src/spi0/sram_cmd.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_dio(&mut self) -> SRAM_DIO_W<SRAM_CMD_SPEC> {
         SRAM_DIO_W::new(self, 0)
     }
     #[doc = "Bit 1 - For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_qio(&mut self) -> SRAM_QIO_W<SRAM_CMD_SPEC> {
         SRAM_QIO_W::new(self, 1)
     }
     #[doc = "Bit 4 - For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_rstio(&mut self) -> SRAM_RSTIO_W<SRAM_CMD_SPEC> {
         SRAM_RSTIO_W::new(self, 4)
     }
diff --git a/esp32/src/spi0/sram_drd_cmd.rs b/esp32/src/spi0/sram_drd_cmd.rs
index 4a05185684..252c308921 100644
--- a/esp32/src/spi0/sram_drd_cmd.rs
+++ b/esp32/src/spi0/sram_drd_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_VALUE_W<SRAM_DRD_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_BITLEN_W<SRAM_DRD_CMD_SPEC> {
diff --git a/esp32/src/spi0/sram_dwr_cmd.rs b/esp32/src/spi0/sram_dwr_cmd.rs
index 926de9628c..c012e9c953 100644
--- a/esp32/src/spi0/sram_dwr_cmd.rs
+++ b/esp32/src/spi0/sram_dwr_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the write command value of command phase for SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_VALUE_W<SRAM_DWR_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_BITLEN_W<SRAM_DWR_CMD_SPEC> {
diff --git a/esp32/src/spi0/tx_crc.rs b/esp32/src/spi0/tx_crc.rs
index 39676fbaf6..bc4b0e4421 100644
--- a/esp32/src/spi0/tx_crc.rs
+++ b/esp32/src/spi0/tx_crc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - For SPI1 the value of crc32 for 256 bits data."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<TX_CRC_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32/src/spi0/user.rs b/esp32/src/spi0/user.rs
index da28c0d016..eabfa23fa1 100644
--- a/esp32/src/spi0/user.rs
+++ b/esp32/src/spi0/user.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
         DOUTDIN_W::new(self, 0)
     }
     #[doc = "Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
         CS_HOLD_W::new(self, 4)
     }
     #[doc = "Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
         CS_SETUP_W::new(self, 5)
     }
     #[doc = "Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_i_edge(&mut self) -> CK_I_EDGE_W<USER_SPEC> {
         CK_I_EDGE_W::new(self, 6)
     }
     #[doc = "Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
         CK_OUT_EDGE_W::new(self, 7)
     }
     #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian"]
     #[inline(always)]
-    #[must_use]
     pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<USER_SPEC> {
         RD_BYTE_ORDER_W::new(self, 10)
     }
     #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian"]
     #[inline(always)]
-    #[must_use]
     pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<USER_SPEC> {
         WR_BYTE_ORDER_W::new(self, 11)
     }
     #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
         FWRITE_DUAL_W::new(self, 12)
     }
     #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
         FWRITE_QUAD_W::new(self, 13)
     }
     #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<USER_SPEC> {
         FWRITE_DIO_W::new(self, 14)
     }
     #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<USER_SPEC> {
         FWRITE_QIO_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
         SIO_W::new(self, 16)
     }
     #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<USER_SPEC> {
         USR_HOLD_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<USER_SPEC> {
         USR_DOUT_HOLD_W::new(self, 18)
     }
     #[doc = "Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<USER_SPEC> {
         USR_DIN_HOLD_W::new(self, 19)
     }
     #[doc = "Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<USER_SPEC> {
         USR_DUMMY_HOLD_W::new(self, 20)
     }
     #[doc = "Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<USER_SPEC> {
         USR_ADDR_HOLD_W::new(self, 21)
     }
     #[doc = "Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<USER_SPEC> {
         USR_CMD_HOLD_W::new(self, 22)
     }
     #[doc = "Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<USER_SPEC> {
         USR_PREP_HOLD_W::new(self, 23)
     }
     #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
         USR_MISO_HIGHPART_W::new(self, 24)
     }
     #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
         USR_MOSI_HIGHPART_W::new(self, 25)
     }
     #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
         USR_DUMMY_IDLE_W::new(self, 26)
     }
     #[doc = "Bit 27 - This bit enable the write-data phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
         USR_MOSI_W::new(self, 27)
     }
     #[doc = "Bit 28 - This bit enable the read-data phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
         USR_MISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
         USR_DUMMY_W::new(self, 29)
     }
     #[doc = "Bit 30 - This bit enable the address phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
         USR_ADDR_W::new(self, 30)
     }
     #[doc = "Bit 31 - This bit enable the command phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
         USR_COMMAND_W::new(self, 31)
     }
diff --git a/esp32/src/spi0/user1.rs b/esp32/src/spi0/user1.rs
index a55f5ac223..8149e6b652 100644
--- a/esp32/src/spi0/user1.rs
+++ b/esp32/src/spi0/user1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
         USR_ADDR_BITLEN_W::new(self, 26)
     }
diff --git a/esp32/src/spi0/user2.rs b/esp32/src/spi0/user2.rs
index 84bb04690b..e3e7c45b78 100644
--- a/esp32/src/spi0/user2.rs
+++ b/esp32/src/spi0/user2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<USER2_SPEC> {
         USR_COMMAND_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1)"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<USER2_SPEC> {
         USR_COMMAND_BITLEN_W::new(self, 28)
     }
diff --git a/esp32/src/spi0/w.rs b/esp32/src/spi0/w.rs
index 2d9fcca16d..88c8c5ce9c 100644
--- a/esp32/src/spi0/w.rs
+++ b/esp32/src/spi0/w.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - data buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn buf(&mut self) -> BUF_W<W_SPEC> {
         BUF_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/int_clr.rs b/esp32/src/timg0/int_clr.rs
index 7032ef83d9..7ded6f0f9a 100644
--- a/esp32/src/timg0/int_clr.rs
+++ b/esp32/src/timg0/int_clr.rs
@@ -17,7 +17,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -25,25 +24,21 @@ impl W {
     }
     #[doc = "Bit 0 - interrupt when timer0 alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - interrupt when timer1 alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt when an interrupt stage timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn lact(&mut self) -> LACT_W<INT_CLR_SPEC> {
         LACT_W::new(self, 3)
     }
@@ -57,7 +52,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0d;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32/src/timg0/int_ena.rs b/esp32/src/timg0/int_ena.rs
index 0d4f6cf43a..6d39b03f38 100644
--- a/esp32/src/timg0/int_ena.rs
+++ b/esp32/src/timg0/int_ena.rs
@@ -67,7 +67,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -75,25 +74,21 @@ impl W {
     }
     #[doc = "Bit 0 - interrupt when timer0 alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - interrupt when timer1 alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt when an interrupt stage timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn lact(&mut self) -> LACT_W<INT_ENA_SPEC> {
         LACT_W::new(self, 3)
     }
diff --git a/esp32/src/timg0/lactalarmhi.rs b/esp32/src/timg0/lactalarmhi.rs
index 4b57128048..ef12c792c1 100644
--- a/esp32/src/timg0/lactalarmhi.rs
+++ b/esp32/src/timg0/lactalarmhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_hi(&mut self) -> ALARM_HI_W<LACTALARMHI_SPEC> {
         ALARM_HI_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/lactalarmlo.rs b/esp32/src/timg0/lactalarmlo.rs
index 23386e6d6d..a206bb5907 100644
--- a/esp32/src/timg0/lactalarmlo.rs
+++ b/esp32/src/timg0/lactalarmlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_lo(&mut self) -> ALARM_LO_W<LACTALARMLO_SPEC> {
         ALARM_LO_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/lactconfig.rs b/esp32/src/timg0/lactconfig.rs
index 20e241cec1..b5acb613e6 100644
--- a/esp32/src/timg0/lactconfig.rs
+++ b/esp32/src/timg0/lactconfig.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_only(&mut self) -> RTC_ONLY_W<LACTCONFIG_SPEC> {
         RTC_ONLY_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn cpst_en(&mut self) -> CPST_EN_W<LACTCONFIG_SPEC> {
         CPST_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn lac_en(&mut self) -> LAC_EN_W<LACTCONFIG_SPEC> {
         LAC_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_en(&mut self) -> ALARM_EN_W<LACTCONFIG_SPEC> {
         ALARM_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn level_int_en(&mut self) -> LEVEL_INT_EN_W<LACTCONFIG_SPEC> {
         LEVEL_INT_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn edge_int_en(&mut self) -> EDGE_INT_EN_W<LACTCONFIG_SPEC> {
         EDGE_INT_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:28"]
     #[inline(always)]
-    #[must_use]
     pub fn divider(&mut self) -> DIVIDER_W<LACTCONFIG_SPEC> {
         DIVIDER_W::new(self, 13)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn autoreload(&mut self) -> AUTORELOAD_W<LACTCONFIG_SPEC> {
         AUTORELOAD_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn increase(&mut self) -> INCREASE_W<LACTCONFIG_SPEC> {
         INCREASE_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<LACTCONFIG_SPEC> {
         EN_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/lactload.rs b/esp32/src/timg0/lactload.rs
index caf07fb09a..badc8660ed 100644
--- a/esp32/src/timg0/lactload.rs
+++ b/esp32/src/timg0/lactload.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LACTLOAD_SPEC> {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LACTLOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/lactloadhi.rs b/esp32/src/timg0/lactloadhi.rs
index 4a156fea6b..9b430b3a0f 100644
--- a/esp32/src/timg0/lactloadhi.rs
+++ b/esp32/src/timg0/lactloadhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LACTLOADHI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/lactloadlo.rs b/esp32/src/timg0/lactloadlo.rs
index d06938be4b..b58ec221df 100644
--- a/esp32/src/timg0/lactloadlo.rs
+++ b/esp32/src/timg0/lactloadlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LACTLOADLO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/lactrtc.rs b/esp32/src/timg0/lactrtc.rs
index 41162856ff..981937b108 100644
--- a/esp32/src/timg0/lactrtc.rs
+++ b/esp32/src/timg0/lactrtc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 6:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_step_len(&mut self) -> RTC_STEP_LEN_W<LACTRTC_SPEC> {
         RTC_STEP_LEN_W::new(self, 6)
     }
diff --git a/esp32/src/timg0/lactupdate.rs b/esp32/src/timg0/lactupdate.rs
index 0be3a31933..1ed240d8c5 100644
--- a/esp32/src/timg0/lactupdate.rs
+++ b/esp32/src/timg0/lactupdate.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LACTUPDATE_SPEC> {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<LACTUPDATE_SPEC> {
         UPDATE_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/ntimers_date.rs b/esp32/src/timg0/ntimers_date.rs
index 8c7dc19fed..5b7b88355c 100644
--- a/esp32/src/timg0/ntimers_date.rs
+++ b/esp32/src/timg0/ntimers_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version of this regfile"]
     #[inline(always)]
-    #[must_use]
     pub fn ntimers_date(&mut self) -> NTIMERS_DATE_W<NTIMERS_DATE_SPEC> {
         NTIMERS_DATE_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/rtccalicfg.rs b/esp32/src/timg0/rtccalicfg.rs
index 0fa6c61504..231e48f5f3 100644
--- a/esp32/src/timg0/rtccalicfg.rs
+++ b/esp32/src/timg0/rtccalicfg.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start_cycling(&mut self) -> RTC_CALI_START_CYCLING_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_CYCLING_W::new(self, 12)
     }
     #[doc = "Bits 13:14"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_clk_sel(&mut self) -> RTC_CALI_CLK_SEL_W<RTCCALICFG_SPEC> {
         RTC_CALI_CLK_SEL_W::new(self, 13)
     }
     #[doc = "Bits 16:30"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_max(&mut self) -> RTC_CALI_MAX_W<RTCCALICFG_SPEC> {
         RTC_CALI_MAX_W::new(self, 16)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start(&mut self) -> RTC_CALI_START_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/t/alarmhi.rs b/esp32/src/timg0/t/alarmhi.rs
index 866d329edf..ae7f34f579 100644
--- a/esp32/src/timg0/t/alarmhi.rs
+++ b/esp32/src/timg0/t/alarmhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Timer 0 time-base counter value higher 32 bits that will trigger the alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_hi(&mut self) -> ALARM_HI_W<ALARMHI_SPEC> {
         ALARM_HI_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/t/alarmlo.rs b/esp32/src/timg0/t/alarmlo.rs
index 26a6c12414..a6f7b9fbf6 100644
--- a/esp32/src/timg0/t/alarmlo.rs
+++ b/esp32/src/timg0/t/alarmlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Timer 0 time-base counter value lower 32 bits that will trigger the alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_lo(&mut self) -> ALARM_LO_W<ALARMLO_SPEC> {
         ALARM_LO_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/t/config.rs b/esp32/src/timg0/t/config.rs
index 7257ced7dd..7a9d3f84a4 100644
--- a/esp32/src/timg0/t/config.rs
+++ b/esp32/src/timg0/t/config.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - When set alarm is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_en(&mut self) -> ALARM_EN_W<CONFIG_SPEC> {
         ALARM_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - When set level type interrupt will be generated during alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn level_int_en(&mut self) -> LEVEL_INT_EN_W<CONFIG_SPEC> {
         LEVEL_INT_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - When set edge type interrupt will be generated during alarm"]
     #[inline(always)]
-    #[must_use]
     pub fn edge_int_en(&mut self) -> EDGE_INT_EN_W<CONFIG_SPEC> {
         EDGE_INT_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:28 - Timer 0 clock (T0_clk) prescale value."]
     #[inline(always)]
-    #[must_use]
     pub fn divider(&mut self) -> DIVIDER_W<CONFIG_SPEC> {
         DIVIDER_W::new(self, 13)
     }
     #[doc = "Bit 29 - When set timer 0 auto-reload at alarming is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn autoreload(&mut self) -> AUTORELOAD_W<CONFIG_SPEC> {
         AUTORELOAD_W::new(self, 29)
     }
     #[doc = "Bit 30 - When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement."]
     #[inline(always)]
-    #[must_use]
     pub fn increase(&mut self) -> INCREASE_W<CONFIG_SPEC> {
         INCREASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - When set timer 0 time-base counter is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CONFIG_SPEC> {
         EN_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/t/load.rs b/esp32/src/timg0/t/load.rs
index 8f24496c3e..14c86f8f14 100644
--- a/esp32/src/timg0/t/load.rs
+++ b/esp32/src/timg0/t/load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LOAD_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value will trigger timer 0 time-base counter reload"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/t/loadhi.rs b/esp32/src/timg0/t/loadhi.rs
index 2475bcd6c7..3df8acfbcd 100644
--- a/esp32/src/timg0/t/loadhi.rs
+++ b/esp32/src/timg0/t/loadhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - higher 32 bits of the value that will load into timer 0 time-base counter"]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LOADHI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/t/loadlo.rs b/esp32/src/timg0/t/loadlo.rs
index cf24d306c4..9c62f49eef 100644
--- a/esp32/src/timg0/t/loadlo.rs
+++ b/esp32/src/timg0/t/loadlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Lower 32 bits of the value that will load into timer 0 time-base counter"]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LOADLO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/t/update.rs b/esp32/src/timg0/t/update.rs
index 8cea281c39..919bbec924 100644
--- a/esp32/src/timg0/t/update.rs
+++ b/esp32/src/timg0/t/update.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)"]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<UPDATE_SPEC> {
         UPDATE_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/timgclk.rs b/esp32/src/timg0/timgclk.rs
index fe6bcfad25..43936509bd 100644
--- a/esp32/src/timg0/timgclk.rs
+++ b/esp32/src/timg0/timgclk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Force clock enable for this regfile"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<TIMGCLK_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/wdtconfig0.rs b/esp32/src/timg0/wdtconfig0.rs
index 3ca19407d1..02efaa3e78 100644
--- a/esp32/src/timg0/wdtconfig0.rs
+++ b/esp32/src/timg0/wdtconfig0.rs
@@ -469,61 +469,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 14 - When set flash boot protection is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 14)
     }
     #[doc = "Bits 15:17 - length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 18)
     }
     #[doc = "Bit 21 - When set level type interrupt generation is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_LEVEL_INT_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - When set edge type interrupt generation is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EDGE_INT_EN_W::new(self, 22)
     }
     #[doc = "Bits 23:24 - Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 29)
     }
     #[doc = "Bit 31 - When set SWDT is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32/src/timg0/wdtconfig1.rs b/esp32/src/timg0/wdtconfig1.rs
index 1c86f5576b..8d95afa48f 100644
--- a/esp32/src/timg0/wdtconfig1.rs
+++ b/esp32/src/timg0/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:31 - SWDT clock prescale value. Period = 12.5ns * value stored in this register"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_clk_prescale(&mut self) -> WDT_CLK_PRESCALE_W<WDTCONFIG1_SPEC> {
         WDT_CLK_PRESCALE_W::new(self, 16)
     }
diff --git a/esp32/src/timg0/wdtconfig2.rs b/esp32/src/timg0/wdtconfig2.rs
index 92405c7a27..4e224504ac 100644
--- a/esp32/src/timg0/wdtconfig2.rs
+++ b/esp32/src/timg0/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value in SWDT clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/wdtconfig3.rs b/esp32/src/timg0/wdtconfig3.rs
index a20667407d..999b1a4584 100644
--- a/esp32/src/timg0/wdtconfig3.rs
+++ b/esp32/src/timg0/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value in SWDT clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/wdtconfig4.rs b/esp32/src/timg0/wdtconfig4.rs
index f8b7470d95..b2382d588c 100644
--- a/esp32/src/timg0/wdtconfig4.rs
+++ b/esp32/src/timg0/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value in SWDT clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/wdtconfig5.rs b/esp32/src/timg0/wdtconfig5.rs
index e3b9499922..48647c1b24 100644
--- a/esp32/src/timg0/wdtconfig5.rs
+++ b/esp32/src/timg0/wdtconfig5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value in SWDT clock cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG5_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/wdtfeed.rs b/esp32/src/timg0/wdtfeed.rs
index 5695164d71..c000a6d019 100644
--- a/esp32/src/timg0/wdtfeed.rs
+++ b/esp32/src/timg0/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value will feed SWDT"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 0)
     }
diff --git a/esp32/src/timg0/wdtwprotect.rs b/esp32/src/timg0/wdtwprotect.rs
index 4cb67cc122..aa11612115 100644
--- a/esp32/src/timg0/wdtwprotect.rs
+++ b/esp32/src/timg0/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - If change its value from default then write protection is on."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/bus_timing_0.rs b/esp32/src/twai0/bus_timing_0.rs
index c0fb1dde40..54c99a489f 100644
--- a/esp32/src/twai0/bus_timing_0.rs
+++ b/esp32/src/twai0/bus_timing_0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
-    #[must_use]
     pub fn baud_presc(&mut self) -> BAUD_PRESC_W<BUS_TIMING_0_SPEC> {
         BAUD_PRESC_W::new(self, 0)
     }
     #[doc = "Bits 6:7 - Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_jump_width(&mut self) -> SYNC_JUMP_WIDTH_W<BUS_TIMING_0_SPEC> {
         SYNC_JUMP_WIDTH_W::new(self, 6)
     }
diff --git a/esp32/src/twai0/bus_timing_1.rs b/esp32/src/twai0/bus_timing_1.rs
index edd5e6575c..387797e218 100644
--- a/esp32/src/twai0/bus_timing_1.rs
+++ b/esp32/src/twai0/bus_timing_1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg1(&mut self) -> TIME_SEG1_W<BUS_TIMING_1_SPEC> {
         TIME_SEG1_W::new(self, 0)
     }
     #[doc = "Bits 4:6 - The width of PBS2."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg2(&mut self) -> TIME_SEG2_W<BUS_TIMING_1_SPEC> {
         TIME_SEG2_W::new(self, 4)
     }
     #[doc = "Bit 7 - The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times"]
     #[inline(always)]
-    #[must_use]
     pub fn time_samp(&mut self) -> TIME_SAMP_W<BUS_TIMING_1_SPEC> {
         TIME_SAMP_W::new(self, 7)
     }
diff --git a/esp32/src/twai0/clock_divider.rs b/esp32/src/twai0/clock_divider.rs
index 44b86c2f02..e4352a1719 100644
--- a/esp32/src/twai0/clock_divider.rs
+++ b/esp32/src/twai0/clock_divider.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
-    #[must_use]
     pub fn cd(&mut self) -> CD_W<CLOCK_DIVIDER_SPEC> {
         CD_W::new(self, 0)
     }
     #[doc = "Bit 3 - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
     #[inline(always)]
-    #[must_use]
     pub fn clock_off(&mut self) -> CLOCK_OFF_W<CLOCK_DIVIDER_SPEC> {
         CLOCK_OFF_W::new(self, 3)
     }
     #[doc = "Bit 7 - This bit can be configured under reset mode. 1: Extended mode, compatiable with CAN2.0B; 0: Basic mode"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_mode(&mut self) -> EXT_MODE_W<CLOCK_DIVIDER_SPEC> {
         EXT_MODE_W::new(self, 7)
     }
diff --git a/esp32/src/twai0/cmd.rs b/esp32/src/twai0/cmd.rs
index 9dec5c5851..7f85b98347 100644
--- a/esp32/src/twai0/cmd.rs
+++ b/esp32/src/twai0/cmd.rs
@@ -19,31 +19,26 @@ impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set the bit to 1 to allow the driving nodes start transmission."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_req(&mut self) -> TX_REQ_W<CMD_SPEC> {
         TX_REQ_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to 1 to cancel a pending transmission request."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_tx(&mut self) -> ABORT_TX_W<CMD_SPEC> {
         ABORT_TX_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to 1 to release the RX buffer."]
     #[inline(always)]
-    #[must_use]
     pub fn release_buf(&mut self) -> RELEASE_BUF_W<CMD_SPEC> {
         RELEASE_BUF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to 1 to clear the data overrun status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn clr_overrun(&mut self) -> CLR_OVERRUN_W<CMD_SPEC> {
         CLR_OVERRUN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously."]
     #[inline(always)]
-    #[must_use]
     pub fn self_rx_req(&mut self) -> SELF_RX_REQ_W<CMD_SPEC> {
         SELF_RX_REQ_W::new(self, 4)
     }
diff --git a/esp32/src/twai0/data_0.rs b/esp32/src/twai0/data_0.rs
index 9da54a5102..0d31668320 100644
--- a/esp32/src/twai0/data_0.rs
+++ b/esp32/src/twai0/data_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_0(&mut self) -> TX_BYTE_0_W<DATA_0_SPEC> {
         TX_BYTE_0_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_1.rs b/esp32/src/twai0/data_1.rs
index 4fca4af070..b45d9c5e99 100644
--- a/esp32/src/twai0/data_1.rs
+++ b/esp32/src/twai0/data_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_1(&mut self) -> TX_BYTE_1_W<DATA_1_SPEC> {
         TX_BYTE_1_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_10.rs b/esp32/src/twai0/data_10.rs
index d3a1181d8d..756d4b4006 100644
--- a/esp32/src/twai0/data_10.rs
+++ b/esp32/src/twai0/data_10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_10(&mut self) -> TX_BYTE_10_W<DATA_10_SPEC> {
         TX_BYTE_10_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_11.rs b/esp32/src/twai0/data_11.rs
index a07192b292..80e75ecb8f 100644
--- a/esp32/src/twai0/data_11.rs
+++ b/esp32/src/twai0/data_11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_11(&mut self) -> TX_BYTE_11_W<DATA_11_SPEC> {
         TX_BYTE_11_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_12.rs b/esp32/src/twai0/data_12.rs
index c6b1c97f51..20646c57b9 100644
--- a/esp32/src/twai0/data_12.rs
+++ b/esp32/src/twai0/data_12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_12(&mut self) -> TX_BYTE_12_W<DATA_12_SPEC> {
         TX_BYTE_12_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_2.rs b/esp32/src/twai0/data_2.rs
index 3179326e84..0c7db88aa8 100644
--- a/esp32/src/twai0/data_2.rs
+++ b/esp32/src/twai0/data_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_2(&mut self) -> TX_BYTE_2_W<DATA_2_SPEC> {
         TX_BYTE_2_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_3.rs b/esp32/src/twai0/data_3.rs
index b639a7b9bf..e7df26464e 100644
--- a/esp32/src/twai0/data_3.rs
+++ b/esp32/src/twai0/data_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_3(&mut self) -> TX_BYTE_3_W<DATA_3_SPEC> {
         TX_BYTE_3_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_4.rs b/esp32/src/twai0/data_4.rs
index 4f473f3008..90ff6b33db 100644
--- a/esp32/src/twai0/data_4.rs
+++ b/esp32/src/twai0/data_4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_4(&mut self) -> TX_BYTE_4_W<DATA_4_SPEC> {
         TX_BYTE_4_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_5.rs b/esp32/src/twai0/data_5.rs
index c622efb8c4..7f9f1e5590 100644
--- a/esp32/src/twai0/data_5.rs
+++ b/esp32/src/twai0/data_5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_5(&mut self) -> TX_BYTE_5_W<DATA_5_SPEC> {
         TX_BYTE_5_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_6.rs b/esp32/src/twai0/data_6.rs
index 994c3b5883..73a15eebef 100644
--- a/esp32/src/twai0/data_6.rs
+++ b/esp32/src/twai0/data_6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_6(&mut self) -> TX_BYTE_6_W<DATA_6_SPEC> {
         TX_BYTE_6_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_7.rs b/esp32/src/twai0/data_7.rs
index 28c5d98ef9..c637a8aa7b 100644
--- a/esp32/src/twai0/data_7.rs
+++ b/esp32/src/twai0/data_7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_7(&mut self) -> TX_BYTE_7_W<DATA_7_SPEC> {
         TX_BYTE_7_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_8.rs b/esp32/src/twai0/data_8.rs
index 45046802aa..3d1d76d086 100644
--- a/esp32/src/twai0/data_8.rs
+++ b/esp32/src/twai0/data_8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_8(&mut self) -> TX_BYTE_8_W<DATA_8_SPEC> {
         TX_BYTE_8_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/data_9.rs b/esp32/src/twai0/data_9.rs
index 09d489b574..7a9e68c967 100644
--- a/esp32/src/twai0/data_9.rs
+++ b/esp32/src/twai0/data_9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_9(&mut self) -> TX_BYTE_9_W<DATA_9_SPEC> {
         TX_BYTE_9_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/err_warning_limit.rs b/esp32/src/twai0/err_warning_limit.rs
index 4a0c61301c..df1aa0b277 100644
--- a/esp32/src/twai0/err_warning_limit.rs
+++ b/esp32/src/twai0/err_warning_limit.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warning_limit(&mut self) -> ERR_WARNING_LIMIT_W<ERR_WARNING_LIMIT_SPEC> {
         ERR_WARNING_LIMIT_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/int_ena.rs b/esp32/src/twai0/int_ena.rs
index 8241d7fde8..b95bee9c9f 100644
--- a/esp32/src/twai0/int_ena.rs
+++ b/esp32/src/twai0/int_ena.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_int_ena(&mut self) -> RX_INT_ENA_W<INT_ENA_SPEC> {
         RX_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to 1 to enable transmit interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_int_ena(&mut self) -> TX_INT_ENA_W<INT_ENA_SPEC> {
         TX_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable error warning interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warn_int_ena(&mut self) -> ERR_WARN_INT_ENA_W<INT_ENA_SPEC> {
         ERR_WARN_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable data overrun interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn overrun_int_ena(&mut self) -> OVERRUN_INT_ENA_W<INT_ENA_SPEC> {
         OVERRUN_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 4 - THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise"]
     #[inline(always)]
-    #[must_use]
     pub fn brp_div(&mut self) -> BRP_DIV_W<INT_ENA_SPEC> {
         BRP_DIV_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable error passive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INT_ENA_SPEC> {
         ERR_PASSIVE_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to 1 to enable arbitration lost interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arb_lost_int_ena(&mut self) -> ARB_LOST_INT_ENA_W<INT_ENA_SPEC> {
         ARB_LOST_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to 1 to enable error interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INT_ENA_SPEC> {
         BUS_ERR_INT_ENA_W::new(self, 7)
     }
diff --git a/esp32/src/twai0/mode.rs b/esp32/src/twai0/mode.rs
index ddce5ed67c..deebf1574c 100644
--- a/esp32/src/twai0/mode.rs
+++ b/esp32/src/twai0/mode.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn reset_mode(&mut self) -> RESET_MODE_W<MODE_SPEC> {
         RESET_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter."]
     #[inline(always)]
-    #[must_use]
     pub fn listen_only_mode(&mut self) -> LISTEN_ONLY_MODE_W<MODE_SPEC> {
         LISTEN_ONLY_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command."]
     #[inline(always)]
-    #[must_use]
     pub fn self_test_mode(&mut self) -> SELF_TEST_MODE_W<MODE_SPEC> {
         SELF_TEST_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_mode(&mut self) -> RX_FILTER_MODE_W<MODE_SPEC> {
         RX_FILTER_MODE_W::new(self, 3)
     }
diff --git a/esp32/src/twai0/rx_err_cnt.rs b/esp32/src/twai0/rx_err_cnt.rs
index 0e7eedf680..b421e30b14 100644
--- a/esp32/src/twai0/rx_err_cnt.rs
+++ b/esp32/src/twai0/rx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_err_cnt(&mut self) -> RX_ERR_CNT_W<RX_ERR_CNT_SPEC> {
         RX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32/src/twai0/tx_err_cnt.rs b/esp32/src/twai0/tx_err_cnt.rs
index 64ad2e844e..59fbc2d773 100644
--- a/esp32/src/twai0/tx_err_cnt.rs
+++ b/esp32/src/twai0/tx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_err_cnt(&mut self) -> TX_ERR_CNT_W<TX_ERR_CNT_SPEC> {
         TX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/at_cmd_char.rs b/esp32/src/uart0/at_cmd_char.rs
index 53d46fc04a..0956b75cdf 100644
--- a/esp32/src/uart0/at_cmd_char.rs
+++ b/esp32/src/uart0/at_cmd_char.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W<AT_CMD_CHAR_SPEC> {
         AT_CMD_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to configure the num of continous at_cmd chars received by receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn char_num(&mut self) -> CHAR_NUM_W<AT_CMD_CHAR_SPEC> {
         CHAR_NUM_W::new(self, 8)
     }
diff --git a/esp32/src/uart0/at_cmd_gaptout.rs b/esp32/src/uart0/at_cmd_gaptout.rs
index a9d08bed20..8f13fa1626 100644
--- a/esp32/src/uart0/at_cmd_gaptout.rs
+++ b/esp32/src/uart0/at_cmd_gaptout.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W<AT_CMD_GAPTOUT_SPEC> {
         RX_GAP_TOUT_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/at_cmd_postcnt.rs b/esp32/src/uart0/at_cmd_postcnt.rs
index 6418d3d365..faef65087b 100644
--- a/esp32/src/uart0/at_cmd_postcnt.rs
+++ b/esp32/src/uart0/at_cmd_postcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char."]
     #[inline(always)]
-    #[must_use]
     pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W<AT_CMD_POSTCNT_SPEC> {
         POST_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/at_cmd_precnt.rs b/esp32/src/uart0/at_cmd_precnt.rs
index 4977216dba..8bbbe4d1b7 100644
--- a/esp32/src/uart0/at_cmd_precnt.rs
+++ b/esp32/src/uart0/at_cmd_precnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W<AT_CMD_PRECNT_SPEC> {
         PRE_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/autobaud.rs b/esp32/src/uart0/autobaud.rs
index f6fe2f2499..2cdf79109b 100644
--- a/esp32/src/uart0/autobaud.rs
+++ b/esp32/src/uart0/autobaud.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit for detecting baudrate."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<AUTOBAUD_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_filt(&mut self) -> GLITCH_FILT_W<AUTOBAUD_SPEC> {
         GLITCH_FILT_W::new(self, 8)
     }
diff --git a/esp32/src/uart0/clkdiv.rs b/esp32/src/uart0/clkdiv.rs
index 4f3840bcec..7fc118a456 100644
--- a/esp32/src/uart0/clkdiv.rs
+++ b/esp32/src/uart0/clkdiv.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The register value is the integer part of the frequency divider's factor."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SPEC> {
         CLKDIV_W::new(self, 0)
     }
     #[doc = "Bits 20:23 - The register value is the decimal part of the frequency divider's factor."]
     #[inline(always)]
-    #[must_use]
     pub fn frag(&mut self) -> FRAG_W<CLKDIV_SPEC> {
         FRAG_W::new(self, 20)
     }
diff --git a/esp32/src/uart0/conf0.rs b/esp32/src/uart0/conf0.rs
index 54368a967c..ef4fa29f2f 100644
--- a/esp32/src/uart0/conf0.rs
+++ b/esp32/src/uart0/conf0.rs
@@ -274,157 +274,131 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode. 0:even 1:odd"]
     #[inline(always)]
-    #[must_use]
     pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
         PARITY_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable uart parity check."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
         PARITY_EN_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits"]
     #[inline(always)]
-    #[must_use]
     pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
         BIT_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits"]
     #[inline(always)]
-    #[must_use]
     pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
         STOP_BIT_NUM_W::new(self, 4)
     }
     #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
         SW_RTS_W::new(self, 6)
     }
     #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control.."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF0_SPEC> {
         SW_DTR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enbale transmitter to send 0 when the process of sending data is done."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
         TXD_BRK_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable irda loopback mode."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
         IRDA_DPLX_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the start enable bit for irda transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
         IRDA_TX_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
         IRDA_WCTL_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to inverse the level value of irda transmitter's level."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
         IRDA_TX_INV_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to inverse the level value of irda receiver's level."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
         IRDA_RX_INV_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
     #[inline(always)]
-    #[must_use]
     pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
         LOOPBACK_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable transmitter's flow control function."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
         TX_FLOW_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to enable irda protocol."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
         IRDA_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to reset uart receiver's fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
         RXFIFO_RST_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to reset uart transmitter's fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
         TXFIFO_RST_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
         RXD_INV_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_inv(&mut self) -> CTS_INV_W<CONF0_SPEC> {
         CTS_INV_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF0_SPEC> {
         DSR_INV_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
         TXD_INV_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rts_inv(&mut self) -> RTS_INV_W<CONF0_SPEC> {
         RTS_INV_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF0_SPEC> {
         DTR_INV_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1.force clock on for registers.support clock only when write registers"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong."]
     #[inline(always)]
-    #[must_use]
     pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
         ERR_WR_MASK_W::new(self, 26)
     }
     #[doc = "Bit 27 - This register is used to select the clock.1.apb clock 0:ref_tick"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_ref_always_on(&mut self) -> TICK_REF_ALWAYS_ON_W<CONF0_SPEC> {
         TICK_REF_ALWAYS_ON_W::new(self, 27)
     }
diff --git a/esp32/src/uart0/conf1.rs b/esp32/src/uart0/conf1.rs
index bcd5ab62d1..a976f1e662 100644
--- a/esp32/src/uart0/conf1.rs
+++ b/esp32/src/uart0/conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd)."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<CONF1_SPEC> {
         RXFIFO_FULL_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 8:14 - when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<CONF1_SPEC> {
         TXFIFO_EMPTY_THRHD_W::new(self, 8)
     }
     #[doc = "Bits 16:22 - when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W<CONF1_SPEC> {
         RX_FLOW_THRHD_W::new(self, 16)
     }
     #[doc = "Bit 23 - This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<CONF1_SPEC> {
         RX_FLOW_EN_W::new(self, 23)
     }
     #[doc = "Bits 24:30 - This register is used to configure the timeout value for uart receiver receiving a byte."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W<CONF1_SPEC> {
         RX_TOUT_THRHD_W::new(self, 24)
     }
     #[doc = "Bit 31 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<CONF1_SPEC> {
         RX_TOUT_EN_W::new(self, 31)
     }
diff --git a/esp32/src/uart0/date.rs b/esp32/src/uart0/date.rs
index 548abf5c55..de9377a7bd 100644
--- a/esp32/src/uart0/date.rs
+++ b/esp32/src/uart0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/fifo.rs b/esp32/src/uart0/fifo.rs
index 4807221a00..18b603a593 100644
--- a/esp32/src/uart0/fifo.rs
+++ b/esp32/src/uart0/fifo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register stores one byte data read by rx fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rd_byte(&mut self) -> RXFIFO_RD_BYTE_W<FIFO_SPEC> {
         RXFIFO_RD_BYTE_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/flow_conf.rs b/esp32/src/uart0/flow_conf.rs
index ac2c57cf96..9d28b6ae6d 100644
--- a/esp32/src/uart0/flow_conf.rs
+++ b/esp32/src/uart0/flow_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff ."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W<FLOW_CONF_SPEC> {
         SW_FLOW_CON_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to remove flow control char from the received data."]
     #[inline(always)]
-    #[must_use]
     pub fn xonoff_del(&mut self) -> XONOFF_DEL_W<FLOW_CONF_SPEC> {
         XONOFF_DEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear ctsn to stop the transmitter from sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xon(&mut self) -> FORCE_XON_W<FLOW_CONF_SPEC> {
         FORCE_XON_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to set ctsn to enable the transmitter to go on sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xoff(&mut self) -> FORCE_XOFF_W<FLOW_CONF_SPEC> {
         FORCE_XOFF_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to send xon char. it is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xon(&mut self) -> SEND_XON_W<FLOW_CONF_SPEC> {
         SEND_XON_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to send xoff char. it is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xoff(&mut self) -> SEND_XOFF_W<FLOW_CONF_SPEC> {
         SEND_XOFF_W::new(self, 5)
     }
diff --git a/esp32/src/uart0/id.rs b/esp32/src/uart0/id.rs
index 2311895150..b0e9a357d4 100644
--- a/esp32/src/uart0/id.rs
+++ b/esp32/src/uart0/id.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn id(&mut self) -> ID_W<ID_SPEC> {
         ID_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/idle_conf.rs b/esp32/src/uart0/idle_conf.rs
index 07227da622..03bc8b79cc 100644
--- a/esp32/src/uart0/idle_conf.rs
+++ b/esp32/src/uart0/idle_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W<IDLE_CONF_SPEC> {
         RX_IDLE_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W<IDLE_CONF_SPEC> {
         TX_IDLE_NUM_W::new(self, 10)
     }
     #[doc = "Bits 20:27 - This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W<IDLE_CONF_SPEC> {
         TX_BRK_NUM_W::new(self, 20)
     }
diff --git a/esp32/src/uart0/int_clr.rs b/esp32/src/uart0/int_clr.rs
index fd834e8625..c015b9a282 100644
--- a/esp32/src/uart0/int_clr.rs
+++ b/esp32/src/uart0/int_clr.rs
@@ -47,115 +47,96 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the sw_xon_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the rs485_clash_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
diff --git a/esp32/src/uart0/int_ena.rs b/esp32/src/uart0/int_ena.rs
index c8663dd3a1..cf02ec6f2c 100644
--- a/esp32/src/uart0/int_ena.rs
+++ b/esp32/src/uart0/int_ena.rs
@@ -204,115 +204,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_ENA_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_ENA_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_ENA_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_ENA_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_ENA_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_ENA_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_ENA_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_ENA_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_ENA_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_ENA_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_ENA_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_ENA_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_ENA_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_ENA_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
diff --git a/esp32/src/uart0/mem_conf.rs b/esp32/src/uart0/mem_conf.rs
index d053a03d45..6675e09418 100644
--- a/esp32/src/uart0/mem_conf.rs
+++ b/esp32/src/uart0/mem_conf.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_pd(&mut self) -> MEM_PD_W<MEM_CONF_SPEC> {
         MEM_PD_W::new(self, 0)
     }
     #[doc = "Bits 3:6 - This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_size(&mut self) -> RX_SIZE_W<MEM_CONF_SPEC> {
         RX_SIZE_W::new(self, 3)
     }
     #[doc = "Bits 7:10 - This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_size(&mut self) -> TX_SIZE_W<MEM_CONF_SPEC> {
         TX_SIZE_W::new(self, 7)
     }
     #[doc = "Bits 15:17 - Refer to the rx_flow_thrhd's description."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_thrhd_h3(&mut self) -> RX_FLOW_THRHD_H3_W<MEM_CONF_SPEC> {
         RX_FLOW_THRHD_H3_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - Refer to the rx_tout_thrhd's description."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_thrhd_h3(&mut self) -> RX_TOUT_THRHD_H3_W<MEM_CONF_SPEC> {
         RX_TOUT_THRHD_H3_W::new(self, 18)
     }
     #[doc = "Bits 21:22 - Refer to the uart_xon_threshold's description."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_threshold_h2(&mut self) -> XON_THRESHOLD_H2_W<MEM_CONF_SPEC> {
         XON_THRESHOLD_H2_W::new(self, 21)
     }
     #[doc = "Bits 23:24 - Refer to the uart_xoff_threshold's description."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_threshold_h2(&mut self) -> XOFF_THRESHOLD_H2_W<MEM_CONF_SPEC> {
         XOFF_THRESHOLD_H2_W::new(self, 23)
     }
     #[doc = "Bits 25:27 - Refer to the rxfifo_full_thrhd's description."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mem_full_thrhd(&mut self) -> RX_MEM_FULL_THRHD_W<MEM_CONF_SPEC> {
         RX_MEM_FULL_THRHD_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - Refer to txfifo_empty_thrhd's description."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mem_empty_thrhd(&mut self) -> TX_MEM_EMPTY_THRHD_W<MEM_CONF_SPEC> {
         TX_MEM_EMPTY_THRHD_W::new(self, 28)
     }
diff --git a/esp32/src/uart0/rs485_conf.rs b/esp32/src/uart0/rs485_conf.rs
index ef385fa8b0..c8dec3c09e 100644
--- a/esp32/src/uart0/rs485_conf.rs
+++ b/esp32/src/uart0/rs485_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to choose rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_en(&mut self) -> RS485_EN_W<RS485_CONF_SPEC> {
         RS485_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl0_en(&mut self) -> DL0_EN_W<RS485_CONF_SPEC> {
         DL0_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl1_en(&mut self) -> DL1_EN_W<RS485_CONF_SPEC> {
         DL1_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable loopback transmitter's output data signal to receiver's input data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485tx_rx_en(&mut self) -> RS485TX_RX_EN_W<RS485_CONF_SPEC> {
         RS485TX_RX_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485rxby_tx_en(&mut self) -> RS485RXBY_TX_EN_W<RS485_CONF_SPEC> {
         RS485RXBY_TX_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - This register is used to delay the receiver's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_rx_dly_num(&mut self) -> RS485_RX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_RX_DLY_NUM_W::new(self, 5)
     }
     #[doc = "Bits 6:9 - This register is used to delay the transmitter's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_tx_dly_num(&mut self) -> RS485_TX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_TX_DLY_NUM_W::new(self, 6)
     }
diff --git a/esp32/src/uart0/sleep_conf.rs b/esp32/src/uart0/sleep_conf.rs
index 41c9ab75ad..c618d326da 100644
--- a/esp32/src/uart0/sleep_conf.rs
+++ b/esp32/src/uart0/sleep_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - When the input rxd edge changes more than this register value. the uart is active from light sleeping mode."]
     #[inline(always)]
-    #[must_use]
     pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W<SLEEP_CONF_SPEC> {
         ACTIVE_THRESHOLD_W::new(self, 0)
     }
diff --git a/esp32/src/uart0/swfc_conf.rs b/esp32/src/uart0/swfc_conf.rs
index 81d4fdbb68..d0efc3162e 100644
--- a/esp32/src/uart0/swfc_conf.rs
+++ b/esp32/src/uart0/swfc_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W<SWFC_CONF_SPEC> {
         XON_THRESHOLD_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W<SWFC_CONF_SPEC> {
         XOFF_THRESHOLD_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - This register stores the xon flow control char."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_char(&mut self) -> XON_CHAR_W<SWFC_CONF_SPEC> {
         XON_CHAR_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - This register stores the xoff flow control char."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_char(&mut self) -> XOFF_CHAR_W<SWFC_CONF_SPEC> {
         XOFF_CHAR_W::new(self, 24)
     }
diff --git a/esp32/src/uhci0/ahb_test.rs b/esp32/src/uhci0/ahb_test.rs
index 8fc21822b7..0262067e33 100644
--- a/esp32/src/uhci0/ahb_test.rs
+++ b/esp32/src/uhci0/ahb_test.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
         AHB_TESTMODE_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - The two bits represent ahb bus address bit\\[20:19\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
         AHB_TESTADDR_W::new(self, 4)
     }
diff --git a/esp32/src/uhci0/conf0.rs b/esp32/src/uhci0/conf0.rs
index 36a4352bac..b3cc801477 100644
--- a/esp32/src/uhci0/conf0.rs
+++ b/esp32/src/uhci0/conf0.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in link operations."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<CONF0_SPEC> {
         IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset out link operations."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<CONF0_SPEC> {
         OUT_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset dma ahb fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<CONF0_SPEC> {
         AHBM_FIFO_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset dma ahb interface."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<CONF0_SPEC> {
         AHBM_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable loop test for in links."]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<CONF0_SPEC> {
         IN_LOOP_TEST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable loop test for out links."]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<CONF0_SPEC> {
         OUT_LOOP_TEST_W::new(self, 5)
     }
     #[doc = "Bit 6 - when in link's length is 0 go on to use the next in link automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<CONF0_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 6)
     }
     #[doc = "Bit 7 - don't use"]
     #[inline(always)]
-    #[must_use]
     pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<CONF0_SPEC> {
         OUT_NO_RESTART_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<CONF0_SPEC> {
         OUT_EOF_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to use UART to transmit or receive data."]
     #[inline(always)]
-    #[must_use]
     pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
         UART0_CE_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to use UART1 to transmit or receive data."]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
         UART1_CE_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to use UART2 to transmit or receive data."]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_ce(&mut self) -> UART2_CE_W<CONF0_SPEC> {
         UART2_CE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to enable DMA in links to use burst mode."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<CONF0_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to enable DMA out links to use burst mode."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<CONF0_SPEC> {
         INDSCR_BURST_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable DMA burst MODE"]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<CONF0_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<CONF0_SPEC> {
         MEM_TRANS_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to use special char to separate the data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
         SEPER_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to enable to use head packet before the data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
         HEAD_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame"]
     #[inline(always)]
-    #[must_use]
     pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
         CRC_REC_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
         UART_IDLE_EOF_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
         LEN_EOF_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
         ENCODE_CRC_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to enable clock-gating for read or write registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to enable to use brk char as the end of a data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
         UART_RX_BRK_EOF_EN_W::new(self, 23)
     }
diff --git a/esp32/src/uhci0/conf1.rs b/esp32/src/uhci0/conf1.rs
index 0d4f316381..4390b7cf1d 100644
--- a/esp32/src/uhci0/conf1.rs
+++ b/esp32/src/uhci0/conf1.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable decoder to check check_sum in packet header."]
     #[inline(always)]
-    #[must_use]
     pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
         CHECK_SUM_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable decoder to check seq num in packet header."]
     #[inline(always)]
-    #[must_use]
     pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
         CHECK_SEQ_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to disable crc calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
         CRC_DISABLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to save packet header ."]
     #[inline(always)]
-    #[must_use]
     pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
         SAVE_HEAD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable hardware replace check_sum in packet header automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
         TX_CHECK_SUM_RE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable hardware replace ack num in packet header automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
         TX_ACK_NUM_RE_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to check the owner bit in link descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn check_owner(&mut self) -> CHECK_OWNER_W<CONF1_SPEC> {
         CHECK_OWNER_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable software way to add packet header."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
         WAIT_SW_START_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to start inserting the packet header."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
         SW_START_W::new(self, 8)
     }
     #[doc = "Bits 9:20 - when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<CONF1_SPEC> {
         DMA_INFIFO_FULL_THRS_W::new(self, 9)
     }
diff --git a/esp32/src/uhci0/date.rs b/esp32/src/uhci0/date.rs
index f1af596836..6d4992e8d0 100644
--- a/esp32/src/uhci0/date.rs
+++ b/esp32/src/uhci0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - version information"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32/src/uhci0/dma_in_link.rs b/esp32/src/uhci0/dma_in_link.rs
index 76716cdc79..3f1f3c357d 100644
--- a/esp32/src/uhci0/dma_in_link.rs
+++ b/esp32/src/uhci0/dma_in_link.rs
@@ -72,31 +72,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register stores the least 20 bits of the first in link descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<DMA_IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - 1:when a packet is wrong in link descriptor returns to the descriptor which is lately used."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<DMA_IN_LINK_SPEC> {
         INLINK_AUTO_RET_W::new(self, 20)
     }
     #[doc = "Bit 28 - Set this bit to stop dealing with the in link descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<DMA_IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start dealing with the in link descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<DMA_IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to mount on new in link descriptors"]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<DMA_IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/uhci0/dma_in_pop.rs b/esp32/src/uhci0/dma_in_pop.rs
index 5dc3e4ca1b..3c8608a105 100644
--- a/esp32/src/uhci0/dma_in_pop.rs
+++ b/esp32/src/uhci0/dma_in_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16 - Set this bit to pop data in in link descriptor's fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_pop(&mut self) -> INFIFO_POP_W<DMA_IN_POP_SPEC> {
         INFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32/src/uhci0/dma_out_link.rs b/esp32/src/uhci0/dma_out_link.rs
index acde30891f..71004a4538 100644
--- a/esp32/src/uhci0/dma_out_link.rs
+++ b/esp32/src/uhci0/dma_out_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register stores the least 20 bits of the first out link descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set this bit to stop dealing with the out link descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start dealing with the out link descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to mount on new out link descriptors"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32/src/uhci0/dma_out_push.rs b/esp32/src/uhci0/dma_out_push.rs
index fd807ae36c..a1c6c9354a 100644
--- a/esp32/src/uhci0/dma_out_push.rs
+++ b/esp32/src/uhci0/dma_out_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This is the data need to be pushed into out link descriptor's fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<DMA_OUT_PUSH_SPEC> {
         OUTFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16 - Set this bit to push data in out link descriptor's fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<DMA_OUT_PUSH_SPEC> {
         OUTFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32/src/uhci0/esc_conf.rs b/esp32/src/uhci0/esc_conf.rs
index 2ab2bb5db4..e00215ac07 100644
--- a/esp32/src/uhci0/esc_conf.rs
+++ b/esp32/src/uhci0/esc_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register stores the seperator char seperator char is used to seperate the data frame."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_char(&mut self) -> SEPER_CHAR_W<ESC_CONF_SPEC> {
         SEPER_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register stores thee first char used to replace seperator char in data."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR0_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR1_W::new(self, 16)
     }
diff --git a/esp32/src/uhci0/escape_conf.rs b/esp32/src/uhci0/escape_conf.rs
index 4825c85a7e..9e9e89c5f8 100644
--- a/esp32/src/uhci0/escape_conf.rs
+++ b/esp32/src/uhci0/escape_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable 0xc0 char decode when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_C0_ESC_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable 0xdb char decode when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_DB_ESC_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable flow control char 0x11 decode when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_11_ESC_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable flow control char 0x13 decode when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_13_ESC_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable 0xc0 char replace when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_C0_ESC_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable 0xdb char replace when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_DB_ESC_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable flow control char 0x11 replace when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_11_ESC_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable flow control char 0x13 replace when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_13_ESC_EN_W::new(self, 7)
     }
diff --git a/esp32/src/uhci0/hung_conf.rs b/esp32/src/uhci0/hung_conf.rs
index a8e2f2886e..69684e41f9 100644
--- a/esp32/src/uhci0/hung_conf.rs
+++ b/esp32/src/uhci0/hung_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - The enable bit for txfifo receive data timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_ENA_W::new(self, 11)
     }
     #[doc = "Bits 12:19 - This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_W::new(self, 12)
     }
     #[doc = "Bits 20:22 - The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_SHIFT_W::new(self, 20)
     }
     #[doc = "Bit 23 - This is the enable bit for DMA send data timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_ENA_W::new(self, 23)
     }
diff --git a/esp32/src/uhci0/int_clr.rs b/esp32/src/uhci0/int_clr.rs
index 80b344aedd..7419fbe69d 100644
--- a/esp32/src/uhci0/int_clr.rs
+++ b/esp32/src/uhci0/int_clr.rs
@@ -43,103 +43,86 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
         IN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
         IN_DSCR_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
         OUT_DSCR_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_q(&mut self) -> SEND_S_Q_W<INT_CLR_SPEC> {
         SEND_S_Q_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_q(&mut self) -> SEND_A_Q_W<INT_CLR_SPEC> {
         SEND_A_Q_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_CLR_SPEC> {
         DMA_INFIFO_FULL_WM_W::new(self, 16)
     }
diff --git a/esp32/src/uhci0/int_ena.rs b/esp32/src/uhci0/int_ena.rs
index 33173ddec2..cbcbc09e81 100644
--- a/esp32/src/uhci0/int_ena.rs
+++ b/esp32/src/uhci0/int_ena.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_ENA_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_ENA_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_ENA_SPEC> {
         IN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_ENA_SPEC> {
         IN_DSCR_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_ENA_SPEC> {
         OUT_DSCR_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_ENA_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_ENA_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_q(&mut self) -> SEND_S_Q_W<INT_ENA_SPEC> {
         SEND_S_Q_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_q(&mut self) -> SEND_A_Q_W<INT_ENA_SPEC> {
         SEND_A_Q_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_ENA_SPEC> {
         DMA_INFIFO_FULL_WM_W::new(self, 16)
     }
diff --git a/esp32/src/uhci0/pkt_thres.rs b/esp32/src/uhci0/pkt_thres.rs
index 89e62ad8b7..461e4fd61f 100644
--- a/esp32/src/uhci0/pkt_thres.rs
+++ b/esp32/src/uhci0/pkt_thres.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:12 - when the amount of packet payload is greater than this value the process of receiving data is done."]
     #[inline(always)]
-    #[must_use]
     pub fn pkt_thrs(&mut self) -> PKT_THRS_W<PKT_THRES_SPEC> {
         PKT_THRS_W::new(self, 0)
     }
diff --git a/esp32/src/uhci0/q/word0.rs b/esp32/src/uhci0/q/word0.rs
index 253ee559a0..8746abbe91 100644
--- a/esp32/src/uhci0/q/word0.rs
+++ b/esp32/src/uhci0/q/word0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register stores the content of short packet's first dword"]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD0_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32/src/uhci0/q/word1.rs b/esp32/src/uhci0/q/word1.rs
index 09082000e1..fdd73ccb28 100644
--- a/esp32/src/uhci0/q/word1.rs
+++ b/esp32/src/uhci0/q/word1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register stores the content of short packet's second dword"]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD1_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32/src/uhci0/quick_sent.rs b/esp32/src/uhci0/quick_sent.rs
index dc5dce4f92..67e762ee8e 100644
--- a/esp32/src/uhci0/quick_sent.rs
+++ b/esp32/src/uhci0/quick_sent.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - The bits are used to choose which short packet"]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_NUM_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to enable send a short packet"]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - The bits are used to choose which short packet"]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_NUM_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to enable continuously send the same short packet"]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_EN_W::new(self, 7)
     }
diff --git a/esp32s2/Cargo.toml b/esp32s2/Cargo.toml
index ffa73b70d0..2778cdd015 100644
--- a/esp32s2/Cargo.toml
+++ b/esp32s2/Cargo.toml
@@ -30,7 +30,6 @@ test = false
 [dependencies]
 critical-section = { version = "1.1.3", optional = true }
 vcell = "0.1.3"
-xtensa-lx = "0.9.0"
 defmt = { version = "0.3.8", optional = true }
 
 [features]
diff --git a/esp32s2/src/aes/aad_block_num.rs b/esp32s2/src/aes/aad_block_num.rs
index 17ebb02e16..25abbabd3c 100644
--- a/esp32s2/src/aes/aad_block_num.rs
+++ b/esp32s2/src/aes/aad_block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the ADD Block Number for the GCM operation."]
     #[inline(always)]
-    #[must_use]
     pub fn aad_block_num(&mut self) -> AAD_BLOCK_NUM_W<AAD_BLOCK_NUM_SPEC> {
         AAD_BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/block_mode.rs b/esp32s2/src/aes/block_mode.rs
index 79574e5183..f1b8eeccdc 100644
--- a/esp32s2/src/aes/block_mode.rs
+++ b/esp32s2/src/aes/block_mode.rs
@@ -2,12 +2,12 @@
 pub type R = crate::R<BLOCK_MODE_SPEC>;
 #[doc = "Register `BLOCK_MODE` writer"]
 pub type W = crate::W<BLOCK_MODE_SPEC>;
-#[doc = "Field `BLOCK_MODE` reader - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. &amp; 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &amp;"]
+#[doc = "Field `BLOCK_MODE` reader - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. & 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &"]
 pub type BLOCK_MODE_R = crate::FieldReader;
-#[doc = "Field `BLOCK_MODE` writer - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. &amp; 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &amp;"]
+#[doc = "Field `BLOCK_MODE` writer - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. & 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &"]
 pub type BLOCK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 impl R {
-    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. &amp; 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &amp;"]
+    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. & 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &"]
     #[inline(always)]
     pub fn block_mode(&self) -> BLOCK_MODE_R {
         BLOCK_MODE_R::new((self.bits & 7) as u8)
@@ -22,9 +22,8 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. &amp; 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &amp;"]
+    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. & 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &"]
     #[inline(always)]
-    #[must_use]
     pub fn block_mode(&mut self) -> BLOCK_MODE_W<BLOCK_MODE_SPEC> {
         BLOCK_MODE_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/block_num.rs b/esp32s2/src/aes/block_num.rs
index 8bb5378ffd..a39c510746 100644
--- a/esp32s2/src/aes/block_num.rs
+++ b/esp32s2/src/aes/block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4."]
     #[inline(always)]
-    #[must_use]
     pub fn block_num(&mut self) -> BLOCK_NUM_W<BLOCK_NUM_SPEC> {
         BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/continue_.rs b/esp32s2/src/aes/continue_.rs
index 45fe89abe3..2c3baddfd9 100644
--- a/esp32s2/src/aes/continue_.rs
+++ b/esp32s2/src/aes/continue_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to continue AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
         CONTINUE_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/date.rs b/esp32s2/src/aes/date.rs
index 4d28b4a300..6590d07ffc 100644
--- a/esp32s2/src/aes/date.rs
+++ b/esp32s2/src/aes/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/dma_enable.rs b/esp32s2/src/aes/dma_enable.rs
index 71d0855150..cab96f6288 100644
--- a/esp32s2/src/aes/dma_enable.rs
+++ b/esp32s2/src/aes/dma_enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Defines the working mode of the AES Accelerator. For details, see Table 1. 1'h0: typical AES operation 1'h1: DMA-AES operation"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_enable(&mut self) -> DMA_ENABLE_W<DMA_ENABLE_SPEC> {
         DMA_ENABLE_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/dma_exit.rs b/esp32s2/src/aes/dma_exit.rs
index 261345c1cc..825ec822d3 100644
--- a/esp32s2/src/aes/dma_exit.rs
+++ b/esp32s2/src/aes/dma_exit.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_EXIT_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_exit(&mut self) -> DMA_EXIT_W<DMA_EXIT_SPEC> {
         DMA_EXIT_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/endian.rs b/esp32s2/src/aes/endian.rs
index 0efd26a81a..7481d54160 100644
--- a/esp32s2/src/aes/endian.rs
+++ b/esp32s2/src/aes/endian.rs
@@ -2,12 +2,12 @@
 pub type R = crate::R<ENDIAN_SPEC>;
 #[doc = "Register `ENDIAN` writer"]
 pub type W = crate::W<ENDIAN_SPEC>;
-#[doc = "Field `ENDIAN` reader - Defines the endianness of input and output texts. &amp; \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &amp;"]
+#[doc = "Field `ENDIAN` reader - Defines the endianness of input and output texts. & \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &"]
 pub type ENDIAN_R = crate::FieldReader;
-#[doc = "Field `ENDIAN` writer - Defines the endianness of input and output texts. &amp; \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &amp;"]
+#[doc = "Field `ENDIAN` writer - Defines the endianness of input and output texts. & \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &"]
 pub type ENDIAN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
 impl R {
-    #[doc = "Bits 0:5 - Defines the endianness of input and output texts. &amp; \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &amp;"]
+    #[doc = "Bits 0:5 - Defines the endianness of input and output texts. & \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &"]
     #[inline(always)]
     pub fn endian(&self) -> ENDIAN_R {
         ENDIAN_R::new((self.bits & 0x3f) as u8)
@@ -22,9 +22,8 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:5 - Defines the endianness of input and output texts. &amp; \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &amp;"]
+    #[doc = "Bits 0:5 - Defines the endianness of input and output texts. & \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &"]
     #[inline(always)]
-    #[must_use]
     pub fn endian(&mut self) -> ENDIAN_W<ENDIAN_SPEC> {
         ENDIAN_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/inc_sel.rs b/esp32s2/src/aes/inc_sel.rs
index ed9a036844..41a2256951 100644
--- a/esp32s2/src/aes/inc_sel.rs
+++ b/esp32s2/src/aes/inc_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 ."]
     #[inline(always)]
-    #[must_use]
     pub fn inc_sel(&mut self) -> INC_SEL_W<INC_SEL_SPEC> {
         INC_SEL_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/int_clr.rs b/esp32s2/src/aes/int_clr.rs
index 5b95830996..cc9d06e539 100644
--- a/esp32s2/src/aes/int_clr.rs
+++ b/esp32s2/src/aes/int_clr.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to clear AES interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
         INT_CLR_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/int_ena.rs b/esp32s2/src/aes/int_ena.rs
index dc2666bbec..942a7f56bc 100644
--- a/esp32s2/src/aes/int_ena.rs
+++ b/esp32s2/src/aes/int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
         INT_ENA_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/iv_mem.rs b/esp32s2/src/aes/iv_mem.rs
index f45a066e4b..34bc1beba7 100644
--- a/esp32s2/src/aes/iv_mem.rs
+++ b/esp32s2/src/aes/iv_mem.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register stores the %sth 32-bit piece of 128-bit initialization vector"]
     #[inline(always)]
-    #[must_use]
     pub fn iv(&mut self) -> IV_W<IV_MEM_SPEC> {
         IV_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/j0_mem.rs b/esp32s2/src/aes/j0_mem.rs
index e94d18db9a..bf6086888b 100644
--- a/esp32s2/src/aes/j0_mem.rs
+++ b/esp32s2/src/aes/j0_mem.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register stores the %sth 32-bit piece of 128-bit J0"]
     #[inline(always)]
-    #[must_use]
     pub fn j0(&mut self) -> J0_W<J0_MEM_SPEC> {
         J0_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/key.rs b/esp32s2/src/aes/key.rs
index 807bd5088c..9b19d6f124 100644
--- a/esp32s2/src/aes/key.rs
+++ b/esp32s2/src/aes/key.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores AES keys."]
     #[inline(always)]
-    #[must_use]
     pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
         KEY_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/mode.rs b/esp32s2/src/aes/mode.rs
index fd55178249..67fbe89465 100644
--- a/esp32s2/src/aes/mode.rs
+++ b/esp32s2/src/aes/mode.rs
@@ -2,12 +2,12 @@
 pub type R = crate::R<MODE_SPEC>;
 #[doc = "Register `MODE` writer"]
 pub type W = crate::W<MODE_SPEC>;
-#[doc = "Field `MODE` reader - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. &amp; 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &amp;"]
+#[doc = "Field `MODE` reader - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. & 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &"]
 pub type MODE_R = crate::FieldReader;
-#[doc = "Field `MODE` writer - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. &amp; 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &amp;"]
+#[doc = "Field `MODE` writer - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. & 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &"]
 pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 impl R {
-    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. &amp; 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &amp;"]
+    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. & 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &"]
     #[inline(always)]
     pub fn mode(&self) -> MODE_R {
         MODE_R::new((self.bits & 7) as u8)
@@ -20,9 +20,8 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. &amp; 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &amp;"]
+    #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the Typical AES working mode. & 0x0(AES_EN_128): AES-EN-128 # 0x1(AES_EN_192): AES-EN-192 # 0x2(AES_EN_256): AES-EN-256 # 0x4(AES_DE_128): AES-DE-128 # 0x5(AES_DE_192): AES-DE-192 # 0x6(AES_DE_256): AES-DE-256 &"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/remainder_bit_num.rs b/esp32s2/src/aes/remainder_bit_num.rs
index 2fff69e73e..e30a747d36 100644
--- a/esp32s2/src/aes/remainder_bit_num.rs
+++ b/esp32s2/src/aes/remainder_bit_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Stores the Remainder Bit Number for the GCM operation."]
     #[inline(always)]
-    #[must_use]
     pub fn remainder_bit_num(&mut self) -> REMAINDER_BIT_NUM_W<REMAINDER_BIT_NUM_SPEC> {
         REMAINDER_BIT_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/text_in.rs b/esp32s2/src/aes/text_in.rs
index 12e44ad6ae..e5bd545bfc 100644
--- a/esp32s2/src/aes/text_in.rs
+++ b/esp32s2/src/aes/text_in.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the source data when the AES Accelerator operates in the Typical AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn text_in(&mut self) -> TEXT_IN_W<TEXT_IN_SPEC> {
         TEXT_IN_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/text_out.rs b/esp32s2/src/aes/text_out.rs
index c5e507cd0c..5452e1cc98 100644
--- a/esp32s2/src/aes/text_out.rs
+++ b/esp32s2/src/aes/text_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the result data when the AES Accelerator operates in the Typical AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn text_out(&mut self) -> TEXT_OUT_W<TEXT_OUT_SPEC> {
         TEXT_OUT_W::new(self, 0)
     }
diff --git a/esp32s2/src/aes/trigger.rs b/esp32s2/src/aes/trigger.rs
index be94b6331b..bbbde50c77 100644
--- a/esp32s2/src/aes/trigger.rs
+++ b/esp32s2/src/aes/trigger.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
         TRIGGER_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/apb_dac_ctrl.rs b/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
index 93ba291fd7..55983cc066 100644
--- a/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
+++ b/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - Set DAC timer target."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_target(&mut self) -> TIMER_TARGET_W<APB_DAC_CTRL_SPEC> {
         TIMER_TARGET_W::new(self, 0)
     }
     #[doc = "Bit 12 - Enable read dac data."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_en(&mut self) -> TIMER_EN_W<APB_DAC_CTRL_SPEC> {
         TIMER_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Enable DAC alter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn alter_mode(&mut self) -> ALTER_MODE_W<APB_DAC_CTRL_SPEC> {
         ALTER_MODE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Enable DMA_DAC."]
     #[inline(always)]
-    #[must_use]
     pub fn trans(&mut self) -> TRANS_W<APB_DAC_CTRL_SPEC> {
         TRANS_W::new(self, 14)
     }
     #[doc = "Bit 15 - Reset DIG DAC FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn reset_fifo(&mut self) -> RESET_FIFO_W<APB_DAC_CTRL_SPEC> {
         RESET_FIFO_W::new(self, 15)
     }
     #[doc = "Bit 16 - Reset DIG DAC by software."]
     #[inline(always)]
-    #[must_use]
     pub fn rst(&mut self) -> RST_W<APB_DAC_CTRL_SPEC> {
         RST_W::new(self, 16)
     }
diff --git a/esp32s2/src/apb_saradc/arb_ctrl.rs b/esp32s2/src/apb_saradc/arb_ctrl.rs
index 986c772c3e..df36c90ff3 100644
--- a/esp32s2/src/apb_saradc/arb_ctrl.rs
+++ b/esp32s2/src/apb_saradc/arb_ctrl.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - ADC2 arbiter forces to enable DIG ADC2 CTRL."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_force(&mut self) -> APB_FORCE_W<ARB_CTRL_SPEC> {
         APB_FORCE_W::new(self, 2)
     }
     #[doc = "Bit 3 - ADC2 arbiter forces to enable RTC ADC2 CTRL."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_force(&mut self) -> RTC_FORCE_W<ARB_CTRL_SPEC> {
         RTC_FORCE_W::new(self, 3)
     }
     #[doc = "Bit 4 - ADC2 arbiter forces to enable PWDET/PKDET CTRL."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force(&mut self) -> WIFI_FORCE_W<ARB_CTRL_SPEC> {
         WIFI_FORCE_W::new(self, 4)
     }
     #[doc = "Bit 5 - ADC2 arbiter force grant."]
     #[inline(always)]
-    #[must_use]
     pub fn grant_force(&mut self) -> GRANT_FORCE_W<ARB_CTRL_SPEC> {
         GRANT_FORCE_W::new(self, 5)
     }
     #[doc = "Bits 6:7 - Set DIG ADC2 CTRL priority."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_priority(&mut self) -> APB_PRIORITY_W<ARB_CTRL_SPEC> {
         APB_PRIORITY_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Set RTC ADC2 CTRL priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_priority(&mut self) -> RTC_PRIORITY_W<ARB_CTRL_SPEC> {
         RTC_PRIORITY_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Set PWDET/PKDET CTRL priority."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_priority(&mut self) -> WIFI_PRIORITY_W<ARB_CTRL_SPEC> {
         WIFI_PRIORITY_W::new(self, 10)
     }
     #[doc = "Bit 12 - ADC2 arbiter uses fixed priority."]
     #[inline(always)]
-    #[must_use]
     pub fn fix_priority(&mut self) -> FIX_PRIORITY_W<ARB_CTRL_SPEC> {
         FIX_PRIORITY_W::new(self, 12)
     }
diff --git a/esp32s2/src/apb_saradc/clkm_conf.rs b/esp32s2/src/apb_saradc/clkm_conf.rs
index 31239f5f39..63953c3aa6 100644
--- a/esp32s2/src/apb_saradc/clkm_conf.rs
+++ b/esp32s2/src/apb_saradc/clkm_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Integral DIG_ADC clock divider value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
         CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
         CLKM_DIV_B_W::new(self, 8)
     }
     #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
         CLKM_DIV_A_W::new(self, 14)
     }
     #[doc = "Bits 21:22 - 1: select APLL. 2: select APB_CLK. Other values: disable clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
         CLK_SEL_W::new(self, 21)
     }
diff --git a/esp32s2/src/apb_saradc/ctrl.rs b/esp32s2/src/apb_saradc/ctrl.rs
index e6a8feeacf..6e82e7c840 100644
--- a/esp32s2/src/apb_saradc/ctrl.rs
+++ b/esp32s2/src/apb_saradc/ctrl.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 0: select FSM to start SAR ADC. 1: select software to start SAR ADC."]
     #[inline(always)]
-    #[must_use]
     pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
         START_FORCE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Start SAR ADC by software."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CTRL_SPEC> {
         START_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - 0: single-channel scan mode. 1: double-channel scan mode. 2: alternate-channel scan mode."]
     #[inline(always)]
-    #[must_use]
     pub fn work_mode(&mut self) -> WORK_MODE_W<CTRL_SPEC> {
         WORK_MODE_W::new(self, 3)
     }
     #[doc = "Bit 5 - 0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sel(&mut self) -> SAR_SEL_W<CTRL_SPEC> {
         SAR_SEL_W::new(self, 5)
     }
     #[doc = "Bit 6 - SAR clock gate enable bit."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
         SAR_CLK_GATED_W::new(self, 6)
     }
     #[doc = "Bits 7:14 - SAR clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
         SAR_CLK_DIV_W::new(self, 7)
     }
     #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<CTRL_SPEC> {
         SAR1_PATT_LEN_W::new(self, 15)
     }
     #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<CTRL_SPEC> {
         SAR2_PATT_LEN_W::new(self, 19)
     }
     #[doc = "Bit 23 - Clear the pointer of pattern table for DIG ADC1 CTRL."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<CTRL_SPEC> {
         SAR1_PATT_P_CLEAR_W::new(self, 23)
     }
     #[doc = "Bit 24 - Clear the pointer of pattern table for DIG ADC2 CTRL."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<CTRL_SPEC> {
         SAR2_PATT_P_CLEAR_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<CTRL_SPEC> {
         DATA_SAR_SEL_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<CTRL_SPEC> {
         DATA_TO_I2S_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - Force option to xpd sar blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
         XPD_SAR_FORCE_W::new(self, 27)
     }
     #[doc = "Bits 30:31 - Wait arbit signal stable after sar_done."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
         WAIT_ARB_CYCLE_W::new(self, 30)
     }
diff --git a/esp32s2/src/apb_saradc/ctrl2.rs b/esp32s2/src/apb_saradc/ctrl2.rs
index 154c876633..e474f4d055 100644
--- a/esp32s2/src/apb_saradc/ctrl2.rs
+++ b/esp32s2/src/apb_saradc/ctrl2.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable limit times of SAR ADC sample."]
     #[inline(always)]
-    #[must_use]
     pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
         MEAS_NUM_LIMIT_W::new(self, 0)
     }
     #[doc = "Bits 1:8 - Set maximum conversion number."]
     #[inline(always)]
-    #[must_use]
     pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
         MAX_MEAS_NUM_W::new(self, 1)
     }
     #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
         SAR1_INV_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
         SAR2_INV_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
         TIMER_SEL_W::new(self, 11)
     }
     #[doc = "Bits 12:23 - Set SAR ADC timer target."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
         TIMER_TARGET_W::new(self, 12)
     }
     #[doc = "Bit 24 - Enable SAR ADC timer trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
         TIMER_EN_W::new(self, 24)
     }
diff --git a/esp32s2/src/apb_saradc/ctrl_date.rs b/esp32s2/src/apb_saradc/ctrl_date.rs
index d3bf3b8c0d..a34fa9aada 100644
--- a/esp32s2/src/apb_saradc/ctrl_date.rs
+++ b/esp32s2/src/apb_saradc/ctrl_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<CTRL_DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/dma_conf.rs b/esp32s2/src/apb_saradc/dma_conf.rs
index c3d64152c5..d108ef5d2a 100644
--- a/esp32s2/src/apb_saradc/dma_conf.rs
+++ b/esp32s2/src/apb_saradc/dma_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Generate dma_in_suc_eof when sample cnt = spi_eof_num."]
     #[inline(always)]
-    #[must_use]
     pub fn adc_eof_num(&mut self) -> ADC_EOF_NUM_W<DMA_CONF_SPEC> {
         ADC_EOF_NUM_W::new(self, 0)
     }
     #[doc = "Bit 30 - Reset DIG ADC CTRL status."]
     #[inline(always)]
-    #[must_use]
     pub fn adc_reset_fsm(&mut self) -> ADC_RESET_FSM_W<DMA_CONF_SPEC> {
         ADC_RESET_FSM_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit, DIG ADC CTRL uses SPI DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn adc_trans(&mut self) -> ADC_TRANS_W<DMA_CONF_SPEC> {
         ADC_TRANS_W::new(self, 31)
     }
diff --git a/esp32s2/src/apb_saradc/filter_ctrl.rs b/esp32s2/src/apb_saradc/filter_ctrl.rs
index 1ce78a1dfe..afdc5bba1f 100644
--- a/esp32s2/src/apb_saradc/filter_ctrl.rs
+++ b/esp32s2/src/apb_saradc/filter_ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reset ADC2 filter."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_filter_reset(&mut self) -> ADC2_FILTER_RESET_W<FILTER_CTRL_SPEC> {
         ADC2_FILTER_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Reset ADC1 filter."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_filter_reset(&mut self) -> ADC1_FILTER_RESET_W<FILTER_CTRL_SPEC> {
         ADC1_FILTER_RESET_W::new(self, 1)
     }
     #[doc = "Bits 16:22 - Set filter factor for DIG ADC2 CRTL."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_filter_factor(&mut self) -> ADC2_FILTER_FACTOR_W<FILTER_CTRL_SPEC> {
         ADC2_FILTER_FACTOR_W::new(self, 16)
     }
     #[doc = "Bits 23:29 - Set filter factor for DIG ADC1 CRTL."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_filter_factor(&mut self) -> ADC1_FILTER_FACTOR_W<FILTER_CTRL_SPEC> {
         ADC1_FILTER_FACTOR_W::new(self, 23)
     }
     #[doc = "Bit 30 - Enable DIG ADC2 CRTL filter."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_filter_en(&mut self) -> ADC2_FILTER_EN_W<FILTER_CTRL_SPEC> {
         ADC2_FILTER_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Enable DIG ADC1 CRTL filter."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_filter_en(&mut self) -> ADC1_FILTER_EN_W<FILTER_CTRL_SPEC> {
         ADC1_FILTER_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/apb_saradc/fsm.rs b/esp32s2/src/apb_saradc/fsm.rs
index 39b7453768..ac44f5f1ae 100644
--- a/esp32s2/src/apb_saradc/fsm.rs
+++ b/esp32s2/src/apb_saradc/fsm.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:23 - sample number"]
     #[inline(always)]
-    #[must_use]
     pub fn sample_num(&mut self) -> SAMPLE_NUM_W<FSM_SPEC> {
         SAMPLE_NUM_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - sample cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn sample_cycle(&mut self) -> SAMPLE_CYCLE_W<FSM_SPEC> {
         SAMPLE_CYCLE_W::new(self, 24)
     }
diff --git a/esp32s2/src/apb_saradc/fsm_wait.rs b/esp32s2/src/apb_saradc/fsm_wait.rs
index e62797d924..825e3b791f 100644
--- a/esp32s2/src/apb_saradc/fsm_wait.rs
+++ b/esp32s2/src/apb_saradc/fsm_wait.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - xpd wait"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_wait(&mut self) -> XPD_WAIT_W<FSM_WAIT_SPEC> {
         XPD_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - reset time"]
     #[inline(always)]
-    #[must_use]
     pub fn rstb_wait(&mut self) -> RSTB_WAIT_W<FSM_WAIT_SPEC> {
         RSTB_WAIT_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - standby wait"]
     #[inline(always)]
-    #[must_use]
     pub fn standby_wait(&mut self) -> STANDBY_WAIT_W<FSM_WAIT_SPEC> {
         STANDBY_WAIT_W::new(self, 16)
     }
diff --git a/esp32s2/src/apb_saradc/int_clr.rs b/esp32s2/src/apb_saradc/int_clr.rs
index 78edc681c7..e450fac542 100644
--- a/esp32s2/src/apb_saradc/int_clr.rs
+++ b/esp32s2/src/apb_saradc/int_clr.rs
@@ -17,25 +17,21 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 28 - Clear bit of APB_SARADC_ADC2_THRES_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_thres(&mut self) -> ADC2_THRES_W<INT_CLR_SPEC> {
         ADC2_THRES_W::new(self, 28)
     }
     #[doc = "Bit 29 - Clear bit of APB_SARADC_ADC1_THRES_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_thres(&mut self) -> ADC1_THRES_W<INT_CLR_SPEC> {
         ADC1_THRES_W::new(self, 29)
     }
     #[doc = "Bit 30 - Clear bit of APB_SARADC_ADC2_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
         ADC2_DONE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Clear bit of APB_SARADC_ADC1_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
         ADC1_DONE_W::new(self, 31)
     }
diff --git a/esp32s2/src/apb_saradc/int_ena.rs b/esp32s2/src/apb_saradc/int_ena.rs
index b869b81385..72979acd5a 100644
--- a/esp32s2/src/apb_saradc/int_ena.rs
+++ b/esp32s2/src/apb_saradc/int_ena.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 28 - Enable bit of APB_SARADC_ADC2_THRES_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_thres(&mut self) -> ADC2_THRES_W<INT_ENA_SPEC> {
         ADC2_THRES_W::new(self, 28)
     }
     #[doc = "Bit 29 - Enable bit of APB_SARADC_ADC1_THRES_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_thres(&mut self) -> ADC1_THRES_W<INT_ENA_SPEC> {
         ADC1_THRES_W::new(self, 29)
     }
     #[doc = "Bit 30 - Enable bit of APB_SARADC_ADC2_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_ENA_SPEC> {
         ADC2_DONE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Enable bit of APB_SARADC_ADC1_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_ENA_SPEC> {
         ADC1_DONE_W::new(self, 31)
     }
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab1.rs b/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
index 8a1e425870..fa1bd64382 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab1(&mut self) -> SAR1_PATT_TAB1_W<SAR1_PATT_TAB1_SPEC> {
         SAR1_PATT_TAB1_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab2.rs b/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
index a4e52df2b6..fbf639ee62 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab2(&mut self) -> SAR1_PATT_TAB2_W<SAR1_PATT_TAB2_SPEC> {
         SAR1_PATT_TAB2_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab3.rs b/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
index 926158c398..a013601755 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 8 ~ 11 for pattern table 1 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab3(&mut self) -> SAR1_PATT_TAB3_W<SAR1_PATT_TAB3_SPEC> {
         SAR1_PATT_TAB3_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab4.rs b/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
index 72f12d6e9d..25d0d89fae 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 12 ~ 15 for pattern table 1 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab4(&mut self) -> SAR1_PATT_TAB4_W<SAR1_PATT_TAB4_SPEC> {
         SAR1_PATT_TAB4_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab1.rs b/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
index c6f764a99c..0b131ae990 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab1(&mut self) -> SAR2_PATT_TAB1_W<SAR2_PATT_TAB1_SPEC> {
         SAR2_PATT_TAB1_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab2.rs b/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
index 1dea7070fa..55e8662100 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 4 ~ 7 for pattern table 2 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab2(&mut self) -> SAR2_PATT_TAB2_W<SAR2_PATT_TAB2_SPEC> {
         SAR2_PATT_TAB2_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab3.rs b/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
index 617ade9401..3efb9cf800 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 8 ~ 11 for pattern table 2 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab3(&mut self) -> SAR2_PATT_TAB3_W<SAR2_PATT_TAB3_SPEC> {
         SAR2_PATT_TAB3_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab4.rs b/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
index e165ce3fae..8bb14f8245 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Item 12 ~ 15 for pattern table 2 (each item one byte)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab4(&mut self) -> SAR2_PATT_TAB4_W<SAR2_PATT_TAB4_SPEC> {
         SAR2_PATT_TAB4_W::new(self, 0)
     }
diff --git a/esp32s2/src/apb_saradc/thres_ctrl.rs b/esp32s2/src/apb_saradc/thres_ctrl.rs
index f4222f94c1..b05299f17a 100644
--- a/esp32s2/src/apb_saradc/thres_ctrl.rs
+++ b/esp32s2/src/apb_saradc/thres_ctrl.rs
@@ -6,13 +6,13 @@ pub type W = crate::W<THRES_CTRL_SPEC>;
 pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - Clock gate enable."]
 pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `ADC2_THRES_MODE` reader - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+#[doc = "Field `ADC2_THRES_MODE` reader - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
 pub type ADC2_THRES_MODE_R = crate::BitReader;
-#[doc = "Field `ADC2_THRES_MODE` writer - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+#[doc = "Field `ADC2_THRES_MODE` writer - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
 pub type ADC2_THRES_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `ADC1_THRES_MODE` reader - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+#[doc = "Field `ADC1_THRES_MODE` reader - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
 pub type ADC1_THRES_MODE_R = crate::BitReader;
-#[doc = "Field `ADC1_THRES_MODE` writer - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+#[doc = "Field `ADC1_THRES_MODE` writer - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
 pub type ADC1_THRES_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `ADC2_THRES` reader - ADC2 threshold."]
 pub type ADC2_THRES_R = crate::FieldReader<u16>;
@@ -36,12 +36,12 @@ impl R {
     pub fn clk_en(&self) -> CLK_EN_R {
         CLK_EN_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bit 2 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+    #[doc = "Bit 2 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
     #[inline(always)]
     pub fn adc2_thres_mode(&self) -> ADC2_THRES_MODE_R {
         ADC2_THRES_MODE_R::new(((self.bits >> 2) & 1) != 0)
     }
-    #[doc = "Bit 3 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+    #[doc = "Bit 3 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
     #[inline(always)]
     pub fn adc1_thres_mode(&self) -> ADC1_THRES_MODE_R {
         ADC1_THRES_MODE_R::new(((self.bits >> 3) & 1) != 0)
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Clock gate enable."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<THRES_CTRL_SPEC> {
         CLK_EN_W::new(self, 0)
     }
-    #[doc = "Bit 2 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+    #[doc = "Bit 2 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_thres_mode(&mut self) -> ADC2_THRES_MODE_W<THRES_CTRL_SPEC> {
         ADC2_THRES_MODE_W::new(self, 2)
     }
-    #[doc = "Bit 3 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt."]
+    #[doc = "Bit 3 - 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_thres_mode(&mut self) -> ADC1_THRES_MODE_W<THRES_CTRL_SPEC> {
         ADC1_THRES_MODE_W::new(self, 3)
     }
     #[doc = "Bits 4:16 - ADC2 threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_thres(&mut self) -> ADC2_THRES_W<THRES_CTRL_SPEC> {
         ADC2_THRES_W::new(self, 4)
     }
     #[doc = "Bits 17:29 - ADC1 threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_thres(&mut self) -> ADC1_THRES_W<THRES_CTRL_SPEC> {
         ADC1_THRES_W::new(self, 17)
     }
     #[doc = "Bit 30 - Enable ADC2 threshold monitor."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_thres_en(&mut self) -> ADC2_THRES_EN_W<THRES_CTRL_SPEC> {
         ADC2_THRES_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Enable ADC1 threshold monitor."]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_thres_en(&mut self) -> ADC1_THRES_EN_W<THRES_CTRL_SPEC> {
         ADC1_THRES_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/bb/bbpd_ctrl.rs b/esp32s2/src/bb/bbpd_ctrl.rs
index 968dce20ce..6de8322c9b 100644
--- a/esp32s2/src/bb/bbpd_ctrl.rs
+++ b/esp32s2/src/bb/bbpd_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pd(&mut self) -> DC_EST_FORCE_PD_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pu(&mut self) -> DC_EST_FORCE_PU_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pd(&mut self) -> FFT_FORCE_PD_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pu(&mut self) -> FFT_FORCE_PU_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PU_W::new(self, 3)
     }
diff --git a/esp32s2/src/dedicated_gpio/in_dly.rs b/esp32s2/src/dedicated_gpio/in_dly.rs
index 66ba778867..ebe5a24224 100644
--- a/esp32s2/src/dedicated_gpio/in_dly.rs
+++ b/esp32s2/src/dedicated_gpio/in_dly.rs
@@ -83,7 +83,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch(&mut self, n: u8) -> CH_W<IN_DLY_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -91,49 +90,41 @@ impl W {
     }
     #[doc = "Bits 0:1 - Configure GPIO0 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Configure GPIO1 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Configure GPIO2 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Configure GPIO3 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Configure GPIO4 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Configure GPIO5 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Configure GPIO6 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Configure GPIO7 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH_W<IN_DLY_SPEC> {
         CH_W::new(self, 14)
     }
diff --git a/esp32s2/src/dedicated_gpio/intr_clr.rs b/esp32s2/src/dedicated_gpio/intr_clr.rs
index 65182d4b11..04ad63a321 100644
--- a/esp32s2/src/dedicated_gpio/intr_clr.rs
+++ b/esp32s2/src/dedicated_gpio/intr_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `GPIO0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self, n: u8) -> GPIO_W<INTR_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -21,49 +20,41 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the DEDIC_GPIO0_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the DEDIC_GPIO1_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the DEDIC_GPIO2_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the DEDIC_GPIO3_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the DEDIC_GPIO4_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the DEDIC_GPIO5_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the DEDIC_GPIO6_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the DEDIC_GPIO7_INT_RAW interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7(&mut self) -> GPIO_W<INTR_CLR_SPEC> {
         GPIO_W::new(self, 7)
     }
diff --git a/esp32s2/src/dedicated_gpio/intr_rcgn.rs b/esp32s2/src/dedicated_gpio/intr_rcgn.rs
index 8a05953605..27ea9aaea7 100644
--- a/esp32s2/src/dedicated_gpio/intr_rcgn.rs
+++ b/esp32s2/src/dedicated_gpio/intr_rcgn.rs
@@ -83,7 +83,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `INTR_MODE_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch(&mut self, n: u8) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -91,49 +90,41 @@ impl W {
     }
     #[doc = "Bits 0:2 - Configure channel 0 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch0(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - Configure channel 1 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch1(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - Configure channel 2 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch2(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - Configure channel 3 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch3(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - Configure channel 4 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch4(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - Configure channel 5 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch5(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - Configure channel 6 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch6(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 18)
     }
     #[doc = "Bits 21:23 - Configure channel 7 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn intr_mode_ch7(&mut self) -> INTR_MODE_CH_W<INTR_RCGN_SPEC> {
         INTR_MODE_CH_W::new(self, 21)
     }
diff --git a/esp32s2/src/dedicated_gpio/intr_rls.rs b/esp32s2/src/dedicated_gpio/intr_rls.rs
index b9f5914971..9e8734014a 100644
--- a/esp32s2/src/dedicated_gpio/intr_rls.rs
+++ b/esp32s2/src/dedicated_gpio/intr_rls.rs
@@ -83,7 +83,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `GPIO0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self, n: u8) -> GPIO_W<INTR_RLS_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -91,49 +90,41 @@ impl W {
     }
     #[doc = "Bit 0 - The enable bit for DEDIC_GPIO0_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for DEDIC_GPIO1_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for DEDIC_GPIO2_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for DEDIC_GPIO3_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for DEDIC_GPIO4_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for DEDIC_GPIO5_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for DEDIC_GPIO6_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for DEDIC_GPIO7_INT_ST register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7(&mut self) -> GPIO_W<INTR_RLS_SPEC> {
         GPIO_W::new(self, 7)
     }
diff --git a/esp32s2/src/dedicated_gpio/out_cpu.rs b/esp32s2/src/dedicated_gpio/out_cpu.rs
index 19c6715199..18ba8fe810 100644
--- a/esp32s2/src/dedicated_gpio/out_cpu.rs
+++ b/esp32s2/src/dedicated_gpio/out_cpu.rs
@@ -83,7 +83,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `SEL0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self, n: u8) -> SEL_W<OUT_CPU_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -91,49 +90,41 @@ impl W {
     }
     #[doc = "Bit 0 - Select GPIO out value configured by registers or CPU instructions for channel 0. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel0(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Select GPIO out value configured by registers or CPU instructions for channel 1. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel1(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Select GPIO out value configured by registers or CPU instructions for channel 2. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel2(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Select GPIO out value configured by registers or CPU instructions for channel 3. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel3(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 3)
     }
     #[doc = "Bit 4 - Select GPIO out value configured by registers or CPU instructions for channel 4. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel4(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 4)
     }
     #[doc = "Bit 5 - Select GPIO out value configured by registers or CPU instructions for channel 5. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel5(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 5)
     }
     #[doc = "Bit 6 - Select GPIO out value configured by registers or CPU instructions for channel 6. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel6(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 6)
     }
     #[doc = "Bit 7 - Select GPIO out value configured by registers or CPU instructions for channel 7. 0: Configured by registers. 1: configured by CPU instructions."]
     #[inline(always)]
-    #[must_use]
     pub fn sel7(&mut self) -> SEL_W<OUT_CPU_SPEC> {
         SEL_W::new(self, 7)
     }
diff --git a/esp32s2/src/dedicated_gpio/out_drt.rs b/esp32s2/src/dedicated_gpio/out_drt.rs
index 1d08b4f1a9..72df751755 100644
--- a/esp32s2/src/dedicated_gpio/out_drt.rs
+++ b/esp32s2/src/dedicated_gpio/out_drt.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_DRT_SPEC> {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure directive output value of 8-channel dedicated GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn value(&mut self) -> VALUE_W<OUT_DRT_SPEC> {
         VALUE_W::new(self, 0)
     }
diff --git a/esp32s2/src/dedicated_gpio/out_idv.rs b/esp32s2/src/dedicated_gpio/out_idv.rs
index 588a9a8e07..8e780b3b55 100644
--- a/esp32s2/src/dedicated_gpio/out_idv.rs
+++ b/esp32s2/src/dedicated_gpio/out_idv.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch(&mut self, n: u8) -> CH_W<OUT_IDV_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -21,49 +20,41 @@ impl W {
     }
     #[doc = "Bits 0:1 - Configure channel 0 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Configure channel 1 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Configure channel 2 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Configure channel 3 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Configure channel 4 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Configure channel 5 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Configure channel 6 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Configure channel 7 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH_W<OUT_IDV_SPEC> {
         CH_W::new(self, 14)
     }
diff --git a/esp32s2/src/dedicated_gpio/out_msk.rs b/esp32s2/src/dedicated_gpio/out_msk.rs
index e54fe6b915..a856ce2ff1 100644
--- a/esp32s2/src/dedicated_gpio/out_msk.rs
+++ b/esp32s2/src/dedicated_gpio/out_msk.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_MSK_SPEC> {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure updated output value of 8-channel dedicated GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn out_value(&mut self) -> OUT_VALUE_W<OUT_MSK_SPEC> {
         OUT_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to configure channels which would be updated. 1: corresponding channel's output would be updated."]
     #[inline(always)]
-    #[must_use]
     pub fn out_msk(&mut self) -> OUT_MSK_W<OUT_MSK_SPEC> {
         OUT_MSK_W::new(self, 8)
     }
diff --git a/esp32s2/src/ds/date.rs b/esp32s2/src/ds/date.rs
index 9f930bc8bf..b97a19b87e 100644
--- a/esp32s2/src/ds/date.rs
+++ b/esp32s2/src/ds/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/ds/iv_.rs b/esp32s2/src/ds/iv_.rs
index e4df2b5b4f..1687597eca 100644
--- a/esp32s2/src/ds/iv_.rs
+++ b/esp32s2/src/ds/iv_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<IV__SPEC> {
 impl W {
     #[doc = "Bits 0:31 - IV block data."]
     #[inline(always)]
-    #[must_use]
     pub fn iv(&mut self) -> IV_W<IV__SPEC> {
         IV_W::new(self, 0)
     }
diff --git a/esp32s2/src/ds/set_finish.rs b/esp32s2/src/ds/set_finish.rs
index 438f904447..7c92f1c4ac 100644
--- a/esp32s2/src/ds/set_finish.rs
+++ b/esp32s2/src/ds/set_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to end DS operation."]
     #[inline(always)]
-    #[must_use]
     pub fn set_finish(&mut self) -> SET_FINISH_W<SET_FINISH_SPEC> {
         SET_FINISH_W::new(self, 0)
     }
diff --git a/esp32s2/src/ds/set_me.rs b/esp32s2/src/ds/set_me.rs
index 0648c538e8..b60b3df552 100644
--- a/esp32s2/src/ds/set_me.rs
+++ b/esp32s2/src/ds/set_me.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_ME_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to start DS operation."]
     #[inline(always)]
-    #[must_use]
     pub fn set_me(&mut self) -> SET_ME_W<SET_ME_SPEC> {
         SET_ME_W::new(self, 0)
     }
diff --git a/esp32s2/src/ds/set_start.rs b/esp32s2/src/ds/set_start.rs
index cea7e99be5..0e64fc1a3b 100644
--- a/esp32s2/src/ds/set_start.rs
+++ b/esp32s2/src/ds/set_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to activate the DS peripheral."]
     #[inline(always)]
-    #[must_use]
     pub fn set_start(&mut self) -> SET_START_W<SET_START_SPEC> {
         SET_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/efuse/clk.rs b/esp32s2/src/efuse/clk.rs
index 9540284388..4700be4c16 100644
--- a/esp32s2/src/efuse/clk.rs
+++ b/esp32s2/src/efuse/clk.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - If set, forces eFuse SRAM into power-saving mode."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_mem_force_pd(&mut self) -> EFUSE_MEM_FORCE_PD_W<CLK_SPEC> {
         EFUSE_MEM_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - If set, forces to activate clock signal of eFuse SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<CLK_SPEC> {
         MEM_CLK_FORCE_ON_W::new(self, 1)
     }
     #[doc = "Bit 2 - If set, forces eFuse SRAM into working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_mem_force_pu(&mut self) -> EFUSE_MEM_FORCE_PU_W<CLK_SPEC> {
         EFUSE_MEM_FORCE_PU_W::new(self, 2)
     }
     #[doc = "Bit 16 - If set, forces to enable clock signal of eFuse memory."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CLK_SPEC> {
         EN_W::new(self, 16)
     }
diff --git a/esp32s2/src/efuse/cmd.rs b/esp32s2/src/efuse/cmd.rs
index baaf4145e4..fe0688f848 100644
--- a/esp32s2/src/efuse/cmd.rs
+++ b/esp32s2/src/efuse/cmd.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
-    #[must_use]
     pub fn read_cmd(&mut self) -> READ_CMD_W<CMD_SPEC> {
         READ_CMD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to send programming command."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_cmd(&mut self) -> PGM_CMD_W<CMD_SPEC> {
         PGM_CMD_W::new(self, 1)
     }
     #[doc = "Bits 2:5 - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn blk_num(&mut self) -> BLK_NUM_W<CMD_SPEC> {
         BLK_NUM_W::new(self, 2)
     }
diff --git a/esp32s2/src/efuse/conf.rs b/esp32s2/src/efuse/conf.rs
index 84ef65c69c..2f67907dca 100644
--- a/esp32s2/src/efuse/conf.rs
+++ b/esp32s2/src/efuse/conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command. 0x5AA5: Operate read command."]
     #[inline(always)]
-    #[must_use]
     pub fn op_code(&mut self) -> OP_CODE_W<CONF_SPEC> {
         OP_CODE_W::new(self, 0)
     }
diff --git a/esp32s2/src/efuse/dac_conf.rs b/esp32s2/src/efuse/dac_conf.rs
index 386dc3b935..dbc17b47fc 100644
--- a/esp32s2/src/efuse/dac_conf.rs
+++ b/esp32s2/src/efuse/dac_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_div(&mut self) -> DAC_CLK_DIV_W<DAC_CONF_SPEC> {
         DAC_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bit 8 - Don't care."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_pad_sel(&mut self) -> DAC_CLK_PAD_SEL_W<DAC_CONF_SPEC> {
         DAC_CLK_PAD_SEL_W::new(self, 8)
     }
     #[doc = "Bits 9:16 - Controls the rising period of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_num(&mut self) -> DAC_NUM_W<DAC_CONF_SPEC> {
         DAC_NUM_W::new(self, 9)
     }
     #[doc = "Bit 17 - Reduces the power supply of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn oe_clr(&mut self) -> OE_CLR_W<DAC_CONF_SPEC> {
         OE_CLR_W::new(self, 17)
     }
diff --git a/esp32s2/src/efuse/date.rs b/esp32s2/src/efuse/date.rs
index 3f56546368..f79a6d4eed 100644
--- a/esp32s2/src/efuse/date.rs
+++ b/esp32s2/src/efuse/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/efuse/int_clr.rs b/esp32s2/src/efuse/int_clr.rs
index 670d58f7e5..230f4356f1 100644
--- a/esp32s2/src/efuse/int_clr.rs
+++ b/esp32s2/src/efuse/int_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The clear signal for read_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_CLR_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear signal for pgm_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_CLR_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32s2/src/efuse/int_ena.rs b/esp32s2/src/efuse/int_ena.rs
index 424c4f079d..3d4c9086ee 100644
--- a/esp32s2/src/efuse/int_ena.rs
+++ b/esp32s2/src/efuse/int_ena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_ENA_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for pgm_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_ENA_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32s2/src/efuse/pgm_check_value.rs b/esp32s2/src/efuse/pgm_check_value.rs
index 983b988037..0a357311dc 100644
--- a/esp32s2/src/efuse/pgm_check_value.rs
+++ b/esp32s2/src/efuse/pgm_check_value.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the %sth 32-bit RS code to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_rs_data(&mut self) -> PGM_RS_DATA_W<PGM_CHECK_VALUE_SPEC> {
         PGM_RS_DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/efuse/pgm_data.rs b/esp32s2/src/efuse/pgm_data.rs
index 4b9758021e..d705d6fad3 100644
--- a/esp32s2/src/efuse/pgm_data.rs
+++ b/esp32s2/src/efuse/pgm_data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the %sth 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data(&mut self) -> PGM_DATA_W<PGM_DATA_SPEC> {
         PGM_DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/efuse/rd_tim_conf.rs b/esp32s2/src/efuse/rd_tim_conf.rs
index c47679d1e4..44615c05c4 100644
--- a/esp32s2/src/efuse/rd_tim_conf.rs
+++ b/esp32s2/src/efuse/rd_tim_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Configures the hold time of read operation."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_a(&mut self) -> THR_A_W<RD_TIM_CONF_SPEC> {
         THR_A_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Configures the length of pulse of read operation."]
     #[inline(always)]
-    #[must_use]
     pub fn trd(&mut self) -> TRD_W<RD_TIM_CONF_SPEC> {
         TRD_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Configures the setup time of read operation."]
     #[inline(always)]
-    #[must_use]
     pub fn tsur_a(&mut self) -> TSUR_A_W<RD_TIM_CONF_SPEC> {
         TSUR_A_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Configures the initial read time of eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn read_init_num(&mut self) -> READ_INIT_NUM_W<RD_TIM_CONF_SPEC> {
         READ_INIT_NUM_W::new(self, 24)
     }
diff --git a/esp32s2/src/efuse/wr_tim_conf0.rs b/esp32s2/src/efuse/wr_tim_conf0.rs
index f4a7234490..e63cf31d17 100644
--- a/esp32s2/src/efuse/wr_tim_conf0.rs
+++ b/esp32s2/src/efuse/wr_tim_conf0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Configures the hold time of programming operation."]
     #[inline(always)]
-    #[must_use]
     pub fn thp_a(&mut self) -> THP_A_W<WR_TIM_CONF0_SPEC> {
         THP_A_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Configures the length of pulse during programming 0 to eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn tpgm_inactive(&mut self) -> TPGM_INACTIVE_W<WR_TIM_CONF0_SPEC> {
         TPGM_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bits 16:31 - Configures the length of pulse during programming 1 to eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn tpgm(&mut self) -> TPGM_W<WR_TIM_CONF0_SPEC> {
         TPGM_W::new(self, 16)
     }
diff --git a/esp32s2/src/efuse/wr_tim_conf1.rs b/esp32s2/src/efuse/wr_tim_conf1.rs
index 3d9950e0f4..60227df45d 100644
--- a/esp32s2/src/efuse/wr_tim_conf1.rs
+++ b/esp32s2/src/efuse/wr_tim_conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Configures the setup time of programming operation."]
     #[inline(always)]
-    #[must_use]
     pub fn tsup_a(&mut self) -> TSUP_A_W<WR_TIM_CONF1_SPEC> {
         TSUP_A_W::new(self, 0)
     }
     #[doc = "Bits 8:23 - Configures the power up time for VDDQ."]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_on_num(&mut self) -> PWR_ON_NUM_W<WR_TIM_CONF1_SPEC> {
         PWR_ON_NUM_W::new(self, 8)
     }
diff --git a/esp32s2/src/efuse/wr_tim_conf2.rs b/esp32s2/src/efuse/wr_tim_conf2.rs
index 2a54a9285a..6c0a829175 100644
--- a/esp32s2/src/efuse/wr_tim_conf2.rs
+++ b/esp32s2/src/efuse/wr_tim_conf2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_off_num(&mut self) -> PWR_OFF_NUM_W<WR_TIM_CONF2_SPEC> {
         PWR_OFF_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs b/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
index 78b8b88a14..3428c2b258 100644
--- a/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
+++ b/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn alloc_wb_hold_arbiter(
         &mut self,
     ) -> ALLOC_WB_HOLD_ARBITER_W<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/cache_conf_misc.rs b/esp32s2/src/extmem/cache_conf_misc.rs
index bd2ab9949e..e100a41284 100644
--- a/esp32s2/src/extmem/cache_conf_misc.rs
+++ b/esp32s2/src/extmem/cache_conf_misc.rs
@@ -42,7 +42,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ignore_preload_mmu_entry_fault(
         &mut self,
     ) -> PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
@@ -50,7 +49,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ignore_sync_mmu_entry_fault(
         &mut self,
     ) -> PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
diff --git a/esp32s2/src/extmem/cache_dbg_int_clr.rs b/esp32s2/src/extmem/cache_dbg_int_clr.rs
index e7e70629d6..92aa67811c 100644
--- a/esp32s2/src/extmem/cache_dbg_int_clr.rs
+++ b/esp32s2/src/extmem/cache_dbg_int_clr.rs
@@ -37,19 +37,16 @@ impl core::fmt::Debug for crate::generic::Reg<CACHE_DBG_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_acs_msk_ic_int_clr(&mut self) -> IBUS_ACS_MSK_IC_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         IBUS_ACS_MSK_IC_INT_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to clear interrupt by ibus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_cnt_ovf_int_clr(&mut self) -> IBUS_CNT_OVF_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         IBUS_CNT_OVF_INT_CLR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to clear interrupt by manual sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_sync_size_fault_int_clr(
         &mut self,
     ) -> IC_SYNC_SIZE_FAULT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
@@ -57,7 +54,6 @@ impl W {
     }
     #[doc = "Bit 3 - The bit is used to clear interrupt by manual pre-load configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_preload_size_fault_int_clr(
         &mut self,
     ) -> IC_PRELOAD_SIZE_FAULT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
@@ -65,31 +61,26 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_reject_int_clr(&mut self) -> ICACHE_REJECT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         ICACHE_REJECT_INT_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5 - The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_set_ilg_int_clr(&mut self) -> ICACHE_SET_ILG_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         ICACHE_SET_ILG_INT_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_acs_msk_dc_int_clr(&mut self) -> DBUS_ACS_MSK_DC_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         DBUS_ACS_MSK_DC_INT_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7 - The bit is used to clear interrupt by dbus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_cnt_ovf_int_clr(&mut self) -> DBUS_CNT_OVF_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         DBUS_CNT_OVF_INT_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - The bit is used to clear interrupt by manual sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dc_sync_size_fault_int_clr(
         &mut self,
     ) -> DC_SYNC_SIZE_FAULT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
@@ -97,7 +88,6 @@ impl W {
     }
     #[doc = "Bit 9 - The bit is used to clear interrupt by manual pre-load configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dc_preload_size_fault_int_clr(
         &mut self,
     ) -> DC_PRELOAD_SIZE_FAULT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
@@ -105,7 +95,6 @@ impl W {
     }
     #[doc = "Bit 10 - The bit is used to clear interrupt by dcache trying to write flash."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_write_flash_int_clr(
         &mut self,
     ) -> DCACHE_WRITE_FLASH_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
@@ -113,19 +102,16 @@ impl W {
     }
     #[doc = "Bit 11 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_reject_int_clr(&mut self) -> DCACHE_REJECT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         DCACHE_REJECT_INT_CLR_W::new(self, 11)
     }
     #[doc = "Bit 12 - The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_set_ilg_int_clr(&mut self) -> DCACHE_SET_ILG_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         DCACHE_SET_ILG_INT_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13 - The bit is used to clear interrupt by mmu entry fault."]
     #[inline(always)]
-    #[must_use]
     pub fn mmu_entry_fault_int_clr(&mut self) -> MMU_ENTRY_FAULT_INT_CLR_W<CACHE_DBG_INT_CLR_SPEC> {
         MMU_ENTRY_FAULT_INT_CLR_W::new(self, 13)
     }
diff --git a/esp32s2/src/extmem/cache_dbg_int_ena.rs b/esp32s2/src/extmem/cache_dbg_int_ena.rs
index 0ac07c4575..5d6d699ec6 100644
--- a/esp32s2/src/extmem/cache_dbg_int_ena.rs
+++ b/esp32s2/src/extmem/cache_dbg_int_ena.rs
@@ -237,25 +237,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the cache track function. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_dbg_en(&mut self) -> CACHE_DBG_EN_W<CACHE_DBG_INT_ENA_SPEC> {
         CACHE_DBG_EN_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_acs_msk_ic_int_ena(&mut self) -> IBUS_ACS_MSK_IC_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         IBUS_ACS_MSK_IC_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to enable interrupt by ibus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_cnt_ovf_int_ena(&mut self) -> IBUS_CNT_OVF_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         IBUS_CNT_OVF_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 4 - The bit is used to enable interrupt by manual sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_sync_size_fault_int_ena(
         &mut self,
     ) -> IC_SYNC_SIZE_FAULT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -263,7 +259,6 @@ impl W {
     }
     #[doc = "Bit 5 - The bit is used to enable interrupt by manual pre-load configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_preload_size_fault_int_ena(
         &mut self,
     ) -> IC_PRELOAD_SIZE_FAULT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -271,13 +266,11 @@ impl W {
     }
     #[doc = "Bit 6 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_reject_int_ena(&mut self) -> ICACHE_REJECT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         ICACHE_REJECT_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_set_preload_ilg_int_ena(
         &mut self,
     ) -> ICACHE_SET_PRELOAD_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -285,7 +278,6 @@ impl W {
     }
     #[doc = "Bit 8 - The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_set_sync_ilg_int_ena(
         &mut self,
     ) -> ICACHE_SET_SYNC_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -293,7 +285,6 @@ impl W {
     }
     #[doc = "Bit 9 - The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_set_lock_ilg_int_ena(
         &mut self,
     ) -> ICACHE_SET_LOCK_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -301,19 +292,16 @@ impl W {
     }
     #[doc = "Bit 10 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_acs_msk_dc_int_ena(&mut self) -> DBUS_ACS_MSK_DC_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         DBUS_ACS_MSK_DC_INT_ENA_W::new(self, 10)
     }
     #[doc = "Bit 11 - The bit is used to enable interrupt by dbus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_cnt_ovf_int_ena(&mut self) -> DBUS_CNT_OVF_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         DBUS_CNT_OVF_INT_ENA_W::new(self, 11)
     }
     #[doc = "Bit 12 - The bit is used to enable interrupt by manual sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dc_sync_size_fault_int_ena(
         &mut self,
     ) -> DC_SYNC_SIZE_FAULT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -321,7 +309,6 @@ impl W {
     }
     #[doc = "Bit 13 - The bit is used to enable interrupt by manual pre-load configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dc_preload_size_fault_int_ena(
         &mut self,
     ) -> DC_PRELOAD_SIZE_FAULT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -329,7 +316,6 @@ impl W {
     }
     #[doc = "Bit 14 - The bit is used to enable interrupt by dcache trying to write flash."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_write_flash_int_ena(
         &mut self,
     ) -> DCACHE_WRITE_FLASH_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -337,13 +323,11 @@ impl W {
     }
     #[doc = "Bit 15 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_reject_int_ena(&mut self) -> DCACHE_REJECT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         DCACHE_REJECT_INT_ENA_W::new(self, 15)
     }
     #[doc = "Bit 16 - The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_set_preload_ilg_int_ena(
         &mut self,
     ) -> DCACHE_SET_PRELOAD_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -351,7 +335,6 @@ impl W {
     }
     #[doc = "Bit 17 - The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_set_sync_ilg_int_ena(
         &mut self,
     ) -> DCACHE_SET_SYNC_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -359,7 +342,6 @@ impl W {
     }
     #[doc = "Bit 18 - The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_set_lock_ilg_int_ena(
         &mut self,
     ) -> DCACHE_SET_LOCK_ILG_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
@@ -367,7 +349,6 @@ impl W {
     }
     #[doc = "Bit 19 - The bit is used to enable interrupt by mmu entry fault."]
     #[inline(always)]
-    #[must_use]
     pub fn mmu_entry_fault_int_ena(&mut self) -> MMU_ENTRY_FAULT_INT_ENA_W<CACHE_DBG_INT_ENA_SPEC> {
         MMU_ENTRY_FAULT_INT_ENA_W::new(self, 19)
     }
diff --git a/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index dd8f973d50..d74ab2f3a0 100644
--- a/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -52,7 +52,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_db_encrypt(
         &mut self,
     ) -> CLK_FORCE_ON_DB_ENCRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
@@ -60,7 +59,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to close clock gating of decrypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_g0cb_decrypt(
         &mut self,
     ) -> CLK_FORCE_ON_G0CB_DECRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
@@ -68,7 +66,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to close clock gating of encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_automatic_encrypt_decrypt(
         &mut self,
     ) -> CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
diff --git a/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
index 56ea0b7af4..6ccdbbc331 100644
--- a/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn record_disable_db_encrypt(
         &mut self,
     ) -> RECORD_DISABLE_DB_ENCRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn record_disable_g0cb_decrypt(
         &mut self,
     ) -> RECORD_DISABLE_G0CB_DECRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
diff --git a/esp32s2/src/extmem/cache_preload_int_ctrl.rs b/esp32s2/src/extmem/cache_preload_int_ctrl.rs
index 3d15535898..c9d7181579 100644
--- a/esp32s2/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32s2/src/extmem/cache_preload_int_ctrl.rs
@@ -66,7 +66,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_int_ena(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_INT_ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
@@ -74,7 +73,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to clear the interrupt by icache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_int_clr(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_INT_CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
@@ -82,7 +80,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_int_ena(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_INT_ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
@@ -90,7 +87,6 @@ impl W {
     }
     #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_int_clr(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_INT_CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/cache_sync_int_ctrl.rs b/esp32s2/src/extmem/cache_sync_int_ctrl.rs
index 528a3a9e7d..47d275d15f 100644
--- a/esp32s2/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32s2/src/extmem/cache_sync_int_ctrl.rs
@@ -54,7 +54,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_sync_int_ena(
         &mut self,
     ) -> PRO_ICACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
@@ -62,7 +61,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to clear the interrupt by icache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_sync_int_clr(
         &mut self,
     ) -> PRO_ICACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
@@ -70,7 +68,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_sync_int_ena(
         &mut self,
     ) -> PRO_DCACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
@@ -78,7 +75,6 @@ impl W {
     }
     #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_sync_int_clr(
         &mut self,
     ) -> PRO_DCACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/clock_gate.rs b/esp32s2/src/extmem/clock_gate.rs
index 5416f9931a..87231641c1 100644
--- a/esp32s2/src/extmem/clock_gate.rs
+++ b/esp32s2/src/extmem/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_cache_acs_cnt_clr.rs b/esp32s2/src/extmem/pro_cache_acs_cnt_clr.rs
index 82f4ac16c0..d669519fc3 100644
--- a/esp32s2/src/extmem/pro_cache_acs_cnt_clr.rs
+++ b/esp32s2/src/extmem/pro_cache_acs_cnt_clr.rs
@@ -13,7 +13,6 @@ impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_ACS_CNT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_acs_cnt_clr(
         &mut self,
     ) -> PRO_DCACHE_ACS_CNT_CLR_W<PRO_CACHE_ACS_CNT_CLR_SPEC> {
@@ -21,7 +20,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_acs_cnt_clr(
         &mut self,
     ) -> PRO_ICACHE_ACS_CNT_CLR_W<PRO_CACHE_ACS_CNT_CLR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs b/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
index f3ce0ac113..65d9228cd9 100644
--- a/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
@@ -53,7 +53,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mmu_mem_force_on(
         &mut self,
     ) -> PRO_CACHE_MMU_MEM_FORCE_ON_W<PRO_CACHE_MMU_POWER_CTRL_SPEC> {
@@ -61,7 +60,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mmu_mem_force_pd(
         &mut self,
     ) -> PRO_CACHE_MMU_MEM_FORCE_PD_W<PRO_CACHE_MMU_POWER_CTRL_SPEC> {
@@ -69,7 +67,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_mmu_mem_force_pu(
         &mut self,
     ) -> PRO_CACHE_MMU_MEM_FORCE_PU_W<PRO_CACHE_MMU_POWER_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs b/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
index ff3a759878..5ce6c53f6f 100644
--- a/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
+++ b/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_flash_wrap_around(
         &mut self,
     ) -> PRO_CACHE_FLASH_WRAP_AROUND_W<PRO_CACHE_WRAP_AROUND_CTRL_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to enable wrap around mode when read data from spiram."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_sram_rd_wrap_around(
         &mut self,
     ) -> PRO_CACHE_SRAM_RD_WRAP_AROUND_W<PRO_CACHE_WRAP_AROUND_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs b/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
index 4afd0edc27..1ceb8bc497 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
@@ -93,7 +93,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_mode(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_MODE_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -101,7 +100,6 @@ impl W {
     }
     #[doc = "Bits 1:2 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_step(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_STEP_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -109,7 +107,6 @@ impl W {
     }
     #[doc = "Bit 3 - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_order(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_ORDER_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -117,7 +114,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_rqst(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_RQST_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -125,7 +121,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_size(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SIZE_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -133,7 +128,6 @@ impl W {
     }
     #[doc = "Bit 8 - The bits are used to enable the second section for conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct0_ena(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT0_ENA_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
@@ -141,7 +135,6 @@ impl W {
     }
     #[doc = "Bit 9 - The bits are used to enable the first section for conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct1_ena(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT1_ENA_W<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs b/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
index fa268295d7..5399508ad8 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct0_addr(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT0_ADDR_W<PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs b/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
index 69584db21b..c7f13483c3 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct0_size(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT0_SIZE_W<PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs b/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
index 840af3e5e1..e9379ecfbf 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct1_addr(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT1_ADDR_W<PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs b/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
index 5170a46142..42cd4b8804 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_sct1_size(
         &mut self,
     ) -> PRO_DCACHE_AUTOLOAD_SCT1_SIZE_W<PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_ctrl.rs b/esp32s2/src/extmem/pro_dcache_ctrl.rs
index 2519e3a987..f588eb4ef8 100644
--- a/esp32s2/src/extmem/pro_dcache_ctrl.rs
+++ b/esp32s2/src/extmem/pro_dcache_ctrl.rs
@@ -199,19 +199,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_enable(&mut self) -> PRO_DCACHE_ENABLE_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_setsize_mode(&mut self) -> PRO_DCACHE_SETSIZE_MODE_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_SETSIZE_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_blocksize_mode(
         &mut self,
     ) -> PRO_DCACHE_BLOCKSIZE_MODE_W<PRO_DCACHE_CTRL_SPEC> {
@@ -219,7 +216,6 @@ impl W {
     }
     #[doc = "Bit 8 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_invalidate_ena(
         &mut self,
     ) -> PRO_DCACHE_INVALIDATE_ENA_W<PRO_DCACHE_CTRL_SPEC> {
@@ -227,49 +223,41 @@ impl W {
     }
     #[doc = "Bit 10 - The bit is used to enable flush operation. It will be cleared by hardware after flush operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_flush_ena(&mut self) -> PRO_DCACHE_FLUSH_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_FLUSH_ENA_W::new(self, 10)
     }
     #[doc = "Bit 12 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_clean_ena(&mut self) -> PRO_DCACHE_CLEAN_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_CLEAN_ENA_W::new(self, 12)
     }
     #[doc = "Bit 14 - The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock0_en(&mut self) -> PRO_DCACHE_LOCK0_EN_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_LOCK0_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock1_en(&mut self) -> PRO_DCACHE_LOCK1_EN_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_LOCK1_EN_W::new(self, 15)
     }
     #[doc = "Bit 18 - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_autoload_ena(&mut self) -> PRO_DCACHE_AUTOLOAD_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_AUTOLOAD_ENA_W::new(self, 18)
     }
     #[doc = "Bit 20 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_ena(&mut self) -> PRO_DCACHE_PRELOAD_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_PRELOAD_ENA_W::new(self, 20)
     }
     #[doc = "Bit 22 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_unlock_ena(&mut self) -> PRO_DCACHE_UNLOCK_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_UNLOCK_ENA_W::new(self, 22)
     }
     #[doc = "Bit 24 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock_ena(&mut self) -> PRO_DCACHE_LOCK_ENA_W<PRO_DCACHE_CTRL_SPEC> {
         PRO_DCACHE_LOCK_ENA_W::new(self, 24)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_ctrl1.rs b/esp32s2/src/extmem/pro_dcache_ctrl1.rs
index f00954f796..e6ac4c4de4 100644
--- a/esp32s2/src/extmem/pro_dcache_ctrl1.rs
+++ b/esp32s2/src/extmem/pro_dcache_ctrl1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable dbus0, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_mask_bus0(&mut self) -> PRO_DCACHE_MASK_BUS0_W<PRO_DCACHE_CTRL1_SPEC> {
         PRO_DCACHE_MASK_BUS0_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to disable dbus1, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_mask_bus1(&mut self) -> PRO_DCACHE_MASK_BUS1_W<PRO_DCACHE_CTRL1_SPEC> {
         PRO_DCACHE_MASK_BUS1_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to disable dbus2, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_mask_bus2(&mut self) -> PRO_DCACHE_MASK_BUS2_W<PRO_DCACHE_CTRL1_SPEC> {
         PRO_DCACHE_MASK_BUS2_W::new(self, 2)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_lock0_addr.rs b/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
index e25e3fd90a..90ca4b6c9f 100644
--- a/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock0_addr(&mut self) -> PRO_DCACHE_LOCK0_ADDR_W<PRO_DCACHE_LOCK0_ADDR_SPEC> {
         PRO_DCACHE_LOCK0_ADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_lock0_size.rs b/esp32s2/src/extmem/pro_dcache_lock0_size.rs
index 2a93006900..c7259067a5 100644
--- a/esp32s2/src/extmem/pro_dcache_lock0_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock0_size(&mut self) -> PRO_DCACHE_LOCK0_SIZE_W<PRO_DCACHE_LOCK0_SIZE_SPEC> {
         PRO_DCACHE_LOCK0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_lock1_addr.rs b/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
index 31f27a7f0d..db1c0ec547 100644
--- a/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock1_addr(&mut self) -> PRO_DCACHE_LOCK1_ADDR_W<PRO_DCACHE_LOCK1_ADDR_SPEC> {
         PRO_DCACHE_LOCK1_ADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_lock1_size.rs b/esp32s2/src/extmem/pro_dcache_lock1_size.rs
index 3b0fbd05bb..0923f800d5 100644
--- a/esp32s2/src/extmem/pro_dcache_lock1_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_lock1_size(&mut self) -> PRO_DCACHE_LOCK1_SIZE_W<PRO_DCACHE_LOCK1_SIZE_SPEC> {
         PRO_DCACHE_LOCK1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_dcache_mem_sync0.rs b/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
index 615fc46ff4..628953a281 100644
--- a/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
+++ b/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_memsync_addr(
         &mut self,
     ) -> PRO_DCACHE_MEMSYNC_ADDR_W<PRO_DCACHE_MEM_SYNC0_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_mem_sync1.rs b/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
index 0e6e4d297e..34e474838e 100644
--- a/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
+++ b/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18 - The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_memsync_size(
         &mut self,
     ) -> PRO_DCACHE_MEMSYNC_SIZE_W<PRO_DCACHE_MEM_SYNC1_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_preload_addr.rs b/esp32s2/src/extmem/pro_dcache_preload_addr.rs
index d090bc061e..8a56bf19ed 100644
--- a/esp32s2/src/extmem/pro_dcache_preload_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_preload_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_addr(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_ADDR_W<PRO_DCACHE_PRELOAD_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_preload_size.rs b/esp32s2/src/extmem/pro_dcache_preload_size.rs
index f65b928b85..ee0bf47e44 100644
--- a/esp32s2/src/extmem/pro_dcache_preload_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_preload_size.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_size(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_SIZE_W<PRO_DCACHE_PRELOAD_SIZE_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bit 10 - The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_order(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_ORDER_W<PRO_DCACHE_PRELOAD_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs b/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
index 64f61841f6..b569497c07 100644
--- a/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
@@ -53,7 +53,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_tag_mem_force_on(
         &mut self,
     ) -> PRO_DCACHE_TAG_MEM_FORCE_ON_W<PRO_DCACHE_TAG_POWER_CTRL_SPEC> {
@@ -61,7 +60,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_tag_mem_force_pd(
         &mut self,
     ) -> PRO_DCACHE_TAG_MEM_FORCE_PD_W<PRO_DCACHE_TAG_POWER_CTRL_SPEC> {
@@ -69,7 +67,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_tag_mem_force_pu(
         &mut self,
     ) -> PRO_DCACHE_TAG_MEM_FORCE_PU_W<PRO_DCACHE_TAG_POWER_CTRL_SPEC> {
diff --git a/esp32s2/src/extmem/pro_extmem_reg_date.rs b/esp32s2/src/extmem/pro_extmem_reg_date.rs
index 3d202033c5..17b3553e8f 100644
--- a/esp32s2/src/extmem/pro_extmem_reg_date.rs
+++ b/esp32s2/src/extmem/pro_extmem_reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_extmem_reg_date(&mut self) -> PRO_EXTMEM_REG_DATE_W<PRO_EXTMEM_REG_DATE_SPEC> {
         PRO_EXTMEM_REG_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_icache_autoload_cfg.rs b/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
index df9709f888..70e63f5143 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
@@ -93,7 +93,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_mode(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_MODE_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -101,7 +100,6 @@ impl W {
     }
     #[doc = "Bits 1:2 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_step(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_STEP_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -109,7 +107,6 @@ impl W {
     }
     #[doc = "Bit 3 - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_order(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_ORDER_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -117,7 +114,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_rqst(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_RQST_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -125,7 +121,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_size(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SIZE_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -133,7 +128,6 @@ impl W {
     }
     #[doc = "Bit 8 - The bits are used to enable the second section for conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct0_ena(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT0_ENA_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
@@ -141,7 +135,6 @@ impl W {
     }
     #[doc = "Bit 9 - The bits are used to enable the first section for conditional pre-load operation."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct1_ena(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT1_ENA_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs b/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
index a468f5eb5e..0b12527a57 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct0_addr(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT0_ADDR_W<PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs b/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
index 735b39ce4e..e5cc0942fb 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct0_size(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT0_SIZE_W<PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs b/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
index 56b280d7cb..dc6762f826 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct1_addr(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT1_ADDR_W<PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs b/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
index 8af93bd760..92662b0a9d 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_sct1_size(
         &mut self,
     ) -> PRO_ICACHE_AUTOLOAD_SCT1_SIZE_W<PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_ctrl.rs b/esp32s2/src/extmem/pro_icache_ctrl.rs
index 5cf7ed655c..974e3bed0b 100644
--- a/esp32s2/src/extmem/pro_icache_ctrl.rs
+++ b/esp32s2/src/extmem/pro_icache_ctrl.rs
@@ -163,19 +163,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_enable(&mut self) -> PRO_ICACHE_ENABLE_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_setsize_mode(&mut self) -> PRO_ICACHE_SETSIZE_MODE_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_SETSIZE_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_blocksize_mode(
         &mut self,
     ) -> PRO_ICACHE_BLOCKSIZE_MODE_W<PRO_ICACHE_CTRL_SPEC> {
@@ -183,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 8 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_invalidate_ena(
         &mut self,
     ) -> PRO_ICACHE_INVALIDATE_ENA_W<PRO_ICACHE_CTRL_SPEC> {
@@ -191,37 +187,31 @@ impl W {
     }
     #[doc = "Bit 14 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock0_en(&mut self) -> PRO_ICACHE_LOCK0_EN_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_LOCK0_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock1_en(&mut self) -> PRO_ICACHE_LOCK1_EN_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_LOCK1_EN_W::new(self, 15)
     }
     #[doc = "Bit 18 - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_autoload_ena(&mut self) -> PRO_ICACHE_AUTOLOAD_ENA_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_AUTOLOAD_ENA_W::new(self, 18)
     }
     #[doc = "Bit 20 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_ena(&mut self) -> PRO_ICACHE_PRELOAD_ENA_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_PRELOAD_ENA_W::new(self, 20)
     }
     #[doc = "Bit 22 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_unlock_ena(&mut self) -> PRO_ICACHE_UNLOCK_ENA_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_UNLOCK_ENA_W::new(self, 22)
     }
     #[doc = "Bit 24 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock_ena(&mut self) -> PRO_ICACHE_LOCK_ENA_W<PRO_ICACHE_CTRL_SPEC> {
         PRO_ICACHE_LOCK_ENA_W::new(self, 24)
     }
diff --git a/esp32s2/src/extmem/pro_icache_ctrl1.rs b/esp32s2/src/extmem/pro_icache_ctrl1.rs
index 4dcfd59618..7c3c779724 100644
--- a/esp32s2/src/extmem/pro_icache_ctrl1.rs
+++ b/esp32s2/src/extmem/pro_icache_ctrl1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable ibus0, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_mask_bus0(&mut self) -> PRO_ICACHE_MASK_BUS0_W<PRO_ICACHE_CTRL1_SPEC> {
         PRO_ICACHE_MASK_BUS0_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to disable ibus1, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_mask_bus1(&mut self) -> PRO_ICACHE_MASK_BUS1_W<PRO_ICACHE_CTRL1_SPEC> {
         PRO_ICACHE_MASK_BUS1_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to disable ibus2, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_mask_bus2(&mut self) -> PRO_ICACHE_MASK_BUS2_W<PRO_ICACHE_CTRL1_SPEC> {
         PRO_ICACHE_MASK_BUS2_W::new(self, 2)
     }
diff --git a/esp32s2/src/extmem/pro_icache_lock0_addr.rs b/esp32s2/src/extmem/pro_icache_lock0_addr.rs
index eebf54b2d2..1ce8eeea31 100644
--- a/esp32s2/src/extmem/pro_icache_lock0_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_lock0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock0_addr(&mut self) -> PRO_ICACHE_LOCK0_ADDR_W<PRO_ICACHE_LOCK0_ADDR_SPEC> {
         PRO_ICACHE_LOCK0_ADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_icache_lock0_size.rs b/esp32s2/src/extmem/pro_icache_lock0_size.rs
index 82bbf9e5fc..725ce66b32 100644
--- a/esp32s2/src/extmem/pro_icache_lock0_size.rs
+++ b/esp32s2/src/extmem/pro_icache_lock0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock0_size(&mut self) -> PRO_ICACHE_LOCK0_SIZE_W<PRO_ICACHE_LOCK0_SIZE_SPEC> {
         PRO_ICACHE_LOCK0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_icache_lock1_addr.rs b/esp32s2/src/extmem/pro_icache_lock1_addr.rs
index 99390da157..eb1459e383 100644
--- a/esp32s2/src/extmem/pro_icache_lock1_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_lock1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock1_addr(&mut self) -> PRO_ICACHE_LOCK1_ADDR_W<PRO_ICACHE_LOCK1_ADDR_SPEC> {
         PRO_ICACHE_LOCK1_ADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_icache_lock1_size.rs b/esp32s2/src/extmem/pro_icache_lock1_size.rs
index 6f23b1277e..190b98cfdb 100644
--- a/esp32s2/src/extmem/pro_icache_lock1_size.rs
+++ b/esp32s2/src/extmem/pro_icache_lock1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_lock1_size(&mut self) -> PRO_ICACHE_LOCK1_SIZE_W<PRO_ICACHE_LOCK1_SIZE_SPEC> {
         PRO_ICACHE_LOCK1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/extmem/pro_icache_mem_sync0.rs b/esp32s2/src/extmem/pro_icache_mem_sync0.rs
index 6bef1d8851..77b943b3fd 100644
--- a/esp32s2/src/extmem/pro_icache_mem_sync0.rs
+++ b/esp32s2/src/extmem/pro_icache_mem_sync0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_memsync_addr(
         &mut self,
     ) -> PRO_ICACHE_MEMSYNC_ADDR_W<PRO_ICACHE_MEM_SYNC0_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_mem_sync1.rs b/esp32s2/src/extmem/pro_icache_mem_sync1.rs
index 3ae8d2b596..39c7c6eba6 100644
--- a/esp32s2/src/extmem/pro_icache_mem_sync1.rs
+++ b/esp32s2/src/extmem/pro_icache_mem_sync1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18 - The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_memsync_size(
         &mut self,
     ) -> PRO_ICACHE_MEMSYNC_SIZE_W<PRO_ICACHE_MEM_SYNC1_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_preload_addr.rs b/esp32s2/src/extmem/pro_icache_preload_addr.rs
index 3287f449d6..78974f41ff 100644
--- a/esp32s2/src/extmem/pro_icache_preload_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_preload_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_addr(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_ADDR_W<PRO_ICACHE_PRELOAD_ADDR_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_preload_size.rs b/esp32s2/src/extmem/pro_icache_preload_size.rs
index 2c0a259475..e70fffed70 100644
--- a/esp32s2/src/extmem/pro_icache_preload_size.rs
+++ b/esp32s2/src/extmem/pro_icache_preload_size.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_size(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_SIZE_W<PRO_ICACHE_PRELOAD_SIZE_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bit 10 - The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_order(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_ORDER_W<PRO_ICACHE_PRELOAD_SIZE_SPEC> {
diff --git a/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs b/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
index 6045071469..e9323693f9 100644
--- a/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
@@ -53,7 +53,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_tag_mem_force_on(
         &mut self,
     ) -> PRO_ICACHE_TAG_MEM_FORCE_ON_W<PRO_ICACHE_TAG_POWER_CTRL_SPEC> {
@@ -61,7 +60,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_tag_mem_force_pd(
         &mut self,
     ) -> PRO_ICACHE_TAG_MEM_FORCE_PD_W<PRO_ICACHE_TAG_POWER_CTRL_SPEC> {
@@ -69,7 +67,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_tag_mem_force_pu(
         &mut self,
     ) -> PRO_ICACHE_TAG_MEM_FORCE_PU_W<PRO_ICACHE_TAG_POWER_CTRL_SPEC> {
diff --git a/esp32s2/src/generic.rs b/esp32s2/src/generic.rs
index d57106cb27..a7cb020aef 100644
--- a/esp32s2/src/generic.rs
+++ b/esp32s2/src/generic.rs
@@ -524,18 +524,60 @@ impl<REG: Resettable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " In the latter case, other fields will be set to their reset value."]
     #[inline(always)]
-    pub fn write<F>(&self, f: F)
+    pub fn write<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes bits to a `Writable` register and produce a value."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[doc = ""]
+    #[doc = " Values can be returned from the closure:"]
+    #[doc = " ```ignore"]
+    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn from_write<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Writable> Reg<REG> {
@@ -547,17 +589,37 @@ impl<REG: Writable> Reg<REG> {
     #[doc = ""]
     #[doc = " Unsafe to use with registers which don't allow to write 0."]
     #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F)
+    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::Ux::default(),
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes 0 to a `Writable` register and produces a value."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable + Writable> Reg<REG> {
@@ -587,25 +649,75 @@ impl<REG: Readable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " Other fields will have the value they had before the call to `modify`."]
     #[inline(always)]
-    pub fn modify<F>(&self, f: F)
+    pub fn modify<F>(&self, f: F) -> REG::Ux
     where
         for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
     {
         let bits = self.register.get();
-        self.register.set(
-            f(
-                &R {
-                    bits,
-                    _reg: marker::PhantomData,
-                },
-                &mut W {
-                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                    _reg: marker::PhantomData,
-                },
-            )
-            .bits,
+        let value = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut W {
+                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            },
+        )
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Modifies the contents of the register by reading and then writing it"]
+    #[doc = " and produces a value."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.modify(|r, w| {"]
+    #[doc = "     let new_bits = r.bits() | 3;"]
+    #[doc = "     unsafe {"]
+    #[doc = "         w.bits(new_bits);"]
+    #[doc = "     }"]
+    #[doc = ""]
+    #[doc = "     new_bits"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn from_modify<F, T>(&self, f: F) -> T
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+    {
+        let bits = self.register.get();
+        let mut writer = W {
+            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut writer,
         );
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
diff --git a/esp32s2/src/generic/raw.rs b/esp32s2/src/generic/raw.rs
index 81f5779524..d60a23a7cc 100644
--- a/esp32s2/src/generic/raw.rs
+++ b/esp32s2/src/generic/raw.rs
@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
         }
     }
 }
+#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
         }
     }
 }
+#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s2/src/gpio/bt_select.rs b/esp32s2/src/gpio/bt_select.rs
index 65eb997aaf..91bfe6cf9e 100644
--- a/esp32s2/src/gpio/bt_select.rs
+++ b/esp32s2/src/gpio/bt_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_sel(&mut self) -> BT_SEL_W<BT_SELECT_SPEC> {
         BT_SEL_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/clock_gate.rs b/esp32s2/src/gpio/clock_gate.rs
index 916092034c..c74a0b6b10 100644
--- a/esp32s2/src/gpio/clock_gate.rs
+++ b/esp32s2/src/gpio/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Clock gating enable bit. If set to 1, the clock is free running."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable.rs b/esp32s2/src/gpio/enable.rs
index 2811fb244d..8dc9628d91 100644
--- a/esp32s2/src/gpio/enable.rs
+++ b/esp32s2/src/gpio/enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable register."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable1.rs b/esp32s2/src/gpio/enable1.rs
index 71a65984e3..d6488c58f0 100644
--- a/esp32s2/src/gpio/enable1.rs
+++ b/esp32s2/src/gpio/enable1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO32~53 output enable register."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE1_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable1_w1tc.rs b/esp32s2/src/gpio/enable1_w1tc.rs
index cce920373e..ad522fbc0c 100644
--- a/esp32s2/src/gpio/enable1_w1tc.rs
+++ b/esp32s2/src/gpio/enable1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_w1tc(&mut self) -> ENABLE1_W1TC_W<ENABLE1_W1TC_SPEC> {
         ENABLE1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable1_w1ts.rs b/esp32s2/src/gpio/enable1_w1ts.rs
index 0883886ab3..bbb5dab7b5 100644
--- a/esp32s2/src/gpio/enable1_w1ts.rs
+++ b/esp32s2/src/gpio/enable1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_w1ts(&mut self) -> ENABLE1_W1TS_W<ENABLE1_W1TS_SPEC> {
         ENABLE1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable_w1tc.rs b/esp32s2/src/gpio/enable_w1tc.rs
index e513fd0522..25b42e192a 100644
--- a/esp32s2/src/gpio/enable_w1tc.rs
+++ b/esp32s2/src/gpio/enable_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/enable_w1ts.rs b/esp32s2/src/gpio/enable_w1ts.rs
index 0923e48b69..c1ba571419 100644
--- a/esp32s2/src/gpio/enable_w1ts.rs
+++ b/esp32s2/src/gpio/enable_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1ts(&mut self) -> ENABLE_W1TS_W<ENABLE_W1TS_SPEC> {
         ENABLE_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/func_in_sel_cfg.rs b/esp32s2/src/gpio/func_in_sel_cfg.rs
index b0e1057c19..da7646d6e6 100644
--- a/esp32s2/src/gpio/func_in_sel_cfg.rs
+++ b/esp32s2/src/gpio/func_in_sel_cfg.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input."]
     #[inline(always)]
-    #[must_use]
     pub fn in_sel(&mut self) -> IN_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_SEL_W::new(self, 0)
     }
     #[doc = "Bit 6 - Invert the input value. 1: invert enabled; 0: invert disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn in_inv_sel(&mut self) -> IN_INV_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_INV_SEL_W::new(self, 6)
     }
     #[doc = "Bit 7 - Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals directly to peripheral configured in IO_MUX."]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         SEL_W::new(self, 7)
     }
diff --git a/esp32s2/src/gpio/func_out_sel_cfg.rs b/esp32s2/src/gpio/func_out_sel_cfg.rs
index 9fdbbd0cb3..a837a8927d 100644
--- a/esp32s2/src/gpio/func_out_sel_cfg.rs
+++ b/esp32s2/src/gpio/func_out_sel_cfg.rs
@@ -2,9 +2,9 @@
 pub type R = crate::R<FUNC_OUT_SEL_CFG_SPEC>;
 #[doc = "Register `FUNC%s_OUT_SEL_CFG` writer"]
 pub type W = crate::W<FUNC_OUT_SEL_CFG_SPEC>;
-#[doc = "Field `OUT_SEL` reader - Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
+#[doc = "Field `OUT_SEL` reader - Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
 pub type OUT_SEL_R = crate::FieldReader<u16>;
-#[doc = "Field `OUT_SEL` writer - Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
+#[doc = "Field `OUT_SEL` writer - Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
 pub type OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
 #[doc = "Field `INV_SEL` reader - 0: Do not invert the output value; 1: Invert the output value."]
 pub type INV_SEL_R = crate::BitReader;
@@ -19,7 +19,7 @@ pub type OEN_INV_SEL_R = crate::BitReader;
 #[doc = "Field `OEN_INV_SEL` writer - 0: Do not invert the output enable signal; 1: Invert the output enable signal."]
 pub type OEN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
+    #[doc = "Bits 0:8 - Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
     #[inline(always)]
     pub fn out_sel(&self) -> OUT_SEL_R {
         OUT_SEL_R::new((self.bits & 0x01ff) as u16)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
+    #[doc = "Bits 0:8 - Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
     #[inline(always)]
-    #[must_use]
     pub fn out_sel(&mut self) -> OUT_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OUT_SEL_W::new(self, 0)
     }
     #[doc = "Bit 9 - 0: Do not invert the output value; 1: Invert the output value."]
     #[inline(always)]
-    #[must_use]
     pub fn inv_sel(&mut self) -> INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         INV_SEL_W::new(self, 9)
     }
     #[doc = "Bit 10 - 0: Use output enable signal from peripheral; 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn oen_sel(&mut self) -> OEN_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_SEL_W::new(self, 10)
     }
     #[doc = "Bit 11 - 0: Do not invert the output enable signal; 1: Invert the output enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn oen_inv_sel(&mut self) -> OEN_INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_INV_SEL_W::new(self, 11)
     }
diff --git a/esp32s2/src/gpio/in_.rs b/esp32s2/src/gpio/in_.rs
index 848b3b08cf..2a6895ef2d 100644
--- a/esp32s2/src/gpio/in_.rs
+++ b/esp32s2/src/gpio/in_.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level."]
     #[inline(always)]
-    #[must_use]
     pub fn data_next(&mut self) -> DATA_NEXT_W<IN_SPEC> {
         DATA_NEXT_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out.rs b/esp32s2/src/gpio/out.rs
index a6535c0d2e..3e1327a511 100644
--- a/esp32s2/src/gpio/out.rs
+++ b/esp32s2/src/gpio/out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid."]
     #[inline(always)]
-    #[must_use]
     pub fn data_orig(&mut self) -> DATA_ORIG_W<OUT_SPEC> {
         DATA_ORIG_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out1.rs b/esp32s2/src/gpio/out1.rs
index 1bdbd7b0bb..280dff2c23 100644
--- a/esp32s2/src/gpio/out1.rs
+++ b/esp32s2/src/gpio/out1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid."]
     #[inline(always)]
-    #[must_use]
     pub fn data_orig(&mut self) -> DATA_ORIG_W<OUT1_SPEC> {
         DATA_ORIG_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out1_w1tc.rs b/esp32s2/src/gpio/out1_w1tc.rs
index e513e6e41e..f3728ceae9 100644
--- a/esp32s2/src/gpio/out1_w1tc.rs
+++ b/esp32s2/src/gpio/out1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output value clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn out1_w1tc(&mut self) -> OUT1_W1TC_W<OUT1_W1TC_SPEC> {
         OUT1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out1_w1ts.rs b/esp32s2/src/gpio/out1_w1ts.rs
index f5f7e6fa78..ccc5b059c9 100644
--- a/esp32s2/src/gpio/out1_w1ts.rs
+++ b/esp32s2/src/gpio/out1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output value set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn out1_w1ts(&mut self) -> OUT1_W1TS_W<OUT1_W1TS_SPEC> {
         OUT1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out_w1tc.rs b/esp32s2/src/gpio/out_w1tc.rs
index 63e2e1ac8f..f44609e55c 100644
--- a/esp32s2/src/gpio/out_w1tc.rs
+++ b/esp32s2/src/gpio/out_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output clear register. If the value 1 is written to a bit here, the cor- responding bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn out_w1tc(&mut self) -> OUT_W1TC_W<OUT_W1TC_SPEC> {
         OUT_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/out_w1ts.rs b/esp32s2/src/gpio/out_w1ts.rs
index 64390a825d..e22dab5f23 100644
--- a/esp32s2/src/gpio/out_w1ts.rs
+++ b/esp32s2/src/gpio/out_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn out_w1ts(&mut self) -> OUT_W1TS_W<OUT_W1TS_SPEC> {
         OUT_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/pin.rs b/esp32s2/src/gpio/pin.rs
index 8cf7d5ebff..202a35e04f 100644
--- a/esp32s2/src/gpio/pin.rs
+++ b/esp32s2/src/gpio/pin.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge."]
     #[inline(always)]
-    #[must_use]
     pub fn sync2_bypass(&mut self) -> SYNC2_BYPASS_W<PIN_SPEC> {
         SYNC2_BYPASS_W::new(self, 0)
     }
     #[doc = "Bit 2 - Pad driver selection. 0: normal output; 1: open drain output.."]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge."]
     #[inline(always)]
-    #[must_use]
     pub fn sync1_bypass(&mut self) -> SYNC1_BYPASS_W<PIN_SPEC> {
         SYNC1_BYPASS_W::new(self, 3)
     }
     #[doc = "Bits 7:9 - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)"]
     #[inline(always)]
-    #[must_use]
     pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
         INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
         WAKEUP_ENABLE_W::new(self, 10)
     }
     #[doc = "Bits 11:12 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn config(&mut self) -> CONFIG_W<PIN_SPEC> {
         CONFIG_W::new(self, 11)
     }
     #[doc = "Bits 13:17 - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<PIN_SPEC> {
         INT_ENA_W::new(self, 13)
     }
diff --git a/esp32s2/src/gpio/reg_date.rs b/esp32s2/src/gpio/reg_date.rs
index 96e68c347d..42eb16378f 100644
--- a/esp32s2/src/gpio/reg_date.rs
+++ b/esp32s2/src/gpio/reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<REG_DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/sdio_select.rs b/esp32s2/src/gpio/sdio_select.rs
index cd6ececf13..eb5bec3366 100644
--- a/esp32s2/src/gpio/sdio_select.rs
+++ b/esp32s2/src/gpio/sdio_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_sel(&mut self) -> SDIO_SEL_W<SDIO_SELECT_SPEC> {
         SDIO_SEL_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status.rs b/esp32s2/src/gpio/status.rs
index c26d0e825d..5b8811692f 100644
--- a/esp32s2/src/gpio/status.rs
+++ b/esp32s2/src/gpio/status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 interrupt status register."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt(&mut self) -> INTERRUPT_W<STATUS_SPEC> {
         INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status1.rs b/esp32s2/src/gpio/status1.rs
index 25b9cb9c47..860ba8abf8 100644
--- a/esp32s2/src/gpio/status1.rs
+++ b/esp32s2/src/gpio/status1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 interrupt status register."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt(&mut self) -> INTERRUPT_W<STATUS1_SPEC> {
         INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status1_w1tc.rs b/esp32s2/src/gpio/status1_w1tc.rs
index f4bcef3368..f80c11682a 100644
--- a/esp32s2/src/gpio/status1_w1tc.rs
+++ b/esp32s2/src/gpio/status1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. Recommended operation: use this register to clear GPIO_STATUS1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn status1_w1tc(&mut self) -> STATUS1_W1TC_W<STATUS1_W1TC_SPEC> {
         STATUS1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status1_w1ts.rs b/esp32s2/src/gpio/status1_w1ts.rs
index cc2d9a4560..b0a55383ea 100644
--- a/esp32s2/src/gpio/status1_w1ts.rs
+++ b/esp32s2/src/gpio/status1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. Recommended operation: use this register to set GPIO_STATUS1_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn status1_w1ts(&mut self) -> STATUS1_W1TS_W<STATUS1_W1TS_SPEC> {
         STATUS1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status_w1tc.rs b/esp32s2/src/gpio/status_w1tc.rs
index bf5f2c61e4..c15de182ed 100644
--- a/esp32s2/src/gpio/status_w1tc.rs
+++ b/esp32s2/src/gpio/status_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT."]
     #[inline(always)]
-    #[must_use]
     pub fn status_w1tc(&mut self) -> STATUS_W1TC_W<STATUS_W1TC_SPEC> {
         STATUS_W1TC_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio/status_w1ts.rs b/esp32s2/src/gpio/status_w1ts.rs
index 075be6c021..e5c92849c5 100644
--- a/esp32s2/src/gpio/status_w1ts.rs
+++ b/esp32s2/src/gpio/status_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT."]
     #[inline(always)]
-    #[must_use]
     pub fn status_w1ts(&mut self) -> STATUS_W1TS_W<STATUS_W1TS_SPEC> {
         STATUS_W1TS_W::new(self, 0)
     }
diff --git a/esp32s2/src/gpio_sd/clock_gate.rs b/esp32s2/src/gpio_sd/clock_gate.rs
index f999d3d68b..b7ff11c04b 100644
--- a/esp32s2/src/gpio_sd/clock_gate.rs
+++ b/esp32s2/src/gpio_sd/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/gpio_sd/sigmadelta.rs b/esp32s2/src/gpio_sd/sigmadelta.rs
index 909f3094da..c2c6acecd6 100644
--- a/esp32s2/src/gpio_sd/sigmadelta.rs
+++ b/esp32s2/src/gpio_sd/sigmadelta.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
-    #[must_use]
     pub fn in_(&mut self) -> IN_W<SIGMADELTA_SPEC> {
         IN_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<SIGMADELTA_SPEC> {
         PRESCALE_W::new(self, 8)
     }
diff --git a/esp32s2/src/gpio_sd/sigmadelta_misc.rs b/esp32s2/src/gpio_sd/sigmadelta_misc.rs
index 3e02554677..311f926403 100644
--- a/esp32s2/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32s2/src/gpio_sd/sigmadelta_misc.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
-    #[must_use]
     pub fn function_clk_en(&mut self) -> FUNCTION_CLK_EN_W<SIGMADELTA_MISC_SPEC> {
         FUNCTION_CLK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_swap(&mut self) -> SPI_SWAP_W<SIGMADELTA_MISC_SPEC> {
         SPI_SWAP_W::new(self, 31)
     }
diff --git a/esp32s2/src/gpio_sd/version.rs b/esp32s2/src/gpio_sd/version.rs
index 0cdf6644ed..993b6a131d 100644
--- a/esp32s2/src/gpio_sd/version.rs
+++ b/esp32s2/src/gpio_sd/version.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W<VERSION_SPEC> {
         GPIO_SD_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/date.rs b/esp32s2/src/hmac/date.rs
index 0b52532e5b..43c4f138e2 100644
--- a/esp32s2/src/hmac/date.rs
+++ b/esp32s2/src/hmac/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/one_block.rs b/esp32s2/src/hmac/one_block.rs
index 1517936d66..a51e4aca53 100644
--- a/esp32s2/src/hmac/one_block.rs
+++ b/esp32s2/src/hmac/one_block.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ONE_BLOCK_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to show no padding is required."]
     #[inline(always)]
-    #[must_use]
     pub fn set_one_block(&mut self) -> SET_ONE_BLOCK_W<ONE_BLOCK_SPEC> {
         SET_ONE_BLOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_invalidate_ds.rs b/esp32s2/src/hmac/set_invalidate_ds.rs
index 7e6fc064b1..c1b45be38b 100644
--- a/esp32s2/src/hmac/set_invalidate_ds.rs
+++ b/esp32s2/src/hmac/set_invalidate_ds.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_INVALIDATE_DS_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear calculation results in DS function under downstream mode."]
     #[inline(always)]
-    #[must_use]
     pub fn set_invalidate_ds(&mut self) -> SET_INVALIDATE_DS_W<SET_INVALIDATE_DS_SPEC> {
         SET_INVALIDATE_DS_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_invalidate_jtag.rs b/esp32s2/src/hmac/set_invalidate_jtag.rs
index f61dc56fef..e701ebc1ee 100644
--- a/esp32s2/src/hmac/set_invalidate_jtag.rs
+++ b/esp32s2/src/hmac/set_invalidate_jtag.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_INVALIDATE_JTAG_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear calculation results in JTAG re-enable function under downstream mode."]
     #[inline(always)]
-    #[must_use]
     pub fn set_invalidate_jtag(&mut self) -> SET_INVALIDATE_JTAG_W<SET_INVALIDATE_JTAG_SPEC> {
         SET_INVALIDATE_JTAG_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_message_end.rs b/esp32s2/src/hmac/set_message_end.rs
index af64ee9cb8..08b86da0f4 100644
--- a/esp32s2/src/hmac/set_message_end.rs
+++ b/esp32s2/src/hmac/set_message_end.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_END_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to start hardware padding."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_end(&mut self) -> SET_TEXT_END_W<SET_MESSAGE_END_SPEC> {
         SET_TEXT_END_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_message_ing.rs b/esp32s2/src/hmac/set_message_ing.rs
index d28acb5378..628c695fc2 100644
--- a/esp32s2/src/hmac/set_message_ing.rs
+++ b/esp32s2/src/hmac/set_message_ing.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_ING_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to show there are still some message blocks to be processed."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_ing(&mut self) -> SET_TEXT_ING_W<SET_MESSAGE_ING_SPEC> {
         SET_TEXT_ING_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_message_one.rs b/esp32s2/src/hmac/set_message_one.rs
index 84f799ff35..a60f517ead 100644
--- a/esp32s2/src/hmac/set_message_one.rs
+++ b/esp32s2/src/hmac/set_message_one.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_ONE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Call SHA to calculate one message block."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_one(&mut self) -> SET_TEXT_ONE_W<SET_MESSAGE_ONE_SPEC> {
         SET_TEXT_ONE_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_message_pad.rs b/esp32s2/src/hmac/set_message_pad.rs
index 823cabaa88..e165e459bd 100644
--- a/esp32s2/src/hmac/set_message_pad.rs
+++ b/esp32s2/src/hmac/set_message_pad.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_PAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to let software do padding job."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_pad(&mut self) -> SET_TEXT_PAD_W<SET_MESSAGE_PAD_SPEC> {
         SET_TEXT_PAD_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_para_finish.rs b/esp32s2/src/hmac/set_para_finish.rs
index 2edbec2cab..f8a313828c 100644
--- a/esp32s2/src/hmac/set_para_finish.rs
+++ b/esp32s2/src/hmac/set_para_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to finish HMAC configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn set_para_end(&mut self) -> SET_PARA_END_W<SET_PARA_FINISH_SPEC> {
         SET_PARA_END_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_para_key.rs b/esp32s2/src/hmac/set_para_key.rs
index 03a2ad8c49..654389d2fd 100644
--- a/esp32s2/src/hmac/set_para_key.rs
+++ b/esp32s2/src/hmac/set_para_key.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_KEY_SPEC> {
 impl W {
     #[doc = "Bits 0:2 - Select hmac key."]
     #[inline(always)]
-    #[must_use]
     pub fn key_set(&mut self) -> KEY_SET_W<SET_PARA_KEY_SPEC> {
         KEY_SET_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_para_purpose.rs b/esp32s2/src/hmac/set_para_purpose.rs
index 9434722c26..5b3fa4e8b1 100644
--- a/esp32s2/src/hmac/set_para_purpose.rs
+++ b/esp32s2/src/hmac/set_para_purpose.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_PURPOSE_SPEC> {
 impl W {
     #[doc = "Bits 0:3 - Set hmac purpose."]
     #[inline(always)]
-    #[must_use]
     pub fn purpose_set(&mut self) -> PURPOSE_SET_W<SET_PARA_PURPOSE_SPEC> {
         PURPOSE_SET_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_result_finish.rs b/esp32s2/src/hmac/set_result_finish.rs
index 17a0a47b48..d3ddf71b59 100644
--- a/esp32s2/src/hmac/set_result_finish.rs
+++ b/esp32s2/src/hmac/set_result_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_RESULT_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to end upstream and clear the calculation result."]
     #[inline(always)]
-    #[must_use]
     pub fn set_result_end(&mut self) -> SET_RESULT_END_W<SET_RESULT_FINISH_SPEC> {
         SET_RESULT_END_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/set_start.rs b/esp32s2/src/hmac/set_start.rs
index 1e159beb10..b7a2440a29 100644
--- a/esp32s2/src/hmac/set_start.rs
+++ b/esp32s2/src/hmac/set_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable HMAC."]
     #[inline(always)]
-    #[must_use]
     pub fn set_start(&mut self) -> SET_START_W<SET_START_SPEC> {
         SET_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/hmac/wr_message_.rs b/esp32s2/src/hmac/wr_message_.rs
index 9b54c24cd1..5a4057f47a 100644
--- a/esp32s2/src/hmac/wr_message_.rs
+++ b/esp32s2/src/hmac/wr_message_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE__SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Store the %sth 32-bit of message."]
     #[inline(always)]
-    #[must_use]
     pub fn wdata(&mut self) -> WDATA_W<WR_MESSAGE__SPEC> {
         WDATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/comd.rs b/esp32s2/src/i2c0/comd.rs
index bda2cbe5c2..71564c245d 100644
--- a/esp32s2/src/i2c0/comd.rs
+++ b/esp32s2/src/i2c0/comd.rs
@@ -170,37 +170,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Number of bytes to be sent or received for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_num(&mut self) -> BYTE_NUM_W<COMD_SPEC> {
         BYTE_NUM_W::new(self, 0)
     }
     #[doc = "Bit 8 - Acknowledge check enable for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_check_en(&mut self) -> ACK_CHECK_EN_W<COMD_SPEC> {
         ACK_CHECK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Acknowledge expected for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_exp(&mut self) -> ACK_EXP_W<COMD_SPEC> {
         ACK_EXP_W::new(self, 9)
     }
     #[doc = "Bit 10 - Acknowledge value for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_value(&mut self) -> ACK_VALUE_W<COMD_SPEC> {
         ACK_VALUE_W::new(self, 10)
     }
     #[doc = "Bits 11:13 - Opcode part of command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn opcode(&mut self) -> OPCODE_W<COMD_SPEC> {
         OPCODE_W::new(self, 11)
     }
     #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to high level."]
     #[inline(always)]
-    #[must_use]
     pub fn command_done(&mut self) -> COMMAND_DONE_W<COMD_SPEC> {
         COMMAND_DONE_W::new(self, 31)
     }
diff --git a/esp32s2/src/i2c0/ctr.rs b/esp32s2/src/i2c0/ctr.rs
index 79880886e2..3995ecab32 100644
--- a/esp32s2/src/i2c0/ctr.rs
+++ b/esp32s2/src/i2c0/ctr.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 0: direct output. 1: open drain output."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - 0: direct output. 1: open drain output."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
     #[inline(always)]
-    #[must_use]
     pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
         SAMPLE_SCL_LEVEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
         RX_FULL_ACK_LEVEL_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
         MS_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to start sending the data in TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
         TRANS_START_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit. 0: send data from the most significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
         TX_LSB_FIRST_W::new(self, 6)
     }
     #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit. 0: receive data from the most significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
         RX_LSB_FIRST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
         CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the enable bit for I2C bus arbitration function."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
         ARBITRATION_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - This register is used to reset the SCL_FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
         FSM_RST_W::new(self, 10)
     }
     #[doc = "Bit 11 - This register is used to control the REF_TICK."]
     #[inline(always)]
-    #[must_use]
     pub fn ref_always_on(&mut self) -> REF_ALWAYS_ON_W<CTR_SPEC> {
         REF_ALWAYS_ON_W::new(self, 11)
     }
diff --git a/esp32s2/src/i2c0/data.rs b/esp32s2/src/i2c0/data.rs
index 1ac18cdb42..abb76357df 100644
--- a/esp32s2/src/i2c0/data.rs
+++ b/esp32s2/src/i2c0/data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The value of RX FIFO read data."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_rdata(&mut self) -> FIFO_RDATA_W<DATA_SPEC> {
         FIFO_RDATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/date.rs b/esp32s2/src/i2c0/date.rs
index 72426532e8..ffbce42e98 100644
--- a/esp32s2/src/i2c0/date.rs
+++ b/esp32s2/src/i2c0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/fifo_conf.rs b/esp32s2/src/i2c0/fifo_conf.rs
index 09d12cca34..a43832926e 100644
--- a/esp32s2/src/i2c0/fifo_conf.rs
+++ b/esp32s2/src/i2c0/fifo_conf.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
         RXFIFO_WM_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD\\[4:0\\], I2C_TXFIFO_WM_INT_RAW bit will be valid."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
         TXFIFO_WM_THRHD_W::new(self, 5)
     }
     #[doc = "Bit 10 - Set this bit to enable APB non-FIFO mode."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<FIFO_CONF_SPEC> {
         NONFIFO_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W<FIFO_CONF_SPEC> {
         FIFO_ADDR_CFG_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to reset RX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<FIFO_CONF_SPEC> {
         RX_FIFO_RST_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to reset TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<FIFO_CONF_SPEC> {
         TX_FIFO_RST_W::new(self, 13)
     }
     #[doc = "Bits 14:19 - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_rx_thres(&mut self) -> NONFIFO_RX_THRES_W<FIFO_CONF_SPEC> {
         NONFIFO_RX_THRES_W::new(self, 14)
     }
     #[doc = "Bits 20:25 - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_tx_thres(&mut self) -> NONFIFO_TX_THRES_W<FIFO_CONF_SPEC> {
         NONFIFO_TX_THRES_W::new(self, 20)
     }
     #[doc = "Bit 26 - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W<FIFO_CONF_SPEC> {
         FIFO_PRT_EN_W::new(self, 26)
     }
diff --git a/esp32s2/src/i2c0/fifo_st.rs b/esp32s2/src/i2c0/fifo_st.rs
index 31b9d0d578..1ccabccdff 100644
--- a/esp32s2/src/i2c0/fifo_st.rs
+++ b/esp32s2/src/i2c0/fifo_st.rs
@@ -58,13 +58,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20 - Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_update(&mut self) -> RX_UPDATE_W<FIFO_ST_SPEC> {
         RX_UPDATE_W::new(self, 20)
     }
     #[doc = "Bit 21 - Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_update(&mut self) -> TX_UPDATE_W<FIFO_ST_SPEC> {
         TX_UPDATE_W::new(self, 21)
     }
diff --git a/esp32s2/src/i2c0/int_clr.rs b/esp32s2/src/i2c0/int_clr.rs
index 526670b2bd..a81fd836b8 100644
--- a/esp32s2/src/i2c0/int_clr.rs
+++ b/esp32s2/src/i2c0/int_clr.rs
@@ -43,103 +43,86 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
         RXFIFO_WM_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
         TXFIFO_WM_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
         BYTE_TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
         MST_TXFIFO_UDF_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
         TXFIFO_OVF_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
         RXFIFO_UDF_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
         SCL_ST_TO_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
         SCL_MAIN_ST_TO_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
         DET_START_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_CLR_SPEC> {
         SLAVE_STRETCH_W::new(self, 16)
     }
diff --git a/esp32s2/src/i2c0/int_ena.rs b/esp32s2/src/i2c0/int_ena.rs
index 63dad7d59d..f3b0b2f407 100644
--- a/esp32s2/src/i2c0/int_ena.rs
+++ b/esp32s2/src/i2c0/int_ena.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_ENA_SPEC> {
         RXFIFO_WM_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_ENA_SPEC> {
         TXFIFO_WM_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_ENA_SPEC> {
         BYTE_TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_ENA_SPEC> {
         MST_TXFIFO_UDF_W::new(self, 6)
     }
     #[doc = "Bit 7 - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_ENA_SPEC> {
         TXFIFO_OVF_W::new(self, 11)
     }
     #[doc = "Bit 12 - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_ENA_SPEC> {
         RXFIFO_UDF_W::new(self, 12)
     }
     #[doc = "Bit 13 - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_ENA_SPEC> {
         SCL_ST_TO_W::new(self, 13)
     }
     #[doc = "Bit 14 - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_ENA_SPEC> {
         SCL_MAIN_ST_TO_W::new(self, 14)
     }
     #[doc = "Bit 15 - The raw interrupt bit for I2C_DET_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn det_start(&mut self) -> DET_START_W<INT_ENA_SPEC> {
         DET_START_W::new(self, 15)
     }
     #[doc = "Bit 16 - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_ENA_SPEC> {
         SLAVE_STRETCH_W::new(self, 16)
     }
diff --git a/esp32s2/src/i2c0/scl_filter_cfg.rs b/esp32s2/src/i2c0/scl_filter_cfg.rs
index 81bf8a9a7d..7158cfc803 100644
--- a/esp32s2/src/i2c0/scl_filter_cfg.rs
+++ b/esp32s2/src/i2c0/scl_filter_cfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<SCL_FILTER_CFG_SPEC> {
         SCL_FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 4 - This is the filter enable bit for SCL."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<SCL_FILTER_CFG_SPEC> {
         SCL_FILTER_EN_W::new(self, 4)
     }
diff --git a/esp32s2/src/i2c0/scl_high_period.rs b/esp32s2/src/i2c0/scl_high_period.rs
index 61757e1fa9..1cecb0f67d 100644
--- a/esp32s2/src/i2c0/scl_high_period.rs
+++ b/esp32s2/src/i2c0/scl_high_period.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_HIGH_PERIOD_W::new(self, 0)
     }
     #[doc = "Bits 14:27 - This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_WAIT_HIGH_PERIOD_W::new(self, 14)
     }
diff --git a/esp32s2/src/i2c0/scl_low_period.rs b/esp32s2/src/i2c0/scl_low_period.rs
index 8f6255b22d..ba38779d6a 100644
--- a/esp32s2/src/i2c0/scl_low_period.rs
+++ b/esp32s2/src/i2c0/scl_low_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<SCL_LOW_PERIOD_SPEC> {
         SCL_LOW_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_main_st_time_out.rs b/esp32s2/src/i2c0/scl_main_st_time_out.rs
index c1dc9dd008..aa9fd77ceb 100644
--- a/esp32s2/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32s2/src/i2c0/scl_main_st_time_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The threshold value of SCL_MAIN_FSM state unchanged period."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<SCL_MAIN_ST_TIME_OUT_SPEC> {
         SCL_MAIN_ST_TO_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_rstart_setup.rs b/esp32s2/src/i2c0/scl_rstart_setup.rs
index 962c366cee..debbc0c031 100644
--- a/esp32s2/src/i2c0/scl_rstart_setup.rs
+++ b/esp32s2/src/i2c0/scl_rstart_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_RSTART_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_sp_conf.rs b/esp32s2/src/i2c0/scl_sp_conf.rs
index 8d1a050e19..456e740d50 100644
--- a/esp32s2/src/i2c0/scl_sp_conf.rs
+++ b/esp32s2/src/i2c0/scl_sp_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM\\[4:0\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W<SCL_SP_CONF_SPEC> {
         SCL_RST_SLV_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W<SCL_SP_CONF_SPEC> {
         SCL_RST_SLV_NUM_W::new(self, 1)
     }
     #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W<SCL_SP_CONF_SPEC> {
         SCL_PD_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W<SCL_SP_CONF_SPEC> {
         SDA_PD_EN_W::new(self, 7)
     }
diff --git a/esp32s2/src/i2c0/scl_st_time_out.rs b/esp32s2/src/i2c0/scl_st_time_out.rs
index 66d8159025..e36b606e6e 100644
--- a/esp32s2/src/i2c0/scl_st_time_out.rs
+++ b/esp32s2/src/i2c0/scl_st_time_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The threshold value of SCL_FSM state unchanged period."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<SCL_ST_TIME_OUT_SPEC> {
         SCL_ST_TO_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_start_hold.rs b/esp32s2/src/i2c0/scl_start_hold.rs
index 61e1bd9f6d..39c716d315 100644
--- a/esp32s2/src/i2c0/scl_start_hold.rs
+++ b/esp32s2/src/i2c0/scl_start_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_START_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_stop_hold.rs b/esp32s2/src/i2c0/scl_stop_hold.rs
index 64102d779e..fcc6412e61 100644
--- a/esp32s2/src/i2c0/scl_stop_hold.rs
+++ b/esp32s2/src/i2c0/scl_stop_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_stop_setup.rs b/esp32s2/src/i2c0/scl_stop_setup.rs
index 7047ebdd72..143273f66b 100644
--- a/esp32s2/src/i2c0/scl_stop_setup.rs
+++ b/esp32s2/src/i2c0/scl_stop_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/scl_stretch_conf.rs b/esp32s2/src/i2c0/scl_stretch_conf.rs
index d580a733f1..b4c734d5ee 100644
--- a/esp32s2/src/i2c0/scl_stretch_conf.rs
+++ b/esp32s2/src/i2c0/scl_stretch_conf.rs
@@ -36,19 +36,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
-    #[must_use]
     pub fn stretch_protect_num(&mut self) -> STRETCH_PROTECT_NUM_W<SCL_STRETCH_CONF_SPEC> {
         STRETCH_PROTECT_NUM_W::new(self, 0)
     }
     #[doc = "Bit 10 - The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_scl_stretch_en(&mut self) -> SLAVE_SCL_STRETCH_EN_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_SCL_STRETCH_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the I2C slave SCL stretch function."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_scl_stretch_clr(&mut self) -> SLAVE_SCL_STRETCH_CLR_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_SCL_STRETCH_CLR_W::new(self, 11)
     }
diff --git a/esp32s2/src/i2c0/sda_filter_cfg.rs b/esp32s2/src/i2c0/sda_filter_cfg.rs
index 995c0d983b..cf277938ef 100644
--- a/esp32s2/src/i2c0/sda_filter_cfg.rs
+++ b/esp32s2/src/i2c0/sda_filter_cfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<SDA_FILTER_CFG_SPEC> {
         SDA_FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 4 - This is the filter enable bit for SDA."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<SDA_FILTER_CFG_SPEC> {
         SDA_FILTER_EN_W::new(self, 4)
     }
diff --git a/esp32s2/src/i2c0/sda_hold.rs b/esp32s2/src/i2c0/sda_hold.rs
index 63a85f8c4a..2a6bb18ab1 100644
--- a/esp32s2/src/i2c0/sda_hold.rs
+++ b/esp32s2/src/i2c0/sda_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/sda_sample.rs b/esp32s2/src/i2c0/sda_sample.rs
index 57a1759a93..b956f06843 100644
--- a/esp32s2/src/i2c0/sda_sample.rs
+++ b/esp32s2/src/i2c0/sda_sample.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_SAMPLE_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2c0/slave_addr.rs b/esp32s2/src/i2c0/slave_addr.rs
index ee01a15ed5..1b27ba5ce3 100644
--- a/esp32s2/src/i2c0/slave_addr.rs
+++ b/esp32s2/src/i2c0/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - This field is used to enable the slave 10-bit addressing mode in master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
         ADDR_10BIT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/i2c0/to.rs b/esp32s2/src/i2c0/to.rs
index 978aa9acd6..331b730055 100644
--- a/esp32s2/src/i2c0/to.rs
+++ b/esp32s2/src/i2c0/to.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out_value(&mut self) -> TIME_OUT_VALUE_W<TO_SPEC> {
         TIME_OUT_VALUE_W::new(self, 0)
     }
     #[doc = "Bit 24 - This is the enable bit for time out control."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out_en(&mut self) -> TIME_OUT_EN_W<TO_SPEC> {
         TIME_OUT_EN_W::new(self, 24)
     }
diff --git a/esp32s2/src/i2s0/clkm_conf.rs b/esp32s2/src/i2s0/clkm_conf.rs
index 2418b799f2..194a61c00a 100644
--- a/esp32s2/src/i2s0/clkm_conf.rs
+++ b/esp32s2/src/i2s0/clkm_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value."]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
         CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:13 - Fractional clock divider numerator value."]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
         CLKM_DIV_B_W::new(self, 8)
     }
     #[doc = "Bits 14:19 - Fractional clock divider denominator value."]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
         CLKM_DIV_A_W::new(self, 14)
     }
     #[doc = "Bit 20 - Set this bit to enable clock gate."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
         CLK_EN_W::new(self, 20)
     }
     #[doc = "Bits 21:22 - Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
         CLK_SEL_W::new(self, 21)
     }
diff --git a/esp32s2/src/i2s0/conf.rs b/esp32s2/src/i2s0/conf.rs
index f77295ac78..7376a7c6b7 100644
--- a/esp32s2/src/i2s0/conf.rs
+++ b/esp32s2/src/i2s0/conf.rs
@@ -274,157 +274,131 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_reset(&mut self) -> TX_RESET_W<CONF_SPEC> {
         TX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_reset(&mut self) -> RX_RESET_W<CONF_SPEC> {
         RX_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<CONF_SPEC> {
         TX_FIFO_RESET_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset RX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<CONF_SPEC> {
         RX_FIFO_RESET_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to start transmitting data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<CONF_SPEC> {
         TX_START_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to start receiving data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<CONF_SPEC> {
         RX_START_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable slave transmitter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<CONF_SPEC> {
         TX_SLAVE_MOD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable slave receiver mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<CONF_SPEC> {
         RX_SLAVE_MOD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to transmit right channel data first."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_right_first(&mut self) -> TX_RIGHT_FIRST_W<CONF_SPEC> {
         TX_RIGHT_FIRST_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to receive right channel data first."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_right_first(&mut self) -> RX_RIGHT_FIRST_W<CONF_SPEC> {
         RX_RIGHT_FIRST_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to enable transmitter in Phillips standard mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<CONF_SPEC> {
         TX_MSB_SHIFT_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to enable receiver in Phillips standard mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<CONF_SPEC> {
         RX_MSB_SHIFT_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to enable transmitter in PCM standard mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_short_sync(&mut self) -> TX_SHORT_SYNC_W<CONF_SPEC> {
         TX_SHORT_SYNC_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to enable receiver in PCM standard mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_short_sync(&mut self) -> RX_SHORT_SYNC_W<CONF_SPEC> {
         RX_SHORT_SYNC_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable transmitter in mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono(&mut self) -> TX_MONO_W<CONF_SPEC> {
         TX_MONO_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable receiver in mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono(&mut self) -> RX_MONO_W<CONF_SPEC> {
         RX_MONO_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to place right channel data at the MSB in TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_right(&mut self) -> TX_MSB_RIGHT_W<CONF_SPEC> {
         TX_MSB_RIGHT_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to place right channel data at the MSB in RX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_right(&mut self) -> RX_MSB_RIGHT_W<CONF_SPEC> {
         RX_MSB_RIGHT_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first_dma(&mut self) -> TX_LSB_FIRST_DMA_W<CONF_SPEC> {
         TX_LSB_FIRST_DMA_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first_dma(&mut self) -> RX_LSB_FIRST_DMA_W<CONF_SPEC> {
         RX_LSB_FIRST_DMA_W::new(self, 19)
     }
     #[doc = "Bit 20 - Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<CONF_SPEC> {
         SIG_LOOPBACK_W::new(self, 20)
     }
     #[doc = "Bit 24 - 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dma_equal(&mut self) -> TX_DMA_EQUAL_W<CONF_SPEC> {
         TX_DMA_EQUAL_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dma_equal(&mut self) -> RX_DMA_EQUAL_W<CONF_SPEC> {
         RX_DMA_EQUAL_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable I2S to prepare data earlier."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_req_en(&mut self) -> PRE_REQ_EN_W<CONF_SPEC> {
         PRE_REQ_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - I2S TX byte endianness."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W<CONF_SPEC> {
         TX_BIG_ENDIAN_W::new(self, 27)
     }
     #[doc = "Bit 28 - I2S RX byte endianness."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<CONF_SPEC> {
         RX_BIG_ENDIAN_W::new(self, 28)
     }
diff --git a/esp32s2/src/i2s0/conf1.rs b/esp32s2/src/i2s0/conf1.rs
index 21e1c3dcfd..b9aaf9e2c8 100644
--- a/esp32s2/src/i2s0/conf1.rs
+++ b/esp32s2/src/i2s0/conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<CONF1_SPEC> {
         TX_PCM_CONF_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to bypass Compress/Decompress module for transmitted data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<CONF1_SPEC> {
         TX_PCM_BYPASS_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<CONF1_SPEC> {
         RX_PCM_CONF_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to bypass Compress/Decompress module for received data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<CONF1_SPEC> {
         RX_PCM_BYPASS_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to stop the output of BCK signal and WS signal when TX FIFO is empty."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<CONF1_SPEC> {
         TX_STOP_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_zeros_rm_en(&mut self) -> TX_ZEROS_RM_EN_W<CONF1_SPEC> {
         TX_ZEROS_RM_EN_W::new(self, 9)
     }
diff --git a/esp32s2/src/i2s0/conf2.rs b/esp32s2/src/i2s0/conf2.rs
index eac5081dbd..be1e00299e 100644
--- a/esp32s2/src/i2s0/conf2.rs
+++ b/esp32s2/src/i2s0/conf2.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable camera mode."]
     #[inline(always)]
-    #[must_use]
     pub fn camera_en(&mut self) -> CAMERA_EN_W<CONF2_SPEC> {
         CAMERA_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - LCD WR double for one datum."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_tx_wrx2_en(&mut self) -> LCD_TX_WRX2_EN_W<CONF2_SPEC> {
         LCD_TX_WRX2_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to duplicate data pairs (Frame Form 2) in LCD mode."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_tx_sdx2_en(&mut self) -> LCD_TX_SDX2_EN_W<CONF2_SPEC> {
         LCD_TX_SDX2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - for debug camera mode enable"]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable_test_en(&mut self) -> DATA_ENABLE_TEST_EN_W<CONF2_SPEC> {
         DATA_ENABLE_TEST_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - for debug camera mode enable"]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable(&mut self) -> DATA_ENABLE_W<CONF2_SPEC> {
         DATA_ENABLE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable LCD mode."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_en(&mut self) -> LCD_EN_W<CONF2_SPEC> {
         LCD_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable the function that ADC mode is triggered by external signal."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_adc_start_en(&mut self) -> EXT_ADC_START_EN_W<CONF2_SPEC> {
         EXT_ADC_START_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks."]
     #[inline(always)]
-    #[must_use]
     pub fn inter_valid_en(&mut self) -> INTER_VALID_EN_W<CONF2_SPEC> {
         INTER_VALID_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to reset FIFO in camera mode."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_sync_fifo_reset(&mut self) -> CAM_SYNC_FIFO_RESET_W<CONF2_SPEC> {
         CAM_SYNC_FIFO_RESET_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to loopback PCLK from I2S0I_WS_out."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clk_loopback(&mut self) -> CAM_CLK_LOOPBACK_W<CONF2_SPEC> {
         CAM_CLK_LOOPBACK_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to enable I2S VSYNC filter function."]
     #[inline(always)]
-    #[must_use]
     pub fn vsync_filter_en(&mut self) -> VSYNC_FILTER_EN_W<CONF2_SPEC> {
         VSYNC_FILTER_EN_W::new(self, 10)
     }
     #[doc = "Bits 11:13 - Configure the I2S VSYNC filter threshold value."]
     #[inline(always)]
-    #[must_use]
     pub fn vsync_filter_thres(&mut self) -> VSYNC_FILTER_THRES_W<CONF2_SPEC> {
         VSYNC_FILTER_THRES_W::new(self, 11)
     }
diff --git a/esp32s2/src/i2s0/conf_chan.rs b/esp32s2/src/i2s0/conf_chan.rs
index 0f877274d7..45450601bc 100644
--- a/esp32s2/src/i2s0/conf_chan.rs
+++ b/esp32s2/src/i2s0/conf_chan.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - I2S transmitter channel mode configuration bits."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<CONF_CHAN_SPEC> {
         TX_CHAN_MOD_W::new(self, 0)
     }
     #[doc = "Bits 3:4 - I2S receiver channel mode configuration bits."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_chan_mod(&mut self) -> RX_CHAN_MOD_W<CONF_CHAN_SPEC> {
         RX_CHAN_MOD_W::new(self, 3)
     }
diff --git a/esp32s2/src/i2s0/conf_sigle_data.rs b/esp32s2/src/i2s0/conf_sigle_data.rs
index 9381fa631e..f1408276d1 100644
--- a/esp32s2/src/i2s0/conf_sigle_data.rs
+++ b/esp32s2/src/i2s0/conf_sigle_data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT."]
     #[inline(always)]
-    #[must_use]
     pub fn sigle_data(&mut self) -> SIGLE_DATA_W<CONF_SIGLE_DATA_SPEC> {
         SIGLE_DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2s0/date.rs b/esp32s2/src/i2s0/date.rs
index 8613f6e8d8..22dd9de606 100644
--- a/esp32s2/src/i2s0/date.rs
+++ b/esp32s2/src/i2s0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2s0/fifo_conf.rs b/esp32s2/src/i2s0/fifo_conf.rs
index ef3a853366..a3e63bd86e 100644
--- a/esp32s2/src/i2s0/fifo_conf.rs
+++ b/esp32s2/src/i2s0/fifo_conf.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data_num(&mut self) -> RX_DATA_NUM_W<FIFO_CONF_SPEC> {
         RX_DATA_NUM_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM\\[5:0\\]. (TX FIFO is almost empty threshold.)"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data_num(&mut self) -> TX_DATA_NUM_W<FIFO_CONF_SPEC> {
         TX_DATA_NUM_W::new(self, 6)
     }
     #[doc = "Bit 12 - Set this bit to enable I2S DMA mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dscr_en(&mut self) -> DSCR_EN_W<FIFO_CONF_SPEC> {
         DSCR_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:15 - Transmitter FIFO mode configuration bits"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_mod(&mut self) -> TX_FIFO_MOD_W<FIFO_CONF_SPEC> {
         TX_FIFO_MOD_W::new(self, 13)
     }
     #[doc = "Bits 16:18 - Receiver FIFO mode configuration bits"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_mod(&mut self) -> RX_FIFO_MOD_W<FIFO_CONF_SPEC> {
         RX_FIFO_MOD_W::new(self, 16)
     }
     #[doc = "Bit 19 - The bit should always be set to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_mod_force_en(&mut self) -> TX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
         TX_FIFO_MOD_FORCE_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - The bit should always be set to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_mod_force_en(&mut self) -> RX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
         RX_FIFO_MOD_FORCE_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - force write back rx data to memory"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_sync(&mut self) -> RX_FIFO_SYNC_W<FIFO_CONF_SPEC> {
         RX_FIFO_SYNC_W::new(self, 21)
     }
     #[doc = "Bit 22 - Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_24msb_en(&mut self) -> RX_24MSB_EN_W<FIFO_CONF_SPEC> {
         RX_24MSB_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_24msb_en(&mut self) -> TX_24MSB_EN_W<FIFO_CONF_SPEC> {
         TX_24MSB_EN_W::new(self, 23)
     }
diff --git a/esp32s2/src/i2s0/in_link.rs b/esp32s2/src/i2s0/in_link.rs
index 5e04c22c26..3790b74a9f 100644
--- a/esp32s2/src/i2s0/in_link.rs
+++ b/esp32s2/src/i2s0/in_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of first inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set this bit to stop inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to restart inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32s2/src/i2s0/infifo_pop.rs b/esp32s2/src/i2s0/infifo_pop.rs
index 4242d79d77..cdf04a3a80 100644
--- a/esp32s2/src/i2s0/infifo_pop.rs
+++ b/esp32s2/src/i2s0/infifo_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16 - APB in FIFO pop."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_pop(&mut self) -> INFIFO_POP_W<INFIFO_POP_SPEC> {
         INFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32s2/src/i2s0/int_clr.rs b/esp32s2/src/i2s0/int_clr.rs
index 440cd56c81..272562e4d2 100644
--- a/esp32s2/src/i2s0/int_clr.rs
+++ b/esp32s2/src/i2s0/int_clr.rs
@@ -45,109 +45,91 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear I2S_RX_TAKE_DATA_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn take_data(&mut self) -> TAKE_DATA_W<INT_CLR_SPEC> {
         TAKE_DATA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear I2S_TX_PUT_DATA_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn put_data(&mut self) -> PUT_DATA_W<INT_CLR_SPEC> {
         PUT_DATA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear I2S_RX_WFULL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wfull(&mut self) -> RX_WFULL_W<INT_CLR_SPEC> {
         RX_WFULL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear I2S_RX_REMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rempty(&mut self) -> RX_REMPTY_W<INT_CLR_SPEC> {
         RX_REMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear I2S_TX_WFULL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wfull(&mut self) -> TX_WFULL_W<INT_CLR_SPEC> {
         TX_WFULL_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear I2S_TX_REMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rempty(&mut self) -> TX_REMPTY_W<INT_CLR_SPEC> {
         TX_REMPTY_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear I2S_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear I2S_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear I2S_IN_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
         IN_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear I2S_IN_SUC_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 9)
     }
     #[doc = "Bit 10 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear I2S_OUT_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear I2S_OUT_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear I2S_IN_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
         IN_DSCR_ERR_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear I2S_OUT_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
         OUT_DSCR_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear I2S_IN_DSCR_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear I2S_OUT_TOTAL_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear I2S_V_SYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn v_sync(&mut self) -> V_SYNC_W<INT_CLR_SPEC> {
         V_SYNC_W::new(self, 17)
     }
diff --git a/esp32s2/src/i2s0/int_ena.rs b/esp32s2/src/i2s0/int_ena.rs
index 877bfb75d3..9041d8e598 100644
--- a/esp32s2/src/i2s0/int_ena.rs
+++ b/esp32s2/src/i2s0/int_ena.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2S_RX_TAKE_DATA_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_take_data(&mut self) -> RX_TAKE_DATA_W<INT_ENA_SPEC> {
         RX_TAKE_DATA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for I2S_TX_PUT_DATA_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_put_data(&mut self) -> TX_PUT_DATA_W<INT_ENA_SPEC> {
         TX_PUT_DATA_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for I2S_RX_WFULL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wfull(&mut self) -> RX_WFULL_W<INT_ENA_SPEC> {
         RX_WFULL_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for I2S_RX_REMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rempty(&mut self) -> RX_REMPTY_W<INT_ENA_SPEC> {
         RX_REMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt enable bit for I2S_TX_WFULL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wfull(&mut self) -> TX_WFULL_W<INT_ENA_SPEC> {
         TX_WFULL_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for I2S_TX_REMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rempty(&mut self) -> TX_REMPTY_W<INT_ENA_SPEC> {
         TX_REMPTY_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for I2S_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for I2S_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for I2S_IN_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_ENA_SPEC> {
         IN_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for I2S_IN_SUC_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 9)
     }
     #[doc = "Bit 10 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for I2S_OUT_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12 - The interrupt enable bit for I2S_OUT_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for I2S_IN_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_ENA_SPEC> {
         IN_DSCR_ERR_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for I2S_OUT_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_ENA_SPEC> {
         OUT_DSCR_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for I2S_IN_DSCR_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_ENA_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 15)
     }
     #[doc = "Bit 16 - The interrupt enable bit for I2S_OUT_TOTAL_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for I2S_V_SYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn v_sync(&mut self) -> V_SYNC_W<INT_ENA_SPEC> {
         V_SYNC_W::new(self, 17)
     }
diff --git a/esp32s2/src/i2s0/lc_conf.rs b/esp32s2/src/i2s0/lc_conf.rs
index 9888a615af..d3b79e1391 100644
--- a/esp32s2/src/i2s0/lc_conf.rs
+++ b/esp32s2/src/i2s0/lc_conf.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<LC_CONF_SPEC> {
         IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset out-DMA FSM. Set this bit before the DMA configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<LC_CONF_SPEC> {
         OUT_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset AHB interface cmdFIFO of DMA. Set this bit before the DMA configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<LC_CONF_SPEC> {
         AHBM_FIFO_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset AHB interface of DMA. Set this bit before the DMA configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<LC_CONF_SPEC> {
         AHBM_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to loop test inlink."]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<LC_CONF_SPEC> {
         OUT_LOOP_TEST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to loop test outlink."]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<LC_CONF_SPEC> {
         IN_LOOP_TEST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable outlink-written-back automatically when out buffer is transmitted done."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<LC_CONF_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 6)
     }
     #[doc = "Bit 7 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<LC_CONF_SPEC> {
         OUT_NO_RESTART_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - DMA out EOF flag generation mode. 1: When DMA has popped all data from the FIFO. 0: When AHB has pushed all data to the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<LC_CONF_SPEC> {
         OUT_EOF_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - DMA outlink descriptor transfer mode configuration bit. 1: Prepare outlink descriptor with burst mode. 0: Prepare outlink descriptor with byte mode."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<LC_CONF_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - DMA inlink descriptor transfer mode configuration bit. 1: Prepare inlink descriptor with burst mode. 0: Prepare inlink descriptor with byte mode."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<LC_CONF_SPEC> {
         INDSCR_BURST_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Transmitter data transfer mode configuration bit. 1: Prepare out data with burst mode. 0: Prepare out data with byte mode."]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<LC_CONF_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to enable check owner bit by hardware."]
     #[inline(always)]
-    #[must_use]
     pub fn check_owner(&mut self) -> CHECK_OWNER_W<LC_CONF_SPEC> {
         CHECK_OWNER_W::new(self, 12)
     }
     #[doc = "Bit 13 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<LC_CONF_SPEC> {
         MEM_TRANS_EN_W::new(self, 13)
     }
     #[doc = "Bits 14:15 - DMA access external memory block size. 0: 16 bytes. 1: 32 bytes. 2: 64 bytes. 3: reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_mem_bk_size(&mut self) -> EXT_MEM_BK_SIZE_W<LC_CONF_SPEC> {
         EXT_MEM_BK_SIZE_W::new(self, 14)
     }
diff --git a/esp32s2/src/i2s0/lc_hung_conf.rs b/esp32s2/src/i2s0/lc_hung_conf.rs
index 416bf149d3..9ef88c34cd 100644
--- a/esp32s2/src/i2s0/lc_hung_conf.rs
+++ b/esp32s2/src/i2s0/lc_hung_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value."]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - The bits are used to set the tick counter threshold. The tick counter is clocked by APB_CLK. The tick counter threshold is 88000/2^I2S_LC_FIFO_TIMEOUT_SHIFT. The tick counter is reset when it reaches the threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - The enable bit for FIFO timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
     }
diff --git a/esp32s2/src/i2s0/out_link.rs b/esp32s2/src/i2s0/out_link.rs
index 18976e93ef..4f799a670e 100644
--- a/esp32s2/src/i2s0/out_link.rs
+++ b/esp32s2/src/i2s0/out_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of first outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set this bit to stop outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to restart outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32s2/src/i2s0/outfifo_push.rs b/esp32s2/src/i2s0/outfifo_push.rs
index 0de3e531df..d35e42d488 100644
--- a/esp32s2/src/i2s0/outfifo_push.rs
+++ b/esp32s2/src/i2s0/outfifo_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - APB out FIFO write data."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<OUTFIFO_PUSH_SPEC> {
         OUTFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16 - APB out FIFO push."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<OUTFIFO_PUSH_SPEC> {
         OUTFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32s2/src/i2s0/pd_conf.rs b/esp32s2/src/i2s0/pd_conf.rs
index b1874655b0..8f6ed9d02c 100644
--- a/esp32s2/src/i2s0/pd_conf.rs
+++ b/esp32s2/src/i2s0/pd_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Force FIFO power-down."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_force_pd(&mut self) -> FIFO_FORCE_PD_W<PD_CONF_SPEC> {
         FIFO_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Force FIFO power-up."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_force_pu(&mut self) -> FIFO_FORCE_PU_W<PD_CONF_SPEC> {
         FIFO_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2 - Force I2S memory power-down."]
     #[inline(always)]
-    #[must_use]
     pub fn plc_mem_force_pd(&mut self) -> PLC_MEM_FORCE_PD_W<PD_CONF_SPEC> {
         PLC_MEM_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Force I2S memory power-up."]
     #[inline(always)]
-    #[must_use]
     pub fn plc_mem_force_pu(&mut self) -> PLC_MEM_FORCE_PU_W<PD_CONF_SPEC> {
         PLC_MEM_FORCE_PU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Force DMA FIFO power-down."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_force_pd(&mut self) -> DMA_RAM_FORCE_PD_W<PD_CONF_SPEC> {
         DMA_RAM_FORCE_PD_W::new(self, 4)
     }
     #[doc = "Bit 5 - Force DMA FIFO power-up."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_force_pu(&mut self) -> DMA_RAM_FORCE_PU_W<PD_CONF_SPEC> {
         DMA_RAM_FORCE_PU_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to force on DMA RAM clock."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_clk_fo(&mut self) -> DMA_RAM_CLK_FO_W<PD_CONF_SPEC> {
         DMA_RAM_CLK_FO_W::new(self, 6)
     }
diff --git a/esp32s2/src/i2s0/rxeof_num.rs b/esp32s2/src/i2s0/rxeof_num.rs
index 2793a84e9c..7f84120e49 100644
--- a/esp32s2/src/i2s0/rxeof_num.rs
+++ b/esp32s2/src/i2s0/rxeof_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<RXEOF_NUM_SPEC> {
         RX_EOF_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/i2s0/sample_rate_conf.rs b/esp32s2/src/i2s0/sample_rate_conf.rs
index 785157085e..f7bb71dda0 100644
--- a/esp32s2/src/i2s0/sample_rate_conf.rs
+++ b/esp32s2/src/i2s0/sample_rate_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Bit clock configuration bits in transmitter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<SAMPLE_RATE_CONF_SPEC> {
         TX_BCK_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - Bit clock configuration bits in receiver mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<SAMPLE_RATE_CONF_SPEC> {
         RX_BCK_DIV_NUM_W::new(self, 6)
     }
     #[doc = "Bits 12:17 - Set the bits to configure bit length of I2S transmitter channel, the value of which can only be 8, 16, 24 and 32."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<SAMPLE_RATE_CONF_SPEC> {
         TX_BITS_MOD_W::new(self, 12)
     }
     #[doc = "Bits 18:23 - Set the bits to configure bit length of I2S receiver channel, the value of which can only be 8, 16, 24 and 32."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<SAMPLE_RATE_CONF_SPEC> {
         RX_BITS_MOD_W::new(self, 18)
     }
diff --git a/esp32s2/src/i2s0/timing.rs b/esp32s2/src/i2s0/timing.rs
index cd9cca1901..3132b19783 100644
--- a/esp32s2/src/i2s0/timing.rs
+++ b/esp32s2/src/i2s0/timing.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_delay(&mut self) -> TX_BCK_IN_DELAY_W<TIMING_SPEC> {
         TX_BCK_IN_DELAY_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_in_delay(&mut self) -> TX_WS_IN_DELAY_W<TIMING_SPEC> {
         TX_WS_IN_DELAY_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_in_delay(&mut self) -> RX_BCK_IN_DELAY_W<TIMING_SPEC> {
         RX_BCK_IN_DELAY_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_in_delay(&mut self) -> RX_WS_IN_DELAY_W<TIMING_SPEC> {
         RX_WS_IN_DELAY_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd_in_delay(&mut self) -> RX_SD_IN_DELAY_W<TIMING_SPEC> {
         RX_SD_IN_DELAY_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_out_delay(&mut self) -> TX_BCK_OUT_DELAY_W<TIMING_SPEC> {
         TX_BCK_OUT_DELAY_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_out_delay(&mut self) -> TX_WS_OUT_DELAY_W<TIMING_SPEC> {
         TX_WS_OUT_DELAY_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd_out_delay(&mut self) -> TX_SD_OUT_DELAY_W<TIMING_SPEC> {
         TX_SD_OUT_DELAY_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_out_delay(&mut self) -> RX_WS_OUT_DELAY_W<TIMING_SPEC> {
         RX_WS_OUT_DELAY_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_out_delay(&mut self) -> RX_BCK_OUT_DELAY_W<TIMING_SPEC> {
         RX_BCK_OUT_DELAY_W::new(self, 18)
     }
     #[doc = "Bit 20 - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dsync_sw(&mut self) -> TX_DSYNC_SW_W<TIMING_SPEC> {
         TX_DSYNC_SW_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dsync_sw(&mut self) -> RX_DSYNC_SW_W<TIMING_SPEC> {
         RX_DSYNC_SW_W::new(self, 21)
     }
     #[doc = "Bits 22:23 - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn data_enable_delay(&mut self) -> DATA_ENABLE_DELAY_W<TIMING_SPEC> {
         DATA_ENABLE_DELAY_W::new(self, 22)
     }
     #[doc = "Bit 24 - Set this bit to invert BCK signal input to the slave transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_inv(&mut self) -> TX_BCK_IN_INV_W<TIMING_SPEC> {
         TX_BCK_IN_INV_W::new(self, 24)
     }
diff --git a/esp32s2/src/interrupt_core0/clock_gate.rs b/esp32s2/src/interrupt_core0/clock_gate.rs
index 992d5c79c2..0b9c284cf1 100644
--- a/esp32s2/src/interrupt_core0/clock_gate.rs
+++ b/esp32s2/src/interrupt_core0/clock_gate.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit is used to disable all NMI interrupt signals to CPU."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_nmi_mask_hw(&mut self) -> PRO_NMI_MASK_HW_W<CLOCK_GATE_SPEC> {
         PRO_NMI_MASK_HW_W::new(self, 1)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs b/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
index 1a322c50e3..6754421d13 100644
--- a/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map AES_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_aes_intr_map(&mut self) -> PRO_AES_INTR_MAP_W<PRO_AES_INTR_MAP_SPEC> {
         PRO_AES_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs b/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
index e2b4ff03e7..cf12a71bfb 100644
--- a/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_apb_adc_int_map(&mut self) -> PRO_APB_ADC_INT_MAP_W<PRO_APB_ADC_INT_MAP_SPEC> {
         PRO_APB_ADC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs b/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
index aba70a303b..eefbe07bb0 100644
--- a/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_apb_peri_error_int_map(
         &mut self,
     ) -> PRO_APB_PERI_ERROR_INT_MAP_W<PRO_APB_PERI_ERROR_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs b/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
index 4df5f90dfd..caf917a9f1 100644
--- a/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_assist_debug_intr_map(
         &mut self,
     ) -> PRO_ASSIST_DEBUG_INTR_MAP_W<PRO_ASSIST_DEBUG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_bb_int_map.rs b/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
index 688a0f57c8..c2165242af 100644
--- a/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bb_int_map(&mut self) -> PRO_BB_INT_MAP_W<PRO_BB_INT_MAP_SPEC> {
         PRO_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs b/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
index eff33bb82b..17b4329186 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_bb_int_map(&mut self) -> PRO_BT_BB_INT_MAP_W<PRO_BT_BB_INT_MAP_SPEC> {
         PRO_BT_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
index 63cc2ca175..5409a1cfc8 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_bb_nmi_map(&mut self) -> PRO_BT_BB_NMI_MAP_W<PRO_BT_BB_NMI_MAP_SPEC> {
         PRO_BT_BB_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs b/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
index a4a0a463fe..6c61c733f2 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_bt_mac_int_map(&mut self) -> PRO_BT_MAC_INT_MAP_W<PRO_BT_MAC_INT_MAP_SPEC> {
         PRO_BT_MAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs b/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
index 5b4d8071ea..71be6466da 100644
--- a/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ia_int_map(&mut self) -> PRO_CACHE_IA_INT_MAP_W<PRO_CACHE_IA_INT_MAP_SPEC> {
         PRO_CACHE_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_can_int_map.rs b/esp32s2/src/interrupt_core0/pro_can_int_map.rs
index a858641c6d..0c9e78b396 100644
--- a/esp32s2/src/interrupt_core0/pro_can_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_can_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CAN_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_can_int_map(&mut self) -> PRO_CAN_INT_MAP_W<PRO_CAN_INT_MAP_SPEC> {
         PRO_CAN_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
index 436fc0ae5c..770a969771 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_0_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_0_MAP_W<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
index 3b6c75e5be..f66b8f8b9c 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_1_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_1_MAP_W<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
index 22f21e4f20..ad1d802106 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_2_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_2_MAP_W<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
index 4bf3b14906..bcb67452be 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_intr_from_cpu_3_map(
         &mut self,
     ) -> PRO_CPU_INTR_FROM_CPU_3_MAP_W<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
index e6800d6253..8cd377716f 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cpu_peri_error_int_map(
         &mut self,
     ) -> PRO_CPU_PERI_ERROR_INT_MAP_W<PRO_CPU_PERI_ERROR_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
index a44542387a..103868803e 100644
--- a/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_crypto_dma_int_map(
         &mut self,
     ) -> PRO_CRYPTO_DMA_INT_MAP_W<PRO_CRYPTO_DMA_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs b/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
index 3f5be0592f..10a2cff6cf 100644
--- a/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_preload_int_map(
         &mut self,
     ) -> PRO_DCACHE_PRELOAD_INT_MAP_W<PRO_DCACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs b/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
index fbbf2dd910..0e80df07e5 100644
--- a/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_sync_int_map(
         &mut self,
     ) -> PRO_DCACHE_SYNC_INT_MAP_W<PRO_DCACHE_SYNC_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs b/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
index 3ab3d01c6d..9389df11c3 100644
--- a/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dedicated_gpio_in_intr_map(
         &mut self,
     ) -> PRO_DEDICATED_GPIO_IN_INTR_MAP_W<PRO_DEDICATED_GPIO_IN_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs b/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
index 0a2a5b877b..003dfcec59 100644
--- a/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dma_copy_intr_map(&mut self) -> PRO_DMA_COPY_INTR_MAP_W<PRO_DMA_COPY_INTR_MAP_SPEC> {
         PRO_DMA_COPY_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs b/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
index 9b1d79b2d9..cce464ac99 100644
--- a/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_efuse_int_map(&mut self) -> PRO_EFUSE_INT_MAP_W<PRO_EFUSE_INT_MAP_SPEC> {
         PRO_EFUSE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
index b3ddbfabc9..938c5f584f 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_app_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_APP_MAP_W<PRO_GPIO_INTERRUPT_APP_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
index a834e52fe0..5d28f32df7 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_app_nmi_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_APP_NMI_MAP_W<PRO_GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
index 53a1d0ffdd..1677a86f92 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_pro_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_PRO_MAP_W<PRO_GPIO_INTERRUPT_PRO_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
index 17d453e3b9..845dc7a87d 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_gpio_interrupt_pro_nmi_map(
         &mut self,
     ) -> PRO_GPIO_INTERRUPT_PRO_NMI_MAP_W<PRO_GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
index b286d5fcb5..e318fa150d 100644
--- a/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2c_ext0_intr_map(&mut self) -> PRO_I2C_EXT0_INTR_MAP_W<PRO_I2C_EXT0_INTR_MAP_SPEC> {
         PRO_I2C_EXT0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
index a8fd599a02..bbdaab6bc1 100644
--- a/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2c_ext1_intr_map(&mut self) -> PRO_I2C_EXT1_INTR_MAP_W<PRO_I2C_EXT1_INTR_MAP_SPEC> {
         PRO_I2C_EXT1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs b/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
index df60455784..20c939fcd7 100644
--- a/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2s0_int_map(&mut self) -> PRO_I2S0_INT_MAP_W<PRO_I2S0_INT_MAP_SPEC> {
         PRO_I2S0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs b/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
index 2fbb4701d6..709d380e2d 100644
--- a/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i2s1_int_map(&mut self) -> PRO_I2S1_INT_MAP_W<PRO_I2S1_INT_MAP_SPEC> {
         PRO_I2S1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs b/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
index 32cd2137e8..aee561492c 100644
--- a/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_preload_int_map(
         &mut self,
     ) -> PRO_ICACHE_PRELOAD_INT_MAP_W<PRO_ICACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs b/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
index 2c125f9c30..432937b5a9 100644
--- a/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_sync_int_map(
         &mut self,
     ) -> PRO_ICACHE_SYNC_INT_MAP_W<PRO_ICACHE_SYNC_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs b/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
index c3bea5a0f5..5a3507a809 100644
--- a/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ledc_int_map(&mut self) -> PRO_LEDC_INT_MAP_W<PRO_LEDC_INT_MAP_SPEC> {
         PRO_LEDC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs b/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
index 416321110a..559c6903b0 100644
--- a/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mac_intr_map(&mut self) -> PRO_MAC_INTR_MAP_W<PRO_MAC_INTR_MAP_SPEC> {
         PRO_MAC_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
index f8a5884c1a..8302d280a8 100644
--- a/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mac_nmi_map(&mut self) -> PRO_MAC_NMI_MAP_W<PRO_MAC_NMI_MAP_SPEC> {
         PRO_MAC_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
index 2dbce41ed8..9ba590b9d2 100644
--- a/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pcnt_intr_map(&mut self) -> PRO_PCNT_INTR_MAP_W<PRO_PCNT_INTR_MAP_SPEC> {
         PRO_PCNT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
index 30aaf240a5..278dad2605 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_dma_apb_i_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_DMA_APB_I_ILG_INTR_MAP_W<PRO_PMS_DMA_APB_I_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
index 4bab71437c..308fb25b66 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_dma_rx_i_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_DMA_RX_I_ILG_INTR_MAP_W<PRO_PMS_DMA_RX_I_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
index f0c5bf5269..55d2f3b6a4 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_dma_tx_i_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_DMA_TX_I_ILG_INTR_MAP_W<PRO_PMS_DMA_TX_I_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
index 95f896f5d5..9b5943bd55 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_pro_ahb_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_PRO_AHB_ILG_INTR_MAP_W<PRO_PMS_PRO_AHB_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
index eba2ca500c..df22e6242a 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_pro_cache_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_PRO_CACHE_ILG_INTR_MAP_W<PRO_PMS_PRO_CACHE_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
index 8b841bfe11..86f45395d3 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_pro_dport_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_PRO_DPORT_ILG_INTR_MAP_W<PRO_PMS_PRO_DPORT_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
index 6d21c2dd59..a79a34a8e3 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_pro_dram0_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_W<PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
index 3c96165bcb..ce6b439797 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pms_pro_iram0_ilg_intr_map(
         &mut self,
     ) -> PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_W<PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
index 6ff06d0618..18fcb2e82e 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm0_intr_map(&mut self) -> PRO_PWM0_INTR_MAP_W<PRO_PWM0_INTR_MAP_SPEC> {
         PRO_PWM0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
index 649f976d78..6c606519da 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm1_intr_map(&mut self) -> PRO_PWM1_INTR_MAP_W<PRO_PWM1_INTR_MAP_SPEC> {
         PRO_PWM1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
index 20da441cf0..2f0fe317a5 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm2_intr_map(&mut self) -> PRO_PWM2_INTR_MAP_W<PRO_PWM2_INTR_MAP_SPEC> {
         PRO_PWM2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
index 6ea0a215d6..9ca2bb139f 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwm3_intr_map(&mut self) -> PRO_PWM3_INTR_MAP_W<PRO_PWM3_INTR_MAP_SPEC> {
         PRO_PWM3_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
index a5843b3ff2..0f478bbdbe 100644
--- a/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_pwr_intr_map(&mut self) -> PRO_PWR_INTR_MAP_W<PRO_PWR_INTR_MAP_SPEC> {
         PRO_PWR_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
index bf50de6a62..feaaffe86e 100644
--- a/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rmt_intr_map(&mut self) -> PRO_RMT_INTR_MAP_W<PRO_RMT_INTR_MAP_SPEC> {
         PRO_RMT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
index 3fdb2d4304..c837a5a152 100644
--- a/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rsa_intr_map(&mut self) -> PRO_RSA_INTR_MAP_W<PRO_RSA_INTR_MAP_SPEC> {
         PRO_RSA_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
index 7069e5be4c..8207a68b46 100644
--- a/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rtc_core_intr_map(&mut self) -> PRO_RTC_CORE_INTR_MAP_W<PRO_RTC_CORE_INTR_MAP_SPEC> {
         PRO_RTC_CORE_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs b/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
index c8a6bca393..fdd3ff1759 100644
--- a/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwble_irq_map(&mut self) -> PRO_RWBLE_IRQ_MAP_W<PRO_RWBLE_IRQ_MAP_SPEC> {
         PRO_RWBLE_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
index fc6f8b758f..e98ed38ebb 100644
--- a/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwble_nmi_map(&mut self) -> PRO_RWBLE_NMI_MAP_W<PRO_RWBLE_NMI_MAP_SPEC> {
         PRO_RWBLE_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs b/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
index cced69d8cf..322d8eb349 100644
--- a/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwbt_irq_map(&mut self) -> PRO_RWBT_IRQ_MAP_W<PRO_RWBT_IRQ_MAP_SPEC> {
         PRO_RWBT_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
index b2a30a7c35..9512ed82cf 100644
--- a/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_rwbt_nmi_map(&mut self) -> PRO_RWBT_NMI_MAP_W<PRO_RWBT_NMI_MAP_SPEC> {
         PRO_RWBT_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs b/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
index 3a670a05d3..106caddaad 100644
--- a/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_sdio_host_interrupt_map(
         &mut self,
     ) -> PRO_SDIO_HOST_INTERRUPT_MAP_W<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs b/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
index d40c4219a2..f484fcb497 100644
--- a/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_sha_intr_map(&mut self) -> PRO_SHA_INTR_MAP_W<PRO_SHA_INTR_MAP_SPEC> {
         PRO_SHA_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
index 7946822304..41e4242982 100644
--- a/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_slc0_intr_map(&mut self) -> PRO_SLC0_INTR_MAP_W<PRO_SLC0_INTR_MAP_SPEC> {
         PRO_SLC0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
index 4acb096dcd..76d9c3763e 100644
--- a/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_slc1_intr_map(&mut self) -> PRO_SLC1_INTR_MAP_W<PRO_SLC1_INTR_MAP_SPEC> {
         PRO_SLC1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
index ce85b44800..1aed589b7e 100644
--- a/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map AES_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi2_dma_int_map(&mut self) -> PRO_SPI2_DMA_INT_MAP_W<PRO_SPI2_DMA_INT_MAP_SPEC> {
         PRO_SPI2_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
index aec1fb9fcb..bd501a5cab 100644
--- a/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi3_dma_int_map(&mut self) -> PRO_SPI3_DMA_INT_MAP_W<PRO_SPI3_DMA_INT_MAP_SPEC> {
         PRO_SPI3_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
index 2045fbce5f..924c3b4c6e 100644
--- a/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi4_dma_int_map(&mut self) -> PRO_SPI4_DMA_INT_MAP_W<PRO_SPI4_DMA_INT_MAP_SPEC> {
         PRO_SPI4_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
index e51f8ac457..7e3776ef52 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_1_map(&mut self) -> PRO_SPI_INTR_1_MAP_W<PRO_SPI_INTR_1_MAP_SPEC> {
         PRO_SPI_INTR_1_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
index c48dadb696..de7fab7e8c 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_2_map(&mut self) -> PRO_SPI_INTR_2_MAP_W<PRO_SPI_INTR_2_MAP_SPEC> {
         PRO_SPI_INTR_2_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
index 4ac4248875..bce367c460 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_3_map(&mut self) -> PRO_SPI_INTR_3_MAP_W<PRO_SPI_INTR_3_MAP_SPEC> {
         PRO_SPI_INTR_3_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
index 488dee3041..83c637e753 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_intr_4_map(&mut self) -> PRO_SPI_INTR_4_MAP_W<PRO_SPI_INTR_4_MAP_SPEC> {
         PRO_SPI_INTR_4_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs b/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
index 725d23426f..0694572e47 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_spi_mem_reject_intr_map(
         &mut self,
     ) -> PRO_SPI_MEM_REJECT_INTR_MAP_W<PRO_SPI_MEM_REJECT_INTR_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
index 3fff98603d..b0479daa6a 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_systimer_target0_int_map(
         &mut self,
     ) -> PRO_SYSTIMER_TARGET0_INT_MAP_W<PRO_SYSTIMER_TARGET0_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
index c0aa7f361a..c90d7f4f15 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_systimer_target1_int_map(
         &mut self,
     ) -> PRO_SYSTIMER_TARGET1_INT_MAP_W<PRO_SYSTIMER_TARGET1_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
index 38408c1214..f281fb0ac5 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_systimer_target2_int_map(
         &mut self,
     ) -> PRO_SYSTIMER_TARGET2_INT_MAP_W<PRO_SYSTIMER_TARGET2_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
index ba0061a440..3014bf447e 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_lact_edge_int_map(
         &mut self,
     ) -> PRO_TG1_LACT_EDGE_INT_MAP_W<PRO_TG1_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
index 1f5634283e..2c42bfe6d7 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_lact_level_int_map(
         &mut self,
     ) -> PRO_TG1_LACT_LEVEL_INT_MAP_W<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
index a8e4e9cefc..da825ba7af 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t0_edge_int_map(
         &mut self,
     ) -> PRO_TG1_T0_EDGE_INT_MAP_W<PRO_TG1_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
index 73223d204b..aff8f3fa2a 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t0_level_int_map(
         &mut self,
     ) -> PRO_TG1_T0_LEVEL_INT_MAP_W<PRO_TG1_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
index 1809ecca45..317e7e69a0 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t1_edge_int_map(
         &mut self,
     ) -> PRO_TG1_T1_EDGE_INT_MAP_W<PRO_TG1_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
index 68d56e28f4..28a11cfdb4 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_t1_level_int_map(
         &mut self,
     ) -> PRO_TG1_T1_LEVEL_INT_MAP_W<PRO_TG1_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
index bcd40d063c..2b326dedd6 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_wdt_edge_int_map(
         &mut self,
     ) -> PRO_TG1_WDT_EDGE_INT_MAP_W<PRO_TG1_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
index 9a6ae28722..46c6822205 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg1_wdt_level_int_map(
         &mut self,
     ) -> PRO_TG1_WDT_LEVEL_INT_MAP_W<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
index d02fbd0610..c8e671b4d7 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_lact_edge_int_map(
         &mut self,
     ) -> PRO_TG_LACT_EDGE_INT_MAP_W<PRO_TG_LACT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
index d4d8204687..6ab18ebb07 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_lact_level_int_map(
         &mut self,
     ) -> PRO_TG_LACT_LEVEL_INT_MAP_W<PRO_TG_LACT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
index 93cc660b88..732e25f8a0 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t0_edge_int_map(
         &mut self,
     ) -> PRO_TG_T0_EDGE_INT_MAP_W<PRO_TG_T0_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
index 7cb162891f..b83b16b1cf 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t0_level_int_map(
         &mut self,
     ) -> PRO_TG_T0_LEVEL_INT_MAP_W<PRO_TG_T0_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
index 389c4dba94..c09e33f547 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t1_edge_int_map(
         &mut self,
     ) -> PRO_TG_T1_EDGE_INT_MAP_W<PRO_TG_T1_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
index 646fdf3ee1..cc454efad1 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_t1_level_int_map(
         &mut self,
     ) -> PRO_TG_T1_LEVEL_INT_MAP_W<PRO_TG_T1_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
index 6048e374b8..c1251017da 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_wdt_edge_int_map(
         &mut self,
     ) -> PRO_TG_WDT_EDGE_INT_MAP_W<PRO_TG_WDT_EDGE_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
index 4c3e1bd47a..b97c47d865 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_tg_wdt_level_int_map(
         &mut self,
     ) -> PRO_TG_WDT_LEVEL_INT_MAP_W<PRO_TG_WDT_LEVEL_INT_MAP_SPEC> {
diff --git a/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs b/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
index 02d7082512..76dc76fec0 100644
--- a/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_timer_int1_map(&mut self) -> PRO_TIMER_INT1_MAP_W<PRO_TIMER_INT1_MAP_SPEC> {
         PRO_TIMER_INT1_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs b/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
index 157a6f8734..125a2e44c6 100644
--- a/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_timer_int2_map(&mut self) -> PRO_TIMER_INT2_MAP_W<PRO_TIMER_INT2_MAP_SPEC> {
         PRO_TIMER_INT2_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
index 56ee6f8a9b..197f34e50a 100644
--- a/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart1_intr_map(&mut self) -> PRO_UART1_INTR_MAP_W<PRO_UART1_INTR_MAP_SPEC> {
         PRO_UART1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
index d75686b874..caa07b1c42 100644
--- a/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART2_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart2_intr_map(&mut self) -> PRO_UART2_INTR_MAP_W<PRO_UART2_INTR_MAP_SPEC> {
         PRO_UART2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
index a6ec9a9095..a240669dd3 100644
--- a/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uart_intr_map(&mut self) -> PRO_UART_INTR_MAP_W<PRO_UART_INTR_MAP_SPEC> {
         PRO_UART_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
index 874f20920d..7a6fb0dd9e 100644
--- a/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uhci0_intr_map(&mut self) -> PRO_UHCI0_INTR_MAP_W<PRO_UHCI0_INTR_MAP_SPEC> {
         PRO_UHCI0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
index 975d85b64b..652251caaf 100644
--- a/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_uhci1_intr_map(&mut self) -> PRO_UHCI1_INTR_MAP_W<PRO_UHCI1_INTR_MAP_SPEC> {
         PRO_UHCI1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs b/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
index f22dfe4ca5..319f75968f 100644
--- a/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map USB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_usb_intr_map(&mut self) -> PRO_USB_INTR_MAP_W<PRO_USB_INTR_MAP_SPEC> {
         PRO_USB_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs b/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
index bf8d02db91..5f20940a28 100644
--- a/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to map WDG_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_wdg_int_map(&mut self) -> PRO_WDG_INT_MAP_W<PRO_WDG_INT_MAP_SPEC> {
         PRO_WDG_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/interrupt_core0/reg_date.rs b/esp32s2/src/interrupt_core0/reg_date.rs
index 829e2ecfeb..366046bb46 100644
--- a/esp32s2/src/interrupt_core0/reg_date.rs
+++ b/esp32s2/src/interrupt_core0/reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - This is the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_reg_date(&mut self) -> INTERRUPT_REG_DATE_W<REG_DATE_SPEC> {
         INTERRUPT_REG_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/io_mux/date.rs b/esp32s2/src/io_mux/date.rs
index dcec28d94c..4525d40a9f 100644
--- a/esp32s2/src/io_mux/date.rs
+++ b/esp32s2/src/io_mux/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn version(&mut self) -> VERSION_W<DATE_SPEC> {
         VERSION_W::new(self, 0)
     }
diff --git a/esp32s2/src/io_mux/gpio0.rs b/esp32s2/src/io_mux/gpio0.rs
index 3d336d4083..c8281e3bd8 100644
--- a/esp32s2/src/io_mux/gpio0.rs
+++ b/esp32s2/src/io_mux/gpio0.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO0_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO0_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO0_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO0_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO0_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO0_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO0_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO0_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO0_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO0_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO0_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio1.rs b/esp32s2/src/io_mux/gpio1.rs
index 622fe5d172..ddb465b684 100644
--- a/esp32s2/src/io_mux/gpio1.rs
+++ b/esp32s2/src/io_mux/gpio1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO1_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO1_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO1_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO1_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO1_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO1_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO1_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO1_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO1_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO1_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO1_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio10.rs b/esp32s2/src/io_mux/gpio10.rs
index 4cedd5a55e..d400be076f 100644
--- a/esp32s2/src/io_mux/gpio10.rs
+++ b/esp32s2/src/io_mux/gpio10.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO10_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO10_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO10_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO10_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO10_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO10_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO10_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO10_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO10_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO10_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO10_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio11.rs b/esp32s2/src/io_mux/gpio11.rs
index 9378365b5e..fad72f5934 100644
--- a/esp32s2/src/io_mux/gpio11.rs
+++ b/esp32s2/src/io_mux/gpio11.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO11_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO11_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO11_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO11_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO11_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO11_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO11_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO11_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO11_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO11_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO11_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio12.rs b/esp32s2/src/io_mux/gpio12.rs
index 68d2362299..c15eb1b142 100644
--- a/esp32s2/src/io_mux/gpio12.rs
+++ b/esp32s2/src/io_mux/gpio12.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO12_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO12_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO12_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO12_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO12_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO12_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO12_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO12_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO12_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO12_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO12_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio13.rs b/esp32s2/src/io_mux/gpio13.rs
index 3d5c19d32e..0f36ce79c0 100644
--- a/esp32s2/src/io_mux/gpio13.rs
+++ b/esp32s2/src/io_mux/gpio13.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO13_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO13_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO13_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO13_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO13_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO13_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO13_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO13_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO13_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO13_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO13_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio14.rs b/esp32s2/src/io_mux/gpio14.rs
index 26be89d24d..9ab1f6b2ea 100644
--- a/esp32s2/src/io_mux/gpio14.rs
+++ b/esp32s2/src/io_mux/gpio14.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO14_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO14_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO14_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO14_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO14_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO14_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO14_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO14_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO14_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO14_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO14_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio15.rs b/esp32s2/src/io_mux/gpio15.rs
index f03086aed1..b8cd99954b 100644
--- a/esp32s2/src/io_mux/gpio15.rs
+++ b/esp32s2/src/io_mux/gpio15.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO15_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO15_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO15_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO15_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO15_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO15_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO15_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO15_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO15_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO15_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO15_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio16.rs b/esp32s2/src/io_mux/gpio16.rs
index 4b55bdee65..16ce56b5f1 100644
--- a/esp32s2/src/io_mux/gpio16.rs
+++ b/esp32s2/src/io_mux/gpio16.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO16_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO16_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO16_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO16_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO16_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO16_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO16_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO16_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO16_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO16_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO16_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio17.rs b/esp32s2/src/io_mux/gpio17.rs
index dbc434775b..e860eecbae 100644
--- a/esp32s2/src/io_mux/gpio17.rs
+++ b/esp32s2/src/io_mux/gpio17.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO17_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO17_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO17_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO17_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO17_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO17_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO17_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO17_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO17_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO17_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO17_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio18.rs b/esp32s2/src/io_mux/gpio18.rs
index b84c055883..296f6a77c2 100644
--- a/esp32s2/src/io_mux/gpio18.rs
+++ b/esp32s2/src/io_mux/gpio18.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO18_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO18_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO18_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO18_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO18_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO18_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO18_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO18_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO18_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO18_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO18_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio19.rs b/esp32s2/src/io_mux/gpio19.rs
index 7ea292fa5b..526f9484a4 100644
--- a/esp32s2/src/io_mux/gpio19.rs
+++ b/esp32s2/src/io_mux/gpio19.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO19_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO19_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO19_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO19_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO19_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO19_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO19_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO19_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO19_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO19_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO19_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio2.rs b/esp32s2/src/io_mux/gpio2.rs
index fb5e4904ca..4634abc160 100644
--- a/esp32s2/src/io_mux/gpio2.rs
+++ b/esp32s2/src/io_mux/gpio2.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO2_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO2_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO2_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO2_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO2_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO2_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO2_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO2_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO2_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO2_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO2_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio20.rs b/esp32s2/src/io_mux/gpio20.rs
index 8c87ae5fc3..0e24d7e29d 100644
--- a/esp32s2/src/io_mux/gpio20.rs
+++ b/esp32s2/src/io_mux/gpio20.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO20_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO20_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO20_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO20_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO20_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO20_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO20_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO20_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO20_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO20_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO20_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio21.rs b/esp32s2/src/io_mux/gpio21.rs
index 7a8ad67303..de3c2dee30 100644
--- a/esp32s2/src/io_mux/gpio21.rs
+++ b/esp32s2/src/io_mux/gpio21.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO21_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO21_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO21_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO21_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO21_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO21_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO21_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO21_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO21_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO21_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO21_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio26.rs b/esp32s2/src/io_mux/gpio26.rs
index 236b56f95b..d3e5a1afaf 100644
--- a/esp32s2/src/io_mux/gpio26.rs
+++ b/esp32s2/src/io_mux/gpio26.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO26_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO26_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO26_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO26_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO26_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO26_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO26_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO26_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO26_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO26_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO26_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio27.rs b/esp32s2/src/io_mux/gpio27.rs
index 4cebc36cbf..3dce19433a 100644
--- a/esp32s2/src/io_mux/gpio27.rs
+++ b/esp32s2/src/io_mux/gpio27.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO27_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO27_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO27_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO27_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO27_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO27_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO27_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO27_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO27_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO27_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO27_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio28.rs b/esp32s2/src/io_mux/gpio28.rs
index 1769a999e6..f5af3479e8 100644
--- a/esp32s2/src/io_mux/gpio28.rs
+++ b/esp32s2/src/io_mux/gpio28.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO28_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO28_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO28_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO28_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO28_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO28_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO28_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO28_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO28_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO28_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO28_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio29.rs b/esp32s2/src/io_mux/gpio29.rs
index 77469cebfe..d8a6a215a4 100644
--- a/esp32s2/src/io_mux/gpio29.rs
+++ b/esp32s2/src/io_mux/gpio29.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO29_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO29_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO29_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO29_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO29_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO29_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO29_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO29_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO29_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO29_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO29_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio3.rs b/esp32s2/src/io_mux/gpio3.rs
index 1547a48617..6c19e29a24 100644
--- a/esp32s2/src/io_mux/gpio3.rs
+++ b/esp32s2/src/io_mux/gpio3.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO3_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO3_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO3_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO3_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO3_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO3_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO3_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO3_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO3_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO3_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO3_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio30.rs b/esp32s2/src/io_mux/gpio30.rs
index bab19b0e2a..8bd1fd50fb 100644
--- a/esp32s2/src/io_mux/gpio30.rs
+++ b/esp32s2/src/io_mux/gpio30.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO30_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO30_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO30_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO30_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO30_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO30_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO30_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO30_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO30_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO30_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO30_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio31.rs b/esp32s2/src/io_mux/gpio31.rs
index 4067dfe244..c97416f189 100644
--- a/esp32s2/src/io_mux/gpio31.rs
+++ b/esp32s2/src/io_mux/gpio31.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO31_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO31_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO31_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO31_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO31_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO31_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO31_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO31_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO31_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO31_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO31_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio32.rs b/esp32s2/src/io_mux/gpio32.rs
index fd24f78067..8d9970ec37 100644
--- a/esp32s2/src/io_mux/gpio32.rs
+++ b/esp32s2/src/io_mux/gpio32.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO32_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO32_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO32_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO32_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO32_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO32_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO32_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO32_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO32_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO32_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO32_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio33.rs b/esp32s2/src/io_mux/gpio33.rs
index 6a49956b1a..b88d71ba13 100644
--- a/esp32s2/src/io_mux/gpio33.rs
+++ b/esp32s2/src/io_mux/gpio33.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO33_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO33_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO33_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO33_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO33_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO33_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO33_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO33_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO33_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO33_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO33_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio34.rs b/esp32s2/src/io_mux/gpio34.rs
index 29174b37f9..df8977b2e5 100644
--- a/esp32s2/src/io_mux/gpio34.rs
+++ b/esp32s2/src/io_mux/gpio34.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO34_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO34_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO34_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO34_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO34_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO34_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO34_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO34_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO34_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO34_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO34_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio35.rs b/esp32s2/src/io_mux/gpio35.rs
index ca22ead649..8c01210f02 100644
--- a/esp32s2/src/io_mux/gpio35.rs
+++ b/esp32s2/src/io_mux/gpio35.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO35_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO35_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO35_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO35_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO35_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO35_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO35_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO35_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO35_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO35_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO35_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio36.rs b/esp32s2/src/io_mux/gpio36.rs
index c29ef0ebc4..cd7aac0ce0 100644
--- a/esp32s2/src/io_mux/gpio36.rs
+++ b/esp32s2/src/io_mux/gpio36.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO36_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO36_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO36_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO36_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO36_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO36_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO36_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO36_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO36_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO36_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO36_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio37.rs b/esp32s2/src/io_mux/gpio37.rs
index aa681997fa..7b3a365c2a 100644
--- a/esp32s2/src/io_mux/gpio37.rs
+++ b/esp32s2/src/io_mux/gpio37.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO37_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO37_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO37_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO37_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO37_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO37_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO37_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO37_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO37_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO37_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO37_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio38.rs b/esp32s2/src/io_mux/gpio38.rs
index 20a027b78e..0f65cfe349 100644
--- a/esp32s2/src/io_mux/gpio38.rs
+++ b/esp32s2/src/io_mux/gpio38.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO38_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO38_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO38_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO38_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO38_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO38_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO38_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO38_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO38_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO38_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO38_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio39.rs b/esp32s2/src/io_mux/gpio39.rs
index cf67d18da5..7629813784 100644
--- a/esp32s2/src/io_mux/gpio39.rs
+++ b/esp32s2/src/io_mux/gpio39.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO39_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO39_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO39_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO39_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO39_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO39_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO39_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO39_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO39_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO39_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO39_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio4.rs b/esp32s2/src/io_mux/gpio4.rs
index 532b176384..55c4f5c32c 100644
--- a/esp32s2/src/io_mux/gpio4.rs
+++ b/esp32s2/src/io_mux/gpio4.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO4_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO4_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO4_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO4_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO4_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO4_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO4_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO4_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO4_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO4_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO4_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio40.rs b/esp32s2/src/io_mux/gpio40.rs
index 2603535f2b..1430c6cf4b 100644
--- a/esp32s2/src/io_mux/gpio40.rs
+++ b/esp32s2/src/io_mux/gpio40.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO40_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO40_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO40_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO40_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO40_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO40_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO40_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO40_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO40_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO40_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO40_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio41.rs b/esp32s2/src/io_mux/gpio41.rs
index d3a37acfb4..850897a592 100644
--- a/esp32s2/src/io_mux/gpio41.rs
+++ b/esp32s2/src/io_mux/gpio41.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO41_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO41_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO41_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO41_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO41_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO41_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO41_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO41_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO41_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO41_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO41_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio42.rs b/esp32s2/src/io_mux/gpio42.rs
index cf68713c87..920434652d 100644
--- a/esp32s2/src/io_mux/gpio42.rs
+++ b/esp32s2/src/io_mux/gpio42.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO42_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO42_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO42_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO42_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO42_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO42_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO42_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO42_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO42_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO42_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO42_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio43.rs b/esp32s2/src/io_mux/gpio43.rs
index a81c402efe..7711872540 100644
--- a/esp32s2/src/io_mux/gpio43.rs
+++ b/esp32s2/src/io_mux/gpio43.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO43_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO43_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO43_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO43_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO43_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO43_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO43_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO43_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO43_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO43_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO43_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio44.rs b/esp32s2/src/io_mux/gpio44.rs
index ae957b3a1d..5be17a3238 100644
--- a/esp32s2/src/io_mux/gpio44.rs
+++ b/esp32s2/src/io_mux/gpio44.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO44_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO44_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO44_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO44_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO44_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO44_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO44_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO44_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO44_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO44_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO44_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio45.rs b/esp32s2/src/io_mux/gpio45.rs
index 29ae3443c4..4567b7e213 100644
--- a/esp32s2/src/io_mux/gpio45.rs
+++ b/esp32s2/src/io_mux/gpio45.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO45_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO45_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO45_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO45_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO45_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO45_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO45_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO45_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO45_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO45_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO45_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio46.rs b/esp32s2/src/io_mux/gpio46.rs
index 1f0ab8f2d5..1bc2da804f 100644
--- a/esp32s2/src/io_mux/gpio46.rs
+++ b/esp32s2/src/io_mux/gpio46.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO46_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO46_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO46_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO46_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO46_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO46_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO46_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO46_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO46_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO46_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO46_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio5.rs b/esp32s2/src/io_mux/gpio5.rs
index d07ede1008..a228404f84 100644
--- a/esp32s2/src/io_mux/gpio5.rs
+++ b/esp32s2/src/io_mux/gpio5.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO5_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO5_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO5_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO5_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO5_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO5_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO5_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO5_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO5_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO5_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO5_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio6.rs b/esp32s2/src/io_mux/gpio6.rs
index 3e6d4d922b..aeed2af792 100644
--- a/esp32s2/src/io_mux/gpio6.rs
+++ b/esp32s2/src/io_mux/gpio6.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO6_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO6_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO6_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO6_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO6_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO6_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO6_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO6_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO6_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO6_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO6_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio7.rs b/esp32s2/src/io_mux/gpio7.rs
index 159bee4d28..5999e6fb2d 100644
--- a/esp32s2/src/io_mux/gpio7.rs
+++ b/esp32s2/src/io_mux/gpio7.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO7_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO7_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO7_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO7_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO7_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO7_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO7_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO7_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO7_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO7_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO7_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio8.rs b/esp32s2/src/io_mux/gpio8.rs
index efe54abb9d..0b0a367429 100644
--- a/esp32s2/src/io_mux/gpio8.rs
+++ b/esp32s2/src/io_mux/gpio8.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO8_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO8_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO8_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO8_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO8_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO8_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO8_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO8_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO8_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO8_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO8_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/gpio9.rs b/esp32s2/src/io_mux/gpio9.rs
index 55c73fe77d..4835249591 100644
--- a/esp32s2/src/io_mux/gpio9.rs
+++ b/esp32s2/src/io_mux/gpio9.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO9_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO9_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO9_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO9_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO9_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO9_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO9_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pin. 1: Input enabled. 0: Input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO9_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO9_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO9_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO9_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s2/src/io_mux/pin_ctrl.rs b/esp32s2/src/io_mux/pin_ctrl.rs
index f5bf2ee1ce..b22d3ddea0 100644
--- a/esp32s2/src/io_mux/pin_ctrl.rs
+++ b/esp32s2/src/io_mux/pin_ctrl.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pin_clk_out1(&mut self) -> PIN_CLK_OUT1_W<PIN_CTRL_SPEC> {
         PIN_CLK_OUT1_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pin_clk_out2(&mut self) -> PIN_CLK_OUT2_W<PIN_CTRL_SPEC> {
         PIN_CLK_OUT2_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pin_clk_out3(&mut self) -> PIN_CLK_OUT3_W<PIN_CTRL_SPEC> {
         PIN_CLK_OUT3_W::new(self, 8)
     }
     #[doc = "Bits 12:14 - IO pin power switch delay, delay unit is one APB clock."]
     #[inline(always)]
-    #[must_use]
     pub fn switch_prt_num(&mut self) -> SWITCH_PRT_NUM_W<PIN_CTRL_SPEC> {
         SWITCH_PRT_NUM_W::new(self, 12)
     }
     #[doc = "Bit 15 - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V."]
     #[inline(always)]
-    #[must_use]
     pub fn pad_power_ctrl(&mut self) -> PAD_POWER_CTRL_W<PIN_CTRL_SPEC> {
         PAD_POWER_CTRL_W::new(self, 15)
     }
diff --git a/esp32s2/src/ledc/ch/conf0.rs b/esp32s2/src/ledc/ch/conf0.rs
index 36bb913649..0453d622e4 100644
--- a/esp32s2/src/ledc/ch/conf0.rs
+++ b/esp32s2/src/ledc/ch/conf0.rs
@@ -76,43 +76,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer 0. 1: select timer 1. 2: select timer 2. 3: select timer 3."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CONF0_SPEC> {
         TIMER_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - Set this bit to enable signal output on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<CONF0_SPEC> {
         SIG_OUT_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_lv(&mut self) -> IDLE_LV_W<CONF0_SPEC> {
         IDLE_LV_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF0_SPEC> {
         PARA_UP_W::new(self, 4)
     }
     #[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_num(&mut self) -> OVF_NUM_W<CONF0_SPEC> {
         OVF_NUM_W::new(self, 5)
     }
     #[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_en(&mut self) -> OVF_CNT_EN_W<CONF0_SPEC> {
         OVF_CNT_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to reset the ovf_cnt of channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_reset(&mut self) -> OVF_CNT_RESET_W<CONF0_SPEC> {
         OVF_CNT_RESET_W::new(self, 16)
     }
diff --git a/esp32s2/src/ledc/ch/conf1.rs b/esp32s2/src/ledc/ch/conf1.rs
index 4701ebe554..3f41b7aef7 100644
--- a/esp32s2/src/ledc/ch/conf1.rs
+++ b/esp32s2/src/ledc/ch/conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_scale(&mut self) -> DUTY_SCALE_W<CONF1_SPEC> {
         DUTY_SCALE_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_cycle(&mut self) -> DUTY_CYCLE_W<CONF1_SPEC> {
         DUTY_CYCLE_W::new(self, 10)
     }
     #[doc = "Bits 20:29 - This register is used to control the number of times the duty cycle will be changed."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_num(&mut self) -> DUTY_NUM_W<CONF1_SPEC> {
         DUTY_NUM_W::new(self, 20)
     }
     #[doc = "Bit 30 - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_inc(&mut self) -> DUTY_INC_W<CONF1_SPEC> {
         DUTY_INC_W::new(self, 30)
     }
     #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_start(&mut self) -> DUTY_START_W<CONF1_SPEC> {
         DUTY_START_W::new(self, 31)
     }
diff --git a/esp32s2/src/ledc/ch/duty.rs b/esp32s2/src/ledc/ch/duty.rs
index 37070b8030..5f06a74543 100644
--- a/esp32s2/src/ledc/ch/duty.rs
+++ b/esp32s2/src/ledc/ch/duty.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<DUTY_SPEC> {
         DUTY_W::new(self, 0)
     }
diff --git a/esp32s2/src/ledc/ch/hpoint.rs b/esp32s2/src/ledc/ch/hpoint.rs
index 6e7c457c81..e5ae51d75e 100644
--- a/esp32s2/src/ledc/ch/hpoint.rs
+++ b/esp32s2/src/ledc/ch/hpoint.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
-    #[must_use]
     pub fn hpoint(&mut self) -> HPOINT_W<HPOINT_SPEC> {
         HPOINT_W::new(self, 0)
     }
diff --git a/esp32s2/src/ledc/conf.rs b/esp32s2/src/ledc/conf.rs
index a22070e914..703566f1a1 100644
--- a/esp32s2/src/ledc/conf.rs
+++ b/esp32s2/src/ledc/conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<CONF_SPEC> {
         APB_CLK_SEL_W::new(self, 0)
     }
     #[doc = "Bit 31 - This bit is used to control clock. 1: Force clock on for register. 0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/ledc/date.rs b/esp32s2/src/ledc/date.rs
index 6aba4bb76d..7352049785 100644
--- a/esp32s2/src/ledc/date.rs
+++ b/esp32s2/src/ledc/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/ledc/int_clr.rs b/esp32s2/src/ledc/int_clr.rs
index 12605167b4..4f57e66a51 100644
--- a/esp32s2/src/ledc/int_clr.rs
+++ b/esp32s2/src/ledc/int_clr.rs
@@ -17,7 +17,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -25,25 +24,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the TIMER0_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the TIMER1_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the TIMER2_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the TIMER3_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -51,7 +46,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -59,49 +53,41 @@ impl W {
     }
     #[doc = "Bit 4 - Set this bit to clear the DUTY_CHNG_END_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the DUTY_CHNG_END_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the DUTY_CHNG_END_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the DUTY_CHNG_END_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the DUTY_CHNG_END_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the DUTY_CHNG_END_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the DUTY_CHNG_END_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the DUTY_CHNG_END_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -109,7 +95,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -117,49 +102,41 @@ impl W {
     }
     #[doc = "Bit 12 - Set this bit to clear the OVF_CNT_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the OVF_CNT_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the OVF_CNT_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the OVF_CNT_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear the OVF_CNT_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the OVF_CNT_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the OVF_CNT_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear the OVF_CNT_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
@@ -173,7 +150,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1011;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s2/src/ledc/int_ena.rs b/esp32s2/src/ledc/int_ena.rs
index bf0c9a05b1..660ac7dc23 100644
--- a/esp32s2/src/ledc/int_ena.rs
+++ b/esp32s2/src/ledc/int_ena.rs
@@ -193,7 +193,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -201,25 +200,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -227,7 +222,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -235,49 +229,41 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for the DUTY_CHNG_END_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for the DUTY_CHNG_END_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -285,7 +271,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -293,49 +278,41 @@ impl W {
     }
     #[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt enable bit for the OVF_CNT_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt enable bit for the OVF_CNT_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
diff --git a/esp32s2/src/ledc/int_raw.rs b/esp32s2/src/ledc/int_raw.rs
index 265bd1febb..da91e6e8eb 100644
--- a/esp32s2/src/ledc/int_raw.rs
+++ b/esp32s2/src/ledc/int_raw.rs
@@ -193,7 +193,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -201,25 +200,21 @@ impl W {
     }
     #[doc = "Bit 0 - Triggered when the timer0 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - Triggered when the timer1 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Triggered when the timer2 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Triggered when the timer3 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -227,7 +222,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -235,49 +229,41 @@ impl W {
     }
     #[doc = "Bit 4 - Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -285,7 +271,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -293,49 +278,41 @@ impl W {
     }
     #[doc = "Bit 12 - Interrupt raw bit for channel 0. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - Interrupt raw bit for channel 1. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - Interrupt raw bit for channel 2. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - Interrupt raw bit for channel 3. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - Interrupt raw bit for channel 4. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Interrupt raw bit for channel 5. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Interrupt raw bit for channel 6. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Interrupt raw bit for channel 7. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
diff --git a/esp32s2/src/ledc/timer/conf.rs b/esp32s2/src/ledc/timer/conf.rs
index 7936d69219..a3d5b84248 100644
--- a/esp32s2/src/ledc/timer/conf.rs
+++ b/esp32s2/src/ledc/timer/conf.rs
@@ -66,37 +66,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
         DUTY_RES_W::new(self, 0)
     }
     #[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_div(&mut self) -> CLK_DIV_W<CONF_SPEC> {
         CLK_DIV_W::new(self, 4)
     }
     #[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
     #[inline(always)]
-    #[must_use]
     pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
         PAUSE_W::new(self, 22)
     }
     #[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
         RST_W::new(self, 23)
     }
     #[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK."]
     #[inline(always)]
-    #[must_use]
     pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
         TICK_SEL_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
         PARA_UP_W::new(self, 25)
     }
diff --git a/esp32s2/src/lib.rs b/esp32s2/src/lib.rs
index 363411d7ca..e100a96513 100644
--- a/esp32s2/src/lib.rs
+++ b/esp32s2/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.33.4 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.33.5 (bfe48e2 2024-11-05))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.5/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
@@ -478,13 +478,8 @@ pub enum Interrupt {
     #[doc = "94 - ICACHE_SYNC"]
     ICACHE_SYNC = 94,
 }
-unsafe impl xtensa_lx::interrupt::InterruptNumber for Interrupt {
-    #[inline(always)]
-    fn number(self) -> u16 {
-        self as u16
-    }
-}
 #[doc = r" TryFromInterruptError"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Debug, Copy, Clone)]
 pub struct TryFromInterruptError(());
 impl Interrupt {
diff --git a/esp32s2/src/pcnt/ctrl.rs b/esp32s2/src/pcnt/ctrl.rs
index 35fba35a95..93fc46ebb7 100644
--- a/esp32s2/src/pcnt/ctrl.rs
+++ b/esp32s2/src/pcnt/ctrl.rs
@@ -112,7 +112,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_RST_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u(&mut self, n: u8) -> CNT_RST_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -120,25 +119,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u0(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 0)
     }
     #[doc = "Bit 2 - Set this bit to clear unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u1(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 2)
     }
     #[doc = "Bit 4 - Set this bit to clear unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u2(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 4)
     }
     #[doc = "Bit 6 - Set this bit to clear unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u3(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 6)
     }
@@ -146,7 +141,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_PAUSE_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u(&mut self, n: u8) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -154,31 +148,26 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to pause unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 1)
     }
     #[doc = "Bit 3 - Set this bit to pause unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to pause unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 5)
     }
     #[doc = "Bit 7 - Set this bit to pause unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 7)
     }
     #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
         CLK_EN_W::new(self, 16)
     }
diff --git a/esp32s2/src/pcnt/date.rs b/esp32s2/src/pcnt/date.rs
index 62c52e7519..e946eed689 100644
--- a/esp32s2/src/pcnt/date.rs
+++ b/esp32s2/src/pcnt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the PCNT version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/pcnt/int_clr.rs b/esp32s2/src/pcnt/int_clr.rs
index 60d2b9e5fc..8122a1e7bd 100644
--- a/esp32s2/src/pcnt/int_clr.rs
+++ b/esp32s2/src/pcnt/int_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -21,25 +20,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
diff --git a/esp32s2/src/pcnt/int_ena.rs b/esp32s2/src/pcnt/int_ena.rs
index 97405ab4c3..c96e98eacf 100644
--- a/esp32s2/src/pcnt/int_ena.rs
+++ b/esp32s2/src/pcnt/int_ena.rs
@@ -59,7 +59,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -67,25 +66,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
diff --git a/esp32s2/src/pcnt/unit/conf0.rs b/esp32s2/src/pcnt/unit/conf0.rs
index 5e715c9173..11efe74c98 100644
--- a/esp32s2/src/pcnt/unit/conf0.rs
+++ b/esp32s2/src/pcnt/unit/conf0.rs
@@ -346,43 +346,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_thres(&mut self) -> FILTER_THRES_W<CONF0_SPEC> {
         FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<CONF0_SPEC> {
         FILTER_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_zero_en(&mut self) -> THR_ZERO_EN_W<CONF0_SPEC> {
         THR_ZERO_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_h_lim_en(&mut self) -> THR_H_LIM_EN_W<CONF0_SPEC> {
         THR_H_LIM_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_l_lim_en(&mut self) -> THR_L_LIM_EN_W<CONF0_SPEC> {
         THR_L_LIM_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres0_en(&mut self) -> THR_THRES0_EN_W<CONF0_SPEC> {
         THR_THRES0_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres1_en(&mut self) -> THR_THRES1_EN_W<CONF0_SPEC> {
         THR_THRES1_EN_W::new(self, 15)
     }
@@ -390,7 +383,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_neg_mode(&mut self, n: u8) -> CH_NEG_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -398,13 +390,11 @@ impl W {
     }
     #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 16)
     }
     #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 24)
     }
@@ -412,7 +402,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_pos_mode(&mut self, n: u8) -> CH_POS_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -420,13 +409,11 @@ impl W {
     }
     #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 18)
     }
     #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 26)
     }
@@ -434,7 +421,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_hctrl_mode(&mut self, n: u8) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -442,13 +428,11 @@ impl W {
     }
     #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 20)
     }
     #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 28)
     }
@@ -456,7 +440,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_lctrl_mode(&mut self, n: u8) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -464,13 +447,11 @@ impl W {
     }
     #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 22)
     }
     #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 30)
     }
diff --git a/esp32s2/src/pcnt/unit/conf1.rs b/esp32s2/src/pcnt/unit/conf1.rs
index 1585465b67..e88cae6aae 100644
--- a/esp32s2/src/pcnt/unit/conf1.rs
+++ b/esp32s2/src/pcnt/unit/conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres0(&mut self) -> CNT_THRES0_W<CONF1_SPEC> {
         CNT_THRES0_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres1(&mut self) -> CNT_THRES1_W<CONF1_SPEC> {
         CNT_THRES1_W::new(self, 16)
     }
diff --git a/esp32s2/src/pcnt/unit/conf2.rs b/esp32s2/src/pcnt/unit/conf2.rs
index cfc60509ee..d7b4aaa798 100644
--- a/esp32s2/src/pcnt/unit/conf2.rs
+++ b/esp32s2/src/pcnt/unit/conf2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_h_lim(&mut self) -> CNT_H_LIM_W<CONF2_SPEC> {
         CNT_H_LIM_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_l_lim(&mut self) -> CNT_L_LIM_W<CONF2_SPEC> {
         CNT_L_LIM_W::new(self, 16)
     }
diff --git a/esp32s2/src/pms/apb_peripheral_0.rs b/esp32s2/src/pms/apb_peripheral_0.rs
index 8ee368397a..9fff1d840f 100644
--- a/esp32s2/src/pms/apb_peripheral_0.rs
+++ b/esp32s2/src/pms/apb_peripheral_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks TX Copy DMA permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peripheral_lock(&mut self) -> APB_PERIPHERAL_LOCK_W<APB_PERIPHERAL_0_SPEC> {
         APB_PERIPHERAL_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/apb_peripheral_1.rs b/esp32s2/src/pms/apb_peripheral_1.rs
index 9e7e1f165f..bb140668f9 100644
--- a/esp32s2/src/pms/apb_peripheral_1.rs
+++ b/esp32s2/src/pms/apb_peripheral_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 splits the data phase of the last access and the address phase of following access."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peripheral_split_burst(
         &mut self,
     ) -> APB_PERIPHERAL_SPLIT_BURST_W<APB_PERIPHERAL_1_SPEC> {
diff --git a/esp32s2/src/pms/apb_peripheral_intr.rs b/esp32s2/src/pms/apb_peripheral_intr.rs
index 24b0b56609..b7d0cb8113 100644
--- a/esp32s2/src/pms/apb_peripheral_intr.rs
+++ b/esp32s2/src/pms/apb_peripheral_intr.rs
@@ -42,7 +42,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for APB peripheral interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peri_byte_error_clr(
         &mut self,
     ) -> APB_PERI_BYTE_ERROR_CLR_W<APB_PERIPHERAL_INTR_SPEC> {
@@ -50,7 +49,6 @@ impl W {
     }
     #[doc = "Bit 1 - The enable signal for APB peripheral access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peri_byte_error_en(&mut self) -> APB_PERI_BYTE_ERROR_EN_W<APB_PERIPHERAL_INTR_SPEC> {
         APB_PERI_BYTE_ERROR_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/cache_mmu_access_0.rs b/esp32s2/src/pms/cache_mmu_access_0.rs
index 2c29446209..deaaff96f4 100644
--- a/esp32s2/src/pms/cache_mmu_access_0.rs
+++ b/esp32s2/src/pms/cache_mmu_access_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache MMU permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_access_lock(&mut self) -> CACHE_MMU_ACCESS_LOCK_W<CACHE_MMU_ACCESS_0_SPEC> {
         CACHE_MMU_ACCESS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/cache_mmu_access_1.rs b/esp32s2/src/pms/cache_mmu_access_1.rs
index adebd18176..76d56753ba 100644
--- a/esp32s2/src/pms/cache_mmu_access_1.rs
+++ b/esp32s2/src/pms/cache_mmu_access_1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 permits read access to MMU memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mmu_rd_acs(&mut self) -> PRO_MMU_RD_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
         PRO_MMU_RD_ACS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 permits write access to MMU memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mmu_wr_acs(&mut self) -> PRO_MMU_WR_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
         PRO_MMU_WR_ACS_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/cache_source_0.rs b/esp32s2/src/pms/cache_source_0.rs
index 4913b2ce16..b2803049b4 100644
--- a/esp32s2/src/pms/cache_source_0.rs
+++ b/esp32s2/src/pms/cache_source_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache access permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_source_lock(&mut self) -> CACHE_SOURCE_LOCK_W<CACHE_SOURCE_0_SPEC> {
         CACHE_SOURCE_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/cache_source_1.rs b/esp32s2/src/pms/cache_source_1.rs
index 3253f644b2..aaf7dfe28c 100644
--- a/esp32s2/src/pms/cache_source_1.rs
+++ b/esp32s2/src/pms/cache_source_1.rs
@@ -92,7 +92,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_i_source_pro_iram1(
         &mut self,
     ) -> PRO_CACHE_I_SOURCE_PRO_IRAM1_W<CACHE_SOURCE_1_SPEC> {
@@ -100,7 +99,6 @@ impl W {
     }
     #[doc = "Bit 1 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_i_source_pro_irom0(
         &mut self,
     ) -> PRO_CACHE_I_SOURCE_PRO_IROM0_W<CACHE_SOURCE_1_SPEC> {
@@ -108,7 +106,6 @@ impl W {
     }
     #[doc = "Bit 2 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_i_source_pro_drom0(
         &mut self,
     ) -> PRO_CACHE_I_SOURCE_PRO_DROM0_W<CACHE_SOURCE_1_SPEC> {
@@ -116,7 +113,6 @@ impl W {
     }
     #[doc = "Bit 3 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_d_source_pro_dram0(
         &mut self,
     ) -> PRO_CACHE_D_SOURCE_PRO_DRAM0_W<CACHE_SOURCE_1_SPEC> {
@@ -124,7 +120,6 @@ impl W {
     }
     #[doc = "Bit 4 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_d_source_pro_dport(
         &mut self,
     ) -> PRO_CACHE_D_SOURCE_PRO_DPORT_W<CACHE_SOURCE_1_SPEC> {
@@ -132,7 +127,6 @@ impl W {
     }
     #[doc = "Bit 5 - xx"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_d_source_pro_drom0(
         &mut self,
     ) -> PRO_CACHE_D_SOURCE_PRO_DROM0_W<CACHE_SOURCE_1_SPEC> {
diff --git a/esp32s2/src/pms/cache_tag_access_0.rs b/esp32s2/src/pms/cache_tag_access_0.rs
index f0ac3cedef..4c0ad672bc 100644
--- a/esp32s2/src/pms/cache_tag_access_0.rs
+++ b/esp32s2/src/pms/cache_tag_access_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache tag permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_tag_access_lock(&mut self) -> CACHE_TAG_ACCESS_LOCK_W<CACHE_TAG_ACCESS_0_SPEC> {
         CACHE_TAG_ACCESS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/cache_tag_access_1.rs b/esp32s2/src/pms/cache_tag_access_1.rs
index b836b73348..a526f0f150 100644
--- a/esp32s2/src/pms/cache_tag_access_1.rs
+++ b/esp32s2/src/pms/cache_tag_access_1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 permits read access to Icache tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i_tag_rd_acs(&mut self) -> PRO_I_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_I_TAG_RD_ACS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 permits write access to Icache tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i_tag_wr_acs(&mut self) -> PRO_I_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_I_TAG_WR_ACS_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 permits read access to Dcache tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_d_tag_rd_acs(&mut self) -> PRO_D_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_D_TAG_RD_ACS_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 permits write access to Dcache tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_d_tag_wr_acs(&mut self) -> PRO_D_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_D_TAG_WR_ACS_W::new(self, 3)
     }
diff --git a/esp32s2/src/pms/clock_gate.rs b/esp32s2/src/pms/clock_gate.rs
index 59ad3752aa..22932d68aa 100644
--- a/esp32s2/src/pms/clock_gate.rs
+++ b/esp32s2/src/pms/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable the clock of permission control module when set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/cpu_peripheral_intr.rs b/esp32s2/src/pms/cpu_peripheral_intr.rs
index a49d6934ea..e688be58d2 100644
--- a/esp32s2/src/pms/cpu_peripheral_intr.rs
+++ b/esp32s2/src/pms/cpu_peripheral_intr.rs
@@ -42,7 +42,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for CPU peripheral access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_peri_byte_error_clr(
         &mut self,
     ) -> CPU_PERI_BYTE_ERROR_CLR_W<CPU_PERIPHERAL_INTR_SPEC> {
@@ -50,7 +49,6 @@ impl W {
     }
     #[doc = "Bit 1 - The enable signal for CPU peripheral access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_peri_byte_error_en(&mut self) -> CPU_PERI_BYTE_ERROR_EN_W<CPU_PERIPHERAL_INTR_SPEC> {
         CPU_PERI_BYTE_ERROR_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/date.rs b/esp32s2/src/pms/date.rs
index 1c72901ed5..e46dee050e 100644
--- a/esp32s2/src/pms/date.rs
+++ b/esp32s2/src/pms/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/dma_apb_i_0.rs b/esp32s2/src/pms/dma_apb_i_0.rs
index d839df2a56..a4f0137e9f 100644
--- a/esp32s2/src/pms/dma_apb_i_0.rs
+++ b/esp32s2/src/pms/dma_apb_i_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks internal DMA permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_lock(&mut self) -> DMA_APB_I_LOCK_W<DMA_APB_I_0_SPEC> {
         DMA_APB_I_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/dma_apb_i_1.rs b/esp32s2/src/pms/dma_apb_i_1.rs
index e66833dca4..424fb93b40 100644
--- a/esp32s2/src/pms/dma_apb_i_1.rs
+++ b/esp32s2/src/pms/dma_apb_i_1.rs
@@ -147,79 +147,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants internal DMA permission to read SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_0_r(&mut self) -> DMA_APB_I_SRAM_0_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_0_R_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 grants internal DMA permission to write SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_0_w(&mut self) -> DMA_APB_I_SRAM_0_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_0_W_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 grants internal DMA permission to read SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_1_r(&mut self) -> DMA_APB_I_SRAM_1_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_1_R_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 grants internal DMA permission to write SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_1_w(&mut self) -> DMA_APB_I_SRAM_1_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_1_W_W::new(self, 3)
     }
     #[doc = "Bit 4 - Setting to 1 grants internal DMA permission to read SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_2_r(&mut self) -> DMA_APB_I_SRAM_2_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_2_R_W::new(self, 4)
     }
     #[doc = "Bit 5 - Setting to 1 grants internal DMA permission to write SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_2_w(&mut self) -> DMA_APB_I_SRAM_2_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_2_W_W::new(self, 5)
     }
     #[doc = "Bit 6 - Setting to 1 grants internal DMA permission to read SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_3_r(&mut self) -> DMA_APB_I_SRAM_3_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_3_R_W::new(self, 6)
     }
     #[doc = "Bit 7 - Setting to 1 grants internal DMA permission to write SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_3_w(&mut self) -> DMA_APB_I_SRAM_3_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_3_W_W::new(self, 7)
     }
     #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for internal DMA access."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_4_spltaddr(&mut self) -> DMA_APB_I_SRAM_4_SPLTADDR_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_4_SPLTADDR_W::new(self, 8)
     }
     #[doc = "Bit 25 - Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_4_l_r(&mut self) -> DMA_APB_I_SRAM_4_L_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_4_L_R_W::new(self, 25)
     }
     #[doc = "Bit 26 - Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_4_l_w(&mut self) -> DMA_APB_I_SRAM_4_L_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_4_L_W_W::new(self, 26)
     }
     #[doc = "Bit 27 - Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_4_h_r(&mut self) -> DMA_APB_I_SRAM_4_H_R_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_4_H_R_W::new(self, 27)
     }
     #[doc = "Bit 28 - Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_sram_4_h_w(&mut self) -> DMA_APB_I_SRAM_4_H_W_W<DMA_APB_I_1_SPEC> {
         DMA_APB_I_SRAM_4_H_W_W::new(self, 28)
     }
diff --git a/esp32s2/src/pms/dma_apb_i_2.rs b/esp32s2/src/pms/dma_apb_i_2.rs
index be8bd78c88..53e0e67dca 100644
--- a/esp32s2/src/pms/dma_apb_i_2.rs
+++ b/esp32s2/src/pms/dma_apb_i_2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for internal DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_ilg_clr(&mut self) -> DMA_APB_I_ILG_CLR_W<DMA_APB_I_2_SPEC> {
         DMA_APB_I_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for internal DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apb_i_ilg_en(&mut self) -> DMA_APB_I_ILG_EN_W<DMA_APB_I_2_SPEC> {
         DMA_APB_I_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/dma_rx_i_0.rs b/esp32s2/src/pms/dma_rx_i_0.rs
index 1e601a0932..23918d66ba 100644
--- a/esp32s2/src/pms/dma_rx_i_0.rs
+++ b/esp32s2/src/pms/dma_rx_i_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks RX Copy DMA permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_lock(&mut self) -> DMA_RX_I_LOCK_W<DMA_RX_I_0_SPEC> {
         DMA_RX_I_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/dma_rx_i_1.rs b/esp32s2/src/pms/dma_rx_i_1.rs
index aa85a6947f..abf3911a5d 100644
--- a/esp32s2/src/pms/dma_rx_i_1.rs
+++ b/esp32s2/src/pms/dma_rx_i_1.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_0_r(&mut self) -> DMA_RX_I_SRAM_0_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_0_R_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_0_w(&mut self) -> DMA_RX_I_SRAM_0_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_0_W_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_1_r(&mut self) -> DMA_RX_I_SRAM_1_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_1_R_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_1_w(&mut self) -> DMA_RX_I_SRAM_1_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_1_W_W::new(self, 3)
     }
     #[doc = "Bit 4 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_2_r(&mut self) -> DMA_RX_I_SRAM_2_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_2_R_W::new(self, 4)
     }
     #[doc = "Bit 5 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_2_w(&mut self) -> DMA_RX_I_SRAM_2_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_2_W_W::new(self, 5)
     }
     #[doc = "Bit 6 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_3_r(&mut self) -> DMA_RX_I_SRAM_3_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_3_R_W::new(self, 6)
     }
     #[doc = "Bit 7 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_3_w(&mut self) -> DMA_RX_I_SRAM_3_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_3_W_W::new(self, 7)
     }
     #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for RX Copy DMA access."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_4_spltaddr(&mut self) -> DMA_RX_I_SRAM_4_SPLTADDR_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_4_SPLTADDR_W::new(self, 8)
     }
     #[doc = "Bit 25 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_4_l_r(&mut self) -> DMA_RX_I_SRAM_4_L_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_4_L_R_W::new(self, 25)
     }
     #[doc = "Bit 26 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_4_l_w(&mut self) -> DMA_RX_I_SRAM_4_L_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_4_L_W_W::new(self, 26)
     }
     #[doc = "Bit 27 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_4_h_r(&mut self) -> DMA_RX_I_SRAM_4_H_R_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_4_H_R_W::new(self, 27)
     }
     #[doc = "Bit 28 - Setting to 1 grants RX Copy DMA permission to write SRAM Block 4~21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_sram_4_h_w(&mut self) -> DMA_RX_I_SRAM_4_H_W_W<DMA_RX_I_1_SPEC> {
         DMA_RX_I_SRAM_4_H_W_W::new(self, 28)
     }
diff --git a/esp32s2/src/pms/dma_rx_i_2.rs b/esp32s2/src/pms/dma_rx_i_2.rs
index 0c261ee8fb..4fe19ba73a 100644
--- a/esp32s2/src/pms/dma_rx_i_2.rs
+++ b/esp32s2/src/pms/dma_rx_i_2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for RX Copy DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_ilg_clr(&mut self) -> DMA_RX_I_ILG_CLR_W<DMA_RX_I_2_SPEC> {
         DMA_RX_I_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for RX Copy DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_i_ilg_en(&mut self) -> DMA_RX_I_ILG_EN_W<DMA_RX_I_2_SPEC> {
         DMA_RX_I_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/dma_tx_i_0.rs b/esp32s2/src/pms/dma_tx_i_0.rs
index 7b073d7f19..3b93560bf6 100644
--- a/esp32s2/src/pms/dma_tx_i_0.rs
+++ b/esp32s2/src/pms/dma_tx_i_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks TX Copy DMA permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_lock(&mut self) -> DMA_TX_I_LOCK_W<DMA_TX_I_0_SPEC> {
         DMA_TX_I_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/dma_tx_i_1.rs b/esp32s2/src/pms/dma_tx_i_1.rs
index 6962795456..25b72ed9b3 100644
--- a/esp32s2/src/pms/dma_tx_i_1.rs
+++ b/esp32s2/src/pms/dma_tx_i_1.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_0_r(&mut self) -> DMA_TX_I_SRAM_0_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_0_R_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_0_w(&mut self) -> DMA_TX_I_SRAM_0_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_0_W_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_1_r(&mut self) -> DMA_TX_I_SRAM_1_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_1_R_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_1_w(&mut self) -> DMA_TX_I_SRAM_1_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_1_W_W::new(self, 3)
     }
     #[doc = "Bit 4 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_2_r(&mut self) -> DMA_TX_I_SRAM_2_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_2_R_W::new(self, 4)
     }
     #[doc = "Bit 5 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_2_w(&mut self) -> DMA_TX_I_SRAM_2_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_2_W_W::new(self, 5)
     }
     #[doc = "Bit 6 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_3_r(&mut self) -> DMA_TX_I_SRAM_3_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_3_R_W::new(self, 6)
     }
     #[doc = "Bit 7 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_3_w(&mut self) -> DMA_TX_I_SRAM_3_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_3_W_W::new(self, 7)
     }
     #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for TX Copy DMA access."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_4_spltaddr(&mut self) -> DMA_TX_I_SRAM_4_SPLTADDR_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_4_SPLTADDR_W::new(self, 8)
     }
     #[doc = "Bit 25 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_4_l_r(&mut self) -> DMA_TX_I_SRAM_4_L_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_4_L_R_W::new(self, 25)
     }
     #[doc = "Bit 26 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_4_l_w(&mut self) -> DMA_TX_I_SRAM_4_L_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_4_L_W_W::new(self, 26)
     }
     #[doc = "Bit 27 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_4_h_r(&mut self) -> DMA_TX_I_SRAM_4_H_R_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_4_H_R_W::new(self, 27)
     }
     #[doc = "Bit 28 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_sram_4_h_w(&mut self) -> DMA_TX_I_SRAM_4_H_W_W<DMA_TX_I_1_SPEC> {
         DMA_TX_I_SRAM_4_H_W_W::new(self, 28)
     }
diff --git a/esp32s2/src/pms/dma_tx_i_2.rs b/esp32s2/src/pms/dma_tx_i_2.rs
index 93cea676d3..8e80d3b934 100644
--- a/esp32s2/src/pms/dma_tx_i_2.rs
+++ b/esp32s2/src/pms/dma_tx_i_2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for TX Copy DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_ilg_clr(&mut self) -> DMA_TX_I_ILG_CLR_W<DMA_TX_I_2_SPEC> {
         DMA_TX_I_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for TX Copy DMA access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_i_ilg_en(&mut self) -> DMA_TX_I_ILG_EN_W<DMA_TX_I_2_SPEC> {
         DMA_TX_I_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/mac_dump_0.rs b/esp32s2/src/pms/mac_dump_0.rs
index e6fa6c1ba8..4e86092c69 100644
--- a/esp32s2/src/pms/mac_dump_0.rs
+++ b/esp32s2/src/pms/mac_dump_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks MAC dump permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_dump_lock(&mut self) -> MAC_DUMP_LOCK_W<MAC_DUMP_0_SPEC> {
         MAC_DUMP_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/mac_dump_1.rs b/esp32s2/src/pms/mac_dump_1.rs
index 547ef5a6db..65b68fc60b 100644
--- a/esp32s2/src/pms/mac_dump_1.rs
+++ b/esp32s2/src/pms/mac_dump_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - Configure MAC dump connection."]
     #[inline(always)]
-    #[must_use]
     pub fn mac_dump_connect(&mut self) -> MAC_DUMP_CONNECT_W<MAC_DUMP_1_SPEC> {
         MAC_DUMP_CONNECT_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/occupy_0.rs b/esp32s2/src/pms/occupy_0.rs
index 49b842f2d3..3880edd510 100644
--- a/esp32s2/src/pms/occupy_0.rs
+++ b/esp32s2/src/pms/occupy_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks occupy permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn occupy_lock(&mut self) -> OCCUPY_LOCK_W<OCCUPY_0_SPEC> {
         OCCUPY_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/occupy_1.rs b/esp32s2/src/pms/occupy_1.rs
index 351b6ed6e8..384b42ae72 100644
--- a/esp32s2/src/pms/occupy_1.rs
+++ b/esp32s2/src/pms/occupy_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Configure whether SRAM Block 0-3 is used as cache memory."]
     #[inline(always)]
-    #[must_use]
     pub fn occupy_cache(&mut self) -> OCCUPY_CACHE_W<OCCUPY_1_SPEC> {
         OCCUPY_CACHE_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/occupy_2.rs b/esp32s2/src/pms/occupy_2.rs
index 24ecf51483..9ffd45fe18 100644
--- a/esp32s2/src/pms/occupy_2.rs
+++ b/esp32s2/src/pms/occupy_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Configure whether SRAM Block 18-21 is used as mac dump."]
     #[inline(always)]
-    #[must_use]
     pub fn occupy_mac_dump(&mut self) -> OCCUPY_MAC_DUMP_W<OCCUPY_2_SPEC> {
         OCCUPY_MAC_DUMP_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/occupy_3.rs b/esp32s2/src/pms/occupy_3.rs
index d5843c6e15..5951a18ac1 100644
--- a/esp32s2/src/pms/occupy_3.rs
+++ b/esp32s2/src/pms/occupy_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Configure one block of SRAM Block 4-21 is used as trace memory."]
     #[inline(always)]
-    #[must_use]
     pub fn occupy_pro_trace(&mut self) -> OCCUPY_PRO_TRACE_W<OCCUPY_3_SPEC> {
         OCCUPY_PRO_TRACE_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_ahb_0.rs b/esp32s2/src/pms/pro_ahb_0.rs
index 7fbf7b29af..44512de581 100644
--- a/esp32s2/src/pms/pro_ahb_0.rs
+++ b/esp32s2/src/pms/pro_ahb_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks PeriBus2 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_lock(&mut self) -> PRO_AHB_LOCK_W<PRO_AHB_0_SPEC> {
         PRO_AHB_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_ahb_1.rs b/esp32s2/src/pms/pro_ahb_1.rs
index d73da51c54..66c3879349 100644
--- a/esp32s2/src/pms/pro_ahb_1.rs
+++ b/esp32s2/src/pms/pro_ahb_1.rs
@@ -87,43 +87,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTCSlow_0 for PeriBus2 access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_spltaddr(&mut self) -> PRO_AHB_RTCSLOW_0_SPLTADDR_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_SPLTADDR_W::new(self, 0)
     }
     #[doc = "Bit 11 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_l_f(&mut self) -> PRO_AHB_RTCSLOW_0_L_F_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_L_F_W::new(self, 11)
     }
     #[doc = "Bit 12 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_l_r(&mut self) -> PRO_AHB_RTCSLOW_0_L_R_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_L_R_W::new(self, 12)
     }
     #[doc = "Bit 13 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_l_w(&mut self) -> PRO_AHB_RTCSLOW_0_L_W_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_L_W_W::new(self, 13)
     }
     #[doc = "Bit 14 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_h_f(&mut self) -> PRO_AHB_RTCSLOW_0_H_F_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_H_F_W::new(self, 14)
     }
     #[doc = "Bit 15 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_h_r(&mut self) -> PRO_AHB_RTCSLOW_0_H_R_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_H_R_W::new(self, 15)
     }
     #[doc = "Bit 16 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_0_h_w(&mut self) -> PRO_AHB_RTCSLOW_0_H_W_W<PRO_AHB_1_SPEC> {
         PRO_AHB_RTCSLOW_0_H_W_W::new(self, 16)
     }
diff --git a/esp32s2/src/pms/pro_ahb_2.rs b/esp32s2/src/pms/pro_ahb_2.rs
index 2c55a377b5..a55019a016 100644
--- a/esp32s2/src/pms/pro_ahb_2.rs
+++ b/esp32s2/src/pms/pro_ahb_2.rs
@@ -87,43 +87,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTCSlow_1 for PeriBus2 access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_spltaddr(&mut self) -> PRO_AHB_RTCSLOW_1_SPLTADDR_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_SPLTADDR_W::new(self, 0)
     }
     #[doc = "Bit 11 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_l_f(&mut self) -> PRO_AHB_RTCSLOW_1_L_F_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_L_F_W::new(self, 11)
     }
     #[doc = "Bit 12 - Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_l_r(&mut self) -> PRO_AHB_RTCSLOW_1_L_R_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_L_R_W::new(self, 12)
     }
     #[doc = "Bit 13 - Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_l_w(&mut self) -> PRO_AHB_RTCSLOW_1_L_W_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_L_W_W::new(self, 13)
     }
     #[doc = "Bit 14 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_h_f(&mut self) -> PRO_AHB_RTCSLOW_1_H_F_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_H_F_W::new(self, 14)
     }
     #[doc = "Bit 15 - Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_h_r(&mut self) -> PRO_AHB_RTCSLOW_1_H_R_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_H_R_W::new(self, 15)
     }
     #[doc = "Bit 16 - Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_rtcslow_1_h_w(&mut self) -> PRO_AHB_RTCSLOW_1_H_W_W<PRO_AHB_2_SPEC> {
         PRO_AHB_RTCSLOW_1_H_W_W::new(self, 16)
     }
diff --git a/esp32s2/src/pms/pro_ahb_3.rs b/esp32s2/src/pms/pro_ahb_3.rs
index 3ae7194f58..09dbb14ae7 100644
--- a/esp32s2/src/pms/pro_ahb_3.rs
+++ b/esp32s2/src/pms/pro_ahb_3.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for PeriBus2 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_ilg_clr(&mut self) -> PRO_AHB_ILG_CLR_W<PRO_AHB_3_SPEC> {
         PRO_AHB_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for PeriBus2 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_ahb_ilg_en(&mut self) -> PRO_AHB_ILG_EN_W<PRO_AHB_3_SPEC> {
         PRO_AHB_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/pro_boot_location_0.rs b/esp32s2/src/pms/pro_boot_location_0.rs
index f1b322b474..7c136aa573 100644
--- a/esp32s2/src/pms/pro_boot_location_0.rs
+++ b/esp32s2/src/pms/pro_boot_location_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks boot remap permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_boot_location_lock(&mut self) -> PRO_BOOT_LOCATION_LOCK_W<PRO_BOOT_LOCATION_0_SPEC> {
         PRO_BOOT_LOCATION_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_boot_location_1.rs b/esp32s2/src/pms/pro_boot_location_1.rs
index 9aaf892fe8..69e8f43e41 100644
--- a/esp32s2/src/pms/pro_boot_location_1.rs
+++ b/esp32s2/src/pms/pro_boot_location_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - If set to 1, enable boot remap function."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_boot_remap(&mut self) -> PRO_BOOT_REMAP_W<PRO_BOOT_LOCATION_1_SPEC> {
         PRO_BOOT_REMAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_cache_0.rs b/esp32s2/src/pms/pro_cache_0.rs
index e25fe017a6..bbde8cc4a9 100644
--- a/esp32s2/src/pms/pro_cache_0.rs
+++ b/esp32s2/src/pms/pro_cache_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_lock(&mut self) -> PRO_CACHE_LOCK_W<PRO_CACHE_0_SPEC> {
         PRO_CACHE_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_cache_1.rs b/esp32s2/src/pms/pro_cache_1.rs
index eeee600e0c..ec1327c6e8 100644
--- a/esp32s2/src/pms/pro_cache_1.rs
+++ b/esp32s2/src/pms/pro_cache_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Configure which SRAM Block will be occupied by Icache or Dcache."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_connect(&mut self) -> PRO_CACHE_CONNECT_W<PRO_CACHE_1_SPEC> {
         PRO_CACHE_CONNECT_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_cache_2.rs b/esp32s2/src/pms/pro_cache_2.rs
index 2cd633fe21..26b7aed065 100644
--- a/esp32s2/src/pms/pro_cache_2.rs
+++ b/esp32s2/src/pms/pro_cache_2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for cache access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ilg_clr(&mut self) -> PRO_CACHE_ILG_CLR_W<PRO_CACHE_2_SPEC> {
         PRO_CACHE_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for cache access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_ilg_en(&mut self) -> PRO_CACHE_ILG_EN_W<PRO_CACHE_2_SPEC> {
         PRO_CACHE_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/pro_dport_0.rs b/esp32s2/src/pms/pro_dport_0.rs
index c425ac7f27..be7b28cf75 100644
--- a/esp32s2/src/pms/pro_dport_0.rs
+++ b/esp32s2/src/pms/pro_dport_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks PeriBus1 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_lock(&mut self) -> PRO_DPORT_LOCK_W<PRO_DPORT_0_SPEC> {
         PRO_DPORT_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dport_1.rs b/esp32s2/src/pms/pro_dport_1.rs
index b9d6e8f7c9..074d1d3a46 100644
--- a/esp32s2/src/pms/pro_dport_1.rs
+++ b/esp32s2/src/pms/pro_dport_1.rs
@@ -93,7 +93,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 denies PeriBus1 bus???s access to APB peripheral."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_apb_peripheral_forbid(
         &mut self,
     ) -> PRO_DPORT_APB_PERIPHERAL_FORBID_W<PRO_DPORT_1_SPEC> {
@@ -101,37 +100,31 @@ impl W {
     }
     #[doc = "Bits 1:11 - Configure the split address of RTC FAST for PeriBus1 access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_rtcslow_spltaddr(&mut self) -> PRO_DPORT_RTCSLOW_SPLTADDR_W<PRO_DPORT_1_SPEC> {
         PRO_DPORT_RTCSLOW_SPLTADDR_W::new(self, 1)
     }
     #[doc = "Bit 12 - Setting to 1 grants PeriBus1 permission to read RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_rtcslow_l_r(&mut self) -> PRO_DPORT_RTCSLOW_L_R_W<PRO_DPORT_1_SPEC> {
         PRO_DPORT_RTCSLOW_L_R_W::new(self, 12)
     }
     #[doc = "Bit 13 - Setting to 1 grants PeriBus1 permission to write RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_rtcslow_l_w(&mut self) -> PRO_DPORT_RTCSLOW_L_W_W<PRO_DPORT_1_SPEC> {
         PRO_DPORT_RTCSLOW_L_W_W::new(self, 13)
     }
     #[doc = "Bit 14 - Setting to 1 grants PeriBus1 permission to read RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_rtcslow_h_r(&mut self) -> PRO_DPORT_RTCSLOW_H_R_W<PRO_DPORT_1_SPEC> {
         PRO_DPORT_RTCSLOW_H_R_W::new(self, 14)
     }
     #[doc = "Bit 15 - Setting to 1 grants PeriBus1 permission to write RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_rtcslow_h_w(&mut self) -> PRO_DPORT_RTCSLOW_H_W_W<PRO_DPORT_1_SPEC> {
         PRO_DPORT_RTCSLOW_H_W_W::new(self, 15)
     }
     #[doc = "Bits 16:19 - Configure whether to enable read protection for user-configured FIFO address."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_reserve_fifo_valid(
         &mut self,
     ) -> PRO_DPORT_RESERVE_FIFO_VALID_W<PRO_DPORT_1_SPEC> {
diff --git a/esp32s2/src/pms/pro_dport_2.rs b/esp32s2/src/pms/pro_dport_2.rs
index 8c6c145d30..42bb5580c1 100644
--- a/esp32s2/src/pms/pro_dport_2.rs
+++ b/esp32s2/src/pms/pro_dport_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_reserve_fifo_0(&mut self) -> PRO_DPORT_RESERVE_FIFO_0_W<PRO_DPORT_2_SPEC> {
         PRO_DPORT_RESERVE_FIFO_0_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dport_3.rs b/esp32s2/src/pms/pro_dport_3.rs
index 3c4ea2ccdb..8cc9c2fec1 100644
--- a/esp32s2/src/pms/pro_dport_3.rs
+++ b/esp32s2/src/pms/pro_dport_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_reserve_fifo_1(&mut self) -> PRO_DPORT_RESERVE_FIFO_1_W<PRO_DPORT_3_SPEC> {
         PRO_DPORT_RESERVE_FIFO_1_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dport_4.rs b/esp32s2/src/pms/pro_dport_4.rs
index 52016c0419..38584dc29d 100644
--- a/esp32s2/src/pms/pro_dport_4.rs
+++ b/esp32s2/src/pms/pro_dport_4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_reserve_fifo_2(&mut self) -> PRO_DPORT_RESERVE_FIFO_2_W<PRO_DPORT_4_SPEC> {
         PRO_DPORT_RESERVE_FIFO_2_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dport_5.rs b/esp32s2/src/pms/pro_dport_5.rs
index f08c0c397d..61cf23e9af 100644
--- a/esp32s2/src/pms/pro_dport_5.rs
+++ b/esp32s2/src/pms/pro_dport_5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_reserve_fifo_3(&mut self) -> PRO_DPORT_RESERVE_FIFO_3_W<PRO_DPORT_5_SPEC> {
         PRO_DPORT_RESERVE_FIFO_3_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dport_6.rs b/esp32s2/src/pms/pro_dport_6.rs
index d62175d72d..d3b749168a 100644
--- a/esp32s2/src/pms/pro_dport_6.rs
+++ b/esp32s2/src/pms/pro_dport_6.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for PeriBus1 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_ilg_clr(&mut self) -> PRO_DPORT_ILG_CLR_W<PRO_DPORT_6_SPEC> {
         PRO_DPORT_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for PeriBus1 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dport_ilg_en(&mut self) -> PRO_DPORT_ILG_EN_W<PRO_DPORT_6_SPEC> {
         PRO_DPORT_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/pro_dram0_0.rs b/esp32s2/src/pms/pro_dram0_0.rs
index 93ed2d4f2a..7ab57e7b1b 100644
--- a/esp32s2/src/pms/pro_dram0_0.rs
+++ b/esp32s2/src/pms/pro_dram0_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks DBUS0 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_lock(&mut self) -> PRO_DRAM0_LOCK_W<PRO_DRAM0_0_SPEC> {
         PRO_DRAM0_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_dram0_1.rs b/esp32s2/src/pms/pro_dram0_1.rs
index bd8d910939..6ab9166cfc 100644
--- a/esp32s2/src/pms/pro_dram0_1.rs
+++ b/esp32s2/src/pms/pro_dram0_1.rs
@@ -147,79 +147,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants DBUS0 permission to read SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_0_r(&mut self) -> PRO_DRAM0_SRAM_0_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_0_R_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 grants DBUS0 permission to write SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_0_w(&mut self) -> PRO_DRAM0_SRAM_0_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_0_W_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 grants DBUS0 permission to read SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_1_r(&mut self) -> PRO_DRAM0_SRAM_1_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_1_R_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 grants DBUS0 permission to write SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_1_w(&mut self) -> PRO_DRAM0_SRAM_1_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_1_W_W::new(self, 3)
     }
     #[doc = "Bit 4 - Setting to 1 grants DBUS0 permission to read SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_2_r(&mut self) -> PRO_DRAM0_SRAM_2_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_2_R_W::new(self, 4)
     }
     #[doc = "Bit 5 - Setting to 1 grants DBUS0 permission to write SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_2_w(&mut self) -> PRO_DRAM0_SRAM_2_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_2_W_W::new(self, 5)
     }
     #[doc = "Bit 6 - Setting to 1 grants DBUS0 permission to read SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_3_r(&mut self) -> PRO_DRAM0_SRAM_3_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_3_R_W::new(self, 6)
     }
     #[doc = "Bit 7 - Setting to 1 grants DBUS0 permission to write SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_3_w(&mut self) -> PRO_DRAM0_SRAM_3_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_3_W_W::new(self, 7)
     }
     #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for DBUS0 access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_4_spltaddr(&mut self) -> PRO_DRAM0_SRAM_4_SPLTADDR_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_4_SPLTADDR_W::new(self, 8)
     }
     #[doc = "Bit 25 - Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_4_l_r(&mut self) -> PRO_DRAM0_SRAM_4_L_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_4_L_R_W::new(self, 25)
     }
     #[doc = "Bit 26 - Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_4_l_w(&mut self) -> PRO_DRAM0_SRAM_4_L_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_4_L_W_W::new(self, 26)
     }
     #[doc = "Bit 27 - Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_4_h_r(&mut self) -> PRO_DRAM0_SRAM_4_H_R_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_4_H_R_W::new(self, 27)
     }
     #[doc = "Bit 28 - Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_sram_4_h_w(&mut self) -> PRO_DRAM0_SRAM_4_H_W_W<PRO_DRAM0_1_SPEC> {
         PRO_DRAM0_SRAM_4_H_W_W::new(self, 28)
     }
diff --git a/esp32s2/src/pms/pro_dram0_2.rs b/esp32s2/src/pms/pro_dram0_2.rs
index 46cb9c80c1..acd649fcbb 100644
--- a/esp32s2/src/pms/pro_dram0_2.rs
+++ b/esp32s2/src/pms/pro_dram0_2.rs
@@ -67,31 +67,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTC FAST for DBUS0 access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_rtcfast_spltaddr(&mut self) -> PRO_DRAM0_RTCFAST_SPLTADDR_W<PRO_DRAM0_2_SPEC> {
         PRO_DRAM0_RTCFAST_SPLTADDR_W::new(self, 0)
     }
     #[doc = "Bit 11 - Setting to 1 grants DBUS0 permission to read RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_rtcfast_l_r(&mut self) -> PRO_DRAM0_RTCFAST_L_R_W<PRO_DRAM0_2_SPEC> {
         PRO_DRAM0_RTCFAST_L_R_W::new(self, 11)
     }
     #[doc = "Bit 12 - Setting to 1 grants DBUS0 permission to write RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_rtcfast_l_w(&mut self) -> PRO_DRAM0_RTCFAST_L_W_W<PRO_DRAM0_2_SPEC> {
         PRO_DRAM0_RTCFAST_L_W_W::new(self, 12)
     }
     #[doc = "Bit 13 - Setting to 1 grants DBUS0 permission to read RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_rtcfast_h_r(&mut self) -> PRO_DRAM0_RTCFAST_H_R_W<PRO_DRAM0_2_SPEC> {
         PRO_DRAM0_RTCFAST_H_R_W::new(self, 13)
     }
     #[doc = "Bit 14 - Setting to 1 grants DBUS0 permission to write RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_rtcfast_h_w(&mut self) -> PRO_DRAM0_RTCFAST_H_W_W<PRO_DRAM0_2_SPEC> {
         PRO_DRAM0_RTCFAST_H_W_W::new(self, 14)
     }
diff --git a/esp32s2/src/pms/pro_dram0_3.rs b/esp32s2/src/pms/pro_dram0_3.rs
index 4e1051f6ee..67270eb07e 100644
--- a/esp32s2/src/pms/pro_dram0_3.rs
+++ b/esp32s2/src/pms/pro_dram0_3.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for DBUS0 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_ilg_clr(&mut self) -> PRO_DRAM0_ILG_CLR_W<PRO_DRAM0_3_SPEC> {
         PRO_DRAM0_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for DBUS0 access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dram0_ilg_en(&mut self) -> PRO_DRAM0_ILG_EN_W<PRO_DRAM0_3_SPEC> {
         PRO_DRAM0_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/pro_iram0_0.rs b/esp32s2/src/pms/pro_iram0_0.rs
index 9782db0cc2..97ce96bef9 100644
--- a/esp32s2/src/pms/pro_iram0_0.rs
+++ b/esp32s2/src/pms/pro_iram0_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks IBUS permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_lock(&mut self) -> PRO_IRAM0_LOCK_W<PRO_IRAM0_0_SPEC> {
         PRO_IRAM0_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_iram0_1.rs b/esp32s2/src/pms/pro_iram0_1.rs
index 598c670403..b39446184a 100644
--- a/esp32s2/src/pms/pro_iram0_1.rs
+++ b/esp32s2/src/pms/pro_iram0_1.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants IBUS permission to fetch SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_0_f(&mut self) -> PRO_IRAM0_SRAM_0_F_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_0_F_W::new(self, 0)
     }
     #[doc = "Bit 1 - Setting to 1 grants IBUS permission to read SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_0_r(&mut self) -> PRO_IRAM0_SRAM_0_R_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_0_R_W::new(self, 1)
     }
     #[doc = "Bit 2 - Setting to 1 grants IBUS permission to write SRAM Block 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_0_w(&mut self) -> PRO_IRAM0_SRAM_0_W_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_0_W_W::new(self, 2)
     }
     #[doc = "Bit 3 - Setting to 1 grants IBUS permission to fetch SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_1_f(&mut self) -> PRO_IRAM0_SRAM_1_F_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_1_F_W::new(self, 3)
     }
     #[doc = "Bit 4 - Setting to 1 grants IBUS permission to read SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_1_r(&mut self) -> PRO_IRAM0_SRAM_1_R_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_1_R_W::new(self, 4)
     }
     #[doc = "Bit 5 - Setting to 1 grants IBUS permission to write SRAM Block 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_1_w(&mut self) -> PRO_IRAM0_SRAM_1_W_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_1_W_W::new(self, 5)
     }
     #[doc = "Bit 6 - Setting to 1 grants IBUS permission to fetch SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_2_f(&mut self) -> PRO_IRAM0_SRAM_2_F_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_2_F_W::new(self, 6)
     }
     #[doc = "Bit 7 - Setting to 1 grants IBUS permission to read SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_2_r(&mut self) -> PRO_IRAM0_SRAM_2_R_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_2_R_W::new(self, 7)
     }
     #[doc = "Bit 8 - Setting to 1 grants IBUS permission to write SRAM Block 2."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_2_w(&mut self) -> PRO_IRAM0_SRAM_2_W_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_2_W_W::new(self, 8)
     }
     #[doc = "Bit 9 - Setting to 1 grants IBUS permission to fetch SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_3_f(&mut self) -> PRO_IRAM0_SRAM_3_F_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_3_F_W::new(self, 9)
     }
     #[doc = "Bit 10 - Setting to 1 grants IBUS permission to read SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_3_r(&mut self) -> PRO_IRAM0_SRAM_3_R_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_3_R_W::new(self, 10)
     }
     #[doc = "Bit 11 - Setting to 1 grants IBUS permission to write SRAM Block 3."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_3_w(&mut self) -> PRO_IRAM0_SRAM_3_W_W<PRO_IRAM0_1_SPEC> {
         PRO_IRAM0_SRAM_3_W_W::new(self, 11)
     }
diff --git a/esp32s2/src/pms/pro_iram0_2.rs b/esp32s2/src/pms/pro_iram0_2.rs
index 1cb127cff3..c778707f76 100644
--- a/esp32s2/src/pms/pro_iram0_2.rs
+++ b/esp32s2/src/pms/pro_iram0_2.rs
@@ -87,43 +87,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:16 - Configure the split address of SRAM Block 4-21 for IBUS access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_spltaddr(&mut self) -> PRO_IRAM0_SRAM_4_SPLTADDR_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_SPLTADDR_W::new(self, 0)
     }
     #[doc = "Bit 17 - Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_l_f(&mut self) -> PRO_IRAM0_SRAM_4_L_F_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_L_F_W::new(self, 17)
     }
     #[doc = "Bit 18 - Setting to 1 grants IBUS permission to read SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_l_r(&mut self) -> PRO_IRAM0_SRAM_4_L_R_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_L_R_W::new(self, 18)
     }
     #[doc = "Bit 19 - Setting to 1 grants IBUS permission to write SRAM Block 4-21 low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_l_w(&mut self) -> PRO_IRAM0_SRAM_4_L_W_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_L_W_W::new(self, 19)
     }
     #[doc = "Bit 20 - Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_h_f(&mut self) -> PRO_IRAM0_SRAM_4_H_F_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_H_F_W::new(self, 20)
     }
     #[doc = "Bit 21 - Setting to 1 grants IBUS permission to read SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_h_r(&mut self) -> PRO_IRAM0_SRAM_4_H_R_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_H_R_W::new(self, 21)
     }
     #[doc = "Bit 22 - Setting to 1 grants IBUS permission to write SRAM Block 4-21 high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_sram_4_h_w(&mut self) -> PRO_IRAM0_SRAM_4_H_W_W<PRO_IRAM0_2_SPEC> {
         PRO_IRAM0_SRAM_4_H_W_W::new(self, 22)
     }
diff --git a/esp32s2/src/pms/pro_iram0_3.rs b/esp32s2/src/pms/pro_iram0_3.rs
index 35a899d5a1..d65b6f38f8 100644
--- a/esp32s2/src/pms/pro_iram0_3.rs
+++ b/esp32s2/src/pms/pro_iram0_3.rs
@@ -87,43 +87,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTC FAST for IBUS access."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_spltaddr(&mut self) -> PRO_IRAM0_RTCFAST_SPLTADDR_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_SPLTADDR_W::new(self, 0)
     }
     #[doc = "Bit 11 - Setting to 1 grants IBUS permission to fetch RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_l_f(&mut self) -> PRO_IRAM0_RTCFAST_L_F_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_L_F_W::new(self, 11)
     }
     #[doc = "Bit 12 - Setting to 1 grants IBUS permission to read RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_l_r(&mut self) -> PRO_IRAM0_RTCFAST_L_R_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_L_R_W::new(self, 12)
     }
     #[doc = "Bit 13 - Setting to 1 grants IBUS permission to write RTC FAST low address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_l_w(&mut self) -> PRO_IRAM0_RTCFAST_L_W_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_L_W_W::new(self, 13)
     }
     #[doc = "Bit 14 - Setting to 1 grants IBUS permission to fetch RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_h_f(&mut self) -> PRO_IRAM0_RTCFAST_H_F_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_H_F_W::new(self, 14)
     }
     #[doc = "Bit 15 - Setting to 1 grants IBUS permission to read RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_h_r(&mut self) -> PRO_IRAM0_RTCFAST_H_R_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_H_R_W::new(self, 15)
     }
     #[doc = "Bit 16 - Setting to 1 grants IBUS permission to write RTC FAST high address region."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_rtcfast_h_w(&mut self) -> PRO_IRAM0_RTCFAST_H_W_W<PRO_IRAM0_3_SPEC> {
         PRO_IRAM0_RTCFAST_H_W_W::new(self, 16)
     }
diff --git a/esp32s2/src/pms/pro_iram0_4.rs b/esp32s2/src/pms/pro_iram0_4.rs
index 78ed32f508..117121ffb3 100644
--- a/esp32s2/src/pms/pro_iram0_4.rs
+++ b/esp32s2/src/pms/pro_iram0_4.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear signal for IBUS access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_ilg_clr(&mut self) -> PRO_IRAM0_ILG_CLR_W<PRO_IRAM0_4_SPEC> {
         PRO_IRAM0_ILG_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for IBUS access interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_iram0_ilg_en(&mut self) -> PRO_IRAM0_ILG_EN_W<PRO_IRAM0_4_SPEC> {
         PRO_IRAM0_ILG_EN_W::new(self, 1)
     }
diff --git a/esp32s2/src/pms/pro_trace_0.rs b/esp32s2/src/pms/pro_trace_0.rs
index 4baa9830ee..d692733b6f 100644
--- a/esp32s2/src/pms/pro_trace_0.rs
+++ b/esp32s2/src/pms/pro_trace_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks trace function permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_trace_lock(&mut self) -> PRO_TRACE_LOCK_W<PRO_TRACE_0_SPEC> {
         PRO_TRACE_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/pro_trace_1.rs b/esp32s2/src/pms/pro_trace_1.rs
index 2e7dc24165..7d4c63663f 100644
--- a/esp32s2/src/pms/pro_trace_1.rs
+++ b/esp32s2/src/pms/pro_trace_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 disables the trace memory function."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_trace_disable(&mut self) -> PRO_TRACE_DISABLE_W<PRO_TRACE_1_SPEC> {
         PRO_TRACE_DISABLE_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/sdio_0.rs b/esp32s2/src/pms/sdio_0.rs
index c31bb08edf..bc330937c6 100644
--- a/esp32s2/src/pms/sdio_0.rs
+++ b/esp32s2/src/pms/sdio_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks SDIO permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_lock(&mut self) -> SDIO_LOCK_W<SDIO_0_SPEC> {
         SDIO_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/pms/sdio_1.rs b/esp32s2/src/pms/sdio_1.rs
index 2fec3e8847..938a466e84 100644
--- a/esp32s2/src/pms/sdio_1.rs
+++ b/esp32s2/src/pms/sdio_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Setting to 1 disables the SDIO function."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_disable(&mut self) -> SDIO_DISABLE_W<SDIO_1_SPEC> {
         SDIO_DISABLE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rmt.rs b/esp32s2/src/rmt.rs
index cdeebd03e5..dd9269b8f0 100644
--- a/esp32s2/src/rmt.rs
+++ b/esp32s2/src/rmt.rs
@@ -59,14 +59,25 @@ impl RegisterBlock {
     pub const fn chconf0(&self, n: usize) -> &CHCONF0 {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(16).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(16)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x10..0x20 - Channel %s configure register 0"]
     #[inline(always)]
     pub fn chconf0_iter(&self) -> impl Iterator<Item = &CHCONF0> {
-        (0..4)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(16).add(8 * n).cast() })
+        (0..4).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(16)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x10 - Channel 0 configure register 0"]
     #[inline(always)]
@@ -93,14 +104,25 @@ impl RegisterBlock {
     pub const fn chconf1(&self, n: usize) -> &CHCONF1 {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(20).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(20)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x14..0x24 - Channel %s configure register 1"]
     #[inline(always)]
     pub fn chconf1_iter(&self) -> impl Iterator<Item = &CHCONF1> {
-        (0..4)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(20).add(8 * n).cast() })
+        (0..4).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(20)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x14 - Channel 0 configure register 1"]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/apb_conf.rs b/esp32s2/src/rmt/apb_conf.rs
index 109f134d2c..f9069f2311 100644
--- a/esp32s2/src/rmt/apb_conf.rs
+++ b/esp32s2/src/rmt/apb_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<APB_CONF_SPEC> {
         APB_FIFO_MASK_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<APB_CONF_SPEC> {
         MEM_TX_WRAP_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable the clock for RMT memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<APB_CONF_SPEC> {
         MEM_CLK_FORCE_ON_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to power down RMT memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<APB_CONF_SPEC> {
         MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<APB_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<APB_CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rmt/ch_rx_carrier_rm.rs b/esp32s2/src/rmt/ch_rx_carrier_rm.rs
index 44001ff925..0444342463 100644
--- a/esp32s2/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32s2/src/rmt/ch_rx_carrier_rm.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_low_thres(&mut self) -> CARRIER_LOW_THRES_W<CH_RX_CARRIER_RM_SPEC> {
         CARRIER_LOW_THRES_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_high_thres(&mut self) -> CARRIER_HIGH_THRES_W<CH_RX_CARRIER_RM_SPEC> {
         CARRIER_HIGH_THRES_W::new(self, 16)
     }
diff --git a/esp32s2/src/rmt/ch_tx_lim.rs b/esp32s2/src/rmt/ch_tx_lim.rs
index e3b56dc150..f7ee6c2294 100644
--- a/esp32s2/src/rmt/ch_tx_lim.rs
+++ b/esp32s2/src/rmt/ch_tx_lim.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lim(&mut self) -> TX_LIM_W<CH_TX_LIM_SPEC> {
         TX_LIM_W::new(self, 0)
     }
     #[doc = "Bits 9:18 - This register is used to configure the maximum loop count when tx_conti_mode is valid."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_loop_num(&mut self) -> TX_LOOP_NUM_W<CH_TX_LIM_SPEC> {
         TX_LOOP_NUM_W::new(self, 9)
     }
     #[doc = "Bit 19 - This register is the enabled bit for loop count."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_loop_cnt_en(&mut self) -> TX_LOOP_CNT_EN_W<CH_TX_LIM_SPEC> {
         TX_LOOP_CNT_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - This register is used to reset the loop count when tx_conti_mode is valid."]
     #[inline(always)]
-    #[must_use]
     pub fn loop_count_reset(&mut self) -> LOOP_COUNT_RESET_W<CH_TX_LIM_SPEC> {
         LOOP_COUNT_RESET_W::new(self, 20)
     }
diff --git a/esp32s2/src/rmt/chcarrier_duty.rs b/esp32s2/src/rmt/chcarrier_duty.rs
index 1aedd08615..a45cf0e6ed 100644
--- a/esp32s2/src/rmt/chcarrier_duty.rs
+++ b/esp32s2/src/rmt/chcarrier_duty.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_low(&mut self) -> CARRIER_LOW_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_LOW_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_high(&mut self) -> CARRIER_HIGH_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_HIGH_W::new(self, 16)
     }
diff --git a/esp32s2/src/rmt/chconf0.rs b/esp32s2/src/rmt/chconf0.rs
index 85440897af..64887fc6cd 100644
--- a/esp32s2/src/rmt/chconf0.rs
+++ b/esp32s2/src/rmt/chconf0.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn div_cnt(&mut self) -> DIV_CNT_W<CHCONF0_SPEC> {
         DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bits 8:23 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_thres(&mut self) -> IDLE_THRES_W<CHCONF0_SPEC> {
         IDLE_THRES_W::new(self, 8)
     }
     #[doc = "Bits 24:26 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_size(&mut self) -> MEM_SIZE_W<CHCONF0_SPEC> {
         MEM_SIZE_W::new(self, 24)
     }
     #[doc = "Bit 27 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_eff_en(&mut self) -> CARRIER_EFF_EN_W<CHCONF0_SPEC> {
         CARRIER_EFF_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_en(&mut self) -> CARRIER_EN_W<CHCONF0_SPEC> {
         CARRIER_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<CHCONF0_SPEC> {
         CARRIER_OUT_LV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rmt/chconf1.rs b/esp32s2/src/rmt/chconf1.rs
index 8b3a6bc071..b96919c527 100644
--- a/esp32s2/src/rmt/chconf1.rs
+++ b/esp32s2/src/rmt/chconf1.rs
@@ -130,85 +130,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<CHCONF1_SPEC> {
         TX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_en(&mut self) -> RX_EN_W<CHCONF1_SPEC> {
         RX_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_wr_rst(&mut self) -> MEM_WR_RST_W<CHCONF1_SPEC> {
         MEM_WR_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_rd_rst(&mut self) -> MEM_RD_RST_W<CHCONF1_SPEC> {
         MEM_RD_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<CHCONF1_SPEC> {
         APB_MEM_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: Transmitter is using the ram."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_owner(&mut self) -> MEM_OWNER_W<CHCONF1_SPEC> {
         MEM_OWNER_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_conti_mode(&mut self) -> TX_CONTI_MODE_W<CHCONF1_SPEC> {
         TX_CONTI_MODE_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the receive filter's enable bit for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_en(&mut self) -> RX_FILTER_EN_W<CHCONF1_SPEC> {
         RX_FILTER_EN_W::new(self, 7)
     }
     #[doc = "Bits 8:15 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_thres(&mut self) -> RX_FILTER_THRES_W<CHCONF1_SPEC> {
         RX_FILTER_THRES_W::new(self, 8)
     }
     #[doc = "Bit 16 - Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn chk_rx_carrier_en(&mut self) -> CHK_RX_CARRIER_EN_W<CHCONF1_SPEC> {
         CHK_RX_CARRIER_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - This bit is used to select the base clock for CHANNEL%s. 1'h1: clk_apb 1'h0:clk_ref"]
     #[inline(always)]
-    #[must_use]
     pub fn ref_always_on(&mut self) -> REF_ALWAYS_ON_W<CHCONF1_SPEC> {
         REF_ALWAYS_ON_W::new(self, 17)
     }
     #[doc = "Bit 18 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_lv(&mut self) -> IDLE_OUT_LV_W<CHCONF1_SPEC> {
         IDLE_OUT_LV_W::new(self, 18)
     }
     #[doc = "Bit 19 - This is the output enable-control bit for CHANNEL%s in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_en(&mut self) -> IDLE_OUT_EN_W<CHCONF1_SPEC> {
         IDLE_OUT_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to stop the transmitter of CHANNEL%s sending data out."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop(&mut self) -> TX_STOP_W<CHCONF1_SPEC> {
         TX_STOP_W::new(self, 20)
     }
diff --git a/esp32s2/src/rmt/chdata.rs b/esp32s2/src/rmt/chdata.rs
index af61e60c88..c7f142c6fa 100644
--- a/esp32s2/src/rmt/chdata.rs
+++ b/esp32s2/src/rmt/chdata.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The read and write data register for CHANNEL%s by apb fifo access."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<CHDATA_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s2/src/rmt/date.rs b/esp32s2/src/rmt/date.rs
index c74cff7bb3..44312f496d 100644
--- a/esp32s2/src/rmt/date.rs
+++ b/esp32s2/src/rmt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rmt/int_clr.rs b/esp32s2/src/rmt/int_clr.rs
index 80ec8bd100..f49be7f37f 100644
--- a/esp32s2/src/rmt/int_clr.rs
+++ b/esp32s2/src/rmt/int_clr.rs
@@ -21,7 +21,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -29,25 +28,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the CH0_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to clear the CH1_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
     #[doc = "Bit 6 - Set this bit to clear the CH2_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 6)
     }
     #[doc = "Bit 9 - Set this bit to clear the CH3_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 9)
     }
@@ -55,7 +50,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -63,25 +57,21 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to clear the CH0_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 1)
     }
     #[doc = "Bit 4 - Set this bit to clear the CH1_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to clear the CH2_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 7)
     }
     #[doc = "Bit 10 - Set this bit to clear the CH3_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 10)
     }
@@ -89,7 +79,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -97,25 +86,21 @@ impl W {
     }
     #[doc = "Bit 2 - Set this bit to clear the CH0_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 2)
     }
     #[doc = "Bit 5 - Set this bit to clear the CH1_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 5)
     }
     #[doc = "Bit 8 - Set this bit to clear the CH2_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 8)
     }
     #[doc = "Bit 11 - Set this bit to clear the CH3_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
         CH_ERR_W::new(self, 11)
     }
@@ -123,7 +108,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -131,25 +115,21 @@ impl W {
     }
     #[doc = "Bit 12 - Set this bit to clear the CH0_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the CH1_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the CH2_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the CH3_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 15)
     }
@@ -157,7 +137,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -165,25 +144,21 @@ impl W {
     }
     #[doc = "Bit 16 - Set this bit to clear the CH0_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the CH1_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the CH2_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear the CH3_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 19)
     }
diff --git a/esp32s2/src/rmt/int_ena.rs b/esp32s2/src/rmt/int_ena.rs
index d153259605..b125409176 100644
--- a/esp32s2/src/rmt/int_ena.rs
+++ b/esp32s2/src/rmt/int_ena.rs
@@ -231,7 +231,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -239,25 +238,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enabled bit for CH0_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 3 - The interrupt enabled bit for CH1_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
     #[doc = "Bit 6 - The interrupt enabled bit for CH2_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 6)
     }
     #[doc = "Bit 9 - The interrupt enabled bit for CH3_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 9)
     }
@@ -265,7 +260,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -273,25 +267,21 @@ impl W {
     }
     #[doc = "Bit 1 - The interrupt enabled bit for CH0_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 1)
     }
     #[doc = "Bit 4 - The interrupt enabled bit for CH1_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 4)
     }
     #[doc = "Bit 7 - The interrupt enabled bit for CH2_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 7)
     }
     #[doc = "Bit 10 - The interrupt enabled bit for CH3_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 10)
     }
@@ -299,7 +289,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -307,25 +296,21 @@ impl W {
     }
     #[doc = "Bit 2 - The interrupt enabled bit for CH0_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 2)
     }
     #[doc = "Bit 5 - The interrupt enabled bit for CH1_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 5)
     }
     #[doc = "Bit 8 - The interrupt enabled bit for CH2_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 8)
     }
     #[doc = "Bit 11 - The interrupt enabled bit for CH3_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
         CH_ERR_W::new(self, 11)
     }
@@ -333,7 +318,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -341,25 +325,21 @@ impl W {
     }
     #[doc = "Bit 12 - The interrupt enabled bit for CH0_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enabled bit for CH1_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enabled bit for CH2_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enabled bit for CH3_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 15)
     }
@@ -367,7 +347,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -375,25 +354,21 @@ impl W {
     }
     #[doc = "Bit 16 - The interrupt enabled bit for CH0_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enabled bit for CH1_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt enabled bit for CH2_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt enabled bit for CH3_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 19)
     }
diff --git a/esp32s2/src/rmt/ref_cnt_rst.rs b/esp32s2/src/rmt/ref_cnt_rst.rs
index bcecdd7494..46d0a4b0b6 100644
--- a/esp32s2/src/rmt/ref_cnt_rst.rs
+++ b/esp32s2/src/rmt/ref_cnt_rst.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This register is used to reset the clock divider of CHANNEL0."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<REF_CNT_RST_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1 - This register is used to reset the clock divider of CHANNEL1."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<REF_CNT_RST_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2 - This register is used to reset the clock divider of CHANNEL2."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<REF_CNT_RST_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3 - This register is used to reset the clock divider of CHANNEL3."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<REF_CNT_RST_SPEC> {
         CH3_W::new(self, 3)
     }
diff --git a/esp32s2/src/rmt/tx_sim.rs b/esp32s2/src/rmt/tx_sim.rs
index edada0cb4d..4d0bb2f875 100644
--- a/esp32s2/src/rmt/tx_sim.rs
+++ b/esp32s2/src/rmt/tx_sim.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<TX_SIM_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<TX_SIM_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<TX_SIM_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<TX_SIM_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4 - This register is used to enable multiple of channels to start sending data synchronously."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<TX_SIM_SPEC> {
         EN_W::new(self, 4)
     }
diff --git a/esp32s2/src/rsa/constant_time.rs b/esp32s2/src/rsa/constant_time.rs
index 625cb661fd..cf167d9094 100644
--- a/esp32s2/src/rsa/constant_time.rs
+++ b/esp32s2/src/rsa/constant_time.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default)."]
     #[inline(always)]
-    #[must_use]
     pub fn constant_time(&mut self) -> CONSTANT_TIME_W<CONSTANT_TIME_SPEC> {
         CONSTANT_TIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/date.rs b/esp32s2/src/rsa/date.rs
index fe9eddb3db..92924ef8d7 100644
--- a/esp32s2/src/rsa/date.rs
+++ b/esp32s2/src/rsa/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/int_clr.rs b/esp32s2/src/rsa/int_clr.rs
index 5d3111f490..e039649cf9 100644
--- a/esp32s2/src/rsa/int_clr.rs
+++ b/esp32s2/src/rsa/int_clr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to clear the RSA interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
         INT_CLR_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/int_ena.rs b/esp32s2/src/rsa/int_ena.rs
index f17e2caca5..be0c1bae4e 100644
--- a/esp32s2/src/rsa/int_ena.rs
+++ b/esp32s2/src/rsa/int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
         INT_ENA_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/m_prime.rs b/esp32s2/src/rsa/m_prime.rs
index 2768d780ae..568621e680 100644
--- a/esp32s2/src/rsa/m_prime.rs
+++ b/esp32s2/src/rsa/m_prime.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores M'."]
     #[inline(always)]
-    #[must_use]
     pub fn m_prime(&mut self) -> M_PRIME_W<M_PRIME_SPEC> {
         M_PRIME_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/mode.rs b/esp32s2/src/rsa/mode.rs
index aff4cd5476..c435ccb4af 100644
--- a/esp32s2/src/rsa/mode.rs
+++ b/esp32s2/src/rsa/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Stores the mode of modular exponentiation."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/modexp_start.rs b/esp32s2/src/rsa/modexp_start.rs
index 5906851c86..d908bfa62c 100644
--- a/esp32s2/src/rsa/modexp_start.rs
+++ b/esp32s2/src/rsa/modexp_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MODEXP_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the modular exponentiation."]
     #[inline(always)]
-    #[must_use]
     pub fn modexp_start(&mut self) -> MODEXP_START_W<MODEXP_START_SPEC> {
         MODEXP_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/modmult_start.rs b/esp32s2/src/rsa/modmult_start.rs
index 7528310bac..5083043494 100644
--- a/esp32s2/src/rsa/modmult_start.rs
+++ b/esp32s2/src/rsa/modmult_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MODMULT_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the modular multiplication."]
     #[inline(always)]
-    #[must_use]
     pub fn modmult_start(&mut self) -> MODMULT_START_W<MODMULT_START_SPEC> {
         MODMULT_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/mult_start.rs b/esp32s2/src/rsa/mult_start.rs
index 001e935b5d..613f74686b 100644
--- a/esp32s2/src/rsa/mult_start.rs
+++ b/esp32s2/src/rsa/mult_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MULT_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the multiplication."]
     #[inline(always)]
-    #[must_use]
     pub fn mult_start(&mut self) -> MULT_START_W<MULT_START_SPEC> {
         MULT_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/search_enable.rs b/esp32s2/src/rsa/search_enable.rs
index 467bdc4429..de4a5c3b8c 100644
--- a/esp32s2/src/rsa/search_enable.rs
+++ b/esp32s2/src/rsa/search_enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default)."]
     #[inline(always)]
-    #[must_use]
     pub fn search_enable(&mut self) -> SEARCH_ENABLE_W<SEARCH_ENABLE_SPEC> {
         SEARCH_ENABLE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rsa/search_pos.rs b/esp32s2/src/rsa/search_pos.rs
index 84816149aa..b44e170e6c 100644
--- a/esp32s2/src/rsa/search_pos.rs
+++ b/esp32s2/src/rsa/search_pos.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - Is used to configure the starting address when the acceleration option of search is used."]
     #[inline(always)]
-    #[must_use]
     pub fn search_pos(&mut self) -> SEARCH_POS_W<SEARCH_POS_SPEC> {
         SEARCH_POS_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/ana_conf.rs b/esp32s2/src/rtc_cntl/ana_conf.rs
index 6bc2ac22ea..b85651898a 100644
--- a/esp32s2/src/rtc_cntl/ana_conf.rs
+++ b/esp32s2/src/rtc_cntl/ana_conf.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 18 - SLEEP_I2CPOR force pd"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_reset_por_force_pd(&mut self) -> I2C_RESET_POR_FORCE_PD_W<ANA_CONF_SPEC> {
         I2C_RESET_POR_FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - SLEEP_I2CPOR force pu"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_reset_por_force_pu(&mut self) -> I2C_RESET_POR_FORCE_PU_W<ANA_CONF_SPEC> {
         I2C_RESET_POR_FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to enable a reset when the system detects a glitch."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_rst_en(&mut self) -> GLITCH_RST_EN_W<ANA_CONF_SPEC> {
         GLITCH_RST_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Sets this bit to FPD the SAR_I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_force_pd(&mut self) -> SAR_I2C_FORCE_PD_W<ANA_CONF_SPEC> {
         SAR_I2C_FORCE_PD_W::new(self, 21)
     }
     #[doc = "Bit 22 - Sets this bit to FPU the SAR_I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_force_pu(&mut self) -> SAR_I2C_FORCE_PU_W<ANA_CONF_SPEC> {
         SAR_I2C_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 23 - Sets this bit to FPD the PLLA."]
     #[inline(always)]
-    #[must_use]
     pub fn plla_force_pd(&mut self) -> PLLA_FORCE_PD_W<ANA_CONF_SPEC> {
         PLLA_FORCE_PD_W::new(self, 23)
     }
     #[doc = "Bit 24 - Sets this bit to FPU the PLLA."]
     #[inline(always)]
-    #[must_use]
     pub fn plla_force_pu(&mut self) -> PLLA_FORCE_PU_W<ANA_CONF_SPEC> {
         PLLA_FORCE_PU_W::new(self, 24)
     }
     #[doc = "Bit 25 - start BBPLL calibration during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<ANA_CONF_SPEC> {
         BBPLL_CAL_SLP_START_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: PVTMON power up , otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<ANA_CONF_SPEC> {
         PVTMON_PU_W::new(self, 26)
     }
     #[doc = "Bit 27 - 1: TXRF_I2C power up , otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<ANA_CONF_SPEC> {
         TXRF_I2C_PU_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: RFRX_PBUS power up , otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<ANA_CONF_SPEC> {
         RFRX_PBUS_PU_W::new(self, 28)
     }
     #[doc = "Bit 30 - 1: CKGEN_I2C power up , otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<ANA_CONF_SPEC> {
         CKGEN_I2C_PU_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1. PLL_I2C power up ,otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<ANA_CONF_SPEC> {
         PLL_I2C_PU_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/bias_conf.rs b/esp32s2/src/rtc_cntl/bias_conf.rs
index 5939459119..7636bd9195 100644
--- a/esp32s2/src/rtc_cntl/bias_conf.rs
+++ b/esp32s2/src/rtc_cntl/bias_conf.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - open bias buf when system in active"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_idle(&mut self) -> BIAS_BUF_IDLE_W<BIAS_CONF_SPEC> {
         BIAS_BUF_IDLE_W::new(self, 10)
     }
     #[doc = "Bit 11 - open bias buf when rtc in wakeup"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_wake(&mut self) -> BIAS_BUF_WAKE_W<BIAS_CONF_SPEC> {
         BIAS_BUF_WAKE_W::new(self, 11)
     }
     #[doc = "Bit 12 - open bias buf when rtc in deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_deep_slp(&mut self) -> BIAS_BUF_DEEP_SLP_W<BIAS_CONF_SPEC> {
         BIAS_BUF_DEEP_SLP_W::new(self, 12)
     }
     #[doc = "Bit 13 - open bias buf when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_monitor(&mut self) -> BIAS_BUF_MONITOR_W<BIAS_CONF_SPEC> {
         BIAS_BUF_MONITOR_W::new(self, 13)
     }
     #[doc = "Bit 14 - xpd cur when rtc in sleep_state"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_cur_deep_slp(&mut self) -> PD_CUR_DEEP_SLP_W<BIAS_CONF_SPEC> {
         PD_CUR_DEEP_SLP_W::new(self, 14)
     }
     #[doc = "Bit 15 - xpd cur when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_cur_monitor(&mut self) -> PD_CUR_MONITOR_W<BIAS_CONF_SPEC> {
         PD_CUR_MONITOR_W::new(self, 15)
     }
     #[doc = "Bit 16 - bias_sleep when rtc in sleep_state"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_sleep_deep_slp(&mut self) -> BIAS_SLEEP_DEEP_SLP_W<BIAS_CONF_SPEC> {
         BIAS_SLEEP_DEEP_SLP_W::new(self, 16)
     }
     #[doc = "Bit 17 - bias_sleep when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_sleep_monitor(&mut self) -> BIAS_SLEEP_MONITOR_W<BIAS_CONF_SPEC> {
         BIAS_SLEEP_MONITOR_W::new(self, 17)
     }
     #[doc = "Bits 18:21 - DBG_ATTEN when rtc in sleep state"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten_deep_slp(&mut self) -> DBG_ATTEN_DEEP_SLP_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_DEEP_SLP_W::new(self, 18)
     }
     #[doc = "Bits 22:25 - DBG_ATTEN when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten_monitor(&mut self) -> DBG_ATTEN_MONITOR_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_MONITOR_W::new(self, 22)
     }
     #[doc = "Bit 26 - ENB_SCK_XTAL"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_sck_xtal(&mut self) -> ENB_SCK_XTAL_W<BIAS_CONF_SPEC> {
         ENB_SCK_XTAL_W::new(self, 26)
     }
     #[doc = "Bit 27 - INC_HEARTBEAT_REFRESH"]
     #[inline(always)]
-    #[must_use]
     pub fn inc_heartbeat_refresh(&mut self) -> INC_HEARTBEAT_REFRESH_W<BIAS_CONF_SPEC> {
         INC_HEARTBEAT_REFRESH_W::new(self, 27)
     }
     #[doc = "Bit 28 - DEC_HEARTBEAT_PERIOD"]
     #[inline(always)]
-    #[must_use]
     pub fn dec_heartbeat_period(&mut self) -> DEC_HEARTBEAT_PERIOD_W<BIAS_CONF_SPEC> {
         DEC_HEARTBEAT_PERIOD_W::new(self, 28)
     }
     #[doc = "Bit 29 - INC_HEARTBEAT_PERIOD"]
     #[inline(always)]
-    #[must_use]
     pub fn inc_heartbeat_period(&mut self) -> INC_HEARTBEAT_PERIOD_W<BIAS_CONF_SPEC> {
         INC_HEARTBEAT_PERIOD_W::new(self, 29)
     }
     #[doc = "Bit 30 - DEC_HEARTBEAT_WIDTH"]
     #[inline(always)]
-    #[must_use]
     pub fn dec_heartbeat_width(&mut self) -> DEC_HEARTBEAT_WIDTH_W<BIAS_CONF_SPEC> {
         DEC_HEARTBEAT_WIDTH_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_bias_i2c(&mut self) -> RST_BIAS_I2C_W<BIAS_CONF_SPEC> {
         RST_BIAS_I2C_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/brown_out.rs b/esp32s2/src/rtc_cntl/brown_out.rs
index 766e5a4d04..5f45ce9093 100644
--- a/esp32s2/src/rtc_cntl/brown_out.rs
+++ b/esp32s2/src/rtc_cntl/brown_out.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enables the brown_out2 to initiate a chip reset."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out2_ena(&mut self) -> BROWN_OUT2_ENA_W<BROWN_OUT_SPEC> {
         BROWN_OUT2_ENA_W::new(self, 0)
     }
     #[doc = "Bits 4:13 - Configures the waiting cycle before sending an interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_wait(&mut self) -> INT_WAIT_W<BROWN_OUT_SPEC> {
         INT_WAIT_W::new(self, 4)
     }
     #[doc = "Bit 14 - Set this bit to enable PD the flash when a brown-out happens."]
     #[inline(always)]
-    #[must_use]
     pub fn close_flash_ena(&mut self) -> CLOSE_FLASH_ENA_W<BROWN_OUT_SPEC> {
         CLOSE_FLASH_ENA_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable PD the RF circuits when a brown-out happens."]
     #[inline(always)]
-    #[must_use]
     pub fn pd_rf_ena(&mut self) -> PD_RF_ENA_W<BROWN_OUT_SPEC> {
         PD_RF_ENA_W::new(self, 15)
     }
     #[doc = "Bits 16:25 - Configures the waiting cycle before the reset after a brown-out."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_wait(&mut self) -> RST_WAIT_W<BROWN_OUT_SPEC> {
         RST_WAIT_W::new(self, 16)
     }
     #[doc = "Bit 26 - Enables to reset brown-out."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_ena(&mut self) -> RST_ENA_W<BROWN_OUT_SPEC> {
         RST_ENA_W::new(self, 26)
     }
     #[doc = "Bit 27 - Selects the reset type when a brown-out happens. 1: chip reset 0: system reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_sel(&mut self) -> RST_SEL_W<BROWN_OUT_SPEC> {
         RST_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - Clears the brown-out counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_clr(&mut self) -> CNT_CLR_W<BROWN_OUT_SPEC> {
         CNT_CLR_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable brown-out detection."]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<BROWN_OUT_SPEC> {
         ENA_W::new(self, 30)
     }
diff --git a/esp32s2/src/rtc_cntl/clk_conf.rs b/esp32s2/src/rtc_cntl/clk_conf.rs
index f73c0fc324..35777540b9 100644
--- a/esp32s2/src/rtc_cntl/clk_conf.rs
+++ b/esp32s2/src/rtc_cntl/clk_conf.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<CLK_CONF_SPEC> {
         CK8M_DIV_SEL_VLD_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
         CK8M_DIV_W::new(self, 4)
     }
     #[doc = "Bit 6 - Set this bit to disable CK8M and CK8M_D256_OUT."]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
         ENB_CK8M_W::new(self, 6)
     }
     #[doc = "Bit 7 - Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256."]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
         ENB_CK8M_DIV_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enable CK_XTAL_32K clock for the digital core."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
         DIG_XTAL32K_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable CK8M_D256_OUT clock for the digital core."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_D256_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to enable 8 MHz clock for the digital core."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_EN_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
         CK8M_DIV_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Set this bit to force no gating to crystal during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         XTAL_FORCE_NOGATING_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to disable force gating to 8 MHz crystal during sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         CK8M_FORCE_NOGATING_W::new(self, 16)
     }
     #[doc = "Bits 17:24 - CK8M_DFREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
         CK8M_DFREQ_W::new(self, 17)
     }
     #[doc = "Bit 25 - Set this bit to FPD the 8 MHz clock."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PD_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to FPU the 8 MHz clock."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PU_W::new(self, 26)
     }
     #[doc = "Bit 29 - Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M."]
     #[inline(always)]
-    #[must_use]
     pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         FAST_CLK_RTC_SEL_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256."]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         ANA_CLK_RTC_SEL_W::new(self, 30)
     }
diff --git a/esp32s2/src/rtc_cntl/cocpu_ctrl.rs b/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
index bb561a9702..10a2c390b1 100644
--- a/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
@@ -106,61 +106,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ULP-RISCV clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<COCPU_CTRL_SPEC> {
         COCPU_CLK_FO_W::new(self, 0)
     }
     #[doc = "Bits 1:6 - Time from ULP-RISCV startup to pull down reset"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<COCPU_CTRL_SPEC> {
         COCPU_START_2_RESET_DIS_W::new(self, 1)
     }
     #[doc = "Bits 7:12 - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<COCPU_CTRL_SPEC> {
         COCPU_START_2_INTR_EN_W::new(self, 7)
     }
     #[doc = "Bit 13 - Shut down ULP-RISCV"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_W::new(self, 13)
     }
     #[doc = "Bits 14:21 - Time from shut down ULP-RISCV to disable clock"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_2_CLK_DIS_W::new(self, 14)
     }
     #[doc = "Bit 22 - This bit is used to reset ULP-RISCV"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_RESET_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - 0: select ULP-RISCV. 1: select ULP-FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<COCPU_CTRL_SPEC> {
         COCPU_SEL_W::new(self, 23)
     }
     #[doc = "Bit 24 - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<COCPU_CTRL_SPEC> {
         COCPU_DONE_FORCE_W::new(self, 24)
     }
     #[doc = "Bit 25 - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_done(&mut self) -> COCPU_DONE_W<COCPU_CTRL_SPEC> {
         COCPU_DONE_W::new(self, 25)
     }
     #[doc = "Bit 26 - Trigger ULP-RISCV register interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<COCPU_CTRL_SPEC> {
         COCPU_SW_INT_TRIGGER_W::new(self, 26)
     }
diff --git a/esp32s2/src/rtc_cntl/cpu_period_conf.rs b/esp32s2/src/rtc_cntl/cpu_period_conf.rs
index 3381b16425..04edff2f76 100644
--- a/esp32s2/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32s2/src/rtc_cntl/cpu_period_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
-    #[must_use]
     pub fn cpusel_conf(&mut self) -> CPUSEL_CONF_W<CPU_PERIOD_CONF_SPEC> {
         CPUSEL_CONF_W::new(self, 29)
     }
     #[doc = "Bits 30:31"]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PERIOD_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 30)
     }
diff --git a/esp32s2/src/rtc_cntl/date.rs b/esp32s2/src/rtc_cntl/date.rs
index fb6d0a73f3..2e840166f4 100644
--- a/esp32s2/src/rtc_cntl/date.rs
+++ b/esp32s2/src/rtc_cntl/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
-    #[must_use]
     pub fn cntl_date(&mut self) -> CNTL_DATE_W<DATE_SPEC> {
         CNTL_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/dig_iso.rs b/esp32s2/src/rtc_cntl/dig_iso.rs
index 4ca30adc50..80f13cbbd5 100644
--- a/esp32s2/src/rtc_cntl/dig_iso.rs
+++ b/esp32s2/src/rtc_cntl/dig_iso.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn force_off(&mut self) -> FORCE_OFF_W<DIG_ISO_SPEC> {
         FORCE_OFF_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn force_on(&mut self) -> FORCE_ON_W<DIG_ISO_SPEC> {
         FORCE_ON_W::new(self, 8)
     }
     #[doc = "Bit 10 - Se this bit to clear the auto-hold enabler for the digital GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn clr_dg_pad_autohold(&mut self) -> CLR_DG_PAD_AUTOHOLD_W<DIG_ISO_SPEC> {
         CLR_DG_PAD_AUTOHOLD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Se this bit to allow the digital GPIOs to enter the autohold status."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_autohold_en(&mut self) -> DG_PAD_AUTOHOLD_EN_W<DIG_ISO_SPEC> {
         DG_PAD_AUTOHOLD_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to disable the force isolation to the digital GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_noiso(&mut self) -> DG_PAD_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_NOISO_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to force isolate the digital GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_iso(&mut self) -> DG_PAD_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_ISO_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit the force unhold the digital GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_unhold(&mut self) -> DG_PAD_FORCE_UNHOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_UNHOLD_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit the force hold the digital GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_hold(&mut self) -> DG_PAD_FORCE_HOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_HOLD_W::new(self, 15)
     }
     #[doc = "Bit 16 - ROM force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_iso(&mut self) -> ROM0_FORCE_ISO_W<DIG_ISO_SPEC> {
         ROM0_FORCE_ISO_W::new(self, 16)
     }
     #[doc = "Bit 17 - ROM force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_noiso(&mut self) -> ROM0_FORCE_NOISO_W<DIG_ISO_SPEC> {
         ROM0_FORCE_NOISO_W::new(self, 17)
     }
     #[doc = "Bit 18 - internal SRAM 0 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_iso(&mut self) -> INTER_RAM0_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM0_FORCE_ISO_W::new(self, 18)
     }
     #[doc = "Bit 19 - internal SRAM 0 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_noiso(&mut self) -> INTER_RAM0_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM0_FORCE_NOISO_W::new(self, 19)
     }
     #[doc = "Bit 20 - internal SRAM 1 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_iso(&mut self) -> INTER_RAM1_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM1_FORCE_ISO_W::new(self, 20)
     }
     #[doc = "Bit 21 - internal SRAM 1 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_noiso(&mut self) -> INTER_RAM1_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM1_FORCE_NOISO_W::new(self, 21)
     }
     #[doc = "Bit 22 - internal SRAM 2 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_iso(&mut self) -> INTER_RAM2_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM2_FORCE_ISO_W::new(self, 22)
     }
     #[doc = "Bit 23 - internal SRAM 2 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_noiso(&mut self) -> INTER_RAM2_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM2_FORCE_NOISO_W::new(self, 23)
     }
     #[doc = "Bit 24 - internal SRAM 3 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_iso(&mut self) -> INTER_RAM3_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM3_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25 - internal SRAM 3 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_noiso(&mut self) -> INTER_RAM3_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM3_FORCE_NOISO_W::new(self, 25)
     }
     #[doc = "Bit 26 - internal SRAM 4 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_iso(&mut self) -> INTER_RAM4_FORCE_ISO_W<DIG_ISO_SPEC> {
         INTER_RAM4_FORCE_ISO_W::new(self, 26)
     }
     #[doc = "Bit 27 - internal SRAM 4 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_noiso(&mut self) -> INTER_RAM4_FORCE_NOISO_W<DIG_ISO_SPEC> {
         INTER_RAM4_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to force isolate the Wi-Fi circuits."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_iso(&mut self) -> WIFI_FORCE_ISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_ISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to disable the force isolation to the Wi-Fi circuits."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_noiso(&mut self) -> WIFI_FORCE_NOISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_NOISO_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to force isolate the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_iso(&mut self) -> DG_WRAP_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_ISO_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to disable the force isolation to the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_noiso(&mut self) -> DG_WRAP_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_NOISO_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/dig_pad_hold.rs b/esp32s2/src/rtc_cntl/dig_pad_hold.rs
index b903fec7bb..3643a28bd8 100644
--- a/esp32s2/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32s2/src/rtc_cntl/dig_pad_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO)."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_pad_hold(&mut self) -> DIG_PAD_HOLD_W<DIG_PAD_HOLD_SPEC> {
         DIG_PAD_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/dig_pwc.rs b/esp32s2/src/rtc_cntl/dig_pwc.rs
index e10a7018e7..d05635522b 100644
--- a/esp32s2/src/rtc_cntl/dig_pwc.rs
+++ b/esp32s2/src/rtc_cntl/dig_pwc.rs
@@ -304,175 +304,146 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - Set this bit to FPD the memories in the digital system in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to FPU the memories in the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 5 - ROM force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_pd(&mut self) -> ROM0_FORCE_PD_W<DIG_PWC_SPEC> {
         ROM0_FORCE_PD_W::new(self, 5)
     }
     #[doc = "Bit 6 - ROM force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_force_pu(&mut self) -> ROM0_FORCE_PU_W<DIG_PWC_SPEC> {
         ROM0_FORCE_PU_W::new(self, 6)
     }
     #[doc = "Bit 7 - internal SRAM 0 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_pd(&mut self) -> INTER_RAM0_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM0_FORCE_PD_W::new(self, 7)
     }
     #[doc = "Bit 8 - internal SRAM 0 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_force_pu(&mut self) -> INTER_RAM0_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM0_FORCE_PU_W::new(self, 8)
     }
     #[doc = "Bit 9 - internal SRAM 1 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_pd(&mut self) -> INTER_RAM1_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM1_FORCE_PD_W::new(self, 9)
     }
     #[doc = "Bit 10 - internal SRAM 1 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_force_pu(&mut self) -> INTER_RAM1_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM1_FORCE_PU_W::new(self, 10)
     }
     #[doc = "Bit 11 - internal SRAM 2 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_pd(&mut self) -> INTER_RAM2_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM2_FORCE_PD_W::new(self, 11)
     }
     #[doc = "Bit 12 - internal SRAM 2 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_force_pu(&mut self) -> INTER_RAM2_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM2_FORCE_PU_W::new(self, 12)
     }
     #[doc = "Bit 13 - internal SRAM 3 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_pd(&mut self) -> INTER_RAM3_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM3_FORCE_PD_W::new(self, 13)
     }
     #[doc = "Bit 14 - internal SRAM 3 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_force_pu(&mut self) -> INTER_RAM3_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM3_FORCE_PU_W::new(self, 14)
     }
     #[doc = "Bit 15 - internal SRAM 4 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_pd(&mut self) -> INTER_RAM4_FORCE_PD_W<DIG_PWC_SPEC> {
         INTER_RAM4_FORCE_PD_W::new(self, 15)
     }
     #[doc = "Bit 16 - internal SRAM 4 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_force_pu(&mut self) -> INTER_RAM4_FORCE_PU_W<DIG_PWC_SPEC> {
         INTER_RAM4_FORCE_PU_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to FPD the Wi-Fi circuit."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pd(&mut self) -> WIFI_FORCE_PD_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PD_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to FPU the Wi-Fi circuit."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pu(&mut self) -> WIFI_FORCE_PU_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PU_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to FPD the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PD_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to FPD the DC-DC convertor in the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PU_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to FPD the DC-DC convertor in the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_dcdc_force_pd(&mut self) -> DG_DCDC_FORCE_PD_W<DIG_PWC_SPEC> {
         DG_DCDC_FORCE_PD_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to FPU the DC-DC convertor in the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_dcdc_force_pu(&mut self) -> DG_DCDC_FORCE_PU_W<DIG_PWC_SPEC> {
         DG_DCDC_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to enable PD for the DC-DC convertor in the digital system."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_dcdc_pd_en(&mut self) -> DG_DCDC_PD_EN_W<DIG_PWC_SPEC> {
         DG_DCDC_PD_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - enable power down ROM in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn rom0_pd_en(&mut self) -> ROM0_PD_EN_W<DIG_PWC_SPEC> {
         ROM0_PD_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - enable power down internal SRAM 0 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram0_pd_en(&mut self) -> INTER_RAM0_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM0_PD_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - enable power down internal SRAM 1 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram1_pd_en(&mut self) -> INTER_RAM1_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM1_PD_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - enable power down internal SRAM 2 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram2_pd_en(&mut self) -> INTER_RAM2_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM2_PD_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - enable power down internal SRAM 3 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram3_pd_en(&mut self) -> INTER_RAM3_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM3_PD_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - enable power down internal SRAM 4 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn inter_ram4_pd_en(&mut self) -> INTER_RAM4_PD_EN_W<DIG_PWC_SPEC> {
         INTER_RAM4_PD_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable PD for the Wi-Fi circuit in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_pd_en(&mut self) -> WIFI_PD_EN_W<DIG_PWC_SPEC> {
         WIFI_PD_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable PD for the digital system in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<DIG_PWC_SPEC> {
         DG_WRAP_PD_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/ext_wakeup1.rs b/esp32s2/src/rtc_cntl/ext_wakeup1.rs
index c286fa86a3..2f32a3de7b 100644
--- a/esp32s2/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32s2/src/rtc_cntl/ext_wakeup1.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Selects a RTC GPIO to be the EXT1 wakeup source."]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP1_SPEC> {
         SEL_W::new(self, 0)
     }
     #[doc = "Bit 22 - Clears the EXT1 wakeup status."]
     #[inline(always)]
-    #[must_use]
     pub fn status_clr(&mut self) -> STATUS_CLR_W<EXT_WAKEUP1_SPEC> {
         STATUS_CLR_W::new(self, 22)
     }
diff --git a/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs b/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
index d49ef346ba..c091db1082 100644
--- a/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - Set this bit to enable the GPIO wakeup event filter."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_wakeup_filter(&mut self) -> GPIO_WAKEUP_FILTER_W<EXT_WAKEUP_CONF_SPEC> {
         GPIO_WAKEUP_FILTER_W::new(self, 29)
     }
     #[doc = "Bit 30 - 0: external wakeup 0 at low level 1: external wakeup 0 at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup0_lv(&mut self) -> EXT_WAKEUP0_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP0_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - 0: external wakeup 1 at low level 1: external wakeup 1 at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup1_lv(&mut self) -> EXT_WAKEUP1_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP1_LV_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/ext_xtl_conf.rs b/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
index f2b1aa1b3b..d42bf4a33a 100644
--- a/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
@@ -192,103 +192,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable the 32 kHz crystal watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_en(&mut self) -> XTAL32K_WDT_EN_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to FPU the 32 kHz crystal watchdog clock."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_clk_fo(&mut self) -> XTAL32K_WDT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_CLK_FO_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset the 32 kHz crystal watchdog by SW."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_reset(&mut self) -> XTAL32K_WDT_RESET_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_RESET_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to FPU the external clock of 32 kHz crystal."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_ext_clk_fo(&mut self) -> XTAL32K_EXT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_EXT_CLK_FO_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to switch to the backup clock when the 32 kHz crystal is dead."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_backup(&mut self) -> XTAL32K_AUTO_BACKUP_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_BACKUP_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to restart the 32 kHz crystal automatically when the 32 kHz crystal is dead."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_restart(&mut self) -> XTAL32K_AUTO_RESTART_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_RESTART_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to switch back to 32 kHz crystal when the 32 kHz crystal is restarted."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_return(&mut self) -> XTAL32K_AUTO_RETURN_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_RETURN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to allow the software to FPD the 32 kHz crystal. Set 0 to allow the FSM to FPD the 32 kHz crystal. (R/W)"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_xpd_force(&mut self) -> XTAL32K_XPD_FORCE_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_XPD_FORCE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Applies an internal clock to help the 32 kHz crystal to start."]
     #[inline(always)]
-    #[must_use]
     pub fn enckinit_xtal_32k(&mut self) -> ENCKINIT_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         ENCKINIT_XTAL_32K_W::new(self, 8)
     }
     #[doc = "Bit 9 - 0: single-end buffer 1: differential buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn dbuf_xtal_32k(&mut self) -> DBUF_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DBUF_XTAL_32K_W::new(self, 9)
     }
     #[doc = "Bits 10:12 - xtal_32k gm control"]
     #[inline(always)]
-    #[must_use]
     pub fn dgm_xtal_32k(&mut self) -> DGM_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DGM_XTAL_32K_W::new(self, 10)
     }
     #[doc = "Bits 13:15 - DRES_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn dres_xtal_32k(&mut self) -> DRES_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DRES_XTAL_32K_W::new(self, 13)
     }
     #[doc = "Bit 16 - XPD_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_xtal_32k(&mut self) -> XPD_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         XPD_XTAL_32K_W::new(self, 16)
     }
     #[doc = "Bits 17:19 - DAC_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_xtal_32k(&mut self) -> DAC_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DAC_XTAL_32K_W::new(self, 17)
     }
     #[doc = "Bit 23 - Selects the 32 kHz crystal clock. 0: selects the external 32 kHz clock. 1: selects clock from the RTC GPIO X32P_C."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_gpio_sel(&mut self) -> XTAL32K_GPIO_SEL_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_GPIO_SEL_W::new(self, 23)
     }
     #[doc = "Bit 30 - 0: powers down XTAL at high level 1: powers down XTAL at low level"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_lv(&mut self) -> XTL_EXT_CTR_LV_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - Enables the GPIO to power down the crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_en(&mut self) -> XTL_EXT_CTR_EN_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/int_clr.rs b/esp32s2/src/rtc_cntl/int_clr.rs
index e44dd1b29d..b3c0fa6221 100644
--- a/esp32s2/src/rtc_cntl/int_clr.rs
+++ b/esp32s2/src/rtc_cntl/int_clr.rs
@@ -49,121 +49,101 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clears the interrupt triggered when the chip wakes up from sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Clears the interrupt triggered when the chip rejects to go to sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Clears the interrupt triggered when the SDIO idles."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enables the RTC watchdog interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Clears the interrupt triggered upon the completion of a touch scanning."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_CLR_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enables the ULP co-processor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_CLR_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - Clears the interrupt triggered upon the completion of a single touch."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_CLR_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Clears the interrupt triggered when a touch is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_CLR_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Clears the interrupt triggered when a touch is released."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_CLR_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Clears the brown out interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Clears the RTC main timer interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - Clears the SAR ADC 1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_CLR_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - Clears the touch sensor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Clears the ULP-RISCV interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_CLR_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - Clears the SAR ADC 2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_CLR_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - Clears the super watchdog interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - Clears the interrupt triggered when the 32 kHz crystal is dead."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_CLR_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - Clears the interrupt triggered when the ULP-RISCV is trapped."]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_CLR_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - Clears the interrupt triggered when touch sensor times out."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_CLR_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - Clears the interrupt triggered when a glitch is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
diff --git a/esp32s2/src/rtc_cntl/int_ena.rs b/esp32s2/src/rtc_cntl/int_ena.rs
index cbb8f03b0f..04242b643a 100644
--- a/esp32s2/src/rtc_cntl/int_ena.rs
+++ b/esp32s2/src/rtc_cntl/int_ena.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enables interruption when the chip wakes up from sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enables interruption when the chip rejects to go to sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enables interruption when the SDIO idles."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enables the RTC watchdog interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Enables interruption upon the completion of a touch scanning."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enables the ULP co-processor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - Enables interruption upon the completion of a single touch."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Enables interruption when a touch is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Enables interruption when a touch is released."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Enables the brown out interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Enables the RTC main timer interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - Enables the SAR ADC 1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enables the touch sensor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_ENA_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Enables the ULP-RISCV interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - Enables the SAR ADC 2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - Enables the super watchdog interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_ENA_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - Enables interruption when the 32 kHz crystal is dead."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - Enables interruption when the ULP-RISCV is trapped."]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enables interruption when touch sensor times out."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - Enables interruption when a glitch is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
diff --git a/esp32s2/src/rtc_cntl/options0.rs b/esp32s2/src/rtc_cntl/options0.rs
index 6a1b7b99e6..0263f2c737 100644
--- a/esp32s2/src/rtc_cntl/options0.rs
+++ b/esp32s2/src/rtc_cntl/options0.rs
@@ -200,127 +200,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\] , reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c0(&mut self) -> SW_STALL_APPCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_APPCPU_C0_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c0(&mut self) -> SW_STALL_PROCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_PROCPU_C0_W::new(self, 2)
     }
     #[doc = "Bit 4 - APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2)"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_appcpu_rst(&mut self) -> SW_APPCPU_RST_W<OPTIONS0_SPEC> {
         SW_APPCPU_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to reset the CPU by SW."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_procpu_rst(&mut self) -> SW_PROCPU_RST_W<OPTIONS0_SPEC> {
         SW_PROCPU_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to FPD BB_I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pd(&mut self) -> BB_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to FPU BB_I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pu(&mut self) -> BB_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PU_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to FPD BB_PLL _I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pd(&mut self) -> BBPLL_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PD_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to FPU BB_PLL _I2C."]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pu(&mut self) -> BBPLL_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PU_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to FPD BB_PLL."]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pd(&mut self) -> BBPLL_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to FPU BB_PLL."]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pu(&mut self) -> BBPLL_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PU_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to FPD the crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pd(&mut self) -> XTL_FORCE_PD_W<OPTIONS0_SPEC> {
         XTL_FORCE_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to FPU the crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pu(&mut self) -> XTL_FORCE_PU_W<OPTIONS0_SPEC> {
         XTL_FORCE_PU_W::new(self, 13)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_iso(&mut self) -> XTL_FORCE_ISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_ISO_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_iso(&mut self) -> PLL_FORCE_ISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_iso(&mut self) -> ANALOG_FORCE_ISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_ISO_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_noiso(&mut self) -> XTL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_NOISO_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_noiso(&mut self) -> PLL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_noiso(&mut self) -> ANALOG_FORCE_NOISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_NOISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to force reset the digital system in deep-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_rst(&mut self) -> DG_WRAP_FORCE_RST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to disable force reset to digital system in deep-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_norst(&mut self) -> DG_WRAP_FORCE_NORST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_NORST_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to reset the system via SW."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_sys_rst(&mut self) -> SW_SYS_RST_W<OPTIONS0_SPEC> {
         SW_SYS_RST_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/options1.rs b/esp32s2/src/rtc_cntl/options1.rs
index 23975a9642..592b93f5ed 100644
--- a/esp32s2/src/rtc_cntl/options1.rs
+++ b/esp32s2/src/rtc_cntl/options1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to force the chip to boot from the download mode."]
     #[inline(always)]
-    #[must_use]
     pub fn force_download_boot(&mut self) -> FORCE_DOWNLOAD_BOOT_W<OPTIONS1_SPEC> {
         FORCE_DOWNLOAD_BOOT_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/pad_hold.rs b/esp32s2/src/rtc_cntl/pad_hold.rs
index 955c3b95ba..17f0175772 100644
--- a/esp32s2/src/rtc_cntl/pad_hold.rs
+++ b/esp32s2/src/rtc_cntl/pad_hold.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Sets the touch GPIO 0 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad0_hold(&mut self) -> TOUCH_PAD0_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD0_HOLD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sets the touch GPIO 1 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad1_hold(&mut self) -> TOUCH_PAD1_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD1_HOLD_W::new(self, 1)
     }
     #[doc = "Bit 2 - Sets the touch GPIO 2 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad2_hold(&mut self) -> TOUCH_PAD2_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD2_HOLD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Sets the touch GPIO 3 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad3_hold(&mut self) -> TOUCH_PAD3_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD3_HOLD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Sets the touch GPIO 4 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad4_hold(&mut self) -> TOUCH_PAD4_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD4_HOLD_W::new(self, 4)
     }
     #[doc = "Bit 5 - Sets the touch GPIO 5 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad5_hold(&mut self) -> TOUCH_PAD5_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD5_HOLD_W::new(self, 5)
     }
     #[doc = "Bit 6 - Sets the touch GPIO 6 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad6_hold(&mut self) -> TOUCH_PAD6_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD6_HOLD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Sets the touch GPIO 7 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad7_hold(&mut self) -> TOUCH_PAD7_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD7_HOLD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Sets the touch GPIO 8 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad8_hold(&mut self) -> TOUCH_PAD8_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD8_HOLD_W::new(self, 8)
     }
     #[doc = "Bit 9 - Sets the touch GPIO 9 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad9_hold(&mut self) -> TOUCH_PAD9_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD9_HOLD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Sets the touch GPIO 10 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad10_hold(&mut self) -> TOUCH_PAD10_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD10_HOLD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Sets the touch GPIO 11 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad11_hold(&mut self) -> TOUCH_PAD11_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD11_HOLD_W::new(self, 11)
     }
     #[doc = "Bit 12 - Sets the touch GPIO 12 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad12_hold(&mut self) -> TOUCH_PAD12_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD12_HOLD_W::new(self, 12)
     }
     #[doc = "Bit 13 - Sets the touch GPIO 13 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad13_hold(&mut self) -> TOUCH_PAD13_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD13_HOLD_W::new(self, 13)
     }
     #[doc = "Bit 14 - Sets the touch GPIO 14 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad14_hold(&mut self) -> TOUCH_PAD14_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD14_HOLD_W::new(self, 14)
     }
     #[doc = "Bit 15 - Sets the x32p to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_hold(&mut self) -> X32P_HOLD_W<PAD_HOLD_SPEC> {
         X32P_HOLD_W::new(self, 15)
     }
     #[doc = "Bit 16 - Sets the x32n to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_hold(&mut self) -> X32N_HOLD_W<PAD_HOLD_SPEC> {
         X32N_HOLD_W::new(self, 16)
     }
     #[doc = "Bit 17 - Sets the pdac1 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_hold(&mut self) -> PDAC1_HOLD_W<PAD_HOLD_SPEC> {
         PDAC1_HOLD_W::new(self, 17)
     }
     #[doc = "Bit 18 - Sets the pdac2 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_hold(&mut self) -> PDAC2_HOLD_W<PAD_HOLD_SPEC> {
         PDAC2_HOLD_W::new(self, 18)
     }
     #[doc = "Bit 19 - Sets the RTG GPIO 19 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn pad19_hold(&mut self) -> PAD19_HOLD_W<PAD_HOLD_SPEC> {
         PAD19_HOLD_W::new(self, 19)
     }
     #[doc = "Bit 20 - Sets the RTG GPIO 20 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn pad20_hold(&mut self) -> PAD20_HOLD_W<PAD_HOLD_SPEC> {
         PAD20_HOLD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Sets the RTG GPIO 21 to hold."]
     #[inline(always)]
-    #[must_use]
     pub fn pad21_hold(&mut self) -> PAD21_HOLD_W<PAD_HOLD_SPEC> {
         PAD21_HOLD_W::new(self, 21)
     }
diff --git a/esp32s2/src/rtc_cntl/pwc.rs b/esp32s2/src/rtc_cntl/pwc.rs
index 35266d859c..0fa549505c 100644
--- a/esp32s2/src/rtc_cntl/pwc.rs
+++ b/esp32s2/src/rtc_cntl/pwc.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to disable the force isolation to the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_noiso(&mut self) -> FASTMEM_FORCE_NOISO_W<PWC_SPEC> {
         FASTMEM_FORCE_NOISO_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to force isolate the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_iso(&mut self) -> FASTMEM_FORCE_ISO_W<PWC_SPEC> {
         FASTMEM_FORCE_ISO_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to disable the force isolation to the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_noiso(&mut self) -> SLOWMEM_FORCE_NOISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_NOISO_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to force isolate the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_iso(&mut self) -> SLOWMEM_FORCE_ISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_ISO_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to force isolate the RTC peripherals."]
     #[inline(always)]
-    #[must_use]
     pub fn force_iso(&mut self) -> FORCE_ISO_W<PWC_SPEC> {
         FORCE_ISO_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to disable the force isolation to the RTC peripherals."]
     #[inline(always)]
-    #[must_use]
     pub fn force_noiso(&mut self) -> FORCE_NOISO_W<PWC_SPEC> {
         FORCE_NOISO_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set 1 to FPD the RTC fast memory when the CPU is powered down. Set 0 to FPD the RTC fast memory when the RTC main state machine is powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_folw_cpu(&mut self) -> FASTMEM_FOLW_CPU_W<PWC_SPEC> {
         FASTMEM_FOLW_CPU_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to force not retain the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpd(&mut self) -> FASTMEM_FORCE_LPD_W<PWC_SPEC> {
         FASTMEM_FORCE_LPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to force retain the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpu(&mut self) -> FASTMEM_FORCE_LPU_W<PWC_SPEC> {
         FASTMEM_FORCE_LPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set 1 to FPD the RTC slow memory when the CPU is powered down. Set 0 to FPD the RTC slow memory when the RTC main state machine is powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_folw_cpu(&mut self) -> SLOWMEM_FOLW_CPU_W<PWC_SPEC> {
         SLOWMEM_FOLW_CPU_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to force not retain the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpd(&mut self) -> SLOWMEM_FORCE_LPD_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to force retain the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpu(&mut self) -> SLOWMEM_FORCE_LPU_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPU_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to FPD the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_pd(&mut self) -> FASTMEM_FORCE_PD_W<PWC_SPEC> {
         FASTMEM_FORCE_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to FPU the RTC fast memory."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_pu(&mut self) -> FASTMEM_FORCE_PU_W<PWC_SPEC> {
         FASTMEM_FORCE_PU_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable PD for the RTC fast memory in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_pd_en(&mut self) -> FASTMEM_PD_EN_W<PWC_SPEC> {
         FASTMEM_PD_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to FPD the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_pd(&mut self) -> SLOWMEM_FORCE_PD_W<PWC_SPEC> {
         SLOWMEM_FORCE_PD_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to FPU the RTC slow memory."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_pu(&mut self) -> SLOWMEM_FORCE_PU_W<PWC_SPEC> {
         SLOWMEM_FORCE_PU_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to enable PD for the RTC slow memory in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_pd_en(&mut self) -> SLOWMEM_PD_EN_W<PWC_SPEC> {
         SLOWMEM_PD_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to FPD the RTC peripherals."]
     #[inline(always)]
-    #[must_use]
     pub fn force_pd(&mut self) -> FORCE_PD_W<PWC_SPEC> {
         FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to FPU the RTC peripherals."]
     #[inline(always)]
-    #[must_use]
     pub fn force_pu(&mut self) -> FORCE_PU_W<PWC_SPEC> {
         FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to enable PD for the RTC peripherals in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn pd_en(&mut self) -> PD_EN_W<PWC_SPEC> {
         PD_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit the force hold the RTC GPIOs."]
     #[inline(always)]
-    #[must_use]
     pub fn pad_force_hold(&mut self) -> PAD_FORCE_HOLD_W<PWC_SPEC> {
         PAD_FORCE_HOLD_W::new(self, 21)
     }
diff --git a/esp32s2/src/rtc_cntl/reg.rs b/esp32s2/src/rtc_cntl/reg.rs
index b119372794..31d150c326 100644
--- a/esp32s2/src/rtc_cntl/reg.rs
+++ b/esp32s2/src/rtc_cntl/reg.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:10 - Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_reg_dbias_slp(&mut self) -> DIG_REG_DBIAS_SLP_W<REG_SPEC> {
         DIG_REG_DBIAS_SLP_W::new(self, 8)
     }
     #[doc = "Bits 11:13 - Configures the regulation factor for the digital system voltage regulator when the CPU is in active status."]
     #[inline(always)]
-    #[must_use]
     pub fn dig_reg_dbias_wak(&mut self) -> DIG_REG_DBIAS_WAK_W<REG_SPEC> {
         DIG_REG_DBIAS_WAK_W::new(self, 11)
     }
     #[doc = "Bits 14:21 - Configures the frequency of the RTC clocks."]
     #[inline(always)]
-    #[must_use]
     pub fn sck_dcap(&mut self) -> SCK_DCAP_W<REG_SPEC> {
         SCK_DCAP_W::new(self, 14)
     }
     #[doc = "Bits 22:24 - Configures the regulation factor for the low-power voltage regulator when the CPU is in sleep status."]
     #[inline(always)]
-    #[must_use]
     pub fn dbias_slp(&mut self) -> DBIAS_SLP_W<REG_SPEC> {
         DBIAS_SLP_W::new(self, 22)
     }
     #[doc = "Bits 25:27 - Configures the regulation factor for the low-power voltage regulator when the CPU is in active status."]
     #[inline(always)]
-    #[must_use]
     pub fn dbias_wak(&mut self) -> DBIAS_WAK_W<REG_SPEC> {
         DBIAS_WAK_W::new(self, 25)
     }
     #[doc = "Bit 28 - RTC_DBOOST force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pd(&mut self) -> DBOOST_FORCE_PD_W<REG_SPEC> {
         DBOOST_FORCE_PD_W::new(self, 28)
     }
     #[doc = "Bit 29 - RTC_DBOOST force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pu(&mut self) -> DBOOST_FORCE_PU_W<REG_SPEC> {
         DBOOST_FORCE_PU_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to FPD the RTC_REG, which means decreasing its voltage to 0.8 V or lower."]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_force_pd(&mut self) -> REGULATOR_FORCE_PD_W<REG_SPEC> {
         REGULATOR_FORCE_PD_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to FPU the RTC_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_force_pu(&mut self) -> REGULATOR_FORCE_PU_W<REG_SPEC> {
         REGULATOR_FORCE_PU_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/reset_state.rs b/esp32s2/src/rtc_cntl/reset_state.rs
index e9bf971039..c72b16f33c 100644
--- a/esp32s2/src/rtc_cntl/reset_state.rs
+++ b/esp32s2/src/rtc_cntl/reset_state.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_stat_vector_sel(&mut self) -> APPCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         APPCPU_STAT_VECTOR_SEL_W::new(self, 12)
     }
     #[doc = "Bit 13 - Selects the CPU state vector."]
     #[inline(always)]
-    #[must_use]
     pub fn procpu_stat_vector_sel(&mut self) -> PROCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         PROCPU_STAT_VECTOR_SEL_W::new(self, 13)
     }
diff --git a/esp32s2/src/rtc_cntl/sdio_act_conf.rs b/esp32s2/src/rtc_cntl/sdio_act_conf.rs
index ee297ddfde..7ff21e0bf1 100644
--- a/esp32s2/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32s2/src/rtc_cntl/sdio_act_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 22:31 - configure sdio act dnum"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W<SDIO_ACT_CONF_SPEC> {
         SDIO_ACT_DNUM_W::new(self, 22)
     }
diff --git a/esp32s2/src/rtc_cntl/sdio_conf.rs b/esp32s2/src/rtc_cntl/sdio_conf.rs
index f6fcf447d9..be8ca5b7d1 100644
--- a/esp32s2/src/rtc_cntl/sdio_conf.rs
+++ b/esp32s2/src/rtc_cntl/sdio_conf.rs
@@ -172,91 +172,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_timer_target(&mut self) -> SDIO_TIMER_TARGET_W<SDIO_CONF_SPEC> {
         SDIO_TIMER_TARGET_W::new(self, 0)
     }
     #[doc = "Bits 9:10 - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dthdrv(&mut self) -> SDIO_DTHDRV_W<SDIO_CONF_SPEC> {
         SDIO_DTHDRV_W::new(self, 9)
     }
     #[doc = "Bits 11:12 - ability to prevent LDO from overshoot"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dcap(&mut self) -> SDIO_DCAP_W<SDIO_CONF_SPEC> {
         SDIO_DCAP_W::new(self, 11)
     }
     #[doc = "Bits 13:14 - add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_initi(&mut self) -> SDIO_INITI_W<SDIO_CONF_SPEC> {
         SDIO_INITI_W::new(self, 13)
     }
     #[doc = "Bit 15 - 0 to set init\\[1:0\\]=0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_en_initi(&mut self) -> SDIO_EN_INITI_W<SDIO_CONF_SPEC> {
         SDIO_EN_INITI_W::new(self, 15)
     }
     #[doc = "Bits 16:18 - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dcurlim(&mut self) -> SDIO_DCURLIM_W<SDIO_CONF_SPEC> {
         SDIO_DCURLIM_W::new(self, 16)
     }
     #[doc = "Bit 19 - select current limit mode"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_modecurlim(&mut self) -> SDIO_MODECURLIM_W<SDIO_CONF_SPEC> {
         SDIO_MODECURLIM_W::new(self, 19)
     }
     #[doc = "Bit 20 - enable current limit"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_encurlim(&mut self) -> SDIO_ENCURLIM_W<SDIO_CONF_SPEC> {
         SDIO_ENCURLIM_W::new(self, 20)
     }
     #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_reg_pd_en(&mut self) -> SDIO_REG_PD_EN_W<SDIO_CONF_SPEC> {
         SDIO_REG_PD_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: use SW option to control SDIO_REG 0: use state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_force(&mut self) -> SDIO_FORCE_W<SDIO_CONF_SPEC> {
         SDIO_FORCE_W::new(self, 22)
     }
     #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<SDIO_CONF_SPEC> {
         SDIO_TIEH_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<SDIO_CONF_SPEC> {
         DREFL_SDIO_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<SDIO_CONF_SPEC> {
         DREFM_SDIO_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<SDIO_CONF_SPEC> {
         DREFH_SDIO_W::new(self, 29)
     }
     #[doc = "Bit 31 - SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sdio(&mut self) -> XPD_SDIO_W<SDIO_CONF_SPEC> {
         XPD_SDIO_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/slow_clk_conf.rs b/esp32s2/src/rtc_cntl/slow_clk_conf.rs
index f5cb6e897a..5f692dd69f 100644
--- a/esp32s2/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32s2/src/rtc_cntl/slow_clk_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 22 - Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock."]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<SLOW_CLK_CONF_SPEC> {
         ANA_CLK_DIV_VLD_W::new(self, 22)
     }
     #[doc = "Bits 23:30 - Set the rtc_clk divider."]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<SLOW_CLK_CONF_SPEC> {
         ANA_CLK_DIV_W::new(self, 23)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<SLOW_CLK_CONF_SPEC> {
         SLOW_CLK_NEXT_EDGE_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/slp_reject_conf.rs b/esp32s2/src/rtc_cntl/slp_reject_conf.rs
index 57b4cbc104..f795139635 100644
--- a/esp32s2/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32s2/src/rtc_cntl/slp_reject_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 13:29 - Set this bit to enable reject-to-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_reject_ena(&mut self) -> SLEEP_REJECT_ENA_W<SLP_REJECT_CONF_SPEC> {
         SLEEP_REJECT_ENA_W::new(self, 13)
     }
     #[doc = "Bit 30 - Set this bit to enable reject-to-light-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn light_slp_reject_en(&mut self) -> LIGHT_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         LIGHT_SLP_REJECT_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable reject-to-deep-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn deep_slp_reject_en(&mut self) -> DEEP_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         DEEP_SLP_REJECT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/slp_timer0.rs b/esp32s2/src/rtc_cntl/slp_timer0.rs
index bf71e456de..7e2b161742 100644
--- a/esp32s2/src/rtc_cntl/slp_timer0.rs
+++ b/esp32s2/src/rtc_cntl/slp_timer0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Sets the lower 32 bits of the trigger threshold for the RTC timer."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_lo(&mut self) -> SLP_VAL_LO_W<SLP_TIMER0_SPEC> {
         SLP_VAL_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/slp_timer1.rs b/esp32s2/src/rtc_cntl/slp_timer1.rs
index b6e7a86a3e..56fd1357f6 100644
--- a/esp32s2/src/rtc_cntl/slp_timer1.rs
+++ b/esp32s2/src/rtc_cntl/slp_timer1.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Sets the higher 16 bits of the trigger threshold for the RTC timer."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<SLP_TIMER1_SPEC> {
         SLP_VAL_HI_W::new(self, 0)
     }
     #[doc = "Bit 16 - Sets this bit to enable the timer alarm."]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<SLP_TIMER1_SPEC> {
         MAIN_TIMER_ALARM_EN_W::new(self, 16)
     }
diff --git a/esp32s2/src/rtc_cntl/state0.rs b/esp32s2/src/rtc_cntl/state0.rs
index d55c5c8275..d5a8897990 100644
--- a/esp32s2/src/rtc_cntl/state0.rs
+++ b/esp32s2/src/rtc_cntl/state0.rs
@@ -66,37 +66,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Sends a SW RTC interrupt to CPU."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_cpu_int(&mut self) -> SW_CPU_INT_W<STATE0_SPEC> {
         SW_CPU_INT_W::new(self, 0)
     }
     #[doc = "Bit 1 - Clears the RTC reject-to-sleep cause."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject_cause_clr(&mut self) -> SLP_REJECT_CAUSE_CLR_W<STATE0_SPEC> {
         SLP_REJECT_CAUSE_CLR_W::new(self, 1)
     }
     #[doc = "Bit 22 - 1: APB to RTC using bridge 0: APB to RTC using sync"]
     #[inline(always)]
-    #[must_use]
     pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<STATE0_SPEC> {
         APB2RTC_BRIDGE_SEL_W::new(self, 22)
     }
     #[doc = "Bit 29 - Sleep wakeup bit."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<STATE0_SPEC> {
         SLP_WAKEUP_W::new(self, 29)
     }
     #[doc = "Bit 30 - Sleep reject bit."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<STATE0_SPEC> {
         SLP_REJECT_W::new(self, 30)
     }
     #[doc = "Bit 31 - Sends the chip to sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_en(&mut self) -> SLEEP_EN_W<STATE0_SPEC> {
         SLEEP_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/store0.rs b/esp32s2/src/rtc_cntl/store0.rs
index ddb0ab400b..1d46908ead 100644
--- a/esp32s2/src/rtc_cntl/store0.rs
+++ b/esp32s2/src/rtc_cntl/store0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 0"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch0(&mut self) -> SCRATCH0_W<STORE0_SPEC> {
         SCRATCH0_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store1.rs b/esp32s2/src/rtc_cntl/store1.rs
index a9758cce25..0f0981e56e 100644
--- a/esp32s2/src/rtc_cntl/store1.rs
+++ b/esp32s2/src/rtc_cntl/store1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 1"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch1(&mut self) -> SCRATCH1_W<STORE1_SPEC> {
         SCRATCH1_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store2.rs b/esp32s2/src/rtc_cntl/store2.rs
index 96fbd31ed8..331dbc215e 100644
--- a/esp32s2/src/rtc_cntl/store2.rs
+++ b/esp32s2/src/rtc_cntl/store2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 2"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch2(&mut self) -> SCRATCH2_W<STORE2_SPEC> {
         SCRATCH2_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store3.rs b/esp32s2/src/rtc_cntl/store3.rs
index 50fbed0034..3329450355 100644
--- a/esp32s2/src/rtc_cntl/store3.rs
+++ b/esp32s2/src/rtc_cntl/store3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 3"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch3(&mut self) -> SCRATCH3_W<STORE3_SPEC> {
         SCRATCH3_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store4.rs b/esp32s2/src/rtc_cntl/store4.rs
index c87101ef6c..d0fd6212e6 100644
--- a/esp32s2/src/rtc_cntl/store4.rs
+++ b/esp32s2/src/rtc_cntl/store4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 4."]
     #[inline(always)]
-    #[must_use]
     pub fn scratch4(&mut self) -> SCRATCH4_W<STORE4_SPEC> {
         SCRATCH4_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store5.rs b/esp32s2/src/rtc_cntl/store5.rs
index 81bb399bea..04dfda51b3 100644
--- a/esp32s2/src/rtc_cntl/store5.rs
+++ b/esp32s2/src/rtc_cntl/store5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 5."]
     #[inline(always)]
-    #[must_use]
     pub fn scratch5(&mut self) -> SCRATCH5_W<STORE5_SPEC> {
         SCRATCH5_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store6.rs b/esp32s2/src/rtc_cntl/store6.rs
index 2047c1d3a8..020c109c16 100644
--- a/esp32s2/src/rtc_cntl/store6.rs
+++ b/esp32s2/src/rtc_cntl/store6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 6."]
     #[inline(always)]
-    #[must_use]
     pub fn scratch6(&mut self) -> SCRATCH6_W<STORE6_SPEC> {
         SCRATCH6_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/store7.rs b/esp32s2/src/rtc_cntl/store7.rs
index 5c906cbf80..f8a70d5722 100644
--- a/esp32s2/src/rtc_cntl/store7.rs
+++ b/esp32s2/src/rtc_cntl/store7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reservation register 7."]
     #[inline(always)]
-    #[must_use]
     pub fn scratch7(&mut self) -> SCRATCH7_W<STORE7_SPEC> {
         SCRATCH7_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/sw_cpu_stall.rs b/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
index 1d60a68110..31d1016d48 100644
--- a/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c1(&mut self) -> SW_STALL_APPCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_APPCPU_C1_W::new(self, 20)
     }
     #[doc = "Bits 26:31 - Set this bit to allow the SW to be able to send the CPU into stalling."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c1(&mut self) -> SW_STALL_PROCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_PROCPU_C1_W::new(self, 26)
     }
diff --git a/esp32s2/src/rtc_cntl/swd_conf.rs b/esp32s2/src/rtc_cntl/swd_conf.rs
index 2ec1c573a9..d79f31f167 100644
--- a/esp32s2/src/rtc_cntl/swd_conf.rs
+++ b/esp32s2/src/rtc_cntl/swd_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 18:27 - Adjusts the signal width sent to the super watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_signal_width(&mut self) -> SWD_SIGNAL_WIDTH_W<SWD_CONF_SPEC> {
         SWD_SIGNAL_WIDTH_W::new(self, 18)
     }
     #[doc = "Bit 28 - Set to reset the super watchdog reset flag."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_rst_flag_clr(&mut self) -> SWD_RST_FLAG_CLR_W<SWD_CONF_SPEC> {
         SWD_RST_FLAG_CLR_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set to feed the super watchdog via SW."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_feed(&mut self) -> SWD_FEED_W<SWD_CONF_SPEC> {
         SWD_FEED_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to disable super watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_disable(&mut self) -> SWD_DISABLE_W<SWD_CONF_SPEC> {
         SWD_DISABLE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable automatic watchdog feeding upon interrupts."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_auto_feed_en(&mut self) -> SWD_AUTO_FEED_EN_W<SWD_CONF_SPEC> {
         SWD_AUTO_FEED_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/swd_wprotect.rs b/esp32s2/src/rtc_cntl/swd_wprotect.rs
index 9756138ac8..90bcf1d6e5 100644
--- a/esp32s2/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32s2/src/rtc_cntl/swd_wprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Sets the write protection key of the super watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn swd_wkey(&mut self) -> SWD_WKEY_W<SWD_WPROTECT_SPEC> {
         SWD_WKEY_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/time_update.rs b/esp32s2/src/rtc_cntl/time_update.rs
index 0799aaa3ee..670c2b418f 100644
--- a/esp32s2/src/rtc_cntl/time_update.rs
+++ b/esp32s2/src/rtc_cntl/time_update.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 27 - Selects the triggering condition for the RTC timer. See details in Table 1-2."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sys_stall(&mut self) -> TIMER_SYS_STALL_W<TIME_UPDATE_SPEC> {
         TIMER_SYS_STALL_W::new(self, 27)
     }
     #[doc = "Bit 28 - Selects the triggering condition for the RTC timer. See details in Table 1-2."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_xtl_off(&mut self) -> TIMER_XTL_OFF_W<TIME_UPDATE_SPEC> {
         TIMER_XTL_OFF_W::new(self, 28)
     }
     #[doc = "Bit 29 - Selects the triggering condition for the RTC timer. See details in Table 1-2."]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sys_rst(&mut self) -> TIMER_SYS_RST_W<TIME_UPDATE_SPEC> {
         TIMER_SYS_RST_W::new(self, 29)
     }
     #[doc = "Bit 31 - Selects the triggering condition for the RTC timer. See details in Table 1-2."]
     #[inline(always)]
-    #[must_use]
     pub fn time_update(&mut self) -> TIME_UPDATE_W<TIME_UPDATE_SPEC> {
         TIME_UPDATE_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/timer1.rs b/esp32s2/src/rtc_cntl/timer1.rs
index 3326c4a5ce..6c5f366b01 100644
--- a/esp32s2/src/rtc_cntl/timer1.rs
+++ b/esp32s2/src/rtc_cntl/timer1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enables CPU stalling."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<TIMER1_SPEC> {
         CPU_STALL_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:5 - Sets the CPU stall waiting cycle (using the RTC fast clock)."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<TIMER1_SPEC> {
         CPU_STALL_WAIT_W::new(self, 1)
     }
     #[doc = "Bits 6:13 - Sets the 8 MHz clock waiting (using the RTC slow clock)."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<TIMER1_SPEC> {
         CK8M_WAIT_W::new(self, 6)
     }
     #[doc = "Bits 14:23 - Sets the XTAL waiting cycle (using the RTC slow clock)."]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<TIMER1_SPEC> {
         XTL_BUF_WAIT_W::new(self, 14)
     }
     #[doc = "Bits 24:31 - Sets the PLL waiting cycle (using the RTC slow clock)."]
     #[inline(always)]
-    #[must_use]
     pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<TIMER1_SPEC> {
         PLL_BUF_WAIT_W::new(self, 24)
     }
diff --git a/esp32s2/src/rtc_cntl/timer2.rs b/esp32s2/src/rtc_cntl/timer2.rs
index 7ee66e94f2..b2d30c2dc0 100644
--- a/esp32s2/src/rtc_cntl/timer2.rs
+++ b/esp32s2/src/rtc_cntl/timer2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:23 - Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work."]
     #[inline(always)]
-    #[must_use]
     pub fn ulpcp_touch_start_wait(&mut self) -> ULPCP_TOUCH_START_WAIT_W<TIMER2_SPEC> {
         ULPCP_TOUCH_START_WAIT_W::new(self, 15)
     }
     #[doc = "Bits 24:31 - Sets the minimal cycle for 8 MHz clock (using the RTC slow clock) when powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn min_time_ck8m_off(&mut self) -> MIN_TIME_CK8M_OFF_W<TIMER2_SPEC> {
         MIN_TIME_CK8M_OFF_W::new(self, 24)
     }
diff --git a/esp32s2/src/rtc_cntl/timer3.rs b/esp32s2/src/rtc_cntl/timer3.rs
index b6dd7328fb..9928329391 100644
--- a/esp32s2/src/rtc_cntl/timer3.rs
+++ b/esp32s2/src/rtc_cntl/timer3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_wait_timer(&mut self) -> WIFI_WAIT_TIMER_W<TIMER3_SPEC> {
         WIFI_WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_powerup_timer(&mut self) -> WIFI_POWERUP_TIMER_W<TIMER3_SPEC> {
         WIFI_POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_ram_wait_timer(&mut self) -> ROM_RAM_WAIT_TIMER_W<TIMER3_SPEC> {
         ROM_RAM_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_ram_powerup_timer(&mut self) -> ROM_RAM_POWERUP_TIMER_W<TIMER3_SPEC> {
         ROM_RAM_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s2/src/rtc_cntl/timer4.rs b/esp32s2/src/rtc_cntl/timer4.rs
index 8ed530a175..3e74a0dce3 100644
--- a/esp32s2/src/rtc_cntl/timer4.rs
+++ b/esp32s2/src/rtc_cntl/timer4.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
-    #[must_use]
     pub fn wait_timer(&mut self) -> WAIT_TIMER_W<TIMER4_SPEC> {
         WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15"]
     #[inline(always)]
-    #[must_use]
     pub fn powerup_timer(&mut self) -> POWERUP_TIMER_W<TIMER4_SPEC> {
         POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_wait_timer(&mut self) -> DG_WRAP_WAIT_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_powerup_timer(&mut self) -> DG_WRAP_POWERUP_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s2/src/rtc_cntl/timer5.rs b/esp32s2/src/rtc_cntl/timer5.rs
index 0cbaa5b4e9..fce6944b76 100644
--- a/esp32s2/src/rtc_cntl/timer5.rs
+++ b/esp32s2/src/rtc_cntl/timer5.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:15 - Sets the minimal sleep cycles (using the RTC slow clock)."]
     #[inline(always)]
-    #[must_use]
     pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<TIMER5_SPEC> {
         MIN_SLP_VAL_W::new(self, 8)
     }
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn rtcmem_wait_timer(&mut self) -> RTCMEM_WAIT_TIMER_W<TIMER5_SPEC> {
         RTCMEM_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rtcmem_powerup_timer(&mut self) -> RTCMEM_POWERUP_TIMER_W<TIMER5_SPEC> {
         RTCMEM_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s2/src/rtc_cntl/timer6.rs b/esp32s2/src/rtc_cntl/timer6.rs
index cb8d53673d..660382bd79 100644
--- a/esp32s2/src/rtc_cntl/timer6.rs
+++ b/esp32s2/src/rtc_cntl/timer6.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:24"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_dcdc_wait_timer(&mut self) -> DG_DCDC_WAIT_TIMER_W<TIMER6_SPEC> {
         DG_DCDC_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_dcdc_powerup_timer(&mut self) -> DG_DCDC_POWERUP_TIMER_W<TIMER6_SPEC> {
         DG_DCDC_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_approach.rs b/esp32s2/src/rtc_cntl/touch_approach.rs
index 64b8ab9e35..442b562cbe 100644
--- a/esp32s2/src/rtc_cntl/touch_approach.rs
+++ b/esp32s2/src/rtc_cntl/touch_approach.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 23 - Clear touch sleep channel."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_channel_clr(&mut self) -> TOUCH_SLP_CHANNEL_CLR_W<TOUCH_APPROACH_SPEC> {
         TOUCH_SLP_CHANNEL_CLR_W::new(self, 23)
     }
     #[doc = "Bits 24:31 - Set the total measurement times for the pads in proximity mode. Range: 0 – 255."]
     #[inline(always)]
-    #[must_use]
     pub fn meas_time(&mut self) -> MEAS_TIME_W<TOUCH_APPROACH_SPEC> {
         MEAS_TIME_W::new(self, 24)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_ctrl1.rs b/esp32s2/src/rtc_cntl/touch_ctrl1.rs
index 3a7e6eac39..bce83ea670 100644
--- a/esp32s2/src/rtc_cntl/touch_ctrl1.rs
+++ b/esp32s2/src/rtc_cntl/touch_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Set sleep cycles for touch timer."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W<TOUCH_CTRL1_SPEC> {
         TOUCH_SLEEP_CYCLES_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Configure measurement length (in 8 MHz), i.e., charge/discharge times."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_meas_num(&mut self) -> TOUCH_MEAS_NUM_W<TOUCH_CTRL1_SPEC> {
         TOUCH_MEAS_NUM_W::new(self, 16)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_ctrl2.rs b/esp32s2/src/rtc_cntl/touch_ctrl2.rs
index ccae551b38..67efda0e77 100644
--- a/esp32s2/src/rtc_cntl/touch_ctrl2.rs
+++ b/esp32s2/src/rtc_cntl/touch_ctrl2.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 2:3 - TOUCH attenuation."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drange(&mut self) -> TOUCH_DRANGE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DRANGE_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - TOUCH reference voltage low. 0: 0.5 V 1: 0.6 V 2: 0.7 V 3: 0.8 V."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefl(&mut self) -> TOUCH_DREFL_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DREFL_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - TOUCH reference voltage high. 0: 2.4 V 1: 2.5 V 2: 2.6 V 3: 2.7 V."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefh(&mut self) -> TOUCH_DREFH_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DREFH_W::new(self, 6)
     }
     #[doc = "Bit 8 - TOUCH BIAS power switch."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_bias(&mut self) -> TOUCH_XPD_BIAS_W<TOUCH_CTRL2_SPEC> {
         TOUCH_XPD_BIAS_W::new(self, 8)
     }
     #[doc = "Bits 9:11 - Touch pad 0 reference capacitance."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_refc(&mut self) -> TOUCH_REFC_W<TOUCH_CTRL2_SPEC> {
         TOUCH_REFC_W::new(self, 9)
     }
     #[doc = "Bit 12 - 0: Use bandgap bias. 1: Use self bias."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_dbias(&mut self) -> TOUCH_DBIAS_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DBIAS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Touch timer enable bit."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_timer_en(&mut self) -> TOUCH_SLP_TIMER_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_SLP_TIMER_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - 0: TOUCH_START and TOUCH_XPD are controlled by soft- ware. 1: TOUCH_START and TOUCH_XPD are controlled by the Touch FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_fsm_en(&mut self) -> TOUCH_START_FSM_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_FSM_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Start the Touch FSM, only valid when RTC_CNTL_TOUCH_START_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_en(&mut self) -> TOUCH_START_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 0: Start the Touch FSM by timer. 1: Start Touch FSM by software."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_force(&mut self) -> TOUCH_START_FORCE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_FORCE_W::new(self, 16)
     }
     #[doc = "Bits 17:24 - The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_wait(&mut self) -> TOUCH_XPD_WAIT_W<TOUCH_CTRL2_SPEC> {
         TOUCH_XPD_WAIT_W::new(self, 17)
     }
     #[doc = "Bits 25:26 - When a touch pad is active, sleep cycle could be divided by this number."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_cyc_div(&mut self) -> TOUCH_SLP_CYC_DIV_W<TOUCH_CTRL2_SPEC> {
         TOUCH_SLP_CYC_DIV_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - Force touch timer done."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timer_force_done(&mut self) -> TOUCH_TIMER_FORCE_DONE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_TIMER_FORCE_DONE_W::new(self, 27)
     }
     #[doc = "Bit 29 - Reset TOUCH FSM via software."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_reset(&mut self) -> TOUCH_RESET_W<TOUCH_CTRL2_SPEC> {
         TOUCH_RESET_W::new(self, 29)
     }
     #[doc = "Bit 30 - Touch clock force on."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_clk_fo(&mut self) -> TOUCH_CLK_FO_W<TOUCH_CTRL2_SPEC> {
         TOUCH_CLK_FO_W::new(self, 30)
     }
     #[doc = "Bit 31 - Touch clock enable bit."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_clkgate_en(&mut self) -> TOUCH_CLKGATE_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_CLKGATE_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs b/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
index 88107ebba4..fa380392c1 100644
--- a/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 9:10 - 0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_smooth_lvl(&mut self) -> TOUCH_SMOOTH_LVL_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_SMOOTH_LVL_W::new(self, 9)
     }
     #[doc = "Bits 11:14 - Touch jitter step. Range: 0 – 15."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_jitter_step(&mut self) -> TOUCH_JITTER_STEP_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_JITTER_STEP_W::new(self, 11)
     }
     #[doc = "Bits 15:18 - Negative threshold counter limit."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_neg_noise_limit(&mut self) -> TOUCH_NEG_NOISE_LIMIT_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NEG_NOISE_LIMIT_W::new(self, 15)
     }
     #[doc = "Bits 19:20 - Negative noise threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_neg_noise_thres(&mut self) -> TOUCH_NEG_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NEG_NOISE_THRES_W::new(self, 19)
     }
     #[doc = "Bits 21:22 - Active noise threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_noise_thres(&mut self) -> TOUCH_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NOISE_THRES_W::new(self, 21)
     }
     #[doc = "Bits 23:24 - Touch hysteresis."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_hysteresis(&mut self) -> TOUCH_HYSTERESIS_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_HYSTERESIS_W::new(self, 23)
     }
     #[doc = "Bits 25:27 - Debounce counter."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_debounce(&mut self) -> TOUCH_DEBOUNCE_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_DEBOUNCE_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - Set filter mode. 0: IIR 1/2; 1: IIR 1/4; 2: IIR 1/8; 3: IIR 1/16; 4: IIR 1/32; 5: IIR 1/64; 6: IIR 1/128; 7: Jitter."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_filter_mode(&mut self) -> TOUCH_FILTER_MODE_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_FILTER_MODE_W::new(self, 28)
     }
     #[doc = "Bit 31 - Enable touch filter."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_filter_en(&mut self) -> TOUCH_FILTER_EN_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_FILTER_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs b/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
index 14c2d030ca..2f78227b01 100644
--- a/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
@@ -87,19 +87,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_denoise_res(&mut self) -> TOUCH_DENOISE_RES_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_DENOISE_RES_W::new(self, 0)
     }
     #[doc = "Bit 2 - Touch pad 0 will be used to denoise."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_denoise_en(&mut self) -> TOUCH_DENOISE_EN_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_DENOISE_EN_W::new(self, 2)
     }
     #[doc = "Bit 8 - Inactive touch pads connect to 0: HighZ, 1: GND."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive_connection(
         &mut self,
     ) -> TOUCH_INACTIVE_CONNECTION_W<TOUCH_SCAN_CTRL_SPEC> {
@@ -107,25 +104,21 @@ impl W {
     }
     #[doc = "Bit 9 - Touch pad 14 will be used as shield_pad."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_shield_pad_en(&mut self) -> TOUCH_SHIELD_PAD_EN_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_SHIELD_PAD_EN_W::new(self, 9)
     }
     #[doc = "Bits 10:24 - Pad enable map for touch scan mode."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_pad_map(&mut self) -> TOUCH_SCAN_PAD_MAP_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_SCAN_PAD_MAP_W::new(self, 10)
     }
     #[doc = "Bits 25:27 - Touch 14 buffer driver strength."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_bufdrv(&mut self) -> TOUCH_BUFDRV_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_BUFDRV_W::new(self, 25)
     }
     #[doc = "Bits 28:31 - Select out one pad as guard_ring."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_ring(&mut self) -> TOUCH_OUT_RING_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_OUT_RING_W::new(self, 28)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_slp_thres.rs b/esp32s2/src/rtc_cntl/touch_slp_thres.rs
index 89b5fc3c5b..6a9b934145 100644
--- a/esp32s2/src/rtc_cntl/touch_slp_thres.rs
+++ b/esp32s2/src/rtc_cntl/touch_slp_thres.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Set the threshold for touch sleep pad."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_th(&mut self) -> TOUCH_SLP_TH_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_TH_W::new(self, 0)
     }
     #[doc = "Bit 26 - Enable the proximity mode of touch sleep pad."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_approach_en(&mut self) -> TOUCH_SLP_APPROACH_EN_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_APPROACH_EN_W::new(self, 26)
     }
     #[doc = "Bits 27:31 - Select sleep pad."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_pad(&mut self) -> TOUCH_SLP_PAD_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_PAD_W::new(self, 27)
     }
diff --git a/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs b/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
index de84b4ba2a..ad0e8961a4 100644
--- a/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Set touch timeout threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout_num(&mut self) -> TOUCH_TIMEOUT_NUM_W<TOUCH_TIMEOUT_CTRL_SPEC> {
         TOUCH_TIMEOUT_NUM_W::new(self, 0)
     }
     #[doc = "Bit 22 - Enable touch timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout_en(&mut self) -> TOUCH_TIMEOUT_EN_W<TOUCH_TIMEOUT_CTRL_SPEC> {
         TOUCH_TIMEOUT_EN_W::new(self, 22)
     }
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs b/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
index c76ad0b3b1..2895cf3255 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
@@ -76,43 +76,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_addr_init(&mut self) -> ULP_CP_MEM_ADDR_INIT_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_ADDR_INIT_W::new(self, 0)
     }
     #[doc = "Bits 11:21"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_addr_size(&mut self) -> ULP_CP_MEM_ADDR_SIZE_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_ADDR_SIZE_W::new(self, 11)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_offset_clr(&mut self) -> ULP_CP_MEM_OFFSET_CLR_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_OFFSET_CLR_W::new(self, 22)
     }
     #[doc = "Bit 28 - ULP-FSM clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_clk_fo(&mut self) -> ULP_CP_CLK_FO_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_CLK_FO_W::new(self, 28)
     }
     #[doc = "Bit 29 - ULP-FSM clock software reset"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_reset(&mut self) -> ULP_CP_RESET_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_RESET_W::new(self, 29)
     }
     #[doc = "Bit 30 - Write 1 to start ULP-FSM by software"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_force_start_top(&mut self) -> ULP_CP_FORCE_START_TOP_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_FORCE_START_TOP_W::new(self, 30)
     }
     #[doc = "Bit 31 - Write 1 to start ULP-FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_start_top(&mut self) -> ULP_CP_START_TOP_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_START_TOP_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_timer.rs b/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
index d1ab32d373..67080cff19 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - ULP coprocessor PC initial address"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_pc_init(&mut self) -> ULP_CP_PC_INIT_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_PC_INIT_W::new(self, 0)
     }
     #[doc = "Bit 29 - Enable the option of ULP coprocessor woken up by RTC GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_gpio_wakeup_ena(&mut self) -> ULP_CP_GPIO_WAKEUP_ENA_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_GPIO_WAKEUP_ENA_W::new(self, 29)
     }
     #[doc = "Bit 30 - Disable the option of ULP coprocessor woken up by RTC GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_gpio_wakeup_clr(&mut self) -> ULP_CP_GPIO_WAKEUP_CLR_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_GPIO_WAKEUP_CLR_W::new(self, 30)
     }
     #[doc = "Bit 31 - ULP coprocessor timer enable bit. 0: Disable hardware Timer. 1: Enable hardware timer"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_SLP_TIMER_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
index ac89820730..98ae94a55d 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:31 - Set sleep cycles for ULP coprocessor timer"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_timer_slp_cycle(&mut self) -> ULP_CP_TIMER_SLP_CYCLE_W<ULP_CP_TIMER_1_SPEC> {
         ULP_CP_TIMER_SLP_CYCLE_W::new(self, 8)
     }
diff --git a/esp32s2/src/rtc_cntl/usb_conf.rs b/esp32s2/src/rtc_cntl/usb_conf.rs
index b38fb707ab..8423dffd3e 100644
--- a/esp32s2/src/rtc_cntl/usb_conf.rs
+++ b/esp32s2/src/rtc_cntl/usb_conf.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vrefh(&mut self) -> USB_VREFH_W<USB_CONF_SPEC> {
         USB_VREFH_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vrefl(&mut self) -> USB_VREFL_W<USB_CONF_SPEC> {
         USB_VREFL_W::new(self, 2)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vref_override(&mut self) -> USB_VREF_OVERRIDE_W<USB_CONF_SPEC> {
         USB_VREF_OVERRIDE_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_pull_override(&mut self) -> USB_PAD_PULL_OVERRIDE_W<USB_CONF_SPEC> {
         USB_PAD_PULL_OVERRIDE_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp_pullup(&mut self) -> USB_DP_PULLUP_W<USB_CONF_SPEC> {
         USB_DP_PULLUP_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp_pulldown(&mut self) -> USB_DP_PULLDOWN_W<USB_CONF_SPEC> {
         USB_DP_PULLDOWN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm_pullup(&mut self) -> USB_DM_PULLUP_W<USB_CONF_SPEC> {
         USB_DM_PULLUP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm_pulldown(&mut self) -> USB_DM_PULLDOWN_W<USB_CONF_SPEC> {
         USB_DM_PULLDOWN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pullup_value(&mut self) -> USB_PULLUP_VALUE_W<USB_CONF_SPEC> {
         USB_PULLUP_VALUE_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable_override(&mut self) -> USB_PAD_ENABLE_OVERRIDE_W<USB_CONF_SPEC> {
         USB_PAD_ENABLE_OVERRIDE_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<USB_CONF_SPEC> {
         USB_PAD_ENABLE_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_txm(&mut self) -> USB_TXM_W<USB_CONF_SPEC> {
         USB_TXM_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_txp(&mut self) -> USB_TXP_W<USB_CONF_SPEC> {
         USB_TXP_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_tx_en(&mut self) -> USB_TX_EN_W<USB_CONF_SPEC> {
         USB_TX_EN_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_tx_en_override(&mut self) -> USB_TX_EN_OVERRIDE_W<USB_CONF_SPEC> {
         USB_TX_EN_OVERRIDE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_reset_disable(&mut self) -> USB_RESET_DISABLE_W<USB_CONF_SPEC> {
         USB_RESET_DISABLE_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn io_mux_reset_disable(&mut self) -> IO_MUX_RESET_DISABLE_W<USB_CONF_SPEC> {
         IO_MUX_RESET_DISABLE_W::new(self, 18)
     }
diff --git a/esp32s2/src/rtc_cntl/wakeup_state.rs b/esp32s2/src/rtc_cntl/wakeup_state.rs
index 19156225f8..307f8eb3f7 100644
--- a/esp32s2/src/rtc_cntl/wakeup_state.rs
+++ b/esp32s2/src/rtc_cntl/wakeup_state.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:31 - Enables the wakeup bitmap."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W<WAKEUP_STATE_SPEC> {
         WAKEUP_ENA_W::new(self, 15)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtconfig0.rs b/esp32s2/src/rtc_cntl/wdtconfig0.rs
index 8fd9e9fa6a..55c55821e5 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig0.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_chip_reset_width(&mut self) -> WDT_CHIP_RESET_WIDTH_W<WDTCONFIG0_SPEC> {
         WDT_CHIP_RESET_WIDTH_W::new(self, 0)
     }
     #[doc = "Bit 8 - wdt reset whole chip enable"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_chip_reset_en(&mut self) -> WDT_CHIP_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_CHIP_RESET_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to pause the watchdog in sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<WDTCONFIG0_SPEC> {
         WDT_PAUSE_IN_SLP_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable WDT reset APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_APPCPU_RESET_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to allow the watchdog to be able to reset CPU."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_PROCPU_RESET_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to enable watchdog when the chip boots from flash."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:15 - Sets the length of the system reset counter."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 13)
     }
     #[doc = "Bits 16:18 - Sets the length of the CPU reset counter."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 16)
     }
     #[doc = "Bits 19:21 - 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 19)
     }
     #[doc = "Bits 22:24 - 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 22)
     }
     #[doc = "Bits 25:27 - 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 28)
     }
     #[doc = "Bit 31 - Set this bit to enable the RTC watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtconfig1.rs b/esp32s2/src/rtc_cntl/wdtconfig1.rs
index 546e8f1885..529dd974ba 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 1."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG1_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtconfig2.rs b/esp32s2/src/rtc_cntl/wdtconfig2.rs
index ad25fe3067..6674c8b410 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 2."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtconfig3.rs b/esp32s2/src/rtc_cntl/wdtconfig3.rs
index f3cef40a2a..00bfea0d5c 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 3."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtconfig4.rs b/esp32s2/src/rtc_cntl/wdtconfig4.rs
index 9c56229b91..3cb6852e0d 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 4."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtfeed.rs b/esp32s2/src/rtc_cntl/wdtfeed.rs
index ab70cd4a4a..81240a8a14 100644
--- a/esp32s2/src/rtc_cntl/wdtfeed.rs
+++ b/esp32s2/src/rtc_cntl/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bit 31 - Set 1 to feed the RTC watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_cntl/wdtwprotect.rs b/esp32s2/src/rtc_cntl/wdtwprotect.rs
index d44cfebf32..5d251872c0 100644
--- a/esp32s2/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32s2/src/rtc_cntl/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Sets the write protection key of the watchdog."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs b/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
index 0ea59afa9f..84dcd1fc59 100644
--- a/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
+++ b/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Configures the divider factor for the 32 kHz crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_clk_factor(&mut self) -> XTAL32K_CLK_FACTOR_W<XTAL32K_CLK_FACTOR_SPEC> {
         XTAL32K_CLK_FACTOR_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_cntl/xtal32k_conf.rs b/esp32s2/src/rtc_cntl/xtal32k_conf.rs
index 16fa84de94..cfca25b989 100644
--- a/esp32s2/src/rtc_cntl/xtal32k_conf.rs
+++ b/esp32s2/src/rtc_cntl/xtal32k_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_return_wait(&mut self) -> XTAL32K_RETURN_WAIT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_RETURN_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 4:19 - Defines the maximum waiting cycle before restarting the 32 kHz crystal oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_restart_wait(&mut self) -> XTAL32K_RESTART_WAIT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_RESTART_WAIT_W::new(self, 4)
     }
     #[doc = "Bits 20:27 - Defines the maximum waiting period for clock detection. If no clock is detected after this period, the 32 kHz crystal oscillator can be regarded as dead."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_timeout(&mut self) -> XTAL32K_WDT_TIMEOUT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_WDT_TIMEOUT_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - Defines the maximum allowed restarting period, within which the 32 kHz crystal oscillator can be regarded as stable."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_stable_thres(&mut self) -> XTAL32K_STABLE_THRES_W<XTAL32K_CONF_SPEC> {
         XTAL32K_STABLE_THRES_W::new(self, 28)
     }
diff --git a/esp32s2/src/rtc_i2c/cmd.rs b/esp32s2/src/rtc_i2c/cmd.rs
index e12377cb91..f33ec5c8d6 100644
--- a/esp32s2/src/rtc_i2c/cmd.rs
+++ b/esp32s2/src/rtc_i2c/cmd.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller"]
     #[inline(always)]
-    #[must_use]
     pub fn command(&mut self) -> COMMAND_W<CMD_SPEC> {
         COMMAND_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/ctrl.rs b/esp32s2/src/rtc_i2c/ctrl.rs
index 6fa5d28a7b..a00a7c5b37 100644
--- a/esp32s2/src/rtc_i2c/ctrl.rs
+++ b/esp32s2/src/rtc_i2c/ctrl.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - SDA output mode. 0: open drain. 1: push pull."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - SCL output mode. 0: open drain. 1: push pull."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to configure RTC I²C as a master."]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
         MS_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1, RTC I2C starts sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
         TRANS_START_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
         TX_LSB_FIRST_W::new(self, 4)
     }
     #[doc = "Bit 5 - This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
         RX_LSB_FIRST_W::new(self, 5)
     }
     #[doc = "Bit 29 - RTC I²C controller clock gate."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_gate_en(&mut self) -> CLK_GATE_EN_W<CTRL_SPEC> {
         CLK_GATE_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - RTC I²C software reset."]
     #[inline(always)]
-    #[must_use]
     pub fn reset(&mut self) -> RESET_W<CTRL_SPEC> {
         RESET_W::new(self, 30)
     }
     #[doc = "Bit 31 - rtc i2c reg clk gating"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_i2c/data.rs b/esp32s2/src/rtc_i2c/data.rs
index ce4eda8a0e..660e3fa865 100644
--- a/esp32s2/src/rtc_i2c/data.rs
+++ b/esp32s2/src/rtc_i2c/data.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:15 - The data sent by slave"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tx_data(&mut self) -> SLAVE_TX_DATA_W<DATA_SPEC> {
         SLAVE_TX_DATA_W::new(self, 8)
     }
diff --git a/esp32s2/src/rtc_i2c/date.rs b/esp32s2/src/rtc_i2c/date.rs
index 5214516741..ea84636fde 100644
--- a/esp32s2/src/rtc_i2c/date.rs
+++ b/esp32s2/src/rtc_i2c/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/int_clr.rs b/esp32s2/src/rtc_i2c/int_clr.rs
index adc021c3fa..6fed92cf9d 100644
--- a/esp32s2/src/rtc_i2c/int_clr.rs
+++ b/esp32s2/src/rtc_i2c/int_clr.rs
@@ -27,55 +27,46 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_CLR_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 0)
     }
     #[doc = "Bit 1 - RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 1)
     }
     #[doc = "Bit 2 - RTC_I2C_MASTER_TRAN_COMP_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_CLR_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 2)
     }
     #[doc = "Bit 3 - RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - RTC_I2C_TIME_OUT_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 4)
     }
     #[doc = "Bit 5 - RTC_I2C_ACK_ERR_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn ack_err(&mut self) -> ACK_ERR_W<INT_CLR_SPEC> {
         ACK_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - RTC_I2C_RX_DATA_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data(&mut self) -> RX_DATA_W<INT_CLR_SPEC> {
         RX_DATA_W::new(self, 6)
     }
     #[doc = "Bit 7 - RTC_I2C_TX_DATA_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data(&mut self) -> TX_DATA_W<INT_CLR_SPEC> {
         TX_DATA_W::new(self, 7)
     }
     #[doc = "Bit 8 - RTC_I2C_DETECT_START_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn detect_start(&mut self) -> DETECT_START_W<INT_CLR_SPEC> {
         DETECT_START_W::new(self, 8)
     }
diff --git a/esp32s2/src/rtc_i2c/int_ena.rs b/esp32s2/src/rtc_i2c/int_ena.rs
index d4f403f614..1d21c1414a 100644
--- a/esp32s2/src/rtc_i2c/int_ena.rs
+++ b/esp32s2/src/rtc_i2c/int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 0)
     }
     #[doc = "Bit 1 - RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
         ARBITRATION_LOST_W::new(self, 1)
     }
     #[doc = "Bit 2 - RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 2)
     }
     #[doc = "Bit 3 - RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - RTC_I2C_TIME_OUT_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
         TIME_OUT_W::new(self, 4)
     }
     #[doc = "Bit 5 - RTC_I2C_ACK_ERR_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn ack_err(&mut self) -> ACK_ERR_W<INT_ENA_SPEC> {
         ACK_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - RTC_I2C_RX_DATA_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data(&mut self) -> RX_DATA_W<INT_ENA_SPEC> {
         RX_DATA_W::new(self, 6)
     }
     #[doc = "Bit 7 - RTC_I2C_TX_DATA_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data(&mut self) -> TX_DATA_W<INT_ENA_SPEC> {
         TX_DATA_W::new(self, 7)
     }
     #[doc = "Bit 8 - RTC_I2C_DETECT_START_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn detect_start(&mut self) -> DETECT_START_W<INT_ENA_SPEC> {
         DETECT_START_W::new(self, 8)
     }
diff --git a/esp32s2/src/rtc_i2c/scl_high.rs b/esp32s2/src/rtc_i2c/scl_high.rs
index 4d9425ed8c..944e44fd5d 100644
--- a/esp32s2/src/rtc_i2c/scl_high.rs
+++ b/esp32s2/src/rtc_i2c/scl_high.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many cycles SCL remains high."]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<SCL_HIGH_SPEC> {
         PERIOD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/scl_low.rs b/esp32s2/src/rtc_i2c/scl_low.rs
index 0804392bae..9ec9d74574 100644
--- a/esp32s2/src/rtc_i2c/scl_low.rs
+++ b/esp32s2/src/rtc_i2c/scl_low.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many clock cycles SCL remains low."]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<SCL_LOW_SPEC> {
         PERIOD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/scl_start_period.rs b/esp32s2/src/rtc_i2c/scl_start_period.rs
index 008edd13ad..d1861cca20 100644
--- a/esp32s2/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s2/src/rtc_i2c/scl_start_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait after generating a start condition."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_start_period(&mut self) -> SCL_START_PERIOD_W<SCL_START_PERIOD_SPEC> {
         SCL_START_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/scl_stop_period.rs b/esp32s2/src/rtc_i2c/scl_stop_period.rs
index 2c0c614fa9..3c311494ba 100644
--- a/esp32s2/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s2/src/rtc_i2c/scl_stop_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait before generating a stop condition."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_stop_period(&mut self) -> SCL_STOP_PERIOD_W<SCL_STOP_PERIOD_SPEC> {
         SCL_STOP_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/sda_duty.rs b/esp32s2/src/rtc_i2c/sda_duty.rs
index 95aad65b6a..cfa0efcace 100644
--- a/esp32s2/src/rtc_i2c/sda_duty.rs
+++ b/esp32s2/src/rtc_i2c/sda_duty.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The number of clock cycles between the SDA switch and the falling edge of SCL."]
     #[inline(always)]
-    #[must_use]
     pub fn num(&mut self) -> NUM_W<SDA_DUTY_SPEC> {
         NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_i2c/slave_addr.rs b/esp32s2/src/rtc_i2c/slave_addr.rs
index e98903771e..786a29941a 100644
--- a/esp32s2/src/rtc_i2c/slave_addr.rs
+++ b/esp32s2/src/rtc_i2c/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - This field is used to enable the slave 10-bit addressing mode."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
         ADDR_10BIT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/rtc_i2c/to.rs b/esp32s2/src/rtc_i2c/to.rs
index e282992871..7ad557b377 100644
--- a/esp32s2/src/rtc_i2c/to.rs
+++ b/esp32s2/src/rtc_i2c/to.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - Timeout threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<TO_SPEC> {
         TIME_OUT_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_io.rs b/esp32s2/src/rtc_io.rs
index 6b9bbcedbb..ce33266761 100644
--- a/esp32s2/src/rtc_io.rs
+++ b/esp32s2/src/rtc_io.rs
@@ -117,6 +117,8 @@ impl RegisterBlock {
         &self.xtal_32n_pad
     }
     #[doc = "0xc8..0xd0 - DAC%s configuration register"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `PAD_DAC1` register.</div>"]
     #[inline(always)]
     pub const fn pad_dac(&self, n: usize) -> &PAD_DAC {
         &self.pad_dac[n]
diff --git a/esp32s2/src/rtc_io/enable_w1tc.rs b/esp32s2/src/rtc_io/enable_w1tc.rs
index 45f8bf1847..c76499a711 100644
--- a/esp32s2/src/rtc_io/enable_w1tc.rs
+++ b/esp32s2/src/rtc_io/enable_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_W1TC_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/ext_wakeup0.rs b/esp32s2/src/rtc_io/ext_wakeup0.rs
index f21a50bc36..0722469d67 100644
--- a/esp32s2/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s2/src/rtc_io/ext_wakeup0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - GPIO\\[0-17\\] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP0_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32s2/src/rtc_io/pad_dac.rs b/esp32s2/src/rtc_io/pad_dac.rs
index b8a9f37f94..cec8f96760 100644
--- a/esp32s2/src/rtc_io/pad_dac.rs
+++ b/esp32s2/src/rtc_io/pad_dac.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 3:10 - Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<PAD_DAC_SPEC> {
         DAC_W::new(self, 3)
     }
     #[doc = "Bit 11 - When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_dac(&mut self) -> XPD_DAC_W<PAD_DAC_SPEC> {
         XPD_DAC_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_xpd_force(&mut self) -> DAC_XPD_FORCE_W<PAD_DAC_SPEC> {
         DAC_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<PAD_DAC_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<PAD_DAC_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<PAD_DAC_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<PAD_DAC_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - DAC_1 function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<PAD_DAC_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<PAD_DAC_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<PAD_DAC_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<PAD_DAC_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<PAD_DAC_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/pin.rs b/esp32s2/src/rtc_io/pin.rs
index 3b78b066f6..342811c6f2 100644
--- a/esp32s2/src/rtc_io/pin.rs
+++ b/esp32s2/src/rtc_io/pin.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - Pad driver selection. 0: normal output. 1: open drain."]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 7:9 - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_pin_int_type(&mut self) -> GPIO_PIN_INT_TYPE_W<PIN_SPEC> {
         GPIO_PIN_INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_pin_wakeup_enable(&mut self) -> GPIO_PIN_WAKEUP_ENABLE_W<PIN_SPEC> {
         GPIO_PIN_WAKEUP_ENABLE_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_debug_sel.rs b/esp32s2/src/rtc_io/rtc_debug_sel.rs
index 697fbbddf6..fddbb033a3 100644
--- a/esp32s2/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s2/src/rtc_io/rtc_debug_sel.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel0(&mut self) -> RTC_DEBUG_SEL0_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL0_W::new(self, 0)
     }
     #[doc = "Bits 5:9"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel1(&mut self) -> RTC_DEBUG_SEL1_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL1_W::new(self, 5)
     }
     #[doc = "Bits 10:14"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel2(&mut self) -> RTC_DEBUG_SEL2_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL2_W::new(self, 10)
     }
     #[doc = "Bits 15:19"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel3(&mut self) -> RTC_DEBUG_SEL3_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL3_W::new(self, 15)
     }
     #[doc = "Bits 20:24"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel4(&mut self) -> RTC_DEBUG_SEL4_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL4_W::new(self, 20)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_12m_no_gating(&mut self) -> RTC_DEBUG_12M_NO_GATING_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_12M_NO_GATING_W::new(self, 25)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_enable.rs b/esp32s2/src/rtc_io/rtc_gpio_enable.rs
index 4be3363b6a..4a256686ba 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_enable.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_enable.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
     #[inline(always)]
-    #[must_use]
     pub fn reg_rtcio_reg_gpio_enable(
         &mut self,
     ) -> REG_RTCIO_REG_GPIO_ENABLE_W<RTC_GPIO_ENABLE_SPEC> {
diff --git a/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs b/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs
index 73d12f83e3..56efcc0b68 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_enable_w1ts(&mut self) -> RTC_GPIO_ENABLE_W1TS_W<RTC_GPIO_ENABLE_W1TS_SPEC> {
         RTC_GPIO_ENABLE_W1TS_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_out.rs b/esp32s2/src/rtc_io/rtc_gpio_out.rs
index 33a0231b9c..c0a5663a5b 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_out.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_out_data(&mut self) -> GPIO_OUT_DATA_W<RTC_GPIO_OUT_SPEC> {
         GPIO_OUT_DATA_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs b/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs
index 38419055d3..f9f6184e28 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_out_data_w1tc(&mut self) -> RTC_GPIO_OUT_DATA_W1TC_W<RTC_GPIO_OUT_W1TC_SPEC> {
         RTC_GPIO_OUT_DATA_W1TC_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs b/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs
index 89758c58b1..8fddfccd2a 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_out_data_w1ts(&mut self) -> RTC_GPIO_OUT_DATA_W1TS_W<RTC_GPIO_OUT_W1TS_SPEC> {
         RTC_GPIO_OUT_DATA_W1TS_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_status.rs b/esp32s2/src/rtc_io/rtc_gpio_status.rs
index 2dcd2abd17..a9b0c098d3 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_status.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_status_int(&mut self) -> GPIO_STATUS_INT_W<RTC_GPIO_STATUS_SPEC> {
         GPIO_STATUS_INT_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_status_w1tc.rs b/esp32s2/src/rtc_io/rtc_gpio_status_w1tc.rs
index ef0cdba4f5..d91b16d0c3 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_status_w1tc.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_status_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_status_int_w1tc(&mut self) -> GPIO_STATUS_INT_W1TC_W<RTC_GPIO_STATUS_W1TC_SPEC> {
         GPIO_STATUS_INT_W1TC_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_gpio_status_w1ts.rs b/esp32s2/src/rtc_io/rtc_gpio_status_w1ts.rs
index 83b06cb205..070fdfda8a 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_status_w1ts.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_status_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_status_int_w1ts(&mut self) -> GPIO_STATUS_INT_W1TS_W<RTC_GPIO_STATUS_W1TS_SPEC> {
         GPIO_STATUS_INT_W1TS_W::new(self, 10)
     }
diff --git a/esp32s2/src/rtc_io/rtc_io_date.rs b/esp32s2/src/rtc_io/rtc_io_date.rs
index 00f3cb676b..24ec16a95d 100644
--- a/esp32s2/src/rtc_io/rtc_io_date.rs
+++ b/esp32s2/src/rtc_io/rtc_io_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn io_date(&mut self) -> IO_DATE_W<RTC_IO_DATE_SPEC> {
         IO_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs b/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
index 8e996ddbd3..9c7255cc41 100644
--- a/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
+++ b/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn io_touch_bufsel(&mut self) -> IO_TOUCH_BUFSEL_W<RTC_IO_TOUCH_CTRL_SPEC> {
         IO_TOUCH_BUFSEL_W::new(self, 0)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn io_touch_bufmode(&mut self) -> IO_TOUCH_BUFMODE_W<RTC_IO_TOUCH_CTRL_SPEC> {
         IO_TOUCH_BUFMODE_W::new(self, 4)
     }
diff --git a/esp32s2/src/rtc_io/rtc_pad19.rs b/esp32s2/src/rtc_io/rtc_pad19.rs
index dce09fae5d..b9a63f1958 100644
--- a/esp32s2/src/rtc_io/rtc_pad19.rs
+++ b/esp32s2/src/rtc_io/rtc_pad19.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD19_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD19_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD19_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD19_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD19_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD19_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD19_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD19_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD19_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/rtc_pad20.rs b/esp32s2/src/rtc_io/rtc_pad20.rs
index 2f2ae333db..1fae9486f2 100644
--- a/esp32s2/src/rtc_io/rtc_pad20.rs
+++ b/esp32s2/src/rtc_io/rtc_pad20.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD20_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD20_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD20_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD20_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD20_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD20_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD20_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD20_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD20_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/rtc_pad21.rs b/esp32s2/src/rtc_io/rtc_pad21.rs
index c0f4f7959f..e5089dced8 100644
--- a/esp32s2/src/rtc_io/rtc_pad21.rs
+++ b/esp32s2/src/rtc_io/rtc_pad21.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD21_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD21_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD21_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD21_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD21_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD21_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD21_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD21_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD21_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/sar_i2c_io.rs b/esp32s2/src/rtc_io/sar_i2c_io.rs
index 45f8dd1730..22ea26fb2d 100644
--- a/esp32s2/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s2/src/rtc_io/sar_i2c_io.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 23:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_DEBUG_BIT_SEL_W::new(self, 23)
     }
     #[doc = "Bits 28:29 - Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SCL_SEL_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SDA_SEL_W::new(self, 30)
     }
diff --git a/esp32s2/src/rtc_io/touch_pad.rs b/esp32s2/src/rtc_io/touch_pad.rs
index 284974add3..c8ad3772f5 100644
--- a/esp32s2/src/rtc_io/touch_pad.rs
+++ b/esp32s2/src/rtc_io/touch_pad.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 0: no sleep mode. 1: enable sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - Connect the RTC pad input to digital pad input. 0 is available."]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - Touch sensor power on."]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - The tie option of touch sensor. 0: tie low. 1: tie high."]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - Start touch sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bits 23:25 - Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4."]
     #[inline(always)]
-    #[must_use]
     pub fn dac(&mut self) -> DAC_W<TOUCH_PAD_SPEC> {
         DAC_W::new(self, 23)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/xtal_32n_pad.rs b/esp32s2/src/rtc_io/xtal_32n_pad.rs
index 14d8729720..b1a4283ca6 100644
--- a/esp32s2/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s2/src/rtc_io/xtal_32n_pad.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_ie(&mut self) -> X32N_FUN_IE_W<XTAL_32N_PAD_SPEC> {
         X32N_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_oe(&mut self) -> X32N_SLP_OE_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_ie(&mut self) -> X32N_SLP_IE_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_sel(&mut self) -> X32N_SLP_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_sel(&mut self) -> X32N_FUN_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_mux_sel(&mut self) -> X32N_MUX_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rue(&mut self) -> X32N_RUE_W<XTAL_32N_PAD_SPEC> {
         X32N_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rde(&mut self) -> X32N_RDE_W<XTAL_32N_PAD_SPEC> {
         X32N_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_drv(&mut self) -> X32N_DRV_W<XTAL_32N_PAD_SPEC> {
         X32N_DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/xtal_32p_pad.rs b/esp32s2/src/rtc_io/xtal_32p_pad.rs
index acdc34840c..bea05b001d 100644
--- a/esp32s2/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s2/src/rtc_io/xtal_32p_pad.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_ie(&mut self) -> X32P_FUN_IE_W<XTAL_32P_PAD_SPEC> {
         X32P_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_oe(&mut self) -> X32P_SLP_OE_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_ie(&mut self) -> X32P_SLP_IE_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode. 0: no sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_sel(&mut self) -> X32P_SLP_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - Function selection."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_sel(&mut self) -> X32P_FUN_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO. 0: use digital GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_mux_sel(&mut self) -> X32P_MUX_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rue(&mut self) -> X32P_RUE_W<XTAL_32P_PAD_SPEC> {
         X32P_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rde(&mut self) -> X32P_RDE_W<XTAL_32P_PAD_SPEC> {
         X32P_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA."]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_drv(&mut self) -> X32P_DRV_W<XTAL_32P_PAD_SPEC> {
         X32P_DRV_W::new(self, 29)
     }
diff --git a/esp32s2/src/rtc_io/xtl_ext_ctr.rs b/esp32s2/src/rtc_io/xtl_ext_ctr.rs
index db7c53335f..0146292b17 100644
--- a/esp32s2/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s2/src/rtc_io/xtl_ext_ctr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG\\[30\\] is the crystal power down enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<XTL_EXT_CTR_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32s2/src/sens/sar_amp_ctrl1.rs b/esp32s2/src/sens/sar_amp_ctrl1.rs
index 443388e161..342e074eb2 100644
--- a/esp32s2/src/sens/sar_amp_ctrl1.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W<SAR_AMP_CTRL1_SPEC> {
         SAR_AMP_WAIT1_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W<SAR_AMP_CTRL1_SPEC> {
         SAR_AMP_WAIT2_W::new(self, 16)
     }
diff --git a/esp32s2/src/sens/sar_amp_ctrl2.rs b/esp32s2/src/sens/sar_amp_ctrl2.rs
index a9ea12a64f..023cd9f31b 100644
--- a/esp32s2/src/sens/sar_amp_ctrl2.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl2.rs
@@ -97,31 +97,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dac_xpd_fsm_idle(&mut self) -> SAR1_DAC_XPD_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR1_DAC_XPD_FSM_IDLE_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_amp_fsm_idle(&mut self) -> XPD_SAR_AMP_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         XPD_SAR_AMP_FSM_IDLE_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_fsm_idle(&mut self) -> AMP_RST_FB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         AMP_RST_FB_FSM_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_fsm_idle(&mut self) -> AMP_SHORT_REF_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         AMP_SHORT_REF_FSM_IDLE_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_fsm_idle(
         &mut self,
     ) -> AMP_SHORT_REF_GND_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
@@ -129,19 +124,16 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_fsm_idle(&mut self) -> XPD_SAR_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         XPD_SAR_FSM_IDLE_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_RSTB_FSM_IDLE_W::new(self, 6)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W<SAR_AMP_CTRL2_SPEC> {
         SAR_AMP_WAIT3_W::new(self, 16)
     }
diff --git a/esp32s2/src/sens/sar_amp_ctrl3.rs b/esp32s2/src/sens/sar_amp_ctrl3.rs
index 1cab0030c0..746c04ac42 100644
--- a/esp32s2/src/sens/sar_amp_ctrl3.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl3.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W<SAR_AMP_CTRL3_SPEC> {
         SAR1_DAC_XPD_FSM_W::new(self, 0)
     }
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W<SAR_AMP_CTRL3_SPEC> {
         XPD_SAR_AMP_FSM_W::new(self, 4)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_RST_FB_FSM_W::new(self, 8)
     }
     #[doc = "Bits 12:15"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_SHORT_REF_FSM_W::new(self, 12)
     }
     #[doc = "Bits 16:19"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_SHORT_REF_GND_FSM_W::new(self, 16)
     }
     #[doc = "Bits 20:23"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W<SAR_AMP_CTRL3_SPEC> {
         XPD_SAR_FSM_W::new(self, 20)
     }
     #[doc = "Bits 24:27"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rstb_fsm(&mut self) -> SAR_RSTB_FSM_W<SAR_AMP_CTRL3_SPEC> {
         SAR_RSTB_FSM_W::new(self, 24)
     }
diff --git a/esp32s2/src/sens/sar_atten1.rs b/esp32s2/src/sens/sar_atten1.rs
index 476a96f873..9db784fb63 100644
--- a/esp32s2/src/sens/sar_atten1.rs
+++ b/esp32s2/src/sens/sar_atten1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad. \\[1:0\\] is used for channel 0, \\[3:2\\] is used for channel 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W<SAR_ATTEN1_SPEC> {
         SAR1_ATTEN_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_atten2.rs b/esp32s2/src/sens/sar_atten2.rs
index 35f8b5a133..2027ff6ed1 100644
--- a/esp32s2/src/sens/sar_atten2.rs
+++ b/esp32s2/src/sens/sar_atten2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad. \\[1:0\\] is used for channel 0, \\[3:2\\] is used for channel 1, etc."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W<SAR_ATTEN2_SPEC> {
         SAR2_ATTEN_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_cocpu_int_clr.rs b/esp32s2/src/sens/sar_cocpu_int_clr.rs
index baab14fa2b..4a43aca92b 100644
--- a/esp32s2/src/sens/sar_cocpu_int_clr.rs
+++ b/esp32s2/src/sens/sar_cocpu_int_clr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - TOUCH_DONE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_done_int_clr(
         &mut self,
     ) -> COCPU_TOUCH_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -35,7 +34,6 @@ impl W {
     }
     #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_inactive_int_clr(
         &mut self,
     ) -> COCPU_TOUCH_INACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -43,7 +41,6 @@ impl W {
     }
     #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_active_int_clr(
         &mut self,
     ) -> COCPU_TOUCH_ACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -51,37 +48,31 @@ impl W {
     }
     #[doc = "Bit 3 - SARADC1_DONE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_saradc1_int_clr(&mut self) -> COCPU_SARADC1_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_SARADC1_INT_CLR_W::new(self, 3)
     }
     #[doc = "Bit 4 - SARADC2_DONE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_saradc2_int_clr(&mut self) -> COCPU_SARADC2_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_SARADC2_INT_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5 - TSENS_DONE_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_tsens_int_clr(&mut self) -> COCPU_TSENS_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_TSENS_INT_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6 - RISCV_START_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_int_clr(&mut self) -> COCPU_START_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_START_INT_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7 - SW_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sw_int_clr(&mut self) -> COCPU_SW_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_SW_INT_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - SWD_INT interrupt clear bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_swd_int_clr(&mut self) -> COCPU_SWD_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         COCPU_SWD_INT_CLR_W::new(self, 8)
     }
diff --git a/esp32s2/src/sens/sar_cocpu_int_ena.rs b/esp32s2/src/sens/sar_cocpu_int_ena.rs
index ec4e6206b9..e5128341bb 100644
--- a/esp32s2/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s2/src/sens/sar_cocpu_int_ena.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - TOUCH_DONE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_done_int_ena(
         &mut self,
     ) -> COCPU_TOUCH_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_inactive_int_ena(
         &mut self,
     ) -> COCPU_TOUCH_INACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_touch_active_int_ena(
         &mut self,
     ) -> COCPU_TOUCH_ACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -134,37 +131,31 @@ impl W {
     }
     #[doc = "Bit 3 - SARADC1_DONE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_saradc1_int_ena(&mut self) -> COCPU_SARADC1_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_SARADC1_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 4 - SARADC2_DONE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_saradc2_int_ena(&mut self) -> COCPU_SARADC2_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_SARADC2_INT_ENA_W::new(self, 4)
     }
     #[doc = "Bit 5 - TSENS_DONE_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_tsens_int_ena(&mut self) -> COCPU_TSENS_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_TSENS_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6 - RISCV_START_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_int_ena(&mut self) -> COCPU_START_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_START_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - SW_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sw_int_ena(&mut self) -> COCPU_SW_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_SW_INT_ENA_W::new(self, 7)
     }
     #[doc = "Bit 8 - SWD_INT interrupt enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_swd_int_ena(&mut self) -> COCPU_SWD_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         COCPU_SWD_INT_ENA_W::new(self, 8)
     }
diff --git a/esp32s2/src/sens/sar_cocpu_state.rs b/esp32s2/src/sens/sar_cocpu_state.rs
index a90d44a6be..b5e194932f 100644
--- a/esp32s2/src/sens/sar_cocpu_state.rs
+++ b/esp32s2/src/sens/sar_cocpu_state.rs
@@ -56,7 +56,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 25 - Trigger ULP-RISCV debug registers"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_dbg_trigger(&mut self) -> COCPU_DBG_TRIGGER_W<SAR_COCPU_STATE_SPEC> {
         COCPU_DBG_TRIGGER_W::new(self, 25)
     }
diff --git a/esp32s2/src/sens/sar_dac_ctrl1.rs b/esp32s2/src/sens/sar_dac_ctrl1.rs
index d93d658660..d9aa9366d0 100644
--- a/esp32s2/src/sens/sar_dac_ctrl1.rs
+++ b/esp32s2/src/sens/sar_dac_ctrl1.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Frequency step for CW generator can be used to adjust the frequency."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_fstep(&mut self) -> SW_FSTEP_W<SAR_DAC_CTRL1_SPEC> {
         SW_FSTEP_W::new(self, 0)
     }
     #[doc = "Bit 16 - 0: disable CW generator. 1: enable CW generator."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_tone_en(&mut self) -> SW_TONE_EN_W<SAR_DAC_CTRL1_SPEC> {
         SW_TONE_EN_W::new(self, 16)
     }
     #[doc = "Bits 17:21"]
     #[inline(always)]
-    #[must_use]
     pub fn debug_bit_sel(&mut self) -> DEBUG_BIT_SEL_W<SAR_DAC_CTRL1_SPEC> {
         DEBUG_BIT_SEL_W::new(self, 17)
     }
     #[doc = "Bit 22 - 0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dig_force(&mut self) -> DAC_DIG_FORCE_W<SAR_DAC_CTRL1_SPEC> {
         DAC_DIG_FORCE_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: force PDAC_CLK to low"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_force_low(&mut self) -> DAC_CLK_FORCE_LOW_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_FORCE_LOW_W::new(self, 23)
     }
     #[doc = "Bit 24 - 1: force PDAC_CLK to high"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_force_high(&mut self) -> DAC_CLK_FORCE_HIGH_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_FORCE_HIGH_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: invert PDAC_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_inv(&mut self) -> DAC_CLK_INV_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLK_INV_W::new(self, 25)
     }
     #[doc = "Bit 26 - Reset DAC by software."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_reset(&mut self) -> DAC_RESET_W<SAR_DAC_CTRL1_SPEC> {
         DAC_RESET_W::new(self, 26)
     }
     #[doc = "Bit 27 - DAC clock gate enable bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clkgate_en(&mut self) -> DAC_CLKGATE_EN_W<SAR_DAC_CTRL1_SPEC> {
         DAC_CLKGATE_EN_W::new(self, 27)
     }
diff --git a/esp32s2/src/sens/sar_dac_ctrl2.rs b/esp32s2/src/sens/sar_dac_ctrl2.rs
index 9c38cd60eb..7e5a9a7e70 100644
--- a/esp32s2/src/sens/sar_dac_ctrl2.rs
+++ b/esp32s2/src/sens/sar_dac_ctrl2.rs
@@ -140,7 +140,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_DC1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc(&mut self, n: u8) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -148,13 +147,11 @@ impl W {
     }
     #[doc = "Bits 0:7 - DC offset for DAC1 CW generator."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc1(&mut self) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         DAC_DC_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - DC offset for DAC2 CW generator."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_dc2(&mut self) -> DAC_DC_W<SAR_DAC_CTRL2_SPEC> {
         DAC_DC_W::new(self, 8)
     }
@@ -162,7 +159,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_SCALE1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale(&mut self, n: u8) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -170,13 +166,11 @@ impl W {
     }
     #[doc = "Bits 16:17 - DAC1 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale1(&mut self) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         DAC_SCALE_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - DAC2 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_scale2(&mut self) -> DAC_SCALE_W<SAR_DAC_CTRL2_SPEC> {
         DAC_SCALE_W::new(self, 18)
     }
@@ -184,7 +178,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_INV1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv(&mut self, n: u8) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -192,13 +185,11 @@ impl W {
     }
     #[doc = "Bits 20:21 - Invert DAC1. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv1(&mut self) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         DAC_INV_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - Invert DAC2. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_inv2(&mut self) -> DAC_INV_W<SAR_DAC_CTRL2_SPEC> {
         DAC_INV_W::new(self, 22)
     }
@@ -206,7 +197,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DAC_CW_EN1` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en(&mut self, n: u8) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -214,13 +204,11 @@ impl W {
     }
     #[doc = "Bit 24 - 1: to select CW generator as source to PDAC1_DAC\\[7:0\\] 0: to select register reg_pdac1_dac\\[7:0\\] as source to PDAC1_DAC\\[7:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en1(&mut self) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         DAC_CW_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: to select CW generator as source to PDAC2_DAC\\[7:0\\] 0: to select register reg_pdac2_dac\\[7:0\\] as source to PDAC2_DAC\\[7:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_cw_en2(&mut self) -> DAC_CW_EN_W<SAR_DAC_CTRL2_SPEC> {
         DAC_CW_EN_W::new(self, 25)
     }
diff --git a/esp32s2/src/sens/sar_hall_ctrl.rs b/esp32s2/src/sens/sar_hall_ctrl.rs
index d51305efe5..f4a8995b4f 100644
--- a/esp32s2/src/sens/sar_hall_ctrl.rs
+++ b/esp32s2/src/sens/sar_hall_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall(&mut self) -> XPD_HALL_W<SAR_HALL_CTRL_SPEC> {
         XPD_HALL_W::new(self, 28)
     }
     #[doc = "Bit 29 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall_force(&mut self) -> XPD_HALL_FORCE_W<SAR_HALL_CTRL_SPEC> {
         XPD_HALL_FORCE_W::new(self, 29)
     }
     #[doc = "Bit 30 - Reverse phase of hall sensor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase(&mut self) -> HALL_PHASE_W<SAR_HALL_CTRL_SPEC> {
         HALL_PHASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase_force(&mut self) -> HALL_PHASE_FORCE_W<SAR_HALL_CTRL_SPEC> {
         HALL_PHASE_FORCE_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_i2c_ctrl.rs b/esp32s2/src/sens/sar_i2c_ctrl.rs
index 7b8d8ed74a..668a8d7fd0 100644
--- a/esp32s2/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s2/src/sens/sar_i2c_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_CTRL_W::new(self, 0)
     }
     #[doc = "Bit 28 - Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_W::new(self, 28)
     }
     #[doc = "Bit 29 - 0: RTC I2C started by FSM. 1: RTC I2C started by software."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_FORCE_W::new(self, 29)
     }
diff --git a/esp32s2/src/sens/sar_io_mux_conf.rs b/esp32s2/src/sens/sar_io_mux_conf.rs
index 92bb370997..c321536423 100644
--- a/esp32s2/src/sens/sar_io_mux_conf.rs
+++ b/esp32s2/src/sens/sar_io_mux_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - Reset IO MUX by software"]
     #[inline(always)]
-    #[must_use]
     pub fn iomux_reset(&mut self) -> IOMUX_RESET_W<SAR_IO_MUX_CONF_SPEC> {
         IOMUX_RESET_W::new(self, 30)
     }
     #[doc = "Bit 31 - IO MUX clock gate enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn iomux_clk_gate_en(&mut self) -> IOMUX_CLK_GATE_EN_W<SAR_IO_MUX_CONF_SPEC> {
         IOMUX_CLK_GATE_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_meas1_ctrl1.rs b/esp32s2/src/sens/sar_meas1_ctrl1.rs
index c3c877f0fe..d61c02f6df 100644
--- a/esp32s2/src/sens/sar_meas1_ctrl1.rs
+++ b/esp32s2/src/sens/sar_meas1_ctrl1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 22 - SAR ADC software reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_saradc_reset(&mut self) -> RTC_SARADC_RESET_W<SAR_MEAS1_CTRL1_SPEC> {
         RTC_SARADC_RESET_W::new(self, 22)
     }
     #[doc = "Bit 23 - Enable bit of SAR ADC clock gate."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_saradc_clkgate_en(&mut self) -> RTC_SARADC_CLKGATE_EN_W<SAR_MEAS1_CTRL1_SPEC> {
         RTC_SARADC_CLKGATE_EN_W::new(self, 23)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W<SAR_MEAS1_CTRL1_SPEC> {
         FORCE_XPD_AMP_W::new(self, 24)
     }
     #[doc = "Bits 26:27"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_RST_FB_FORCE_W::new(self, 26)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_SHORT_REF_FORCE_W::new(self, 28)
     }
     #[doc = "Bits 30:31"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_SHORT_REF_GND_FORCE_W::new(self, 30)
     }
diff --git a/esp32s2/src/sens/sar_meas1_ctrl2.rs b/esp32s2/src/sens/sar_meas1_ctrl2.rs
index d467477f4d..b44ffd99f2 100644
--- a/esp32s2/src/sens/sar_meas1_ctrl2.rs
+++ b/esp32s2/src/sens/sar_meas1_ctrl2.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W<SAR_MEAS1_CTRL2_SPEC> {
         MEAS1_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by software. 0: SAR ADC1 controller is started by ULP coprocessor."]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
         MEAS1_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap, active only when SENS_SAR1_EN_PAD_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W<SAR_MEAS1_CTRL2_SPEC> {
         SAR1_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by software. 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
         SAR1_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_meas1_mux.rs b/esp32s2/src/sens/sar_meas1_mux.rs
index ccedb6800d..93ca46a7df 100644
--- a/esp32s2/src/sens/sar_meas1_mux.rs
+++ b/esp32s2/src/sens/sar_meas1_mux.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W<SAR_MEAS1_MUX_SPEC> {
         SAR1_DIG_FORCE_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_meas2_ctrl1.rs b/esp32s2/src/sens/sar_meas2_ctrl1.rs
index 71ad88e87f..d7cb743742 100644
--- a/esp32s2/src/sens/sar_meas2_ctrl1.rs
+++ b/esp32s2/src/sens/sar_meas2_ctrl1.rs
@@ -92,43 +92,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - rtc control pwdet enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_cal_en(&mut self) -> SAR2_PWDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_PWDET_CAL_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - rtc control pkdet enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pkdet_cal_en(&mut self) -> SAR2_PKDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_PKDET_CAL_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - SAR2_EN_TEST"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_test(&mut self) -> SAR2_EN_TEST_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_EN_TEST_W::new(self, 5)
     }
     #[doc = "Bits 6:7"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rstb_force(&mut self) -> SAR2_RSTB_FORCE_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_RSTB_FORCE_W::new(self, 6)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_standby_wait(&mut self) -> SAR2_STANDBY_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_STANDBY_WAIT_W::new(self, 8)
     }
     #[doc = "Bits 16:23"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rstb_wait(&mut self) -> SAR2_RSTB_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_RSTB_WAIT_W::new(self, 16)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_xpd_wait(&mut self) -> SAR2_XPD_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR2_XPD_WAIT_W::new(self, 24)
     }
diff --git a/esp32s2/src/sens/sar_meas2_ctrl2.rs b/esp32s2/src/sens/sar_meas2_ctrl2.rs
index 68bf2c5ba9..ae89d6d8e2 100644
--- a/esp32s2/src/sens/sar_meas2_ctrl2.rs
+++ b/esp32s2/src/sens/sar_meas2_ctrl2.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W<SAR_MEAS2_CTRL2_SPEC> {
         MEAS2_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by software. 0: SAR ADC2 controller is started by ULP coprocessor."]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
         MEAS2_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap, active only whenSENS_SAR2_EN_PAD_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W<SAR_MEAS2_CTRL2_SPEC> {
         SAR2_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by software. 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
         SAR2_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_meas2_mux.rs b/esp32s2/src/sens/sar_meas2_mux.rs
index abb6fb7e86..355b5bc450 100644
--- a/esp32s2/src/sens/sar_meas2_mux.rs
+++ b/esp32s2/src/sens/sar_meas2_mux.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 28:30 - SAR2_PWDET_CCT, PA power detector capacitance tuning."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<SAR_MEAS2_MUX_SPEC> {
         SAR2_PWDET_CCT_W::new(self, 28)
     }
     #[doc = "Bit 31 - In sleep, force to use RTC to control ADC."]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rtc_force(&mut self) -> SAR2_RTC_FORCE_W<SAR_MEAS2_MUX_SPEC> {
         SAR2_RTC_FORCE_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_nouse.rs b/esp32s2/src/sens/sar_nouse.rs
index 7f35cf267f..0bbd57638d 100644
--- a/esp32s2/src/sens/sar_nouse.rs
+++ b/esp32s2/src/sens/sar_nouse.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - sar nouse"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_nouse(&mut self) -> SAR_NOUSE_W<SAR_NOUSE_SPEC> {
         SAR_NOUSE_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_power_xpd_sar.rs b/esp32s2/src/sens/sar_power_xpd_sar.rs
index 7ca1a933e0..8e8dbb2640 100644
--- a/esp32s2/src/sens/sar_power_xpd_sar.rs
+++ b/esp32s2/src/sens/sar_power_xpd_sar.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_sar(&mut self) -> FORCE_XPD_SAR_W<SAR_POWER_XPD_SAR_SPEC> {
         FORCE_XPD_SAR_W::new(self, 29)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn sarclk_en(&mut self) -> SARCLK_EN_W<SAR_POWER_XPD_SAR_SPEC> {
         SARCLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/sens/sar_reader1_ctrl.rs b/esp32s2/src/sens/sar_reader1_ctrl.rs
index 33580b3412..a71a6d1448 100644
--- a/esp32s2/src/sens/sar_reader1_ctrl.rs
+++ b/esp32s2/src/sens/sar_reader1_ctrl.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Clock divider."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_clk_div(&mut self) -> SAR1_CLK_DIV_W<SAR_READER1_CTRL_SPEC> {
         SAR1_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_clk_gated(&mut self) -> SAR1_CLK_GATED_W<SAR_READER1_CTRL_SPEC> {
         SAR1_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_sample_num(&mut self) -> SAR1_SAMPLE_NUM_W<SAR_READER1_CTRL_SPEC> {
         SAR1_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 28 - Invert SAR ADC1 data."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_data_inv(&mut self) -> SAR1_DATA_INV_W<SAR_READER1_CTRL_SPEC> {
         SAR1_DATA_INV_W::new(self, 28)
     }
     #[doc = "Bit 29 - Enable SAR ADC1 to send out interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_int_en(&mut self) -> SAR1_INT_EN_W<SAR_READER1_CTRL_SPEC> {
         SAR1_INT_EN_W::new(self, 29)
     }
diff --git a/esp32s2/src/sens/sar_reader2_ctrl.rs b/esp32s2/src/sens/sar_reader2_ctrl.rs
index e25bcbd298..6b4cb5f245 100644
--- a/esp32s2/src/sens/sar_reader2_ctrl.rs
+++ b/esp32s2/src/sens/sar_reader2_ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_clk_div(&mut self) -> SAR2_CLK_DIV_W<SAR_READER2_CTRL_SPEC> {
         SAR2_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_wait_arb_cycle(&mut self) -> SAR2_WAIT_ARB_CYCLE_W<SAR_READER2_CTRL_SPEC> {
         SAR2_WAIT_ARB_CYCLE_W::new(self, 16)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_clk_gated(&mut self) -> SAR2_CLK_GATED_W<SAR_READER2_CTRL_SPEC> {
         SAR2_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_sample_num(&mut self) -> SAR2_SAMPLE_NUM_W<SAR_READER2_CTRL_SPEC> {
         SAR2_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 29 - Invert SAR ADC2 data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_data_inv(&mut self) -> SAR2_DATA_INV_W<SAR_READER2_CTRL_SPEC> {
         SAR2_DATA_INV_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_int_en(&mut self) -> SAR2_INT_EN_W<SAR_READER2_CTRL_SPEC> {
         SAR2_INT_EN_W::new(self, 30)
     }
diff --git a/esp32s2/src/sens/sar_slave_addr1.rs b/esp32s2/src/sens/sar_slave_addr1.rs
index 6cf448995d..729edce572 100644
--- a/esp32s2/src/sens/sar_slave_addr1.rs
+++ b/esp32s2/src/sens/sar_slave_addr1.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 1"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr1(&mut self) -> I2C_SLAVE_ADDR1_W<SAR_SLAVE_ADDR1_SPEC> {
         I2C_SLAVE_ADDR1_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - RTC I2C slave address 0"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr0(&mut self) -> I2C_SLAVE_ADDR0_W<SAR_SLAVE_ADDR1_SPEC> {
         I2C_SLAVE_ADDR0_W::new(self, 11)
     }
diff --git a/esp32s2/src/sens/sar_slave_addr2.rs b/esp32s2/src/sens/sar_slave_addr2.rs
index 9696837c51..4541122a70 100644
--- a/esp32s2/src/sens/sar_slave_addr2.rs
+++ b/esp32s2/src/sens/sar_slave_addr2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 3"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr3(&mut self) -> I2C_SLAVE_ADDR3_W<SAR_SLAVE_ADDR2_SPEC> {
         I2C_SLAVE_ADDR3_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - RTC I2C slave address 2"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr2(&mut self) -> I2C_SLAVE_ADDR2_W<SAR_SLAVE_ADDR2_SPEC> {
         I2C_SLAVE_ADDR2_W::new(self, 11)
     }
diff --git a/esp32s2/src/sens/sar_slave_addr3.rs b/esp32s2/src/sens/sar_slave_addr3.rs
index debe146d8b..4d68b97388 100644
--- a/esp32s2/src/sens/sar_slave_addr3.rs
+++ b/esp32s2/src/sens/sar_slave_addr3.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr5(&mut self) -> I2C_SLAVE_ADDR5_W<SAR_SLAVE_ADDR3_SPEC> {
         I2C_SLAVE_ADDR5_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - RTC I2C slave address 4"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr4(&mut self) -> I2C_SLAVE_ADDR4_W<SAR_SLAVE_ADDR3_SPEC> {
         I2C_SLAVE_ADDR4_W::new(self, 11)
     }
diff --git a/esp32s2/src/sens/sar_slave_addr4.rs b/esp32s2/src/sens/sar_slave_addr4.rs
index c02a2f742e..efda4d7818 100644
--- a/esp32s2/src/sens/sar_slave_addr4.rs
+++ b/esp32s2/src/sens/sar_slave_addr4.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 7"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr7(&mut self) -> I2C_SLAVE_ADDR7_W<SAR_SLAVE_ADDR4_SPEC> {
         I2C_SLAVE_ADDR7_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - RTC I2C slave address 6"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_slave_addr6(&mut self) -> I2C_SLAVE_ADDR6_W<SAR_SLAVE_ADDR4_SPEC> {
         I2C_SLAVE_ADDR6_W::new(self, 11)
     }
diff --git a/esp32s2/src/sens/sar_touch_chn_st.rs b/esp32s2/src/sens/sar_touch_chn_st.rs
index 676a4254e5..6b4ec5fb8b 100644
--- a/esp32s2/src/sens/sar_touch_chn_st.rs
+++ b/esp32s2/src/sens/sar_touch_chn_st.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:29 - Clear touch channel"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_channel_clr(&mut self) -> TOUCH_CHANNEL_CLR_W<SAR_TOUCH_CHN_ST_SPEC> {
         TOUCH_CHANNEL_CLR_W::new(self, 15)
     }
diff --git a/esp32s2/src/sens/sar_touch_conf.rs b/esp32s2/src/sens/sar_touch_conf.rs
index 863f4242ef..d71d73f676 100644
--- a/esp32s2/src/sens/sar_touch_conf.rs
+++ b/esp32s2/src/sens/sar_touch_conf.rs
@@ -82,37 +82,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - Enable touch controller output."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_outen(&mut self) -> TOUCH_OUTEN_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_OUTEN_W::new(self, 0)
     }
     #[doc = "Bit 15 - Clear all touch active status."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_status_clr(&mut self) -> TOUCH_STATUS_CLR_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_STATUS_CLR_W::new(self, 15)
     }
     #[doc = "Bits 16:17 - 0 and 1: touch_raw_data; 2: base_line; 3: touch_smooth_data."]
     #[inline(always)]
-    #[must_use]
     pub fn touch_data_sel(&mut self) -> TOUCH_DATA_SEL_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_DATA_SEL_W::new(self, 16)
     }
     #[doc = "Bits 20:23 - Indicate which pad is selected as proximity pad2"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_pad2(&mut self) -> TOUCH_APPROACH_PAD2_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_APPROACH_PAD2_W::new(self, 20)
     }
     #[doc = "Bits 24:27 - Indicate which pad is selected as proximity pad1"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_pad1(&mut self) -> TOUCH_APPROACH_PAD1_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_APPROACH_PAD1_W::new(self, 24)
     }
     #[doc = "Bits 28:31 - Indicate which pad is selected as proximity pad0"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_pad0(&mut self) -> TOUCH_APPROACH_PAD0_W<SAR_TOUCH_CONF_SPEC> {
         TOUCH_APPROACH_PAD0_W::new(self, 28)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres1.rs b/esp32s2/src/sens/sar_touch_thres1.rs
index e006b0ca78..4427119ba6 100644
--- a/esp32s2/src/sens/sar_touch_thres1.rs
+++ b/esp32s2/src/sens/sar_touch_thres1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th1(&mut self) -> TOUCH_OUT_TH1_W<SAR_TOUCH_THRES1_SPEC> {
         TOUCH_OUT_TH1_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres10.rs b/esp32s2/src/sens/sar_touch_thres10.rs
index 1c857c015c..397fb5ed11 100644
--- a/esp32s2/src/sens/sar_touch_thres10.rs
+++ b/esp32s2/src/sens/sar_touch_thres10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th10(&mut self) -> TOUCH_OUT_TH10_W<SAR_TOUCH_THRES10_SPEC> {
         TOUCH_OUT_TH10_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres11.rs b/esp32s2/src/sens/sar_touch_thres11.rs
index 4ee5ef8514..b903ad8929 100644
--- a/esp32s2/src/sens/sar_touch_thres11.rs
+++ b/esp32s2/src/sens/sar_touch_thres11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th11(&mut self) -> TOUCH_OUT_TH11_W<SAR_TOUCH_THRES11_SPEC> {
         TOUCH_OUT_TH11_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres12.rs b/esp32s2/src/sens/sar_touch_thres12.rs
index e21e833ad3..7196871edb 100644
--- a/esp32s2/src/sens/sar_touch_thres12.rs
+++ b/esp32s2/src/sens/sar_touch_thres12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th12(&mut self) -> TOUCH_OUT_TH12_W<SAR_TOUCH_THRES12_SPEC> {
         TOUCH_OUT_TH12_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres13.rs b/esp32s2/src/sens/sar_touch_thres13.rs
index d0686c0f56..201f253fb2 100644
--- a/esp32s2/src/sens/sar_touch_thres13.rs
+++ b/esp32s2/src/sens/sar_touch_thres13.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th13(&mut self) -> TOUCH_OUT_TH13_W<SAR_TOUCH_THRES13_SPEC> {
         TOUCH_OUT_TH13_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres14.rs b/esp32s2/src/sens/sar_touch_thres14.rs
index 8e70e4daff..13dbad8390 100644
--- a/esp32s2/src/sens/sar_touch_thres14.rs
+++ b/esp32s2/src/sens/sar_touch_thres14.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th14(&mut self) -> TOUCH_OUT_TH14_W<SAR_TOUCH_THRES14_SPEC> {
         TOUCH_OUT_TH14_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres2.rs b/esp32s2/src/sens/sar_touch_thres2.rs
index 91530f800d..0a40b28abf 100644
--- a/esp32s2/src/sens/sar_touch_thres2.rs
+++ b/esp32s2/src/sens/sar_touch_thres2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th2(&mut self) -> TOUCH_OUT_TH2_W<SAR_TOUCH_THRES2_SPEC> {
         TOUCH_OUT_TH2_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres3.rs b/esp32s2/src/sens/sar_touch_thres3.rs
index 166630df0b..acc46eb1d7 100644
--- a/esp32s2/src/sens/sar_touch_thres3.rs
+++ b/esp32s2/src/sens/sar_touch_thres3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th3(&mut self) -> TOUCH_OUT_TH3_W<SAR_TOUCH_THRES3_SPEC> {
         TOUCH_OUT_TH3_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres4.rs b/esp32s2/src/sens/sar_touch_thres4.rs
index b6148d0d25..1aeede9047 100644
--- a/esp32s2/src/sens/sar_touch_thres4.rs
+++ b/esp32s2/src/sens/sar_touch_thres4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th4(&mut self) -> TOUCH_OUT_TH4_W<SAR_TOUCH_THRES4_SPEC> {
         TOUCH_OUT_TH4_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres5.rs b/esp32s2/src/sens/sar_touch_thres5.rs
index 305cab3d68..36e7a57c10 100644
--- a/esp32s2/src/sens/sar_touch_thres5.rs
+++ b/esp32s2/src/sens/sar_touch_thres5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th5(&mut self) -> TOUCH_OUT_TH5_W<SAR_TOUCH_THRES5_SPEC> {
         TOUCH_OUT_TH5_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres6.rs b/esp32s2/src/sens/sar_touch_thres6.rs
index 53dba64c29..7542ddd666 100644
--- a/esp32s2/src/sens/sar_touch_thres6.rs
+++ b/esp32s2/src/sens/sar_touch_thres6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th6(&mut self) -> TOUCH_OUT_TH6_W<SAR_TOUCH_THRES6_SPEC> {
         TOUCH_OUT_TH6_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres7.rs b/esp32s2/src/sens/sar_touch_thres7.rs
index 269189f3ee..99bba2fffa 100644
--- a/esp32s2/src/sens/sar_touch_thres7.rs
+++ b/esp32s2/src/sens/sar_touch_thres7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th7(&mut self) -> TOUCH_OUT_TH7_W<SAR_TOUCH_THRES7_SPEC> {
         TOUCH_OUT_TH7_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres8.rs b/esp32s2/src/sens/sar_touch_thres8.rs
index 5e27bb5d18..6359e91d52 100644
--- a/esp32s2/src/sens/sar_touch_thres8.rs
+++ b/esp32s2/src/sens/sar_touch_thres8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th8(&mut self) -> TOUCH_OUT_TH8_W<SAR_TOUCH_THRES8_SPEC> {
         TOUCH_OUT_TH8_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_touch_thres9.rs b/esp32s2/src/sens/sar_touch_thres9.rs
index 4cd3a60868..6efb65c9f0 100644
--- a/esp32s2/src/sens/sar_touch_thres9.rs
+++ b/esp32s2/src/sens/sar_touch_thres9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_th9(&mut self) -> TOUCH_OUT_TH9_W<SAR_TOUCH_THRES9_SPEC> {
         TOUCH_OUT_TH9_W::new(self, 0)
     }
diff --git a/esp32s2/src/sens/sar_tsens_ctrl.rs b/esp32s2/src/sens/sar_tsens_ctrl.rs
index cf98d0727f..a7b8c7032b 100644
--- a/esp32s2/src/sens/sar_tsens_ctrl.rs
+++ b/esp32s2/src/sens/sar_tsens_ctrl.rs
@@ -90,37 +90,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Enable temperature sensor to send out interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_int_en(&mut self) -> TSENS_INT_EN_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_INT_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Invert temperature sensor data."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_in_inv(&mut self) -> TSENS_IN_INV_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_IN_INV_W::new(self, 13)
     }
     #[doc = "Bits 14:21 - Temperature sensor clock divider."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_div(&mut self) -> TSENS_CLK_DIV_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_CLK_DIV_W::new(self, 14)
     }
     #[doc = "Bit 22 - Temperature sensor power up."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_power_up(&mut self) -> TSENS_POWER_UP_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_POWER_UP_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: dump out and power up controlled by software. 0: by FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_power_up_force(&mut self) -> TSENS_POWER_UP_FORCE_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_POWER_UP_FORCE_W::new(self, 23)
     }
     #[doc = "Bit 24 - Temperature sensor dump out only active when SENS_TSENS_POWER_UP_FORCE = 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_dump_out(&mut self) -> TSENS_DUMP_OUT_W<SAR_TSENS_CTRL_SPEC> {
         TSENS_DUMP_OUT_W::new(self, 24)
     }
diff --git a/esp32s2/src/sens/sar_tsens_ctrl2.rs b/esp32s2/src/sens/sar_tsens_ctrl2.rs
index 209e517ef6..ca9ababda7 100644
--- a/esp32s2/src/sens/sar_tsens_ctrl2.rs
+++ b/esp32s2/src/sens/sar_tsens_ctrl2.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_xpd_wait(&mut self) -> TSENS_XPD_WAIT_W<SAR_TSENS_CTRL2_SPEC> {
         TSENS_XPD_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_xpd_force(&mut self) -> TSENS_XPD_FORCE_W<SAR_TSENS_CTRL2_SPEC> {
         TSENS_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_inv(&mut self) -> TSENS_CLK_INV_W<SAR_TSENS_CTRL2_SPEC> {
         TSENS_CLK_INV_W::new(self, 14)
     }
     #[doc = "Bit 15 - Enable temperature sensor clock."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clkgate_en(&mut self) -> TSENS_CLKGATE_EN_W<SAR_TSENS_CTRL2_SPEC> {
         TSENS_CLKGATE_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Reset temperature sensor."]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_reset(&mut self) -> TSENS_RESET_W<SAR_TSENS_CTRL2_SPEC> {
         TSENS_RESET_W::new(self, 16)
     }
diff --git a/esp32s2/src/sens/sardate.rs b/esp32s2/src/sens/sardate.rs
index a253c362ce..b4d3e5fd96 100644
--- a/esp32s2/src/sens/sardate.rs
+++ b/esp32s2/src/sens/sardate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version Control Register"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_date(&mut self) -> SAR_DATE_W<SARDATE_SPEC> {
         SAR_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/continue_.rs b/esp32s2/src/sha/continue_.rs
index 38a19b9c63..63195b4673 100644
--- a/esp32s2/src/sha/continue_.rs
+++ b/esp32s2/src/sha/continue_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue Typical SHA calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn continue_op(&mut self) -> CONTINUE_OP_W<CONTINUE_SPEC> {
         CONTINUE_OP_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/date.rs b/esp32s2/src/sha/date.rs
index 0b52532e5b..43c4f138e2 100644
--- a/esp32s2/src/sha/date.rs
+++ b/esp32s2/src/sha/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/dma_block_num.rs b/esp32s2/src/sha/dma_block_num.rs
index 512b1d83c0..bb77762e70 100644
--- a/esp32s2/src/sha/dma_block_num.rs
+++ b/esp32s2/src/sha/dma_block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Defines the DMA-SHA block number."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_block_num(&mut self) -> DMA_BLOCK_NUM_W<DMA_BLOCK_NUM_SPEC> {
         DMA_BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/dma_continue.rs b/esp32s2/src/sha/dma_continue.rs
index ae6bcfd148..7e7d5388f0 100644
--- a/esp32s2/src/sha/dma_continue.rs
+++ b/esp32s2/src/sha/dma_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to continue DMA-SHA calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<DMA_CONTINUE_SPEC> {
         DMA_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/dma_start.rs b/esp32s2/src/sha/dma_start.rs
index b7d266a0cd..86a841fe5b 100644
--- a/esp32s2/src/sha/dma_start.rs
+++ b/esp32s2/src/sha/dma_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start DMA-SHA calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_start(&mut self) -> DMA_START_W<DMA_START_SPEC> {
         DMA_START_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/h_mem.rs b/esp32s2/src/sha/h_mem.rs
index e04084b2be..c7accfb7de 100644
--- a/esp32s2/src/sha/h_mem.rs
+++ b/esp32s2/src/sha/h_mem.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the %sth 32-bit piece of the Hash value."]
     #[inline(always)]
-    #[must_use]
     pub fn h(&mut self) -> H_W<H_MEM_SPEC> {
         H_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/int_clear.rs b/esp32s2/src/sha/int_clear.rs
index 4e110daa53..6c66e8e75f 100644
--- a/esp32s2/src/sha/int_clear.rs
+++ b/esp32s2/src/sha/int_clear.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLEAR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clears DMA-SHA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<INT_CLEAR_SPEC> {
         CLEAR_INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/int_ena.rs b/esp32s2/src/sha/int_ena.rs
index 1a23d00c6a..1ec59fe12a 100644
--- a/esp32s2/src/sha/int_ena.rs
+++ b/esp32s2/src/sha/int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enables DMA-SHA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W<INT_ENA_SPEC> {
         INTERRUPT_ENA_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/m_mem.rs b/esp32s2/src/sha/m_mem.rs
index 76ef987063..edc94ecf05 100644
--- a/esp32s2/src/sha/m_mem.rs
+++ b/esp32s2/src/sha/m_mem.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the %sth 32-bit piece of the message."]
     #[inline(always)]
-    #[must_use]
     pub fn m(&mut self) -> M_W<M_MEM_SPEC> {
         M_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/mode.rs b/esp32s2/src/sha/mode.rs
index d7f759ba91..16a4a8f1f8 100644
--- a/esp32s2/src/sha/mode.rs
+++ b/esp32s2/src/sha/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Defines the SHA algorithm."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/start.rs b/esp32s2/src/sha/start.rs
index c137ae7876..257bb60116 100644
--- a/esp32s2/src/sha/start.rs
+++ b/esp32s2/src/sha/start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to start Typical SHA calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<START_SPEC> {
         START_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/t_length.rs b/esp32s2/src/sha/t_length.rs
index 57a486b5f4..451e591475 100644
--- a/esp32s2/src/sha/t_length.rs
+++ b/esp32s2/src/sha/t_length.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Defines t_length for calculating the initial Hash value for SHA-512/t."]
     #[inline(always)]
-    #[must_use]
     pub fn t_length(&mut self) -> T_LENGTH_W<T_LENGTH_SPEC> {
         T_LENGTH_W::new(self, 0)
     }
diff --git a/esp32s2/src/sha/t_string.rs b/esp32s2/src/sha/t_string.rs
index 65a94ae494..c7668da6e9 100644
--- a/esp32s2/src/sha/t_string.rs
+++ b/esp32s2/src/sha/t_string.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Defines t_string for calculating the initial Hash value for SHA-512/t."]
     #[inline(always)]
-    #[must_use]
     pub fn t_string(&mut self) -> T_STRING_W<T_STRING_SPEC> {
         T_STRING_W::new(self, 0)
     }
diff --git a/esp32s2/src/spi0.rs b/esp32s2/src/spi0.rs
index 71429c244a..d165acb7ef 100644
--- a/esp32s2/src/spi0.rs
+++ b/esp32s2/src/spi0.rs
@@ -137,12 +137,12 @@ impl RegisterBlock {
     #[doc = "0x40 - SPI Memory Cache SCTRL Register"]
     #[inline(always)]
     pub const fn cache_sctrl(&self) -> &CACHE_SCTRL {
-        unsafe { &*(self as *const Self).cast::<u8>().add(64).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).cast() }
     }
     #[doc = "0x40 - SPI interrupt control register"]
     #[inline(always)]
     pub const fn slv_rd_byte(&self) -> &SLV_RD_BYTE {
-        unsafe { &*(self as *const Self).cast::<u8>().add(64).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).cast() }
     }
     #[doc = "0x44 - SPI master status and DMA read byte control register"]
     #[inline(always)]
@@ -152,32 +152,32 @@ impl RegisterBlock {
     #[doc = "0x48 - SPI Memory SRAM DRD CMD Register"]
     #[inline(always)]
     pub const fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD {
-        unsafe { &*(self as *const Self).cast::<u8>().add(72).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(72).cast() }
     }
     #[doc = "0x48 - SPI hold register"]
     #[inline(always)]
     pub const fn hold(&self) -> &HOLD {
-        unsafe { &*(self as *const Self).cast::<u8>().add(72).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(72).cast() }
     }
     #[doc = "0x4c - SPI Memory SRAM DWR CMD Register"]
     #[inline(always)]
     pub const fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD {
-        unsafe { &*(self as *const Self).cast::<u8>().add(76).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(76).cast() }
     }
     #[doc = "0x4c - SPI DMA control register"]
     #[inline(always)]
     pub const fn dma_conf(&self) -> &DMA_CONF {
-        unsafe { &*(self as *const Self).cast::<u8>().add(76).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(76).cast() }
     }
     #[doc = "0x50 - SPI Memory SRAM Clock Register"]
     #[inline(always)]
     pub const fn sram_clk(&self) -> &SRAM_CLK {
-        unsafe { &*(self as *const Self).cast::<u8>().add(80).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(80).cast() }
     }
     #[doc = "0x50 - SPI DMA TX link configuration"]
     #[inline(always)]
     pub const fn dma_out_link(&self) -> &DMA_OUT_LINK {
-        unsafe { &*(self as *const Self).cast::<u8>().add(80).cast() }
+        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(80).cast() }
     }
     #[doc = "0x54 - SPI DMA RX link configuration"]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/addr.rs b/esp32s2/src/spi0/addr.rs
index f208b0b3b2..bf8f64e738 100644
--- a/esp32s2/src/spi0/addr.rs
+++ b/esp32s2/src/spi0/addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 31:8\\]:address to slave, \\[7:0\\]:Reserved. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_value(&mut self) -> USR_ADDR_VALUE_W<ADDR_SPEC> {
         USR_ADDR_VALUE_W::new(self, 0)
     }
diff --git a/esp32s2/src/spi0/cache_sctrl.rs b/esp32s2/src/spi0/cache_sctrl.rs
index a960fac5ae..c83f2c2ecf 100644
--- a/esp32s2/src/spi0/cache_sctrl.rs
+++ b/esp32s2/src/spi0/cache_sctrl.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - For SPI0, in the SPI SRAM mode, cache read flash with 4 bytes command. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_usr_scmd_4byte(&mut self) -> CACHE_USR_SCMD_4BYTE_W<CACHE_SCTRL_SPEC> {
         CACHE_USR_SCMD_4BYTE_W::new(self, 0)
     }
     #[doc = "Bit 1 - For SPI0, in the SPI SRAM mode, SPI dual I/O mode enable. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_DIO_W::new(self, 1)
     }
     #[doc = "Bit 2 - For SPI0, in the SPI SRAM mode, SPI quad I/O mode enable. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_QIO_W::new(self, 2)
     }
     #[doc = "Bit 3 - For SPI0, in the SPI SRAM mode, it is the enable bit of dummy phase for write operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_WR_SRAM_DUMMY_W::new(self, 3)
     }
     #[doc = "Bit 4 - For SPI0, in the SPI SRAM mode, it is the enable bit of dummy phase for read operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_RD_SRAM_DUMMY_W::new(self, 4)
     }
     #[doc = "Bit 5 - For SPI0, in the SPI SRAM mode, cache read SRAM for user define command."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_RCMD_W::new(self, 5)
     }
     #[doc = "Bits 6:13 - For SPI0, in the SRAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_rdummy_cyclelen(&mut self) -> SRAM_RDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
         SRAM_RDUMMY_CYCLELEN_W::new(self, 6)
     }
     #[doc = "Bits 14:19 - For SPI0, in the SRAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<CACHE_SCTRL_SPEC> {
         SRAM_ADDR_BITLEN_W::new(self, 14)
     }
     #[doc = "Bit 20 - For SPI0, in the SPI SRAM mode, cache write SRAM for user define command."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_WCMD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_oct(&mut self) -> SRAM_OCT_W<CACHE_SCTRL_SPEC> {
         SRAM_OCT_W::new(self, 21)
     }
     #[doc = "Bits 22:29 - For SPI0, in the SRAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_wdummy_cyclelen(&mut self) -> SRAM_WDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
         SRAM_WDUMMY_CYCLELEN_W::new(self, 22)
     }
diff --git a/esp32s2/src/spi0/clock.rs b/esp32s2/src/spi0/clock.rs
index cc1b80160f..d7e7729a30 100644
--- a/esp32s2/src/spi0/clock.rs
+++ b/esp32s2/src/spi0/clock.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
         CLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
         CLKCNT_H_W::new(self, 6)
     }
     #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
         CLKCNT_N_W::new(self, 12)
     }
     #[doc = "Bits 18:30 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<CLOCK_SPEC> {
         CLKDIV_PRE_W::new(self, 18)
     }
     #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
         CLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/cmd.rs b/esp32s2/src/spi0/cmd.rs
index 4d710703df..d63fd83a48 100644
--- a/esp32s2/src/spi0/cmd.rs
+++ b/esp32s2/src/spi0/cmd.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:22 - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn conf_bitlen(&mut self) -> CONF_BITLEN_W<CMD_SPEC> {
         CONF_BITLEN_W::new(self, 0)
     }
     #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
         USR_W::new(self, 24)
     }
diff --git a/esp32s2/src/spi0/ctrl.rs b/esp32s2/src/spi0/ctrl.rs
index 59602deccc..4041da00c7 100644
--- a/esp32s2/src/spi0/ctrl.rs
+++ b/esp32s2/src/spi0/ctrl.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_hold_en(&mut self) -> EXT_HOLD_EN_W<CTRL_SPEC> {
         EXT_HOLD_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_out(&mut self) -> DUMMY_OUT_W<CTRL_SPEC> {
         DUMMY_OUT_W::new(self, 3)
     }
     #[doc = "Bit 5 - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CTRL_SPEC> {
         FADDR_DUAL_W::new(self, 5)
     }
     #[doc = "Bit 6 - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CTRL_SPEC> {
         FADDR_QUAD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
         FADDR_OCT_W::new(self, 7)
     }
     #[doc = "Bit 8 - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
         FCMD_DUAL_W::new(self, 8)
     }
     #[doc = "Bit 9 - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
         FCMD_QUAD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
         FCMD_OCT_W::new(self, 10)
     }
     #[doc = "Bit 14 - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
         FREAD_DUAL_W::new(self, 14)
     }
     #[doc = "Bit 15 - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
         FREAD_QUAD_W::new(self, 15)
     }
     #[doc = "Bit 16 - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_oct(&mut self) -> FREAD_OCT_W<CTRL_SPEC> {
         FREAD_OCT_W::new(self, 16)
     }
     #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
         Q_POL_W::new(self, 18)
     }
     #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
         D_POL_W::new(self, 19)
     }
     #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
         WP_W::new(self, 21)
     }
     #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
         RD_BIT_ORDER_W::new(self, 25)
     }
     #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
         WR_BIT_ORDER_W::new(self, 26)
     }
diff --git a/esp32s2/src/spi0/ctrl1.rs b/esp32s2/src/spi0/ctrl1.rs
index ea86a849c0..260bab09f8 100644
--- a/esp32s2/src/spi0/ctrl1.rs
+++ b/esp32s2/src/spi0/ctrl1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode(&mut self) -> CLK_MODE_W<CTRL1_SPEC> {
         CLK_MODE_W::new(self, 0)
     }
     #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<CTRL1_SPEC> {
         CLK_MODE_13_W::new(self, 2)
     }
     #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
     #[inline(always)]
-    #[must_use]
     pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<CTRL1_SPEC> {
         RSCK_DATA_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn w16_17_wr_ena(&mut self) -> W16_17_WR_ENA_W<CTRL1_SPEC> {
         W16_17_WR_ENA_W::new(self, 4)
     }
     #[doc = "Bits 14:19 - SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<CTRL1_SPEC> {
         CS_HOLD_DELAY_W::new(self, 14)
     }
diff --git a/esp32s2/src/spi0/ctrl2.rs b/esp32s2/src/spi0/ctrl2.rs
index 48e2c3cc7b..3395941452 100644
--- a/esp32s2/src/spi0/ctrl2.rs
+++ b/esp32s2/src/spi0/ctrl2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:12 - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<CTRL2_SPEC> {
         CS_SETUP_TIME_W::new(self, 0)
     }
     #[doc = "Bits 13:25 - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<CTRL2_SPEC> {
         CS_HOLD_TIME_W::new(self, 13)
     }
     #[doc = "Bits 26:28 - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<CTRL2_SPEC> {
         CS_DELAY_MODE_W::new(self, 26)
     }
     #[doc = "Bits 29:30 - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<CTRL2_SPEC> {
         CS_DELAY_NUM_W::new(self, 29)
     }
diff --git a/esp32s2/src/spi0/din_mode.rs b/esp32s2/src/spi0/din_mode.rs
index 0574787dcf..ad1900d79c 100644
--- a/esp32s2/src/spi0/din_mode.rs
+++ b/esp32s2/src/spi0/din_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
         DIN0_MODE_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
         DIN1_MODE_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
         DIN2_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
         DIN3_MODE_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_mode(&mut self) -> DIN4_MODE_W<DIN_MODE_SPEC> {
         DIN4_MODE_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_mode(&mut self) -> DIN5_MODE_W<DIN_MODE_SPEC> {
         DIN5_MODE_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_mode(&mut self) -> DIN6_MODE_W<DIN_MODE_SPEC> {
         DIN6_MODE_W::new(self, 18)
     }
     #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_mode(&mut self) -> DIN7_MODE_W<DIN_MODE_SPEC> {
         DIN7_MODE_W::new(self, 21)
     }
     #[doc = "Bit 24 - 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<DIN_MODE_SPEC> {
         TIMING_CLK_ENA_W::new(self, 24)
     }
diff --git a/esp32s2/src/spi0/din_num.rs b/esp32s2/src/spi0/din_num.rs
index 73f755e5e5..850e1c9547 100644
--- a/esp32s2/src/spi0/din_num.rs
+++ b/esp32s2/src/spi0/din_num.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
         DIN0_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
         DIN1_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
         DIN2_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
         DIN3_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
         DIN4_NUM_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
         DIN5_NUM_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
         DIN6_NUM_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
         DIN7_NUM_W::new(self, 14)
     }
diff --git a/esp32s2/src/spi0/dma_conf.rs b/esp32s2/src/spi0/dma_conf.rs
index c5353e2d75..044577e19e 100644
--- a/esp32s2/src/spi0/dma_conf.rs
+++ b/esp32s2/src/spi0/dma_conf.rs
@@ -254,145 +254,121 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - The bit is used to reset in dma fsm and in data fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<DMA_CONF_SPEC> {
         IN_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to reset out dma fsm and out data fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<DMA_CONF_SPEC> {
         OUT_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Reset spi dma ahb master fifo pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<DMA_CONF_SPEC> {
         AHBM_FIFO_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Reset spi dma ahb master."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<DMA_CONF_SPEC> {
         AHBM_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set bit to test in link."]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<DMA_CONF_SPEC> {
         IN_LOOP_TEST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set bit to test out link."]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<DMA_CONF_SPEC> {
         OUT_LOOP_TEST_W::new(self, 7)
     }
     #[doc = "Bit 8 - when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<DMA_CONF_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 8)
     }
     #[doc = "Bit 9 - out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<DMA_CONF_SPEC> {
         OUT_EOF_MODE_W::new(self, 9)
     }
     #[doc = "Bit 10 - read descriptor use burst mode when read data for memory."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<DMA_CONF_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - read descriptor use burst mode when write data to memory."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<DMA_CONF_SPEC> {
         INDSCR_BURST_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - spi dma read data from memory in burst mode."]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<DMA_CONF_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<DMA_CONF_SPEC> {
         MEM_TRANS_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - spi dma read data stop when in continue tx/rx mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_stop(&mut self) -> DMA_RX_STOP_W<DMA_CONF_SPEC> {
         DMA_RX_STOP_W::new(self, 14)
     }
     #[doc = "Bit 15 - spi dma write data stop when in continue tx/rx mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_stop(&mut self) -> DMA_TX_STOP_W<DMA_CONF_SPEC> {
         DMA_TX_STOP_W::new(self, 15)
     }
     #[doc = "Bit 16 - spi dma continue tx/rx data."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<DMA_CONF_SPEC> {
         DMA_CONTINUE_W::new(self, 16)
     }
     #[doc = "Bit 17 - 1: Clear spi_slv_seg_frt_pop_mask. 0 : others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_last_seg_pop_clr(&mut self) -> SLV_LAST_SEG_POP_CLR_W<DMA_CONF_SPEC> {
         SLV_LAST_SEG_POP_CLR_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_slv_seg_trans_en(&mut self) -> DMA_SLV_SEG_TRANS_EN_W<DMA_CONF_SPEC> {
         DMA_SLV_SEG_TRANS_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rx_seg_trans_clr_en(&mut self) -> SLV_RX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
         SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_tx_seg_trans_clr_en(&mut self) -> SLV_TX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
         SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN\\[19:0\\]/ SPI_MST_DMA_RD_BYTELEN\\[19:0\\] in spi dma transition. 0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_en(&mut self) -> RX_EOF_EN_W<DMA_CONF_SPEC> {
         RX_EOF_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1:Clear spi_dma_infifo_full_vld. 0: Do not control it."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_clr(&mut self) -> DMA_INFIFO_FULL_CLR_W<DMA_CONF_SPEC> {
         DMA_INFIFO_FULL_CLR_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_outfifo_empty_clr(&mut self) -> DMA_OUTFIFO_EMPTY_CLR_W<DMA_CONF_SPEC> {
         DMA_OUTFIFO_EMPTY_CLR_W::new(self, 23)
     }
     #[doc = "Bits 26:27 - Select the external memory block size."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_mem_bk_size(&mut self) -> EXT_MEM_BK_SIZE_W<DMA_CONF_SPEC> {
         EXT_MEM_BK_SIZE_W::new(self, 26)
     }
     #[doc = "Bit 28 - 1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX. 0: others. Will be cleared in 1 APB CLK cycles by hardware.."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_clr(&mut self) -> DMA_SEG_TRANS_CLR_W<DMA_CONF_SPEC> {
         DMA_SEG_TRANS_CLR_W::new(self, 28)
     }
diff --git a/esp32s2/src/spi0/dma_in_link.rs b/esp32s2/src/spi0/dma_in_link.rs
index 1888802a67..222a59f1b8 100644
--- a/esp32s2/src/spi0/dma_in_link.rs
+++ b/esp32s2/src/spi0/dma_in_link.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of the first inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<DMA_IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - when the bit is set, the inlink descriptor returns to the first link node when a packet is error."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<DMA_IN_LINK_SPEC> {
         INLINK_AUTO_RET_W::new(self, 20)
     }
     #[doc = "Bit 28 - Set the bit to stop to use inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<DMA_IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set the bit to start to use inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<DMA_IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set the bit to mount on new inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<DMA_IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
     #[doc = "Bit 31 - SPI DMA read data status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_ena(&mut self) -> DMA_RX_ENA_W<DMA_IN_LINK_SPEC> {
         DMA_RX_ENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/dma_int_clr.rs b/esp32s2/src/spi0/dma_int_clr.rs
index 4e3075c421..77725ce80d 100644
--- a/esp32s2/src/spi0/dma_int_clr.rs
+++ b/esp32s2/src/spi0/dma_int_clr.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The clear bit for lack of enough inlink descriptors. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_empty(&mut self) -> INLINK_DSCR_EMPTY_W<DMA_INT_CLR_SPEC> {
         INLINK_DSCR_EMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear bit for outlink descriptor error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_dscr_error(&mut self) -> OUTLINK_DSCR_ERROR_W<DMA_INT_CLR_SPEC> {
         OUTLINK_DSCR_ERROR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The clear bit for inlink descriptor error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_error(&mut self) -> INLINK_DSCR_ERROR_W<DMA_INT_CLR_SPEC> {
         INLINK_DSCR_ERROR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<DMA_INT_CLR_SPEC> {
         IN_DONE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The clear bit for receiving error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<DMA_INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The clear bit for completing receiving all the packets from host. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<DMA_INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<DMA_INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - The clear bit for sending a packet to host done. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<DMA_INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The clear bit for sending all the packets to host done. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<DMA_INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: Clear SPI_INFIFO_FULL_ERR_INT_RAW. 0: not valid. Can be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_full_err(&mut self) -> INFIFO_FULL_ERR_W<DMA_INT_CLR_SPEC> {
         INFIFO_FULL_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: Clear SPI_OUTFIFO_EMPTY_ERR_INT_RAW signal. 0: not valid. Can be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_empty_err(&mut self) -> OUTFIFO_EMPTY_ERR_W<DMA_INT_CLR_SPEC> {
         OUTFIFO_EMPTY_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - The clear bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd6(&mut self) -> SLV_CMD6_W<DMA_INT_CLR_SPEC> {
         SLV_CMD6_W::new(self, 11)
     }
     #[doc = "Bit 12 - The clear bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_CLR_SPEC> {
         SLV_CMD7_W::new(self, 12)
     }
     #[doc = "Bit 13 - The clear bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_CLR_SPEC> {
         SLV_CMD8_W::new(self, 13)
     }
     #[doc = "Bit 14 - The clear bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_CLR_SPEC> {
         SLV_CMD9_W::new(self, 14)
     }
     #[doc = "Bit 15 - The clear bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_CLR_SPEC> {
         SLV_CMDA_W::new(self, 15)
     }
diff --git a/esp32s2/src/spi0/dma_int_ena.rs b/esp32s2/src/spi0/dma_int_ena.rs
index 409e5e6a9e..1b461ac569 100644
--- a/esp32s2/src/spi0/dma_int_ena.rs
+++ b/esp32s2/src/spi0/dma_int_ena.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for lack of enough inlink descriptors. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_empty(&mut self) -> INLINK_DSCR_EMPTY_W<DMA_INT_ENA_SPEC> {
         INLINK_DSCR_EMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for outlink descriptor error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_dscr_error(&mut self) -> OUTLINK_DSCR_ERROR_W<DMA_INT_ENA_SPEC> {
         OUTLINK_DSCR_ERROR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for inlink descriptor error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_dscr_error(&mut self) -> INLINK_DSCR_ERROR_W<DMA_INT_ENA_SPEC> {
         INLINK_DSCR_ERROR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<DMA_INT_ENA_SPEC> {
         IN_DONE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for receiving error. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<DMA_INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for completing receiving all the packets from host. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<DMA_INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<DMA_INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for sending a packet to host done. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<DMA_INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The enable bit for sending all the packets to host done. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<DMA_INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9 - The enable bit for infifo full error interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_full_err(&mut self) -> INFIFO_FULL_ERR_W<DMA_INT_ENA_SPEC> {
         INFIFO_FULL_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - The enable bit for outfifo empty error interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_empty_err(&mut self) -> OUTFIFO_EMPTY_ERR_W<DMA_INT_ENA_SPEC> {
         OUTFIFO_EMPTY_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - The enable bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd6(&mut self) -> SLV_CMD6_W<DMA_INT_ENA_SPEC> {
         SLV_CMD6_W::new(self, 11)
     }
     #[doc = "Bit 12 - The enable bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_ENA_SPEC> {
         SLV_CMD7_W::new(self, 12)
     }
     #[doc = "Bit 13 - The enable bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_ENA_SPEC> {
         SLV_CMD8_W::new(self, 13)
     }
     #[doc = "Bit 14 - The enable bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_ENA_SPEC> {
         SLV_CMD9_W::new(self, 14)
     }
     #[doc = "Bit 15 - The enable bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_ENA_SPEC> {
         SLV_CMDA_W::new(self, 15)
     }
diff --git a/esp32s2/src/spi0/dma_int_raw.rs b/esp32s2/src/spi0/dma_int_raw.rs
index 1263bb44a7..1e1a75a70e 100644
--- a/esp32s2/src/spi0/dma_int_raw.rs
+++ b/esp32s2/src/spi0/dma_int_raw.rs
@@ -152,31 +152,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 11 - The raw bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd6(&mut self) -> SLV_CMD6_W<DMA_INT_RAW_SPEC> {
         SLV_CMD6_W::new(self, 11)
     }
     #[doc = "Bit 12 - The raw bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_RAW_SPEC> {
         SLV_CMD7_W::new(self, 12)
     }
     #[doc = "Bit 13 - The raw bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_RAW_SPEC> {
         SLV_CMD8_W::new(self, 13)
     }
     #[doc = "Bit 14 - The raw bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_RAW_SPEC> {
         SLV_CMD9_W::new(self, 14)
     }
     #[doc = "Bit 15 - The raw bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_RAW_SPEC> {
         SLV_CMDA_W::new(self, 15)
     }
diff --git a/esp32s2/src/spi0/dma_int_st.rs b/esp32s2/src/spi0/dma_int_st.rs
index 045ef157e2..29a069cd1e 100644
--- a/esp32s2/src/spi0/dma_int_st.rs
+++ b/esp32s2/src/spi0/dma_int_st.rs
@@ -152,31 +152,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 11 - The status bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd6(&mut self) -> SLV_CMD6_W<DMA_INT_ST_SPEC> {
         SLV_CMD6_W::new(self, 11)
     }
     #[doc = "Bit 12 - The status bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_ST_SPEC> {
         SLV_CMD7_W::new(self, 12)
     }
     #[doc = "Bit 13 - The status bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_ST_SPEC> {
         SLV_CMD8_W::new(self, 13)
     }
     #[doc = "Bit 14 - The status bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_ST_SPEC> {
         SLV_CMD9_W::new(self, 14)
     }
     #[doc = "Bit 15 - The status bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_ST_SPEC> {
         SLV_CMDA_W::new(self, 15)
     }
diff --git a/esp32s2/src/spi0/dma_out_link.rs b/esp32s2/src/spi0/dma_out_link.rs
index dd76ae637f..0e9175a27b 100644
--- a/esp32s2/src/spi0/dma_out_link.rs
+++ b/esp32s2/src/spi0/dma_out_link.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The address of the first outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set the bit to stop to use outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set the bit to start to use outlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set the bit to mount on new outlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
     #[doc = "Bit 31 - spi dma write data status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_ena(&mut self) -> DMA_TX_ENA_W<DMA_OUT_LINK_SPEC> {
         DMA_TX_ENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/dout_mode.rs b/esp32s2/src/spi0/dout_mode.rs
index 5463ed1711..5be51c3191 100644
--- a/esp32s2/src/spi0/dout_mode.rs
+++ b/esp32s2/src/spi0/dout_mode.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
         DOUT0_MODE_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
         DOUT1_MODE_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
         DOUT2_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
         DOUT3_MODE_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<DOUT_MODE_SPEC> {
         DOUT4_MODE_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<DOUT_MODE_SPEC> {
         DOUT5_MODE_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<DOUT_MODE_SPEC> {
         DOUT6_MODE_W::new(self, 18)
     }
     #[doc = "Bits 21:23 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<DOUT_MODE_SPEC> {
         DOUT7_MODE_W::new(self, 21)
     }
diff --git a/esp32s2/src/spi0/dout_num.rs b/esp32s2/src/spi0/dout_num.rs
index 979cafdbb5..0dcc81bf59 100644
--- a/esp32s2/src/spi0/dout_num.rs
+++ b/esp32s2/src/spi0/dout_num.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout0_num(&mut self) -> DOUT0_NUM_W<DOUT_NUM_SPEC> {
         DOUT0_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout1_num(&mut self) -> DOUT1_NUM_W<DOUT_NUM_SPEC> {
         DOUT1_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout2_num(&mut self) -> DOUT2_NUM_W<DOUT_NUM_SPEC> {
         DOUT2_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout3_num(&mut self) -> DOUT3_NUM_W<DOUT_NUM_SPEC> {
         DOUT3_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout4_num(&mut self) -> DOUT4_NUM_W<DOUT_NUM_SPEC> {
         DOUT4_NUM_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout5_num(&mut self) -> DOUT5_NUM_W<DOUT_NUM_SPEC> {
         DOUT5_NUM_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout6_num(&mut self) -> DOUT6_NUM_W<DOUT_NUM_SPEC> {
         DOUT6_NUM_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout7_num(&mut self) -> DOUT7_NUM_W<DOUT_NUM_SPEC> {
         DOUT7_NUM_W::new(self, 14)
     }
diff --git a/esp32s2/src/spi0/fsm.rs b/esp32s2/src/spi0/fsm.rs
index 5c6e3b31f4..253447e480 100644
--- a/esp32s2/src/spi0/fsm.rs
+++ b/esp32s2/src/spi0/fsm.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 12:31 - Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state.."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_dma_rd_bytelen(&mut self) -> MST_DMA_RD_BYTELEN_W<FSM_SPEC> {
         MST_DMA_RD_BYTELEN_W::new(self, 12)
     }
diff --git a/esp32s2/src/spi0/hold.rs b/esp32s2/src/spi0/hold.rs
index 0c8991980e..9002f0b570 100644
--- a/esp32s2/src/spi0/hold.rs
+++ b/esp32s2/src/spi0/hold.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_hold_ena(&mut self) -> INT_HOLD_ENA_W<HOLD_SPEC> {
         INT_HOLD_ENA_W::new(self, 0)
     }
     #[doc = "Bit 2 - spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn val(&mut self) -> VAL_W<HOLD_SPEC> {
         VAL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_en(&mut self) -> OUT_EN_W<HOLD_SPEC> {
         OUT_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn out_time(&mut self) -> OUT_TIME_W<HOLD_SPEC> {
         OUT_TIME_W::new(self, 4)
     }
     #[doc = "Bit 7 - 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<HOLD_SPEC> {
         DMA_SEG_TRANS_DONE_W::new(self, 7)
     }
diff --git a/esp32s2/src/spi0/lcd_ctrl.rs b/esp32s2/src/spi0/lcd_ctrl.rs
index 9492ea87b5..714e06e5e1 100644
--- a/esp32s2/src/spi0/lcd_ctrl.rs
+++ b/esp32s2/src/spi0/lcd_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hb_front(&mut self) -> LCD_HB_FRONT_W<LCD_CTRL_SPEC> {
         LCD_HB_FRONT_W::new(self, 0)
     }
     #[doc = "Bits 11:20 - It is the vertical active height of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_va_height(&mut self) -> LCD_VA_HEIGHT_W<LCD_CTRL_SPEC> {
         LCD_VA_HEIGHT_W::new(self, 11)
     }
     #[doc = "Bits 21:30 - It is the vertical total height of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vt_height(&mut self) -> LCD_VT_HEIGHT_W<LCD_CTRL_SPEC> {
         LCD_VT_HEIGHT_W::new(self, 21)
     }
     #[doc = "Bit 31 - 1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_mode_en(&mut self) -> LCD_MODE_EN_W<LCD_CTRL_SPEC> {
         LCD_MODE_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/lcd_ctrl1.rs b/esp32s2/src/spi0/lcd_ctrl1.rs
index 13b0383cda..9feb544da1 100644
--- a/esp32s2/src/spi0/lcd_ctrl1.rs
+++ b/esp32s2/src/spi0/lcd_ctrl1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vb_front(&mut self) -> LCD_VB_FRONT_W<LCD_CTRL1_SPEC> {
         LCD_VB_FRONT_W::new(self, 0)
     }
     #[doc = "Bits 8:19 - It is the horizontal active width of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ha_width(&mut self) -> LCD_HA_WIDTH_W<LCD_CTRL1_SPEC> {
         LCD_HA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bits 20:31 - It is the horizontal total width of a frame. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ht_width(&mut self) -> LCD_HT_WIDTH_W<LCD_CTRL1_SPEC> {
         LCD_HT_WIDTH_W::new(self, 20)
     }
diff --git a/esp32s2/src/spi0/lcd_ctrl2.rs b/esp32s2/src/spi0/lcd_ctrl2.rs
index 3db3d73da2..5a3556f283 100644
--- a/esp32s2/src/spi0/lcd_ctrl2.rs
+++ b/esp32s2/src/spi0/lcd_ctrl2.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_width(&mut self) -> LCD_VSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
         LCD_VSYNC_WIDTH_W::new(self, 0)
     }
     #[doc = "Bit 7 - It is the idle value of spi_vsync. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn vsync_idle_pol(&mut self) -> VSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
         VSYNC_IDLE_POL_W::new(self, 7)
     }
     #[doc = "Bits 16:22 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_width(&mut self) -> LCD_HSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
         LCD_HSYNC_WIDTH_W::new(self, 16)
     }
     #[doc = "Bit 23 - It is the idle value of spi_hsync. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn hsync_idle_pol(&mut self) -> HSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
         HSYNC_IDLE_POL_W::new(self, 23)
     }
     #[doc = "Bits 24:31 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_position(&mut self) -> LCD_HSYNC_POSITION_W<LCD_CTRL2_SPEC> {
         LCD_HSYNC_POSITION_W::new(self, 24)
     }
diff --git a/esp32s2/src/spi0/lcd_d_mode.rs b/esp32s2/src/spi0/lcd_d_mode.rs
index 026553b460..203fce5e16 100644
--- a/esp32s2/src/spi0/lcd_d_mode.rs
+++ b/esp32s2/src/spi0/lcd_d_mode.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_dqs_mode(&mut self) -> D_DQS_MODE_W<LCD_D_MODE_SPEC> {
         D_DQS_MODE_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_cd_mode(&mut self) -> D_CD_MODE_W<LCD_D_MODE_SPEC> {
         D_CD_MODE_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_de_mode(&mut self) -> D_DE_MODE_W<LCD_D_MODE_SPEC> {
         D_DE_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_hsync_mode(&mut self) -> D_HSYNC_MODE_W<LCD_D_MODE_SPEC> {
         D_HSYNC_MODE_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_vsync_mode(&mut self) -> D_VSYNC_MODE_W<LCD_D_MODE_SPEC> {
         D_VSYNC_MODE_W::new(self, 12)
     }
     #[doc = "Bit 15 - It is the idle value of spi_de."]
     #[inline(always)]
-    #[must_use]
     pub fn de_idle_pol(&mut self) -> DE_IDLE_POL_W<LCD_D_MODE_SPEC> {
         DE_IDLE_POL_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans."]
     #[inline(always)]
-    #[must_use]
     pub fn hs_blank_en(&mut self) -> HS_BLANK_EN_W<LCD_D_MODE_SPEC> {
         HS_BLANK_EN_W::new(self, 16)
     }
diff --git a/esp32s2/src/spi0/lcd_d_num.rs b/esp32s2/src/spi0/lcd_d_num.rs
index a8dc81abe3..3e198285cc 100644
--- a/esp32s2/src/spi0/lcd_d_num.rs
+++ b/esp32s2/src/spi0/lcd_d_num.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_dqs_num(&mut self) -> D_DQS_NUM_W<LCD_D_NUM_SPEC> {
         D_DQS_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_cd_num(&mut self) -> D_CD_NUM_W<LCD_D_NUM_SPEC> {
         D_CD_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_de_num(&mut self) -> D_DE_NUM_W<LCD_D_NUM_SPEC> {
         D_DE_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_hsync_num(&mut self) -> D_HSYNC_NUM_W<LCD_D_NUM_SPEC> {
         D_HSYNC_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_vsync_num(&mut self) -> D_VSYNC_NUM_W<LCD_D_NUM_SPEC> {
         D_VSYNC_NUM_W::new(self, 8)
     }
diff --git a/esp32s2/src/spi0/misc.rs b/esp32s2/src/spi0/misc.rs
index 3de8b88df3..0af28988f3 100644
--- a/esp32s2/src/spi0/misc.rs
+++ b/esp32s2/src/spi0/misc.rs
@@ -231,7 +231,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 6][n as usize];
@@ -239,133 +238,111 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs2_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to raise high SPI_CS3 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS3 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs3_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to raise high SPI_CS4 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS4 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs4_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to raise high SPI_CS5 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS5 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs5_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
         CK_DIS_W::new(self, 6)
     }
     #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
         MASTER_CS_POL_W::new(self, 7)
     }
     #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<MISC_SPEC> {
         CLK_DATA_DTR_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<MISC_SPEC> {
         DATA_DTR_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<MISC_SPEC> {
         ADDR_DTR_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<MISC_SPEC> {
         CMD_DTR_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cd_data_set(&mut self) -> CD_DATA_SET_W<MISC_SPEC> {
         CD_DATA_SET_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cd_dummy_set(&mut self) -> CD_DUMMY_SET_W<MISC_SPEC> {
         CD_DUMMY_SET_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cd_addr_set(&mut self) -> CD_ADDR_SET_W<MISC_SPEC> {
         CD_ADDR_SET_W::new(self, 22)
     }
     #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
         SLAVE_CS_POL_W::new(self, 23)
     }
     #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<MISC_SPEC> {
         DQS_IDLE_EDGE_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cd_cmd_set(&mut self) -> CD_CMD_SET_W<MISC_SPEC> {
         CD_CMD_SET_W::new(self, 25)
     }
     #[doc = "Bit 26 - The default value of spi_cd. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cd_idle_edge(&mut self) -> CD_IDLE_EDGE_W<MISC_SPEC> {
         CD_IDLE_EDGE_W::new(self, 26)
     }
     #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
         CK_IDLE_EDGE_W::new(self, 29)
     }
     #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
         CS_KEEP_ACTIVE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
         QUAD_DIN_PIN_SWAP_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/miso_dlen.rs b/esp32s2/src/spi0/miso_dlen.rs
index 7a8c442a5b..3f64c490af 100644
--- a/esp32s2/src/spi0/miso_dlen.rs
+++ b/esp32s2/src/spi0/miso_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:22 - The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_dbitlen(&mut self) -> USR_MISO_DBITLEN_W<MISO_DLEN_SPEC> {
         USR_MISO_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32s2/src/spi0/mosi_dlen.rs b/esp32s2/src/spi0/mosi_dlen.rs
index ec732b933d..64cb0299dc 100644
--- a/esp32s2/src/spi0/mosi_dlen.rs
+++ b/esp32s2/src/spi0/mosi_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:22 - The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_dbitlen(&mut self) -> USR_MOSI_DBITLEN_W<MOSI_DLEN_SPEC> {
         USR_MOSI_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32s2/src/spi0/reg_date.rs b/esp32s2/src/spi0/reg_date.rs
index 50d621da34..237ea35dcf 100644
--- a/esp32s2/src/spi0/reg_date.rs
+++ b/esp32s2/src/spi0/reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - SPI register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<REG_DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/spi0/slave.rs b/esp32s2/src/spi0/slave.rs
index c59ca1f86c..47ac615ab7 100644
--- a/esp32s2/src/spi0/slave.rs
+++ b/esp32s2/src/spi0/slave.rs
@@ -132,67 +132,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done(&mut self) -> TRANS_DONE_W<SLAVE_SPEC> {
         TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_rd_buf_done_en(&mut self) -> INT_RD_BUF_DONE_EN_W<SLAVE_SPEC> {
         INT_RD_BUF_DONE_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_wr_buf_done_en(&mut self) -> INT_WR_BUF_DONE_EN_W<SLAVE_SPEC> {
         INT_WR_BUF_DONE_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_rd_dma_done_en(&mut self) -> INT_RD_DMA_DONE_EN_W<SLAVE_SPEC> {
         INT_RD_DMA_DONE_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_wr_dma_done_en(&mut self) -> INT_WR_DMA_DONE_EN_W<SLAVE_SPEC> {
         INT_WR_DMA_DONE_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_trans_done_en(&mut self) -> INT_TRANS_DONE_EN_W<SLAVE_SPEC> {
         INT_TRANS_DONE_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn int_dma_seg_trans_en(&mut self) -> INT_DMA_SEG_TRANS_EN_W<SLAVE_SPEC> {
         INT_DMA_SEG_TRANS_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err_int_en(&mut self) -> SEG_MAGIC_ERR_INT_EN_W<SLAVE_SPEC> {
         SEG_MAGIC_ERR_INT_EN_W::new(self, 11)
     }
     #[doc = "Bit 29 - SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done_auto_clr_en(&mut self) -> TRANS_DONE_AUTO_CLR_EN_W<SLAVE_SPEC> {
         TRANS_DONE_AUTO_CLR_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set SPI work mode. 1: slave mode 0: master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
         MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
         SOFT_RESET_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/slave1.rs b/esp32s2/src/spi0/slave1.rs
index 5341be31e4..9b1d371e88 100644
--- a/esp32s2/src/spi0/slave1.rs
+++ b/esp32s2/src/spi0/slave1.rs
@@ -90,37 +90,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - 1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_addr_err_clr(&mut self) -> SLV_ADDR_ERR_CLR_W<SLAVE1_SPEC> {
         SLV_ADDR_ERR_CLR_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Clear SPI_SLV_CMD_ERR. 0: not valid. Can be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_err_clr(&mut self) -> SLV_CMD_ERR_CLR_W<SLAVE1_SPEC> {
         SLV_CMD_ERR_CLR_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_no_qpi_en(&mut self) -> SLV_NO_QPI_EN_W<SLAVE1_SPEC> {
         SLV_NO_QPI_EN_W::new(self, 12)
     }
     #[doc = "Bit 15 - The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<SLAVE1_SPEC> {
         SLV_WR_DMA_DONE_W::new(self, 15)
     }
     #[doc = "Bits 16:23 - In the slave mode it is the value of command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_last_command(&mut self) -> SLV_LAST_COMMAND_W<SLAVE1_SPEC> {
         SLV_LAST_COMMAND_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - In the slave mode it is the value of address."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_last_addr(&mut self) -> SLV_LAST_ADDR_W<SLAVE1_SPEC> {
         SLV_LAST_ADDR_W::new(self, 24)
     }
diff --git a/esp32s2/src/spi0/slv_rd_byte.rs b/esp32s2/src/spi0/slv_rd_byte.rs
index b048d5708d..ab5d79aff6 100644
--- a/esp32s2/src/spi0/slv_rd_byte.rs
+++ b/esp32s2/src/spi0/slv_rd_byte.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits \\[23:20\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_data_bytelen(&mut self) -> SLV_DATA_BYTELEN_W<SLV_RD_BYTE_SPEC> {
         SLV_DATA_BYTELEN_W::new(self, 0)
     }
     #[doc = "Bit 20 - 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rddma_bytelen_en(&mut self) -> SLV_RDDMA_BYTELEN_EN_W<SLV_RD_BYTE_SPEC> {
         SLV_RDDMA_BYTELEN_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrdma_bytelen_en(&mut self) -> SLV_WRDMA_BYTELEN_EN_W<SLV_RD_BYTE_SPEC> {
         SLV_WRDMA_BYTELEN_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_bytelen_en(&mut self) -> SLV_RDBUF_BYTELEN_EN_W<SLV_RD_BYTE_SPEC> {
         SLV_RDBUF_BYTELEN_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_bytelen_en(&mut self) -> SLV_WRBUF_BYTELEN_EN_W<SLV_RD_BYTE_SPEC> {
         SLV_WRBUF_BYTELEN_EN_W::new(self, 23)
     }
     #[doc = "Bits 24:27 - The magic value of BM table in master DMA seg-trans."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<SLV_RD_BYTE_SPEC> {
         DMA_SEG_MAGIC_VALUE_W::new(self, 24)
     }
     #[doc = "Bit 30 - The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<SLV_RD_BYTE_SPEC> {
         SLV_RD_DMA_DONE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_conf(&mut self) -> USR_CONF_W<SLV_RD_BYTE_SPEC> {
         USR_CONF_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/slv_rdbuf_dlen.rs b/esp32s2/src/spi0/slv_rdbuf_dlen.rs
index 7dcdaeddd6..cb11b8c26c 100644
--- a/esp32s2/src/spi0/slv_rdbuf_dlen.rs
+++ b/esp32s2/src/spi0/slv_rdbuf_dlen.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - In the slave mode it is the length in bytes for read operations. The register value shall be byte_num."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_dma_rd_bytelen(&mut self) -> SLV_DMA_RD_BYTELEN_W<SLV_RDBUF_DLEN_SPEC> {
         SLV_DMA_RD_BYTELEN_W::new(self, 0)
     }
     #[doc = "Bit 24 - The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<SLV_RDBUF_DLEN_SPEC> {
         SLV_RD_BUF_DONE_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<SLV_RDBUF_DLEN_SPEC> {
         SEG_MAGIC_ERR_W::new(self, 25)
     }
diff --git a/esp32s2/src/spi0/slv_wrbuf_dlen.rs b/esp32s2/src/spi0/slv_wrbuf_dlen.rs
index 3f4e713ae8..c95007f431 100644
--- a/esp32s2/src/spi0/slv_wrbuf_dlen.rs
+++ b/esp32s2/src/spi0/slv_wrbuf_dlen.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 24 - The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<SLV_WRBUF_DLEN_SPEC> {
         SLV_WR_BUF_DONE_W::new(self, 24)
     }
     #[doc = "Bits 25:31 - The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN\\[6:0\\] + SPI_CONF_BITLEN\\[23:0\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn conf_base_bitlen(&mut self) -> CONF_BASE_BITLEN_W<SLV_WRBUF_DLEN_SPEC> {
         CONF_BASE_BITLEN_W::new(self, 25)
     }
diff --git a/esp32s2/src/spi0/sram_clk.rs b/esp32s2/src/spi0/sram_clk.rs
index 1052911ae5..526a6ee69b 100644
--- a/esp32s2/src/spi0/sram_clk.rs
+++ b/esp32s2/src/spi0/sram_clk.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - For SPI0 SRAM interface, it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_l(&mut self) -> SCLKCNT_L_W<SRAM_CLK_SPEC> {
         SCLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - For SPI0 SRAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_h(&mut self) -> SCLKCNT_H_W<SRAM_CLK_SPEC> {
         SCLKCNT_H_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - For SPI0 SRAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_n(&mut self) -> SCLKCNT_N_W<SRAM_CLK_SPEC> {
         SCLKCNT_N_W::new(self, 16)
     }
     #[doc = "Bit 31 - For SPI0 SRAM interface, 1: spi_mem_clk is equal to system, 0: spi_mem_clk is divided from system clock."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_equ_sysclk(&mut self) -> SCLK_EQU_SYSCLK_W<SRAM_CLK_SPEC> {
         SCLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/sram_drd_cmd.rs b/esp32s2/src/spi0/sram_drd_cmd.rs
index e82c7d7d50..51e0c6d3b0 100644
--- a/esp32s2/src/spi0/sram_drd_cmd.rs
+++ b/esp32s2/src/spi0/sram_drd_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - For SPI0, when cache mode is enabled, it is the read command value of the command phase for SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_VALUE_W<SRAM_DRD_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_BITLEN_W<SRAM_DRD_CMD_SPEC> {
diff --git a/esp32s2/src/spi0/sram_dwr_cmd.rs b/esp32s2/src/spi0/sram_dwr_cmd.rs
index 41e2976c3c..8ff8d54440 100644
--- a/esp32s2/src/spi0/sram_dwr_cmd.rs
+++ b/esp32s2/src/spi0/sram_dwr_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - For SPI0, when cache mode is enabled, it is the write command value of the command phase for SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_VALUE_W<SRAM_DWR_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_BITLEN_W<SRAM_DWR_CMD_SPEC> {
diff --git a/esp32s2/src/spi0/user.rs b/esp32s2/src/spi0/user.rs
index d10eb1242a..e22b99b420 100644
--- a/esp32s2/src/spi0/user.rs
+++ b/esp32s2/src/spi0/user.rs
@@ -314,181 +314,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
         DOUTDIN_W::new(self, 0)
     }
     #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
         QPI_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn opi_mode(&mut self) -> OPI_MODE_W<USER_SPEC> {
         OPI_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
     #[inline(always)]
-    #[must_use]
     pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
         TSCK_I_EDGE_W::new(self, 5)
     }
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
         CS_HOLD_W::new(self, 6)
     }
     #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
         CS_SETUP_W::new(self, 7)
     }
     #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
     #[inline(always)]
-    #[must_use]
     pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
         RSCK_I_EDGE_W::new(self, 8)
     }
     #[doc = "Bit 9 - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
         CK_OUT_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<USER_SPEC> {
         RD_BYTE_ORDER_W::new(self, 10)
     }
     #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<USER_SPEC> {
         WR_BYTE_ORDER_W::new(self, 11)
     }
     #[doc = "Bit 12 - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
         FWRITE_DUAL_W::new(self, 12)
     }
     #[doc = "Bit 13 - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
         FWRITE_QUAD_W::new(self, 13)
     }
     #[doc = "Bit 14 - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<USER_SPEC> {
         FWRITE_OCT_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<USER_SPEC> {
         USR_CONF_NXT_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
         SIO_W::new(self, 16)
     }
     #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<USER_SPEC> {
         USR_HOLD_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<USER_SPEC> {
         USR_DOUT_HOLD_W::new(self, 18)
     }
     #[doc = "Bit 19 - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<USER_SPEC> {
         USR_DIN_HOLD_W::new(self, 19)
     }
     #[doc = "Bit 20 - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<USER_SPEC> {
         USR_DUMMY_HOLD_W::new(self, 20)
     }
     #[doc = "Bit 21 - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<USER_SPEC> {
         USR_ADDR_HOLD_W::new(self, 21)
     }
     #[doc = "Bit 22 - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<USER_SPEC> {
         USR_CMD_HOLD_W::new(self, 22)
     }
     #[doc = "Bit 23 - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<USER_SPEC> {
         USR_PREP_HOLD_W::new(self, 23)
     }
     #[doc = "Bit 24 - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
         USR_MISO_HIGHPART_W::new(self, 24)
     }
     #[doc = "Bit 25 - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
         USR_MOSI_HIGHPART_W::new(self, 25)
     }
     #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
         USR_DUMMY_IDLE_W::new(self, 26)
     }
     #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
         USR_MOSI_W::new(self, 27)
     }
     #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
         USR_MISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
         USR_DUMMY_W::new(self, 29)
     }
     #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
         USR_ADDR_W::new(self, 30)
     }
     #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
         USR_COMMAND_W::new(self, 31)
     }
diff --git a/esp32s2/src/spi0/user1.rs b/esp32s2/src/spi0/user1.rs
index 7582a78229..5cbea796a0 100644
--- a/esp32s2/src/spi0/user1.rs
+++ b/esp32s2/src/spi0/user1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
         USR_ADDR_BITLEN_W::new(self, 27)
     }
diff --git a/esp32s2/src/spi0/user2.rs b/esp32s2/src/spi0/user2.rs
index ffd38c0a46..7cb8c7ec07 100644
--- a/esp32s2/src/spi0/user2.rs
+++ b/esp32s2/src/spi0/user2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<USER2_SPEC> {
         USR_COMMAND_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<USER2_SPEC> {
         USR_COMMAND_BITLEN_W::new(self, 28)
     }
diff --git a/esp32s2/src/spi0/w.rs b/esp32s2/src/spi0/w.rs
index 9f1f6b5276..48b734d212 100644
--- a/esp32s2/src/spi0/w.rs
+++ b/esp32s2/src/spi0/w.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 32 bits data buffer 0, transferred in the unit of byte. Byte addressable in slave half-duplex mode."]
     #[inline(always)]
-    #[must_use]
     pub fn buf(&mut self) -> BUF_W<W_SPEC> {
         BUF_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/clk_out_en.rs b/esp32s2/src/syscon/clk_out_en.rs
index 3d0b0e150e..5304ba284a 100644
--- a/esp32s2/src/syscon/clk_out_en.rs
+++ b/esp32s2/src/syscon/clk_out_en.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk20_oen(&mut self) -> CLK20_OEN_W<CLK_OUT_EN_SPEC> {
         CLK20_OEN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn clk22_oen(&mut self) -> CLK22_OEN_W<CLK_OUT_EN_SPEC> {
         CLK22_OEN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn clk44_oen(&mut self) -> CLK44_OEN_W<CLK_OUT_EN_SPEC> {
         CLK44_OEN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_bb_oen(&mut self) -> CLK_BB_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_BB_OEN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn clk80_oen(&mut self) -> CLK80_OEN_W<CLK_OUT_EN_SPEC> {
         CLK80_OEN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk160_oen(&mut self) -> CLK160_OEN_W<CLK_OUT_EN_SPEC> {
         CLK160_OEN_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_320m_oen(&mut self) -> CLK_320M_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_320M_OEN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_adc_inf_oen(&mut self) -> CLK_ADC_INF_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_ADC_INF_OEN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_dac_cpu_oen(&mut self) -> CLK_DAC_CPU_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_DAC_CPU_OEN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn clk40x_bb_oen(&mut self) -> CLK40X_BB_OEN_W<CLK_OUT_EN_SPEC> {
         CLK40X_BB_OEN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_xtal_oen(&mut self) -> CLK_XTAL_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_XTAL_OEN_W::new(self, 10)
     }
diff --git a/esp32s2/src/syscon/date.rs b/esp32s2/src/syscon/date.rs
index f1dfdd11b0..64ebc14d55 100644
--- a/esp32s2/src/syscon/date.rs
+++ b/esp32s2/src/syscon/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/ext_mem_pms_lock.rs b/esp32s2/src/syscon/ext_mem_pms_lock.rs
index 6b02563da5..32ec766dca 100644
--- a/esp32s2/src/syscon/ext_mem_pms_lock.rs
+++ b/esp32s2/src/syscon/ext_mem_pms_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_mem_pms_lock(&mut self) -> EXT_MEM_PMS_LOCK_W<EXT_MEM_PMS_LOCK_SPEC> {
         EXT_MEM_PMS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace0_addr.rs b/esp32s2/src/syscon/flash_ace0_addr.rs
index c6db48a711..abd16b6fe7 100644
--- a/esp32s2/src/syscon/flash_ace0_addr.rs
+++ b/esp32s2/src/syscon/flash_ace0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE0_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace0_attr.rs b/esp32s2/src/syscon/flash_ace0_attr.rs
index 9109368f93..d02a77ee9a 100644
--- a/esp32s2/src/syscon/flash_ace0_attr.rs
+++ b/esp32s2/src/syscon/flash_ace0_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace0_attr(&mut self) -> FLASH_ACE0_ATTR_W<FLASH_ACE0_ATTR_SPEC> {
         FLASH_ACE0_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace0_size.rs b/esp32s2/src/syscon/flash_ace0_size.rs
index 04fdaa211c..6857386aae 100644
--- a/esp32s2/src/syscon/flash_ace0_size.rs
+++ b/esp32s2/src/syscon/flash_ace0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace0_size(&mut self) -> FLASH_ACE0_SIZE_W<FLASH_ACE0_SIZE_SPEC> {
         FLASH_ACE0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace1_addr.rs b/esp32s2/src/syscon/flash_ace1_addr.rs
index 30fad631c9..21be5a858e 100644
--- a/esp32s2/src/syscon/flash_ace1_addr.rs
+++ b/esp32s2/src/syscon/flash_ace1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE1_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace1_attr.rs b/esp32s2/src/syscon/flash_ace1_attr.rs
index 5da5e96d03..3a74f5b1c2 100644
--- a/esp32s2/src/syscon/flash_ace1_attr.rs
+++ b/esp32s2/src/syscon/flash_ace1_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace1_attr(&mut self) -> FLASH_ACE1_ATTR_W<FLASH_ACE1_ATTR_SPEC> {
         FLASH_ACE1_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace1_size.rs b/esp32s2/src/syscon/flash_ace1_size.rs
index 1217a47f74..fe44fc82e3 100644
--- a/esp32s2/src/syscon/flash_ace1_size.rs
+++ b/esp32s2/src/syscon/flash_ace1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace1_size(&mut self) -> FLASH_ACE1_SIZE_W<FLASH_ACE1_SIZE_SPEC> {
         FLASH_ACE1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace2_addr.rs b/esp32s2/src/syscon/flash_ace2_addr.rs
index 4a26b7efd2..9efef0c500 100644
--- a/esp32s2/src/syscon/flash_ace2_addr.rs
+++ b/esp32s2/src/syscon/flash_ace2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE2_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace2_attr.rs b/esp32s2/src/syscon/flash_ace2_attr.rs
index 1259027772..d0780bfc74 100644
--- a/esp32s2/src/syscon/flash_ace2_attr.rs
+++ b/esp32s2/src/syscon/flash_ace2_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace2_attr(&mut self) -> FLASH_ACE2_ATTR_W<FLASH_ACE2_ATTR_SPEC> {
         FLASH_ACE2_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace2_size.rs b/esp32s2/src/syscon/flash_ace2_size.rs
index 238f8519b1..f9e8a7ae44 100644
--- a/esp32s2/src/syscon/flash_ace2_size.rs
+++ b/esp32s2/src/syscon/flash_ace2_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace2_size(&mut self) -> FLASH_ACE2_SIZE_W<FLASH_ACE2_SIZE_SPEC> {
         FLASH_ACE2_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace3_addr.rs b/esp32s2/src/syscon/flash_ace3_addr.rs
index 5b323925af..6a7bfb886a 100644
--- a/esp32s2/src/syscon/flash_ace3_addr.rs
+++ b/esp32s2/src/syscon/flash_ace3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE3_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace3_attr.rs b/esp32s2/src/syscon/flash_ace3_attr.rs
index 33e1deb52e..9e562a1bba 100644
--- a/esp32s2/src/syscon/flash_ace3_attr.rs
+++ b/esp32s2/src/syscon/flash_ace3_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace3_attr(&mut self) -> FLASH_ACE3_ATTR_W<FLASH_ACE3_ATTR_SPEC> {
         FLASH_ACE3_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/flash_ace3_size.rs b/esp32s2/src/syscon/flash_ace3_size.rs
index 12d7f8daf8..5a26798347 100644
--- a/esp32s2/src/syscon/flash_ace3_size.rs
+++ b/esp32s2/src/syscon/flash_ace3_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace3_size(&mut self) -> FLASH_ACE3_SIZE_W<FLASH_ACE3_SIZE_SPEC> {
         FLASH_ACE3_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/front_end_mem_pd.rs b/esp32s2/src/syscon/front_end_mem_pd.rs
index 21d97c3024..5c9f7d35e3 100644
--- a/esp32s2/src/syscon/front_end_mem_pd.rs
+++ b/esp32s2/src/syscon/front_end_mem_pd.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pu(&mut self) -> AGC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PU_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pd(&mut self) -> AGC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pu(&mut self) -> PBUS_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PU_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pd(&mut self) -> PBUS_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_mem_force_pu(&mut self) -> DC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         DC_MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_mem_force_pd(&mut self) -> DC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         DC_MEM_FORCE_PD_W::new(self, 5)
     }
diff --git a/esp32s2/src/syscon/host_inf_sel.rs b/esp32s2/src/syscon/host_inf_sel.rs
index e53fccafca..ccccf443d3 100644
--- a/esp32s2/src/syscon/host_inf_sel.rs
+++ b/esp32s2/src/syscon/host_inf_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_io_swap(&mut self) -> PERI_IO_SWAP_W<HOST_INF_SEL_SPEC> {
         PERI_IO_SWAP_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/redcy_sig0.rs b/esp32s2/src/syscon/redcy_sig0.rs
index 2f712a0f24..71ea8c7d1e 100644
--- a/esp32s2/src/syscon/redcy_sig0.rs
+++ b/esp32s2/src/syscon/redcy_sig0.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
-    #[must_use]
     pub fn redcy_sig0(&mut self) -> REDCY_SIG0_W<REDCY_SIG0_SPEC> {
         REDCY_SIG0_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/redcy_sig1.rs b/esp32s2/src/syscon/redcy_sig1.rs
index 806001490a..b42541f853 100644
--- a/esp32s2/src/syscon/redcy_sig1.rs
+++ b/esp32s2/src/syscon/redcy_sig1.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
-    #[must_use]
     pub fn redcy_sig1(&mut self) -> REDCY_SIG1_W<REDCY_SIG1_SPEC> {
         REDCY_SIG1_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sdio_ctrl.rs b/esp32s2/src/syscon/sdio_ctrl.rs
index 826d8ec9fc..3b4e0b7fe7 100644
--- a/esp32s2/src/syscon/sdio_ctrl.rs
+++ b/esp32s2/src/syscon/sdio_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_win_access_en(&mut self) -> SDIO_WIN_ACCESS_EN_W<SDIO_CTRL_SPEC> {
         SDIO_WIN_ACCESS_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/spi_mem_pms_ctrl.rs b/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
index 139bf46006..1897f06259 100644
--- a/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
+++ b/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_mem_reject_clr(&mut self) -> SPI_MEM_REJECT_CLR_W<SPI_MEM_PMS_CTRL_SPEC> {
         SPI_MEM_REJECT_CLR_W::new(self, 1)
     }
diff --git a/esp32s2/src/syscon/sram_ace0_addr.rs b/esp32s2/src/syscon/sram_ace0_addr.rs
index ad02e7be09..20d9f65dea 100644
--- a/esp32s2/src/syscon/sram_ace0_addr.rs
+++ b/esp32s2/src/syscon/sram_ace0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE0_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace0_attr.rs b/esp32s2/src/syscon/sram_ace0_attr.rs
index 012fb41f8e..8bea99fa98 100644
--- a/esp32s2/src/syscon/sram_ace0_attr.rs
+++ b/esp32s2/src/syscon/sram_ace0_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace0_attr(&mut self) -> SRAM_ACE0_ATTR_W<SRAM_ACE0_ATTR_SPEC> {
         SRAM_ACE0_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace0_size.rs b/esp32s2/src/syscon/sram_ace0_size.rs
index 47a32e7f3e..28b0100a4a 100644
--- a/esp32s2/src/syscon/sram_ace0_size.rs
+++ b/esp32s2/src/syscon/sram_ace0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace0_size(&mut self) -> SRAM_ACE0_SIZE_W<SRAM_ACE0_SIZE_SPEC> {
         SRAM_ACE0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace1_addr.rs b/esp32s2/src/syscon/sram_ace1_addr.rs
index 2923e3a2f7..b1cd8d0f87 100644
--- a/esp32s2/src/syscon/sram_ace1_addr.rs
+++ b/esp32s2/src/syscon/sram_ace1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE1_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace1_attr.rs b/esp32s2/src/syscon/sram_ace1_attr.rs
index 91b8627935..8ee9897927 100644
--- a/esp32s2/src/syscon/sram_ace1_attr.rs
+++ b/esp32s2/src/syscon/sram_ace1_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace1_attr(&mut self) -> SRAM_ACE1_ATTR_W<SRAM_ACE1_ATTR_SPEC> {
         SRAM_ACE1_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace1_size.rs b/esp32s2/src/syscon/sram_ace1_size.rs
index 134682497a..c5dc05fbdc 100644
--- a/esp32s2/src/syscon/sram_ace1_size.rs
+++ b/esp32s2/src/syscon/sram_ace1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace1_size(&mut self) -> SRAM_ACE1_SIZE_W<SRAM_ACE1_SIZE_SPEC> {
         SRAM_ACE1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace2_addr.rs b/esp32s2/src/syscon/sram_ace2_addr.rs
index 3b5a63caf5..9e24c9a239 100644
--- a/esp32s2/src/syscon/sram_ace2_addr.rs
+++ b/esp32s2/src/syscon/sram_ace2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE2_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace2_attr.rs b/esp32s2/src/syscon/sram_ace2_attr.rs
index 02ad8cccc9..40fb20ec8f 100644
--- a/esp32s2/src/syscon/sram_ace2_attr.rs
+++ b/esp32s2/src/syscon/sram_ace2_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace2_attr(&mut self) -> SRAM_ACE2_ATTR_W<SRAM_ACE2_ATTR_SPEC> {
         SRAM_ACE2_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace2_size.rs b/esp32s2/src/syscon/sram_ace2_size.rs
index 640c7ea3ee..e564b199a2 100644
--- a/esp32s2/src/syscon/sram_ace2_size.rs
+++ b/esp32s2/src/syscon/sram_ace2_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace2_size(&mut self) -> SRAM_ACE2_SIZE_W<SRAM_ACE2_SIZE_SPEC> {
         SRAM_ACE2_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace3_addr.rs b/esp32s2/src/syscon/sram_ace3_addr.rs
index 77f6b42fab..8194954f5e 100644
--- a/esp32s2/src/syscon/sram_ace3_addr.rs
+++ b/esp32s2/src/syscon/sram_ace3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE3_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace3_attr.rs b/esp32s2/src/syscon/sram_ace3_attr.rs
index 8fd80d6b62..2b313a5d72 100644
--- a/esp32s2/src/syscon/sram_ace3_attr.rs
+++ b/esp32s2/src/syscon/sram_ace3_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace3_attr(&mut self) -> SRAM_ACE3_ATTR_W<SRAM_ACE3_ATTR_SPEC> {
         SRAM_ACE3_ATTR_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sram_ace3_size.rs b/esp32s2/src/syscon/sram_ace3_size.rs
index 006d08bd62..cc7d695d62 100644
--- a/esp32s2/src/syscon/sram_ace3_size.rs
+++ b/esp32s2/src/syscon/sram_ace3_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace3_size(&mut self) -> SRAM_ACE3_SIZE_W<SRAM_ACE3_SIZE_SPEC> {
         SRAM_ACE3_SIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/sysclk_conf.rs b/esp32s2/src/syscon/sysclk_conf.rs
index 924506a44e..de9376d438 100644
--- a/esp32s2/src/syscon/sysclk_conf.rs
+++ b/esp32s2/src/syscon/sysclk_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
         CLK_320M_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
         CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
         RST_TICK_CNT_W::new(self, 12)
     }
diff --git a/esp32s2/src/syscon/tick_conf.rs b/esp32s2/src/syscon/tick_conf.rs
index 8a897d1a15..3f02703851 100644
--- a/esp32s2/src/syscon/tick_conf.rs
+++ b/esp32s2/src/syscon/tick_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<TICK_CONF_SPEC> {
         XTAL_TICK_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<TICK_CONF_SPEC> {
         CK8M_TICK_NUM_W::new(self, 8)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_enable(&mut self) -> TICK_ENABLE_W<TICK_CONF_SPEC> {
         TICK_ENABLE_W::new(self, 16)
     }
diff --git a/esp32s2/src/syscon/wifi_bb_cfg.rs b/esp32s2/src/syscon/wifi_bb_cfg.rs
index d7bb7244d6..5bde8ca55e 100644
--- a/esp32s2/src/syscon/wifi_bb_cfg.rs
+++ b/esp32s2/src/syscon/wifi_bb_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg(&mut self) -> WIFI_BB_CFG_W<WIFI_BB_CFG_SPEC> {
         WIFI_BB_CFG_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/wifi_bb_cfg_2.rs b/esp32s2/src/syscon/wifi_bb_cfg_2.rs
index f27054d4db..b9b3de76a1 100644
--- a/esp32s2/src/syscon/wifi_bb_cfg_2.rs
+++ b/esp32s2/src/syscon/wifi_bb_cfg_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg_2(&mut self) -> WIFI_BB_CFG_2_W<WIFI_BB_CFG_2_SPEC> {
         WIFI_BB_CFG_2_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/wifi_clk_en.rs b/esp32s2/src/syscon/wifi_clk_en.rs
index 1f2c53b71b..c5ddab3a99 100644
--- a/esp32s2/src/syscon/wifi_clk_en.rs
+++ b/esp32s2/src/syscon/wifi_clk_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/syscon/wifi_rst_en.rs b/esp32s2/src/syscon/wifi_rst_en.rs
index 7568846028..83dbc93c26 100644
--- a/esp32s2/src/syscon/wifi_rst_en.rs
+++ b/esp32s2/src/syscon/wifi_rst_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_rst(&mut self) -> WIFI_RST_W<WIFI_RST_EN_SPEC> {
         WIFI_RST_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/bt_lpck_div_frac.rs b/esp32s2/src/system/bt_lpck_div_frac.rs
index bdb046f5c5..2d32b57a0e 100644
--- a/esp32s2/src/system/bt_lpck_div_frac.rs
+++ b/esp32s2/src/system/bt_lpck_div_frac.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 24 - Set this bit to select RTC slow clock as the low power clock."]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_RTC_SLOW_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to select 8m clock as the low power clock."]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_8M_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to select xtal clock as the low power clock."]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to select xtal32k clock as the low power clock."]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL32K_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to enable the RTC low power clock."]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_rtc_en(&mut self) -> LPCLK_RTC_EN_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_RTC_EN_W::new(self, 28)
     }
diff --git a/esp32s2/src/system/bustoextmem_ena.rs b/esp32s2/src/system/bustoextmem_ena.rs
index bd808ebc1f..6324e80303 100644
--- a/esp32s2/src/system/bustoextmem_ena.rs
+++ b/esp32s2/src/system/bustoextmem_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable bus to EDMA."]
     #[inline(always)]
-    #[must_use]
     pub fn bustoextmem_ena(&mut self) -> BUSTOEXTMEM_ENA_W<BUSTOEXTMEM_ENA_SPEC> {
         BUSTOEXTMEM_ENA_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cache_control.rs b/esp32s2/src/system/cache_control.rs
index 407fd80a69..0436ea1574 100644
--- a/esp32s2/src/system/cache_control.rs
+++ b/esp32s2/src/system/cache_control.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of i-cache."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_icache_clk_on(&mut self) -> PRO_ICACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
         PRO_ICACHE_CLK_ON_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable clock of d-cache."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dcache_clk_on(&mut self) -> PRO_DCACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
         PRO_DCACHE_CLK_ON_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset cache."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_cache_reset(&mut self) -> PRO_CACHE_RESET_W<CACHE_CONTROL_SPEC> {
         PRO_CACHE_RESET_W::new(self, 2)
     }
diff --git a/esp32s2/src/system/clock_gate.rs b/esp32s2/src/system/clock_gate.rs
index ef3c77629b..d4d4a1c63e 100644
--- a/esp32s2/src/system/clock_gate.rs
+++ b/esp32s2/src/system/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of this module."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_0.rs b/esp32s2/src/system/cpu_intr_from_cpu_0.rs
index 5b78fc1b4d..77c88961b6 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_0(&mut self) -> CPU_INTR_FROM_CPU_0_W<CPU_INTR_FROM_CPU_0_SPEC> {
         CPU_INTR_FROM_CPU_0_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_1.rs b/esp32s2/src/system/cpu_intr_from_cpu_1.rs
index 5d40e11c15..1c43bbc1cf 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_1(&mut self) -> CPU_INTR_FROM_CPU_1_W<CPU_INTR_FROM_CPU_1_SPEC> {
         CPU_INTR_FROM_CPU_1_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_2.rs b/esp32s2/src/system/cpu_intr_from_cpu_2.rs
index 32e88d99af..b538a804ef 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_2(&mut self) -> CPU_INTR_FROM_CPU_2_W<CPU_INTR_FROM_CPU_2_SPEC> {
         CPU_INTR_FROM_CPU_2_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_3.rs b/esp32s2/src/system/cpu_intr_from_cpu_3.rs
index db53abb33f..b64248c086 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_3(&mut self) -> CPU_INTR_FROM_CPU_3_W<CPU_INTR_FROM_CPU_3_SPEC> {
         CPU_INTR_FROM_CPU_3_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/cpu_per_conf.rs b/esp32s2/src/system/cpu_per_conf.rs
index 1ff9801064..e5c8101b24 100644
--- a/esp32s2/src/system/cpu_per_conf.rs
+++ b/esp32s2/src/system/cpu_per_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to select the clock frequency of CPU or CPU period."]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PER_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - This field is used to select the PLL clock frequency based on CPU period."]
     #[inline(always)]
-    #[must_use]
     pub fn pll_freq_sel(&mut self) -> PLL_FREQ_SEL_W<CPU_PER_CONF_SPEC> {
         PLL_FREQ_SEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_wait_mode_force_on(&mut self) -> CPU_WAIT_MODE_FORCE_ON_W<CPU_PER_CONF_SPEC> {
         CPU_WAIT_MODE_FORCE_ON_W::new(self, 3)
     }
     #[doc = "Bits 4:7 - Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_waiti_delay_num(&mut self) -> CPU_WAITI_DELAY_NUM_W<CPU_PER_CONF_SPEC> {
         CPU_WAITI_DELAY_NUM_W::new(self, 4)
     }
diff --git a/esp32s2/src/system/cpu_peri_clk_en.rs b/esp32s2/src/system/cpu_peri_clk_en.rs
index 7ad16e36e5..b89179ec0b 100644
--- a/esp32s2/src/system/cpu_peri_clk_en.rs
+++ b/esp32s2/src/system/cpu_peri_clk_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - Set this bit to enable clock of DEDICATED GPIO module."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en_dedicated_gpio(&mut self) -> CLK_EN_DEDICATED_GPIO_W<CPU_PERI_CLK_EN_SPEC> {
         CLK_EN_DEDICATED_GPIO_W::new(self, 7)
     }
diff --git a/esp32s2/src/system/cpu_peri_rst_en.rs b/esp32s2/src/system/cpu_peri_rst_en.rs
index ee2c63ebcc..3ec1feaacd 100644
--- a/esp32s2/src/system/cpu_peri_rst_en.rs
+++ b/esp32s2/src/system/cpu_peri_rst_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - Set this bit to reset DEDICATED GPIO module."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_en_dedicated_gpio(&mut self) -> RST_EN_DEDICATED_GPIO_W<CPU_PERI_RST_EN_SPEC> {
         RST_EN_DEDICATED_GPIO_W::new(self, 7)
     }
diff --git a/esp32s2/src/system/date.rs b/esp32s2/src/system/date.rs
index 0517bf080d..219b70e002 100644
--- a/esp32s2/src/system/date.rs
+++ b/esp32s2/src/system/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/external_device_encrypt_decrypt_control.rs b/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
index 95627a578b..f682bcf3c0 100644
--- a/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
@@ -66,7 +66,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable Manual Encryption under SPI Boot mode."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_spi_manual_encrypt(
         &mut self,
     ) -> ENABLE_SPI_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -74,7 +73,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to enable Auto Encryption under Download Boot mode."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_db_encrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_DB_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -82,7 +80,6 @@ impl W {
     }
     #[doc = "Bit 2 - Set this bit to enable Auto Decryption under Download Boot mode."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_g0cb_decrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_G0CB_DECRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -90,7 +87,6 @@ impl W {
     }
     #[doc = "Bit 3 - Set this bit to enable Manual Encryption under Download Boot mode."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_manual_encrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_0.rs b/esp32s2/src/system/jtag_ctrl_0.rs
index 2698b7da1f..4d501702e7 100644
--- a/esp32s2/src/system/jtag_ctrl_0.rs
+++ b/esp32s2/src/system/jtag_ctrl_0.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_0_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_0(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_W<JTAG_CTRL_0_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_1.rs b/esp32s2/src/system/jtag_ctrl_1.rs
index d358fb076c..690f0c85b9 100644
--- a/esp32s2/src/system/jtag_ctrl_1.rs
+++ b/esp32s2/src/system/jtag_ctrl_1.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_1_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_1(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_W<JTAG_CTRL_1_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_2.rs b/esp32s2/src/system/jtag_ctrl_2.rs
index 178d46fb4f..cb124cd36b 100644
--- a/esp32s2/src/system/jtag_ctrl_2.rs
+++ b/esp32s2/src/system/jtag_ctrl_2.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_2_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_2(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_W<JTAG_CTRL_2_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_3.rs b/esp32s2/src/system/jtag_ctrl_3.rs
index de70056fcf..35dc6e8a84 100644
--- a/esp32s2/src/system/jtag_ctrl_3.rs
+++ b/esp32s2/src/system/jtag_ctrl_3.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_3_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_3(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_W<JTAG_CTRL_3_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_4.rs b/esp32s2/src/system/jtag_ctrl_4.rs
index 0cadb32acf..6e12c49bfa 100644
--- a/esp32s2/src/system/jtag_ctrl_4.rs
+++ b/esp32s2/src/system/jtag_ctrl_4.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_4_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_4(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_W<JTAG_CTRL_4_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_5.rs b/esp32s2/src/system/jtag_ctrl_5.rs
index e47b5fdece..efaa48817d 100644
--- a/esp32s2/src/system/jtag_ctrl_5.rs
+++ b/esp32s2/src/system/jtag_ctrl_5.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_5_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_5(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_W<JTAG_CTRL_5_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_6.rs b/esp32s2/src/system/jtag_ctrl_6.rs
index 86f6ebe5c1..a6473f5f1b 100644
--- a/esp32s2/src/system/jtag_ctrl_6.rs
+++ b/esp32s2/src/system/jtag_ctrl_6.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_6_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_6(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_W<JTAG_CTRL_6_SPEC> {
diff --git a/esp32s2/src/system/jtag_ctrl_7.rs b/esp32s2/src/system/jtag_ctrl_7.rs
index ff05eb79fc..d1c2353dd6 100644
--- a/esp32s2/src/system/jtag_ctrl_7.rs
+++ b/esp32s2/src/system/jtag_ctrl_7.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<JTAG_CTRL_7_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn cancel_efuse_disable_jtag_temporary_7(
         &mut self,
     ) -> CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_W<JTAG_CTRL_7_SPEC> {
diff --git a/esp32s2/src/system/lpck_div_int.rs b/esp32s2/src/system/lpck_div_int.rs
index 6f5810b80a..c72aecc821 100644
--- a/esp32s2/src/system/lpck_div_int.rs
+++ b/esp32s2/src/system/lpck_div_int.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - This field is used to set the integer number of the divider value."]
     #[inline(always)]
-    #[must_use]
     pub fn lpck_div_num(&mut self) -> LPCK_DIV_NUM_W<LPCK_DIV_INT_SPEC> {
         LPCK_DIV_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/mem_pd_mask.rs b/esp32s2/src/system/mem_pd_mask.rs
index 1725a5086c..fb879eb6a3 100644
--- a/esp32s2/src/system/mem_pd_mask.rs
+++ b/esp32s2/src/system/mem_pd_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to allow the memory to work as usual when the chip enters the light-sleep state."]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_pd_mask(&mut self) -> LSLP_MEM_PD_MASK_W<MEM_PD_MASK_SPEC> {
         LSLP_MEM_PD_MASK_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/perip_clk_en0.rs b/esp32s2/src/system/perip_clk_en0.rs
index fbbba84121..c8c5b84ba4 100644
--- a/esp32s2/src/system/perip_clk_en0.rs
+++ b/esp32s2/src/system/perip_clk_en0.rs
@@ -334,193 +334,161 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of timers."]
     #[inline(always)]
-    #[must_use]
     pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERS_CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable clock of SPI0 and SPI1."]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI01_CLK_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable clock of UART0."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable clock of WDG."]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         WDG_CLK_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable clock of I2S0."]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2S0_CLK_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable clock of UART1."]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART1_CLK_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable clock of SPI2."]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI2_CLK_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable clock of I2C EXT0."]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2C_EXT0_CLK_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enable clock of UHCI0."]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UHCI0_CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable clock of remote controller."]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         RMT_CLK_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to enable clock of pulse count."]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PCNT_CLK_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to enable clock of LED PWM."]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         LEDC_CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to enable clock of UHCI1."]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UHCI1_CLK_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to enable clock of timer group0."]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERGROUP_CLK_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable clock of eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         EFUSE_CLK_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable clock of timer group1."]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERGROUP1_CLK_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to enable clock of SPI3."]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI3_CLK_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to enable clock of PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM0_CLK_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to enable clock of I2C EXT1."]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_clk_en(&mut self) -> I2C_EXT1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2C_EXT1_CLK_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to enable clock of CAN."]
     #[inline(always)]
-    #[must_use]
     pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TWAI_CLK_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to enable clock of PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM1_CLK_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to enable clock of I2S1."]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2S1_CLK_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to enable clock of SPI2 DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_clk_en(&mut self) -> SPI2_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI2_DMA_CLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to enable clock of USB."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_clk_en(&mut self) -> USB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         USB_CLK_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to enable clock of UART memory."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART_MEM_CLK_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable clock of PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM2_CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable clock of PWM3."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM3_CLK_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable clock of SPI3 DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_clk_en(&mut self) -> SPI3_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI3_DMA_CLK_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to enable clock of SAR ADC."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         APB_SARADC_CLK_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable clock of system timer."]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SYSTIMER_CLK_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable clock of aribiter of ADC2."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         ADC2_ARB_CLK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable clock of SPI4."]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_clk_en(&mut self) -> SPI4_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI4_CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/system/perip_clk_en1.rs b/esp32s2/src/system/perip_clk_en1.rs
index dc401701ae..169d757712 100644
--- a/esp32s2/src/system/perip_clk_en1.rs
+++ b/esp32s2/src/system/perip_clk_en1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - Set this bit to enable clock of cryptography AES."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_aes_clk_en(&mut self) -> CRYPTO_AES_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_AES_CLK_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable clock of cryptography SHA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_sha_clk_en(&mut self) -> CRYPTO_SHA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_SHA_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable clock of cryptography RSA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_rsa_clk_en(&mut self) -> CRYPTO_RSA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_RSA_CLK_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable clock of cryptography Digital Signature."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_ds_clk_en(&mut self) -> CRYPTO_DS_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_DS_CLK_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable clock of cryptography HMAC."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_hmac_clk_en(&mut self) -> CRYPTO_HMAC_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_HMAC_CLK_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable clock of cryptography DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_dma_clk_en(&mut self) -> CRYPTO_DMA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_DMA_CLK_EN_W::new(self, 6)
     }
diff --git a/esp32s2/src/system/perip_rst_en0.rs b/esp32s2/src/system/perip_rst_en0.rs
index f4952621ab..0c9e98f72f 100644
--- a/esp32s2/src/system/perip_rst_en0.rs
+++ b/esp32s2/src/system/perip_rst_en0.rs
@@ -334,193 +334,161 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset timers."]
     #[inline(always)]
-    #[must_use]
     pub fn timers_rst(&mut self) -> TIMERS_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERS_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset SPI0 and SPI1."]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_rst(&mut self) -> SPI01_RST_W<PERIP_RST_EN0_SPEC> {
         SPI01_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset UART0."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rst(&mut self) -> UART_RST_W<PERIP_RST_EN0_SPEC> {
         UART_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset WDG."]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_rst(&mut self) -> WDG_RST_W<PERIP_RST_EN0_SPEC> {
         WDG_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to reset I2S0."]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_rst(&mut self) -> I2S0_RST_W<PERIP_RST_EN0_SPEC> {
         I2S0_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to reset UART1."]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_rst(&mut self) -> UART1_RST_W<PERIP_RST_EN0_SPEC> {
         UART1_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to reset SPI2."]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_rst(&mut self) -> SPI2_RST_W<PERIP_RST_EN0_SPEC> {
         SPI2_RST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to reset I2C EXT0."]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_rst(&mut self) -> I2C_EXT0_RST_W<PERIP_RST_EN0_SPEC> {
         I2C_EXT0_RST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to reset UHCI0."]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_rst(&mut self) -> UHCI0_RST_W<PERIP_RST_EN0_SPEC> {
         UHCI0_RST_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to reset remote controller."]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_rst(&mut self) -> RMT_RST_W<PERIP_RST_EN0_SPEC> {
         RMT_RST_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to reset pulse count."]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_rst(&mut self) -> PCNT_RST_W<PERIP_RST_EN0_SPEC> {
         PCNT_RST_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to reset LED PWM."]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_rst(&mut self) -> LEDC_RST_W<PERIP_RST_EN0_SPEC> {
         LEDC_RST_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to reset UHCI1."]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_rst(&mut self) -> UHCI1_RST_W<PERIP_RST_EN0_SPEC> {
         UHCI1_RST_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to reset timer group0."]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_rst(&mut self) -> TIMERGROUP_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERGROUP_RST_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to reset eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_rst(&mut self) -> EFUSE_RST_W<PERIP_RST_EN0_SPEC> {
         EFUSE_RST_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to reset timer group1."]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_rst(&mut self) -> TIMERGROUP1_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERGROUP1_RST_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to reset SPI3."]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_rst(&mut self) -> SPI3_RST_W<PERIP_RST_EN0_SPEC> {
         SPI3_RST_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to reset PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_rst(&mut self) -> PWM0_RST_W<PERIP_RST_EN0_SPEC> {
         PWM0_RST_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to reset I2C EXT1."]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_rst(&mut self) -> I2C_EXT1_RST_W<PERIP_RST_EN0_SPEC> {
         I2C_EXT1_RST_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to reset CAN."]
     #[inline(always)]
-    #[must_use]
     pub fn twai_rst(&mut self) -> TWAI_RST_W<PERIP_RST_EN0_SPEC> {
         TWAI_RST_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to reset PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_rst(&mut self) -> PWM1_RST_W<PERIP_RST_EN0_SPEC> {
         PWM1_RST_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to reset I2S1."]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_rst(&mut self) -> I2S1_RST_W<PERIP_RST_EN0_SPEC> {
         I2S1_RST_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to reset SPI2 DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_rst(&mut self) -> SPI2_DMA_RST_W<PERIP_RST_EN0_SPEC> {
         SPI2_DMA_RST_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to reset USB."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_rst(&mut self) -> USB_RST_W<PERIP_RST_EN0_SPEC> {
         USB_RST_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to reset UART memory."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_rst(&mut self) -> UART_MEM_RST_W<PERIP_RST_EN0_SPEC> {
         UART_MEM_RST_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to reset PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_rst(&mut self) -> PWM2_RST_W<PERIP_RST_EN0_SPEC> {
         PWM2_RST_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to reset PWM3."]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_rst(&mut self) -> PWM3_RST_W<PERIP_RST_EN0_SPEC> {
         PWM3_RST_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to reset SPI3 DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_rst(&mut self) -> SPI3_DMA_RST_W<PERIP_RST_EN0_SPEC> {
         SPI3_DMA_RST_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to reset SAR ADC."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_saradc_rst(&mut self) -> APB_SARADC_RST_W<PERIP_RST_EN0_SPEC> {
         APB_SARADC_RST_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to reset system timer."]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_rst(&mut self) -> SYSTIMER_RST_W<PERIP_RST_EN0_SPEC> {
         SYSTIMER_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to reset aribiter of ADC2."]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_arb_rst(&mut self) -> ADC2_ARB_RST_W<PERIP_RST_EN0_SPEC> {
         ADC2_ARB_RST_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to reset SPI4."]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_rst(&mut self) -> SPI4_RST_W<PERIP_RST_EN0_SPEC> {
         SPI4_RST_W::new(self, 31)
     }
diff --git a/esp32s2/src/system/perip_rst_en1.rs b/esp32s2/src/system/perip_rst_en1.rs
index 501cc82c1e..372e7e6ad2 100644
--- a/esp32s2/src/system/perip_rst_en1.rs
+++ b/esp32s2/src/system/perip_rst_en1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - Set this bit to reset cryptography AES."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_aes_rst(&mut self) -> CRYPTO_AES_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_AES_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset cryptography SHA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_sha_rst(&mut self) -> CRYPTO_SHA_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_SHA_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset cryptography RSA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_rsa_rst(&mut self) -> CRYPTO_RSA_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_RSA_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to reset cryptography digital signature."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_ds_rst(&mut self) -> CRYPTO_DS_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_DS_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to reset cryptography HMAC."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_hmac_rst(&mut self) -> CRYPTO_HMAC_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_HMAC_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to reset cryptography DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_dma_rst(&mut self) -> CRYPTO_DMA_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_DMA_RST_W::new(self, 6)
     }
diff --git a/esp32s2/src/system/redundant_eco_ctrl.rs b/esp32s2/src/system/redundant_eco_ctrl.rs
index a1051e93ef..4194c4c63c 100644
--- a/esp32s2/src/system/redundant_eco_ctrl.rs
+++ b/esp32s2/src/system/redundant_eco_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The redundant ECO drive bit to avoid optimization in circuits."]
     #[inline(always)]
-    #[must_use]
     pub fn redundant_eco_drive(&mut self) -> REDUNDANT_ECO_DRIVE_W<REDUNDANT_ECO_CTRL_SPEC> {
         REDUNDANT_ECO_DRIVE_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/rom_ctrl_0.rs b/esp32s2/src/system/rom_ctrl_0.rs
index 3709f8d8ff..d490b973ac 100644
--- a/esp32s2/src/system/rom_ctrl_0.rs
+++ b/esp32s2/src/system/rom_ctrl_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to force on clock gate of internal ROM."]
     #[inline(always)]
-    #[must_use]
     pub fn rom_fo(&mut self) -> ROM_FO_W<ROM_CTRL_0_SPEC> {
         ROM_FO_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/rom_ctrl_1.rs b/esp32s2/src/system/rom_ctrl_1.rs
index e931f8f158..c51a02dcb4 100644
--- a/esp32s2/src/system/rom_ctrl_1.rs
+++ b/esp32s2/src/system/rom_ctrl_1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to power down internal ROM."]
     #[inline(always)]
-    #[must_use]
     pub fn rom_force_pd(&mut self) -> ROM_FORCE_PD_W<ROM_CTRL_1_SPEC> {
         ROM_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to power up internal ROM."]
     #[inline(always)]
-    #[must_use]
     pub fn rom_force_pu(&mut self) -> ROM_FORCE_PU_W<ROM_CTRL_1_SPEC> {
         ROM_FORCE_PU_W::new(self, 2)
     }
diff --git a/esp32s2/src/system/rsa_pd_ctrl.rs b/esp32s2/src/system/rsa_pd_ctrl.rs
index 19ec505570..d8cc8f0595 100644
--- a/esp32s2/src/system/rsa_pd_ctrl.rs
+++ b/esp32s2/src/system/rsa_pd_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_pd(&mut self) -> RSA_MEM_PD_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to force power up RSA memory. This bit has the second highest priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_force_pu(&mut self) -> RSA_MEM_FORCE_PU_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to force power down RSA memory. This bit has the highest priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_force_pd(&mut self) -> RSA_MEM_FORCE_PD_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_FORCE_PD_W::new(self, 2)
     }
diff --git a/esp32s2/src/system/rtc_fastmem_config.rs b/esp32s2/src/system/rtc_fastmem_config.rs
index b44367fc76..11352d35d3 100644
--- a/esp32s2/src/system/rtc_fastmem_config.rs
+++ b/esp32s2/src/system/rtc_fastmem_config.rs
@@ -52,19 +52,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 8 - Set this bit to start the CRC of RTC memory."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_start(&mut self) -> RTC_MEM_CRC_START_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_START_W::new(self, 8)
     }
     #[doc = "Bits 9:19 - This field is used to set address of RTC memory for CRC."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_addr(&mut self) -> RTC_MEM_CRC_ADDR_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_ADDR_W::new(self, 9)
     }
     #[doc = "Bits 20:30 - This field is used to set length of RTC memory for CRC based on start address."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_len(&mut self) -> RTC_MEM_CRC_LEN_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_LEN_W::new(self, 20)
     }
diff --git a/esp32s2/src/system/sram_ctrl_0.rs b/esp32s2/src/system/sram_ctrl_0.rs
index b2ec4ca1cf..ea1c7a6423 100644
--- a/esp32s2/src/system/sram_ctrl_0.rs
+++ b/esp32s2/src/system/sram_ctrl_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - This field is used to force on clock gate of internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_fo(&mut self) -> SRAM_FO_W<SRAM_CTRL_0_SPEC> {
         SRAM_FO_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/sram_ctrl_1.rs b/esp32s2/src/system/sram_ctrl_1.rs
index 8eee156452..7b872a65f4 100644
--- a/esp32s2/src/system/sram_ctrl_1.rs
+++ b/esp32s2/src/system/sram_ctrl_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - This field is used to power down internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_force_pd(&mut self) -> SRAM_FORCE_PD_W<SRAM_CTRL_1_SPEC> {
         SRAM_FORCE_PD_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/sram_ctrl_2.rs b/esp32s2/src/system/sram_ctrl_2.rs
index b804a0645f..626201e5a6 100644
--- a/esp32s2/src/system/sram_ctrl_2.rs
+++ b/esp32s2/src/system/sram_ctrl_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - This field is used to power up internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_force_pu(&mut self) -> SRAM_FORCE_PU_W<SRAM_CTRL_2_SPEC> {
         SRAM_FORCE_PU_W::new(self, 0)
     }
diff --git a/esp32s2/src/system/sysclk_conf.rs b/esp32s2/src/system/sysclk_conf.rs
index 55ccb02b03..004d8aa936 100644
--- a/esp32s2/src/system/sysclk_conf.rs
+++ b/esp32s2/src/system/sysclk_conf.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL\\_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
         PRE_DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bits 10:11 - This field is used to select SOC clock."]
     #[inline(always)]
-    #[must_use]
     pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<SYSCLK_CONF_SPEC> {
         SOC_CLK_SEL_W::new(self, 10)
     }
diff --git a/esp32s2/src/systimer/conf.rs b/esp32s2/src/systimer/conf.rs
index a70ca13d8c..aa8cc62086 100644
--- a/esp32s2/src/systimer/conf.rs
+++ b/esp32s2/src/systimer/conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - System timer clock force enable."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_fo(&mut self) -> CLK_FO_W<CONF_SPEC> {
         CLK_FO_W::new(self, 0)
     }
     #[doc = "Bit 31 - Register clock enable."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/systimer/date.rs b/esp32s2/src/systimer/date.rs
index 1ba59f1f8e..502903fc40 100644
--- a/esp32s2/src/systimer/date.rs
+++ b/esp32s2/src/systimer/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/systimer/int_clr.rs b/esp32s2/src/systimer/int_clr.rs
index e4bbd5a8c1..ebeb706c22 100644
--- a/esp32s2/src/systimer/int_clr.rs
+++ b/esp32s2/src/systimer/int_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self, n: u8) -> TARGET_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -21,19 +20,16 @@ impl W {
     }
     #[doc = "Bit 0 - Interrupt clear bit of system timer target 0."]
     #[inline(always)]
-    #[must_use]
     pub fn target0(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Interrupt clear bit of system timer target 1."]
     #[inline(always)]
-    #[must_use]
     pub fn target1(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt clear bit of system timer target 2."]
     #[inline(always)]
-    #[must_use]
     pub fn target2(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 2)
     }
@@ -47,7 +43,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s2/src/systimer/int_ena.rs b/esp32s2/src/systimer/int_ena.rs
index 8da4ef8096..1ae852bd18 100644
--- a/esp32s2/src/systimer/int_ena.rs
+++ b/esp32s2/src/systimer/int_ena.rs
@@ -53,7 +53,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self, n: u8) -> TARGET_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -61,19 +60,16 @@ impl W {
     }
     #[doc = "Bit 0 - Interrupt enable bit of system timer target 0."]
     #[inline(always)]
-    #[must_use]
     pub fn target0(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Interrupt enable bit of system timer target 1."]
     #[inline(always)]
-    #[must_use]
     pub fn target1(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt enable bit of system timer target 2."]
     #[inline(always)]
-    #[must_use]
     pub fn target2(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 2)
     }
diff --git a/esp32s2/src/systimer/load.rs b/esp32s2/src/systimer/load.rs
index 2417d7c91c..7bc581d336 100644
--- a/esp32s2/src/systimer/load.rs
+++ b/esp32s2/src/systimer/load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LOAD_SPEC> {
 impl W {
     #[doc = "Bit 31 - Set this bit to 1, the value stored in SYSTIMER_TIMER_LOAD_HI and in SYSTIMER_TIMER_LOAD_LO will be loaded to system timer"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
         LOAD_W::new(self, 31)
     }
diff --git a/esp32s2/src/systimer/load_hi.rs b/esp32s2/src/systimer/load_hi.rs
index feb10a67ef..cee6fd17f5 100644
--- a/esp32s2/src/systimer/load_hi.rs
+++ b/esp32s2/src/systimer/load_hi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The value to be loaded into system timer, high 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LOAD_HI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/systimer/load_lo.rs b/esp32s2/src/systimer/load_lo.rs
index fbca463174..39590725e6 100644
--- a/esp32s2/src/systimer/load_lo.rs
+++ b/esp32s2/src/systimer/load_lo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The value to be loaded into system timer, low 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LOAD_LO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/systimer/step.rs b/esp32s2/src/systimer/step.rs
index a1d227eadf..26fc939210 100644
--- a/esp32s2/src/systimer/step.rs
+++ b/esp32s2/src/systimer/step.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - Set system timer increment step when using XTAL_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_step(&mut self) -> XTAL_STEP_W<STEP_SPEC> {
         XTAL_STEP_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - Set system timer increment step when using PLL_CLK"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_step(&mut self) -> PLL_STEP_W<STEP_SPEC> {
         PLL_STEP_W::new(self, 10)
     }
diff --git a/esp32s2/src/systimer/target_conf.rs b/esp32s2/src/systimer/target_conf.rs
index d48d58522c..274b0fa15c 100644
--- a/esp32s2/src/systimer/target_conf.rs
+++ b/esp32s2/src/systimer/target_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Set alarm period for system timer target 0, only valid in periodic alarms mode."]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<TARGET_CONF_SPEC> {
         PERIOD_W::new(self, 0)
     }
     #[doc = "Bit 30 - Set work mode for system timer target 0. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode."]
     #[inline(always)]
-    #[must_use]
     pub fn period_mode(&mut self) -> PERIOD_MODE_W<TARGET_CONF_SPEC> {
         PERIOD_MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - System timer target 0 work enable."]
     #[inline(always)]
-    #[must_use]
     pub fn work_en(&mut self) -> WORK_EN_W<TARGET_CONF_SPEC> {
         WORK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/systimer/trgt/hi.rs b/esp32s2/src/systimer/trgt/hi.rs
index fd8dca229c..b507275aa5 100644
--- a/esp32s2/src/systimer/trgt/hi.rs
+++ b/esp32s2/src/systimer/trgt/hi.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - System timer target 0, high 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn hi(&mut self) -> HI_W<HI_SPEC> {
         HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/systimer/trgt/lo.rs b/esp32s2/src/systimer/trgt/lo.rs
index ab337f2ad4..c98e318018 100644
--- a/esp32s2/src/systimer/trgt/lo.rs
+++ b/esp32s2/src/systimer/trgt/lo.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - System timer target 0, low 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn lo(&mut self) -> LO_W<LO_SPEC> {
         LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/systimer/unit_op.rs b/esp32s2/src/systimer/unit_op.rs
index d7f6e5baaa..fbf6847875 100644
--- a/esp32s2/src/systimer/unit_op.rs
+++ b/esp32s2/src/systimer/unit_op.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Update system timer value to registers."]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<UNIT_OP_SPEC> {
         UPDATE_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/int_clr.rs b/esp32s2/src/timg0/int_clr.rs
index 9523dd183c..52433857f0 100644
--- a/esp32s2/src/timg0/int_clr.rs
+++ b/esp32s2/src/timg0/int_clr.rs
@@ -17,7 +17,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -25,25 +24,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the TIMG_T0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the TIMG_T1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the TIMG_WDT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the TIMG_LACT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lact(&mut self) -> LACT_W<INT_CLR_SPEC> {
         LACT_W::new(self, 3)
     }
@@ -57,7 +52,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0d;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s2/src/timg0/int_ena.rs b/esp32s2/src/timg0/int_ena.rs
index bf6f372558..57ed6cfbb3 100644
--- a/esp32s2/src/timg0/int_ena.rs
+++ b/esp32s2/src/timg0/int_ena.rs
@@ -67,7 +67,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -75,25 +74,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the TIMG_T0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the TIMG_T1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the TIMG_WDT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the TIMG_LACT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lact(&mut self) -> LACT_W<INT_ENA_SPEC> {
         LACT_W::new(self, 3)
     }
diff --git a/esp32s2/src/timg0/lactalarmhi.rs b/esp32s2/src/timg0/lactalarmhi.rs
index 15bb7810ad..74dafbfb4c 100644
--- a/esp32s2/src/timg0/lactalarmhi.rs
+++ b/esp32s2/src/timg0/lactalarmhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_hi(&mut self) -> ALARM_HI_W<LACTALARMHI_SPEC> {
         ALARM_HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/lactalarmlo.rs b/esp32s2/src/timg0/lactalarmlo.rs
index 5c359cf0a5..f0047959d4 100644
--- a/esp32s2/src/timg0/lactalarmlo.rs
+++ b/esp32s2/src/timg0/lactalarmlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_lo(&mut self) -> ALARM_LO_W<LACTALARMLO_SPEC> {
         ALARM_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/lactconfig.rs b/esp32s2/src/timg0/lactconfig.rs
index 9662cc78cb..c1f0926609 100644
--- a/esp32s2/src/timg0/lactconfig.rs
+++ b/esp32s2/src/timg0/lactconfig.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 6 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn use_reftick(&mut self) -> USE_REFTICK_W<LACTCONFIG_SPEC> {
         USE_REFTICK_W::new(self, 6)
     }
     #[doc = "Bit 7 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_only(&mut self) -> RTC_ONLY_W<LACTCONFIG_SPEC> {
         RTC_ONLY_W::new(self, 7)
     }
     #[doc = "Bit 8 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn cpst_en(&mut self) -> CPST_EN_W<LACTCONFIG_SPEC> {
         CPST_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn lac_en(&mut self) -> LAC_EN_W<LACTCONFIG_SPEC> {
         LAC_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_en(&mut self) -> ALARM_EN_W<LACTCONFIG_SPEC> {
         ALARM_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn level_int_en(&mut self) -> LEVEL_INT_EN_W<LACTCONFIG_SPEC> {
         LEVEL_INT_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn edge_int_en(&mut self) -> EDGE_INT_EN_W<LACTCONFIG_SPEC> {
         EDGE_INT_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:28 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn divider(&mut self) -> DIVIDER_W<LACTCONFIG_SPEC> {
         DIVIDER_W::new(self, 13)
     }
     #[doc = "Bit 29 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn autoreload(&mut self) -> AUTORELOAD_W<LACTCONFIG_SPEC> {
         AUTORELOAD_W::new(self, 29)
     }
     #[doc = "Bit 30 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn increase(&mut self) -> INCREASE_W<LACTCONFIG_SPEC> {
         INCREASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<LACTCONFIG_SPEC> {
         EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/lactload.rs b/esp32s2/src/timg0/lactload.rs
index 5ec33d3854..808d816f67 100644
--- a/esp32s2/src/timg0/lactload.rs
+++ b/esp32s2/src/timg0/lactload.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LACTLOAD_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LACTLOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/lactloadhi.rs b/esp32s2/src/timg0/lactloadhi.rs
index 8704fe790f..e723abfcac 100644
--- a/esp32s2/src/timg0/lactloadhi.rs
+++ b/esp32s2/src/timg0/lactloadhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LACTLOADHI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/lactloadlo.rs b/esp32s2/src/timg0/lactloadlo.rs
index 17eb7bfb9b..4d7d7d8fa8 100644
--- a/esp32s2/src/timg0/lactloadlo.rs
+++ b/esp32s2/src/timg0/lactloadlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LACTLOADLO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/lactrtc.rs b/esp32s2/src/timg0/lactrtc.rs
index 76ab945f59..62c8e42cc9 100644
--- a/esp32s2/src/timg0/lactrtc.rs
+++ b/esp32s2/src/timg0/lactrtc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 6:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_step_len(&mut self) -> RTC_STEP_LEN_W<LACTRTC_SPEC> {
         RTC_STEP_LEN_W::new(self, 6)
     }
diff --git a/esp32s2/src/timg0/lactupdate.rs b/esp32s2/src/timg0/lactupdate.rs
index 0c1e251b7e..26456e1250 100644
--- a/esp32s2/src/timg0/lactupdate.rs
+++ b/esp32s2/src/timg0/lactupdate.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LACTUPDATE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<LACTUPDATE_SPEC> {
         UPDATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/regclk.rs b/esp32s2/src/timg0/regclk.rs
index 2c4aaa291d..5868e75b49 100644
--- a/esp32s2/src/timg0/regclk.rs
+++ b/esp32s2/src/timg0/regclk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<REGCLK_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/rtccalicfg.rs b/esp32s2/src/timg0/rtccalicfg.rs
index e92d2d8b5e..f980c3ef11 100644
--- a/esp32s2/src/timg0/rtccalicfg.rs
+++ b/esp32s2/src/timg0/rtccalicfg.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - When set, periodic calibration is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start_cycling(&mut self) -> RTC_CALI_START_CYCLING_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_CYCLING_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - Used to select the clock to be calibrated. 0: RTC_CLK. 1: RTC20M_D256_CLK. 2: XTAL32K_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_clk_sel(&mut self) -> RTC_CALI_CLK_SEL_W<RTCCALICFG_SPEC> {
         RTC_CALI_CLK_SEL_W::new(self, 13)
     }
     #[doc = "Bits 16:30 - Calibration time, in cycles of the clock to be calibrated."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_max(&mut self) -> RTC_CALI_MAX_W<RTCCALICFG_SPEC> {
         RTC_CALI_MAX_W::new(self, 16)
     }
     #[doc = "Bit 31 - Set this bit to starts calibration."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start(&mut self) -> RTC_CALI_START_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/rtccalicfg2.rs b/esp32s2/src/timg0/rtccalicfg2.rs
index 9bcb8e66e3..c8e2a89280 100644
--- a/esp32s2/src/timg0/rtccalicfg2.rs
+++ b/esp32s2/src/timg0/rtccalicfg2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_timeout_rst_cnt(&mut self) -> RTC_CALI_TIMEOUT_RST_CNT_W<RTCCALICFG2_SPEC> {
         RTC_CALI_TIMEOUT_RST_CNT_W::new(self, 3)
     }
     #[doc = "Bits 7:31 - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_timeout_thres(&mut self) -> RTC_CALI_TIMEOUT_THRES_W<RTCCALICFG2_SPEC> {
         RTC_CALI_TIMEOUT_THRES_W::new(self, 7)
     }
diff --git a/esp32s2/src/timg0/t/alarmhi.rs b/esp32s2/src/timg0/t/alarmhi.rs
index d608e7c336..aad4ff0ae7 100644
--- a/esp32s2/src/timg0/t/alarmhi.rs
+++ b/esp32s2/src/timg0/t/alarmhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, high 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_hi(&mut self) -> ALARM_HI_W<ALARMHI_SPEC> {
         ALARM_HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/t/alarmlo.rs b/esp32s2/src/timg0/t/alarmlo.rs
index ecc2e8aae8..392a0eb764 100644
--- a/esp32s2/src/timg0/t/alarmlo.rs
+++ b/esp32s2/src/timg0/t/alarmlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_lo(&mut self) -> ALARM_LO_W<ALARMLO_SPEC> {
         ALARM_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/t/config.rs b/esp32s2/src/timg0/t/config.rs
index 1012ac8317..90c0ed8f79 100644
--- a/esp32s2/src/timg0/t/config.rs
+++ b/esp32s2/src/timg0/t/config.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
-    #[must_use]
     pub fn use_xtal(&mut self) -> USE_XTAL_W<CONFIG_SPEC> {
         USE_XTAL_W::new(self, 9)
     }
     #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_en(&mut self) -> ALARM_EN_W<CONFIG_SPEC> {
         ALARM_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - When set, an alarm will generate a level type interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn level_int_en(&mut self) -> LEVEL_INT_EN_W<CONFIG_SPEC> {
         LEVEL_INT_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - When set, an alarm will generate an edge type interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn edge_int_en(&mut self) -> EDGE_INT_EN_W<CONFIG_SPEC> {
         EDGE_INT_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."]
     #[inline(always)]
-    #[must_use]
     pub fn divider(&mut self) -> DIVIDER_W<CONFIG_SPEC> {
         DIVIDER_W::new(self, 13)
     }
     #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn autoreload(&mut self) -> AUTORELOAD_W<CONFIG_SPEC> {
         AUTORELOAD_W::new(self, 29)
     }
     #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
     #[inline(always)]
-    #[must_use]
     pub fn increase(&mut self) -> INCREASE_W<CONFIG_SPEC> {
         INCREASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CONFIG_SPEC> {
         EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/t/load.rs b/esp32s2/src/timg0/t/load.rs
index b437ba594a..c44a604a74 100644
--- a/esp32s2/src/timg0/t/load.rs
+++ b/esp32s2/src/timg0/t/load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LOAD_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value to trigger a timer %s time-base counter reload."]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/t/loadhi.rs b/esp32s2/src/timg0/t/loadhi.rs
index ee6c8b2e51..815927f406 100644
--- a/esp32s2/src/timg0/t/loadhi.rs
+++ b/esp32s2/src/timg0/t/loadhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - High 32 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LOADHI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/t/loadlo.rs b/esp32s2/src/timg0/t/loadlo.rs
index a750b30d1f..f67544d164 100644
--- a/esp32s2/src/timg0/t/loadlo.rs
+++ b/esp32s2/src/timg0/t/loadlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LOADLO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/t/update.rs b/esp32s2/src/timg0/t/update.rs
index 8d735dc57f..e4ed42a343 100644
--- a/esp32s2/src/timg0/t/update.rs
+++ b/esp32s2/src/timg0/t/update.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<UPDATE_SPEC> {
         UPDATE_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/timers_date.rs b/esp32s2/src/timg0/timers_date.rs
index f26eb4ae28..47485a02d0 100644
--- a/esp32s2/src/timg0/timers_date.rs
+++ b/esp32s2/src/timg0/timers_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn timers_date(&mut self) -> TIMERS_DATE_W<TIMERS_DATE_SPEC> {
         TIMERS_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtconfig0.rs b/esp32s2/src/timg0/wdtconfig0.rs
index 446506bc84..f29e1c7faa 100644
--- a/esp32s2/src/timg0/wdtconfig0.rs
+++ b/esp32s2/src/timg0/wdtconfig0.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_APPCPU_RESET_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - WDT reset CPU enable."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_PROCPU_RESET_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - When set, Flash boot protection is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 14)
     }
     #[doc = "Bits 15:17 - System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 18)
     }
     #[doc = "Bit 21 - When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_LEVEL_INT_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EDGE_INT_EN_W::new(self, 22)
     }
     #[doc = "Bits 23:24 - Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 29)
     }
     #[doc = "Bit 31 - When set, MWDT is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/timg0/wdtconfig1.rs b/esp32s2/src/timg0/wdtconfig1.rs
index b9bf04381d..d88a70c2f1 100644
--- a/esp32s2/src/timg0/wdtconfig1.rs
+++ b/esp32s2/src/timg0/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_clk_prescale(&mut self) -> WDT_CLK_PRESCALE_W<WDTCONFIG1_SPEC> {
         WDT_CLK_PRESCALE_W::new(self, 16)
     }
diff --git a/esp32s2/src/timg0/wdtconfig2.rs b/esp32s2/src/timg0/wdtconfig2.rs
index d7aedad9be..2eb13ae372 100644
--- a/esp32s2/src/timg0/wdtconfig2.rs
+++ b/esp32s2/src/timg0/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtconfig3.rs b/esp32s2/src/timg0/wdtconfig3.rs
index 3eb96b1e93..353e861c97 100644
--- a/esp32s2/src/timg0/wdtconfig3.rs
+++ b/esp32s2/src/timg0/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtconfig4.rs b/esp32s2/src/timg0/wdtconfig4.rs
index c522268b4c..adb732fce4 100644
--- a/esp32s2/src/timg0/wdtconfig4.rs
+++ b/esp32s2/src/timg0/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtconfig5.rs b/esp32s2/src/timg0/wdtconfig5.rs
index 61c6bfb1e1..a56ba8caeb 100644
--- a/esp32s2/src/timg0/wdtconfig5.rs
+++ b/esp32s2/src/timg0/wdtconfig5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG5_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtfeed.rs b/esp32s2/src/timg0/wdtfeed.rs
index 85fc2e84ca..c009a9e243 100644
--- a/esp32s2/src/timg0/wdtfeed.rs
+++ b/esp32s2/src/timg0/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value to feed the MWDT."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 0)
     }
diff --git a/esp32s2/src/timg0/wdtwprotect.rs b/esp32s2/src/timg0/wdtwprotect.rs
index f3d13ea457..db5716850f 100644
--- a/esp32s2/src/timg0/wdtwprotect.rs
+++ b/esp32s2/src/timg0/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/bus_timing_0.rs b/esp32s2/src/twai0/bus_timing_0.rs
index 3acc8fe70a..eaaf1004d0 100644
--- a/esp32s2/src/twai0/bus_timing_0.rs
+++ b/esp32s2/src/twai0/bus_timing_0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
-    #[must_use]
     pub fn baud_presc(&mut self) -> BAUD_PRESC_W<BUS_TIMING_0_SPEC> {
         BAUD_PRESC_W::new(self, 0)
     }
     #[doc = "Bits 14:15 - Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_jump_width(&mut self) -> SYNC_JUMP_WIDTH_W<BUS_TIMING_0_SPEC> {
         SYNC_JUMP_WIDTH_W::new(self, 14)
     }
diff --git a/esp32s2/src/twai0/bus_timing_1.rs b/esp32s2/src/twai0/bus_timing_1.rs
index edd5e6575c..387797e218 100644
--- a/esp32s2/src/twai0/bus_timing_1.rs
+++ b/esp32s2/src/twai0/bus_timing_1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg1(&mut self) -> TIME_SEG1_W<BUS_TIMING_1_SPEC> {
         TIME_SEG1_W::new(self, 0)
     }
     #[doc = "Bits 4:6 - The width of PBS2."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg2(&mut self) -> TIME_SEG2_W<BUS_TIMING_1_SPEC> {
         TIME_SEG2_W::new(self, 4)
     }
     #[doc = "Bit 7 - The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times"]
     #[inline(always)]
-    #[must_use]
     pub fn time_samp(&mut self) -> TIME_SAMP_W<BUS_TIMING_1_SPEC> {
         TIME_SAMP_W::new(self, 7)
     }
diff --git a/esp32s2/src/twai0/clock_divider.rs b/esp32s2/src/twai0/clock_divider.rs
index 604cc61578..7c8b88d257 100644
--- a/esp32s2/src/twai0/clock_divider.rs
+++ b/esp32s2/src/twai0/clock_divider.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
-    #[must_use]
     pub fn cd(&mut self) -> CD_W<CLOCK_DIVIDER_SPEC> {
         CD_W::new(self, 0)
     }
     #[doc = "Bit 8 - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
     #[inline(always)]
-    #[must_use]
     pub fn clock_off(&mut self) -> CLOCK_OFF_W<CLOCK_DIVIDER_SPEC> {
         CLOCK_OFF_W::new(self, 8)
     }
diff --git a/esp32s2/src/twai0/cmd.rs b/esp32s2/src/twai0/cmd.rs
index 9dec5c5851..7f85b98347 100644
--- a/esp32s2/src/twai0/cmd.rs
+++ b/esp32s2/src/twai0/cmd.rs
@@ -19,31 +19,26 @@ impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set the bit to 1 to allow the driving nodes start transmission."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_req(&mut self) -> TX_REQ_W<CMD_SPEC> {
         TX_REQ_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to 1 to cancel a pending transmission request."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_tx(&mut self) -> ABORT_TX_W<CMD_SPEC> {
         ABORT_TX_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to 1 to release the RX buffer."]
     #[inline(always)]
-    #[must_use]
     pub fn release_buf(&mut self) -> RELEASE_BUF_W<CMD_SPEC> {
         RELEASE_BUF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to 1 to clear the data overrun status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn clr_overrun(&mut self) -> CLR_OVERRUN_W<CMD_SPEC> {
         CLR_OVERRUN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously."]
     #[inline(always)]
-    #[must_use]
     pub fn self_rx_req(&mut self) -> SELF_RX_REQ_W<CMD_SPEC> {
         SELF_RX_REQ_W::new(self, 4)
     }
diff --git a/esp32s2/src/twai0/data_0.rs b/esp32s2/src/twai0/data_0.rs
index 9da54a5102..0d31668320 100644
--- a/esp32s2/src/twai0/data_0.rs
+++ b/esp32s2/src/twai0/data_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_0(&mut self) -> TX_BYTE_0_W<DATA_0_SPEC> {
         TX_BYTE_0_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_1.rs b/esp32s2/src/twai0/data_1.rs
index 4fca4af070..b45d9c5e99 100644
--- a/esp32s2/src/twai0/data_1.rs
+++ b/esp32s2/src/twai0/data_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_1(&mut self) -> TX_BYTE_1_W<DATA_1_SPEC> {
         TX_BYTE_1_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_10.rs b/esp32s2/src/twai0/data_10.rs
index d3a1181d8d..756d4b4006 100644
--- a/esp32s2/src/twai0/data_10.rs
+++ b/esp32s2/src/twai0/data_10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_10(&mut self) -> TX_BYTE_10_W<DATA_10_SPEC> {
         TX_BYTE_10_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_11.rs b/esp32s2/src/twai0/data_11.rs
index a07192b292..80e75ecb8f 100644
--- a/esp32s2/src/twai0/data_11.rs
+++ b/esp32s2/src/twai0/data_11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_11(&mut self) -> TX_BYTE_11_W<DATA_11_SPEC> {
         TX_BYTE_11_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_12.rs b/esp32s2/src/twai0/data_12.rs
index c6b1c97f51..20646c57b9 100644
--- a/esp32s2/src/twai0/data_12.rs
+++ b/esp32s2/src/twai0/data_12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_12(&mut self) -> TX_BYTE_12_W<DATA_12_SPEC> {
         TX_BYTE_12_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_2.rs b/esp32s2/src/twai0/data_2.rs
index 3179326e84..0c7db88aa8 100644
--- a/esp32s2/src/twai0/data_2.rs
+++ b/esp32s2/src/twai0/data_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_2(&mut self) -> TX_BYTE_2_W<DATA_2_SPEC> {
         TX_BYTE_2_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_3.rs b/esp32s2/src/twai0/data_3.rs
index b639a7b9bf..e7df26464e 100644
--- a/esp32s2/src/twai0/data_3.rs
+++ b/esp32s2/src/twai0/data_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_3(&mut self) -> TX_BYTE_3_W<DATA_3_SPEC> {
         TX_BYTE_3_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_4.rs b/esp32s2/src/twai0/data_4.rs
index 4f473f3008..90ff6b33db 100644
--- a/esp32s2/src/twai0/data_4.rs
+++ b/esp32s2/src/twai0/data_4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_4(&mut self) -> TX_BYTE_4_W<DATA_4_SPEC> {
         TX_BYTE_4_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_5.rs b/esp32s2/src/twai0/data_5.rs
index c622efb8c4..7f9f1e5590 100644
--- a/esp32s2/src/twai0/data_5.rs
+++ b/esp32s2/src/twai0/data_5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_5(&mut self) -> TX_BYTE_5_W<DATA_5_SPEC> {
         TX_BYTE_5_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_6.rs b/esp32s2/src/twai0/data_6.rs
index 994c3b5883..73a15eebef 100644
--- a/esp32s2/src/twai0/data_6.rs
+++ b/esp32s2/src/twai0/data_6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_6(&mut self) -> TX_BYTE_6_W<DATA_6_SPEC> {
         TX_BYTE_6_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_7.rs b/esp32s2/src/twai0/data_7.rs
index 28c5d98ef9..c637a8aa7b 100644
--- a/esp32s2/src/twai0/data_7.rs
+++ b/esp32s2/src/twai0/data_7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_7(&mut self) -> TX_BYTE_7_W<DATA_7_SPEC> {
         TX_BYTE_7_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_8.rs b/esp32s2/src/twai0/data_8.rs
index 45046802aa..3d1d76d086 100644
--- a/esp32s2/src/twai0/data_8.rs
+++ b/esp32s2/src/twai0/data_8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_8(&mut self) -> TX_BYTE_8_W<DATA_8_SPEC> {
         TX_BYTE_8_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/data_9.rs b/esp32s2/src/twai0/data_9.rs
index 09d489b574..7a9e68c967 100644
--- a/esp32s2/src/twai0/data_9.rs
+++ b/esp32s2/src/twai0/data_9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_9(&mut self) -> TX_BYTE_9_W<DATA_9_SPEC> {
         TX_BYTE_9_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/err_warning_limit.rs b/esp32s2/src/twai0/err_warning_limit.rs
index 4a0c61301c..df1aa0b277 100644
--- a/esp32s2/src/twai0/err_warning_limit.rs
+++ b/esp32s2/src/twai0/err_warning_limit.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warning_limit(&mut self) -> ERR_WARNING_LIMIT_W<ERR_WARNING_LIMIT_SPEC> {
         ERR_WARNING_LIMIT_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/int_ena.rs b/esp32s2/src/twai0/int_ena.rs
index 3b6932558a..d3977eaa4a 100644
--- a/esp32s2/src/twai0/int_ena.rs
+++ b/esp32s2/src/twai0/int_ena.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_int_ena(&mut self) -> RX_INT_ENA_W<INT_ENA_SPEC> {
         RX_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to 1 to enable transmit interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_int_ena(&mut self) -> TX_INT_ENA_W<INT_ENA_SPEC> {
         TX_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable error warning interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warn_int_ena(&mut self) -> ERR_WARN_INT_ENA_W<INT_ENA_SPEC> {
         ERR_WARN_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable data overrun interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn overrun_int_ena(&mut self) -> OVERRUN_INT_ENA_W<INT_ENA_SPEC> {
         OVERRUN_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable error passive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INT_ENA_SPEC> {
         ERR_PASSIVE_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to 1 to enable arbitration lost interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arb_lost_int_ena(&mut self) -> ARB_LOST_INT_ENA_W<INT_ENA_SPEC> {
         ARB_LOST_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to 1 to enable error interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INT_ENA_SPEC> {
         BUS_ERR_INT_ENA_W::new(self, 7)
     }
diff --git a/esp32s2/src/twai0/mode.rs b/esp32s2/src/twai0/mode.rs
index ddce5ed67c..deebf1574c 100644
--- a/esp32s2/src/twai0/mode.rs
+++ b/esp32s2/src/twai0/mode.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn reset_mode(&mut self) -> RESET_MODE_W<MODE_SPEC> {
         RESET_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter."]
     #[inline(always)]
-    #[must_use]
     pub fn listen_only_mode(&mut self) -> LISTEN_ONLY_MODE_W<MODE_SPEC> {
         LISTEN_ONLY_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command."]
     #[inline(always)]
-    #[must_use]
     pub fn self_test_mode(&mut self) -> SELF_TEST_MODE_W<MODE_SPEC> {
         SELF_TEST_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_mode(&mut self) -> RX_FILTER_MODE_W<MODE_SPEC> {
         RX_FILTER_MODE_W::new(self, 3)
     }
diff --git a/esp32s2/src/twai0/rx_err_cnt.rs b/esp32s2/src/twai0/rx_err_cnt.rs
index 0e7eedf680..b421e30b14 100644
--- a/esp32s2/src/twai0/rx_err_cnt.rs
+++ b/esp32s2/src/twai0/rx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_err_cnt(&mut self) -> RX_ERR_CNT_W<RX_ERR_CNT_SPEC> {
         RX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32s2/src/twai0/tx_err_cnt.rs b/esp32s2/src/twai0/tx_err_cnt.rs
index 64ad2e844e..59fbc2d773 100644
--- a/esp32s2/src/twai0/tx_err_cnt.rs
+++ b/esp32s2/src/twai0/tx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_err_cnt(&mut self) -> TX_ERR_CNT_W<TX_ERR_CNT_SPEC> {
         TX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/at_cmd_char.rs b/esp32s2/src/uart0/at_cmd_char.rs
index 20e5e654d4..ad811525ec 100644
--- a/esp32s2/src/uart0/at_cmd_char.rs
+++ b/esp32s2/src/uart0/at_cmd_char.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of AT_CMD character."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W<AT_CMD_CHAR_SPEC> {
         AT_CMD_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to configure the number of continuous AT_CMD characters received by the receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn char_num(&mut self) -> CHAR_NUM_W<AT_CMD_CHAR_SPEC> {
         CHAR_NUM_W::new(self, 8)
     }
diff --git a/esp32s2/src/uart0/at_cmd_gaptout.rs b/esp32s2/src/uart0/at_cmd_gaptout.rs
index 6e039a3d61..7f872500dc 100644
--- a/esp32s2/src/uart0/at_cmd_gaptout.rs
+++ b/esp32s2/src/uart0/at_cmd_gaptout.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the AT_CMD characters. It will not take the data as continuous AT_CMD characters when the duration time is less than this register's value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W<AT_CMD_GAPTOUT_SPEC> {
         RX_GAP_TOUT_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/at_cmd_postcnt.rs b/esp32s2/src/uart0/at_cmd_postcnt.rs
index f952e71356..29c03d3fda 100644
--- a/esp32s2/src/uart0/at_cmd_postcnt.rs
+++ b/esp32s2/src/uart0/at_cmd_postcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last AT_CMD and the next data. It will not take the previous data as AT_CMD character when the duration is less than this register's value."]
     #[inline(always)]
-    #[must_use]
     pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W<AT_CMD_POSTCNT_SPEC> {
         POST_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/at_cmd_precnt.rs b/esp32s2/src/uart0/at_cmd_precnt.rs
index 5cb0775a40..761c46961e 100644
--- a/esp32s2/src/uart0/at_cmd_precnt.rs
+++ b/esp32s2/src/uart0/at_cmd_precnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first AT_CMD is received by the receiver. It will not take the next data received as AT_CMD character when the duration is less than this register's value."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W<AT_CMD_PRECNT_SPEC> {
         PRE_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/autobaud.rs b/esp32s2/src/uart0/autobaud.rs
index 2ccfb30fea..822869c0de 100644
--- a/esp32s2/src/uart0/autobaud.rs
+++ b/esp32s2/src/uart0/autobaud.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit for baud rate detection."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<AUTOBAUD_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - When input pulse width is lower than this value, the pulse is ignored. This register is used in autobaud detection."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_filt(&mut self) -> GLITCH_FILT_W<AUTOBAUD_SPEC> {
         GLITCH_FILT_W::new(self, 8)
     }
diff --git a/esp32s2/src/uart0/clkdiv.rs b/esp32s2/src/uart0/clkdiv.rs
index c10dc6cc8d..e19ba5c7c4 100644
--- a/esp32s2/src/uart0/clkdiv.rs
+++ b/esp32s2/src/uart0/clkdiv.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - The integral part of the frequency divisor."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SPEC> {
         CLKDIV_W::new(self, 0)
     }
     #[doc = "Bits 20:23 - The fractional part of the frequency divisor."]
     #[inline(always)]
-    #[must_use]
     pub fn frag(&mut self) -> FRAG_W<CLKDIV_SPEC> {
         FRAG_W::new(self, 20)
     }
diff --git a/esp32s2/src/uart0/conf0.rs b/esp32s2/src/uart0/conf0.rs
index df55f0e50b..6ac9a93269 100644
--- a/esp32s2/src/uart0/conf0.rs
+++ b/esp32s2/src/uart0/conf0.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode. 0: even. 1: odd."]
     #[inline(always)]
-    #[must_use]
     pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
         PARITY_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable UART parity check."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
         PARITY_EN_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - This register is used to set the length of data. 0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
         BIT_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - This register is used to set the length of stop bit. 1: 1 bit. 2: 1.5 bits. 3: 2 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
         STOP_BIT_NUM_W::new(self, 4)
     }
     #[doc = "Bit 6 - This register is used to configure the software RTS signal which is used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
         SW_RTS_W::new(self, 6)
     }
     #[doc = "Bit 7 - This register is used to configure the software DTR signal which is used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF0_SPEC> {
         SW_DTR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enable the transmitter to send NULL characters when the process of sending data is done."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
         TXD_BRK_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable IrDA loopback mode."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
         IRDA_DPLX_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the start enable bit for IrDA transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
         IRDA_TX_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: The IrDA transmitter's 11th bit is the same as 10th bit. 0: Set IrDA transmitter's 11th bit to 0."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
         IRDA_WCTL_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to invert the level of IrDA transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
         IRDA_TX_INV_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to invert the level of IrDA receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
         IRDA_RX_INV_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable UART loopback test mode."]
     #[inline(always)]
-    #[must_use]
     pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
         LOOPBACK_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable flow control function for the transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
         TX_FLOW_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to enable IrDA protocol."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
         IRDA_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to reset the UART RX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
         RXFIFO_RST_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to reset the UART TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
         TXFIFO_RST_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to invert the level of UART RXD signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
         RXD_INV_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to invert the level of UART CTS signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_inv(&mut self) -> CTS_INV_W<CONF0_SPEC> {
         CTS_INV_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to invert the level of UART DSR signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF0_SPEC> {
         DSR_INV_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to invert the level of UART TXD signal."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
         TXD_INV_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to invert the level of UART RTS signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rts_inv(&mut self) -> RTS_INV_W<CONF0_SPEC> {
         RTS_INV_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to invert the level of UART DTR signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF0_SPEC> {
         DTR_INV_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: Force clock on for registers. 0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong."]
     #[inline(always)]
-    #[must_use]
     pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
         ERR_WR_MASK_W::new(self, 26)
     }
     #[doc = "Bit 27 - This register is used to select the clock. 1: APB_CLK. 0: REF_TICK."]
     #[inline(always)]
-    #[must_use]
     pub fn tick_ref_always_on(&mut self) -> TICK_REF_ALWAYS_ON_W<CONF0_SPEC> {
         TICK_REF_ALWAYS_ON_W::new(self, 27)
     }
     #[doc = "Bit 28 - The signal to enable UART RAM clock gating. 1: UART RAM powers on, the data of which can be read and written. 0: UART RAM powers down."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SPEC> {
         MEM_CLK_EN_W::new(self, 28)
     }
diff --git a/esp32s2/src/uart0/conf1.rs b/esp32s2/src/uart0/conf1.rs
index 9bacc70bb8..b9e6e43f67 100644
--- a/esp32s2/src/uart0/conf1.rs
+++ b/esp32s2/src/uart0/conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<CONF1_SPEC> {
         RXFIFO_FULL_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 9:17 - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register's value."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<CONF1_SPEC> {
         TXFIFO_EMPTY_THRHD_W::new(self, 9)
     }
     #[doc = "Bit 29 - Set this bit to stop accumulating idle_cnt when hardware flow control works."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W<CONF1_SPEC> {
         RX_TOUT_FLOW_DIS_W::new(self, 29)
     }
     #[doc = "Bit 30 - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<CONF1_SPEC> {
         RX_FLOW_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - This is the enable bit for UART receiver's timeout function."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<CONF1_SPEC> {
         RX_TOUT_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/uart0/date.rs b/esp32s2/src/uart0/date.rs
index c0c8a01a64..ab5afd4312 100644
--- a/esp32s2/src/uart0/date.rs
+++ b/esp32s2/src/uart0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/fifo.rs b/esp32s2/src/uart0/fifo.rs
index bbd207ed48..044c77bb18 100644
--- a/esp32s2/src/uart0/fifo.rs
+++ b/esp32s2/src/uart0/fifo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rd_byte(&mut self) -> RXFIFO_RD_BYTE_W<FIFO_SPEC> {
         RXFIFO_RD_BYTE_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/flow_conf.rs b/esp32s2/src/uart0/flow_conf.rs
index dd8ee47781..879a3e766e 100644
--- a/esp32s2/src/uart0/flow_conf.rs
+++ b/esp32s2/src/uart0/flow_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W<FLOW_CONF_SPEC> {
         SW_FLOW_CON_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to remove flow control characters from the received data."]
     #[inline(always)]
-    #[must_use]
     pub fn xonoff_del(&mut self) -> XONOFF_DEL_W<FLOW_CONF_SPEC> {
         XONOFF_DEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to force the transmitter to send data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xon(&mut self) -> FORCE_XON_W<FLOW_CONF_SPEC> {
         FORCE_XON_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to stop the transmitter from sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xoff(&mut self) -> FORCE_XOFF_W<FLOW_CONF_SPEC> {
         FORCE_XOFF_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to send an XON character. This bit is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xon(&mut self) -> SEND_XON_W<FLOW_CONF_SPEC> {
         SEND_XON_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to send an XOFF character. This bit is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xoff(&mut self) -> SEND_XOFF_W<FLOW_CONF_SPEC> {
         SEND_XOFF_W::new(self, 5)
     }
diff --git a/esp32s2/src/uart0/id.rs b/esp32s2/src/uart0/id.rs
index 0240cdcbbe..438ae7c335 100644
--- a/esp32s2/src/uart0/id.rs
+++ b/esp32s2/src/uart0/id.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register is used to configure the UART_ID."]
     #[inline(always)]
-    #[must_use]
     pub fn id(&mut self) -> ID_W<ID_SPEC> {
         ID_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/idle_conf.rs b/esp32s2/src/uart0/idle_conf.rs
index 471a948f23..ddc9b14582 100644
--- a/esp32s2/src/uart0/idle_conf.rs
+++ b/esp32s2/src/uart0/idle_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W<IDLE_CONF_SPEC> {
         RX_IDLE_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit)."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W<IDLE_CONF_SPEC> {
         TX_IDLE_NUM_W::new(self, 10)
     }
     #[doc = "Bits 20:27 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W<IDLE_CONF_SPEC> {
         TX_BRK_NUM_W::new(self, 20)
     }
diff --git a/esp32s2/src/uart0/int_clr.rs b/esp32s2/src/uart0/int_clr.rs
index 391d76e1fa..173118e968 100644
--- a/esp32s2/src/uart0/int_clr.rs
+++ b/esp32s2/src/uart0/int_clr.rs
@@ -49,121 +49,101 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear UART_PARITY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear UART_FRM_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear UART_DSR_CHG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear UART_CTS_CHG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear UART_BRK_DET_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear UART_RXFIFO_TOUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear UART_SW_XON_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear UART_SW_XOFF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear UART_GLITCH_DET_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear UART_TX_BRK_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear UART_TX_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear UART_RS485_FRM_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear UART_RS485_CLASH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear UART_WAKEUP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup(&mut self) -> WAKEUP_W<INT_CLR_SPEC> {
         WAKEUP_W::new(self, 19)
     }
diff --git a/esp32s2/src/uart0/int_ena.rs b/esp32s2/src/uart0/int_ena.rs
index 9a742834fe..a1c05b3e3d 100644
--- a/esp32s2/src/uart0/int_ena.rs
+++ b/esp32s2/src/uart0/int_ena.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit for UART_RXFIFO_FULL_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit for UART_TXFIFO_EMPTY_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the enable bit for UART_PARITY_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_ENA_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the enable bit for UART_FRM_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_ENA_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the enable bit for UART_RXFIFO_OVF_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the enable bit for UART_DSR_CHG_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_ENA_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the enable bit for UART_CTS_CHG_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_ENA_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the enable bit for UART_BRK_DET_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_ENA_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the enable bit for UART_RXFIFO_TOUT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_ENA_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the enable bit for UART_SW_XON_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_ENA_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the enable bit for UART_SW_XOFF_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_ENA_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for UART_GLITCH_DET_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for UART_TX_BRK_DONE_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_ENA_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for UART_TX_BRK_IDLE_DONE_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_ENA_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for UART_TX_DONE_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for UART_RS485_PARITY_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_ENA_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - This is the enable bit for UART_RS485_PARITY_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_ENA_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - This is the enable bit for UART_RS485_CLASH_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_ENA_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - This is the enable bit for UART_AT_CMD_CHAR_DET_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_ENA_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
     #[doc = "Bit 19 - This is the enable bit for UART_WAKEUP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup(&mut self) -> WAKEUP_W<INT_ENA_SPEC> {
         WAKEUP_W::new(self, 19)
     }
diff --git a/esp32s2/src/uart0/mem_conf.rs b/esp32s2/src/uart0/mem_conf.rs
index a6b59916a2..5dafbce213 100644
--- a/esp32s2/src/uart0/mem_conf.rs
+++ b/esp32s2/src/uart0/mem_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_size(&mut self) -> RX_SIZE_W<MEM_CONF_SPEC> {
         RX_SIZE_W::new(self, 1)
     }
     #[doc = "Bits 4:6 - This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_size(&mut self) -> TX_SIZE_W<MEM_CONF_SPEC> {
         TX_SIZE_W::new(self, 4)
     }
     #[doc = "Bits 7:15 - This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W<MEM_CONF_SPEC> {
         RX_FLOW_THRHD_W::new(self, 7)
     }
     #[doc = "Bits 16:25 - This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit). The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W<MEM_CONF_SPEC> {
         RX_TOUT_THRHD_W::new(self, 16)
     }
     #[doc = "Bit 26 - Set this bit to force power down UART RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<MEM_CONF_SPEC> {
         MEM_FORCE_PD_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to force power up UART RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<MEM_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 27)
     }
diff --git a/esp32s2/src/uart0/rs485_conf.rs b/esp32s2/src/uart0/rs485_conf.rs
index 5ccb49b1e9..e2f2b52a19 100644
--- a/esp32s2/src/uart0/rs485_conf.rs
+++ b/esp32s2/src/uart0/rs485_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to choose RS485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_en(&mut self) -> RS485_EN_W<RS485_CONF_SPEC> {
         RS485_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl0_en(&mut self) -> DL0_EN_W<RS485_CONF_SPEC> {
         DL0_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl1_en(&mut self) -> DL1_EN_W<RS485_CONF_SPEC> {
         DL1_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable the receiver could receive data when the transmitter is transmitting data in RS485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485tx_rx_en(&mut self) -> RS485TX_RX_EN_W<RS485_CONF_SPEC> {
         RS485TX_RX_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: enable RS485 transmitter to send data when RS485 receiver line is busy. 0: RS485 transmitter should not send data when its receiver is busy."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485rxby_tx_en(&mut self) -> RS485RXBY_TX_EN_W<RS485_CONF_SPEC> {
         RS485RXBY_TX_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - This register is used to delay the receiver's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_rx_dly_num(&mut self) -> RS485_RX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_RX_DLY_NUM_W::new(self, 5)
     }
     #[doc = "Bits 6:9 - This register is used to delay the transmitter's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_tx_dly_num(&mut self) -> RS485_TX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_TX_DLY_NUM_W::new(self, 6)
     }
diff --git a/esp32s2/src/uart0/sleep_conf.rs b/esp32s2/src/uart0/sleep_conf.rs
index d17b0ff3bf..3c1cf600f1 100644
--- a/esp32s2/src/uart0/sleep_conf.rs
+++ b/esp32s2/src/uart0/sleep_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value."]
     #[inline(always)]
-    #[must_use]
     pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W<SLEEP_CONF_SPEC> {
         ACTIVE_THRESHOLD_W::new(self, 0)
     }
diff --git a/esp32s2/src/uart0/swfc_conf0.rs b/esp32s2/src/uart0/swfc_conf0.rs
index fd00cb6133..6365cfbc55 100644
--- a/esp32s2/src/uart0/swfc_conf0.rs
+++ b/esp32s2/src/uart0/swfc_conf0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W<SWFC_CONF0_SPEC> {
         XOFF_THRESHOLD_W::new(self, 0)
     }
     #[doc = "Bits 9:16 - This register stores the XOFF flow control character."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_char(&mut self) -> XOFF_CHAR_W<SWFC_CONF0_SPEC> {
         XOFF_CHAR_W::new(self, 9)
     }
diff --git a/esp32s2/src/uart0/swfc_conf1.rs b/esp32s2/src/uart0/swfc_conf1.rs
index 481e6bce7b..d4fd545137 100644
--- a/esp32s2/src/uart0/swfc_conf1.rs
+++ b/esp32s2/src/uart0/swfc_conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W<SWFC_CONF1_SPEC> {
         XON_THRESHOLD_W::new(self, 0)
     }
     #[doc = "Bits 9:16 - This register stores the XON flow control character."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_char(&mut self) -> XON_CHAR_W<SWFC_CONF1_SPEC> {
         XON_CHAR_W::new(self, 9)
     }
diff --git a/esp32s2/src/uhci0/ahb_test.rs b/esp32s2/src/uhci0/ahb_test.rs
index 92c32d1dbd..b2806cb2a4 100644
--- a/esp32s2/src/uhci0/ahb_test.rs
+++ b/esp32s2/src/uhci0/ahb_test.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
         AHB_TESTMODE_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
         AHB_TESTADDR_W::new(self, 4)
     }
diff --git a/esp32s2/src/uhci0/conf0.rs b/esp32s2/src/uhci0/conf0.rs
index 0f4004512f..eda7f54522 100644
--- a/esp32s2/src/uhci0/conf0.rs
+++ b/esp32s2/src/uhci0/conf0.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in DMA FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<CONF0_SPEC> {
         IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset out DMA FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<CONF0_SPEC> {
         OUT_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset AHB interface cmdFIFO of DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<CONF0_SPEC> {
         AHBM_FIFO_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to reset AHB interface of DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst(&mut self) -> AHBM_RST_W<CONF0_SPEC> {
         AHBM_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<CONF0_SPEC> {
         IN_LOOP_TEST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<CONF0_SPEC> {
         OUT_LOOP_TEST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<CONF0_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 6)
     }
     #[doc = "Bit 7 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<CONF0_SPEC> {
         OUT_NO_RESTART_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<CONF0_SPEC> {
         OUT_EOF_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to link up UHCI and UART0."]
     #[inline(always)]
-    #[must_use]
     pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
         UART0_CE_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to link up UHCI and UART1."]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
         UART1_CE_W::new(self, 10)
     }
     #[doc = "Bit 12 - This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<CONF0_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<CONF0_SPEC> {
         INDSCR_BURST_EN_W::new(self, 13)
     }
     #[doc = "Bit 15 - 1: UHCI transmitted data would be write back into DMA INFIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<CONF0_SPEC> {
         MEM_TRANS_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to separate the data frame using a special character."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
         SEPER_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to encode the data packet with a formatting header."]
     #[inline(always)]
-    #[must_use]
     pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
         HEAD_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to enable UHCI to receive the 16 bit CRC."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
         CRC_REC_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
         UART_IDLE_EOF_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0."]
     #[inline(always)]
-    #[must_use]
     pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
         LEN_EOF_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload."]
     #[inline(always)]
-    #[must_use]
     pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
         ENCODE_CRC_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: Force clock on for registers. 0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
         UART_RX_BRK_EOF_EN_W::new(self, 23)
     }
diff --git a/esp32s2/src/uhci0/conf1.rs b/esp32s2/src/uhci0/conf1.rs
index d7eb2befd2..ad3c23bec2 100644
--- a/esp32s2/src/uhci0/conf1.rs
+++ b/esp32s2/src/uhci0/conf1.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
         CHECK_SUM_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
         CHECK_SEQ_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
         CRC_DISABLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to save the packet header when UHCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
         SAVE_HEAD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
         TX_CHECK_SUM_RE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
         TX_ACK_NUM_RE_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn check_owner(&mut self) -> CHECK_OWNER_W<CONF1_SPEC> {
         CHECK_OWNER_W::new(self, 6)
     }
     #[doc = "Bit 7 - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
         WAIT_SW_START_W::new(self, 7)
     }
     #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
         SW_START_W::new(self, 8)
     }
     #[doc = "Bits 9:20 - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<CONF1_SPEC> {
         DMA_INFIFO_FULL_THRS_W::new(self, 9)
     }
diff --git a/esp32s2/src/uhci0/date.rs b/esp32s2/src/uhci0/date.rs
index 9abdb3435d..eb72f24aeb 100644
--- a/esp32s2/src/uhci0/date.rs
+++ b/esp32s2/src/uhci0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/uhci0/dma_in_link.rs b/esp32s2/src/uhci0/dma_in_link.rs
index 9b17733609..7aa44f722b 100644
--- a/esp32s2/src/uhci0/dma_in_link.rs
+++ b/esp32s2/src/uhci0/dma_in_link.rs
@@ -72,31 +72,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first receive descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<DMA_IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - This is the enable bit to return to current receive descriptor's address, when there are some errors in current packet."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<DMA_IN_LINK_SPEC> {
         INLINK_AUTO_RET_W::new(self, 20)
     }
     #[doc = "Bit 28 - Set this bit to stop dealing with the receive descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<DMA_IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start dealing with the receive descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<DMA_IN_LINK_SPEC> {
         INLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to restart new receive descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<DMA_IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32s2/src/uhci0/dma_in_pop.rs b/esp32s2/src/uhci0/dma_in_pop.rs
index 44fc841e74..9a875aae72 100644
--- a/esp32s2/src/uhci0/dma_in_pop.rs
+++ b/esp32s2/src/uhci0/dma_in_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 16 - Set this bit to pop data from RX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_pop(&mut self) -> INFIFO_POP_W<DMA_IN_POP_SPEC> {
         INFIFO_POP_W::new(self, 16)
     }
diff --git a/esp32s2/src/uhci0/dma_out_link.rs b/esp32s2/src/uhci0/dma_out_link.rs
index 0f60ba0faa..10af9d240a 100644
--- a/esp32s2/src/uhci0/dma_out_link.rs
+++ b/esp32s2/src/uhci0/dma_out_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first transmit descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 28 - Set this bit to stop dealing with the transmit descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to start a new transmit descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to restart the transmit descriptor from the last address."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<DMA_OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 30)
     }
diff --git a/esp32s2/src/uhci0/dma_out_push.rs b/esp32s2/src/uhci0/dma_out_push.rs
index 8ab42cf2a3..0dcfbb700a 100644
--- a/esp32s2/src/uhci0/dma_out_push.rs
+++ b/esp32s2/src/uhci0/dma_out_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This is the data that need to be pushed into TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<DMA_OUT_PUSH_SPEC> {
         OUTFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 16 - Set this bit to push data into TX FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<DMA_OUT_PUSH_SPEC> {
         OUTFIFO_PUSH_W::new(self, 16)
     }
diff --git a/esp32s2/src/uhci0/esc_conf.rs b/esp32s2/src/uhci0/esc_conf.rs
index 3d6546aa3d..f535c6ebd1 100644
--- a/esp32s2/src/uhci0/esc_conf.rs
+++ b/esp32s2/src/uhci0/esc_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to define separators to encode data packets. The default value is 0xC0."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_char(&mut self) -> SEPER_CHAR_W<ESC_CONF_SPEC> {
         SEPER_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to define the first character of SLIP escape sequence. The default value is 0xDB."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR0_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - This register is used to define the second character of SLIP escape sequence. The default value is 0xDC."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR1_W::new(self, 16)
     }
diff --git a/esp32s2/src/uhci0/escape_conf.rs b/esp32s2/src/uhci0/escape_conf.rs
index 9bb5e297ed..21967cde3b 100644
--- a/esp32s2/src/uhci0/escape_conf.rs
+++ b/esp32s2/src/uhci0/escape_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to decode character 0xC0 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_C0_ESC_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to decode character 0xDB when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_DB_ESC_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to decode flow control character 0x11 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_11_ESC_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to decode flow control character 0x13 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_13_ESC_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to replace 0xC0 by special characters when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_C0_ESC_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to replace 0xDB by special characters when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_DB_ESC_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to replace flow control character 0x11 by special characters when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_11_ESC_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to replace flow control character 0x13 by special characters when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_13_ESC_EN_W::new(self, 7)
     }
diff --git a/esp32s2/src/uhci0/hung_conf.rs b/esp32s2/src/uhci0/hung_conf.rs
index 82e0c7aef4..98bbfcf646 100644
--- a/esp32s2/src/uhci0/hung_conf.rs
+++ b/esp32s2/src/uhci0/hung_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - This register is used to configure the maximum tick count."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - This is the enable bit for TX FIFO receive timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_ENA_W::new(self, 11)
     }
     #[doc = "Bits 12:19 - This register stores the timeout value. UHCI produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_W::new(self, 12)
     }
     #[doc = "Bits 20:22 - This register is used to configure the maximum tick count."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_SHIFT_W::new(self, 20)
     }
     #[doc = "Bit 23 - This is the enable bit for DMA send timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_ENA_W::new(self, 23)
     }
diff --git a/esp32s2/src/uhci0/int_clr.rs b/esp32s2/src/uhci0/int_clr.rs
index a2307f8998..3fd3dad5c8 100644
--- a/esp32s2/src/uhci0/int_clr.rs
+++ b/esp32s2/src/uhci0/int_clr.rs
@@ -43,103 +43,86 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear UHCI_RX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear UHCI_TX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear UHCI_IN_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
         IN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear UHCI_OUT_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
         OUT_DONE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear UHCI_OUT_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
         OUT_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
         IN_DSCR_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
         OUT_DSCR_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_CLR_SPEC> {
         SEND_S_REG_Q_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_CLR_SPEC> {
         SEND_A_REG_Q_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_CLR_SPEC> {
         DMA_INFIFO_FULL_WM_W::new(self, 16)
     }
diff --git a/esp32s2/src/uhci0/int_ena.rs b/esp32s2/src/uhci0/int_ena.rs
index e9bbfa6c88..86d59e7826 100644
--- a/esp32s2/src/uhci0/int_ena.rs
+++ b/esp32s2/src/uhci0/int_ena.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_ENA_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_ENA_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<INT_ENA_SPEC> {
         IN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<INT_ENA_SPEC> {
         OUT_DONE_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_ENA_SPEC> {
         OUT_EOF_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_ENA_SPEC> {
         IN_DSCR_ERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_ENA_SPEC> {
         OUT_DSCR_ERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_ENA_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_ENA_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_ENA_SPEC> {
         SEND_S_REG_Q_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_ENA_SPEC> {
         SEND_A_REG_Q_W::new(self, 15)
     }
     #[doc = "Bit 16 - This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_ENA_SPEC> {
         DMA_INFIFO_FULL_WM_W::new(self, 16)
     }
diff --git a/esp32s2/src/uhci0/pkt_thres.rs b/esp32s2/src/uhci0/pkt_thres.rs
index d31412ac4e..557230acbf 100644
--- a/esp32s2/src/uhci0/pkt_thres.rs
+++ b/esp32s2/src/uhci0/pkt_thres.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pkt_thrs(&mut self) -> PKT_THRS_W<PKT_THRES_SPEC> {
         PKT_THRS_W::new(self, 0)
     }
diff --git a/esp32s2/src/uhci0/q/word0.rs b/esp32s2/src/uhci0/q/word0.rs
index 84df3f16b3..259eea811b 100644
--- a/esp32s2/src/uhci0/q/word0.rs
+++ b/esp32s2/src/uhci0/q/word0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD0_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32s2/src/uhci0/q/word1.rs b/esp32s2/src/uhci0/q/word1.rs
index 410644dba5..3c2866edea 100644
--- a/esp32s2/src/uhci0/q/word1.rs
+++ b/esp32s2/src/uhci0/q/word1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD1_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32s2/src/uhci0/quick_sent.rs b/esp32s2/src/uhci0/quick_sent.rs
index ebe29444a9..e2a382c982 100644
--- a/esp32s2/src/uhci0/quick_sent.rs
+++ b/esp32s2/src/uhci0/quick_sent.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - This register is used to specify the single_send mode."]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_NUM_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to enable single_send mode to send short packets."]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - This register is used to specify the always_send mode."]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_NUM_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to enable always_send mode to send short packets."]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_EN_W::new(self, 7)
     }
diff --git a/esp32s2/src/usb0.rs b/esp32s2/src/usb0.rs
index 59eed2f399..7819d5d3ea 100644
--- a/esp32s2/src/usb0.rs
+++ b/esp32s2/src/usb0.rs
@@ -160,6 +160,8 @@ impl RegisterBlock {
         &self.hptxfsiz
     }
     #[doc = "0x104..0x114 - "]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `DIEPTXF1` register.</div>"]
     #[inline(always)]
     pub const fn dieptxf(&self, n: usize) -> &DIEPTXF {
         &self.dieptxf[n]
@@ -302,6 +304,8 @@ impl RegisterBlock {
         &self.in_ep0
     }
     #[doc = "0x920..0x9e0 - Device IN endpoints 1-6"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `IN_EP1` cluster.</div>"]
     #[inline(always)]
     pub const fn in_ep(&self, n: usize) -> &IN_EP {
         &self.in_ep[n]
@@ -348,6 +352,8 @@ impl RegisterBlock {
         &self.out_ep0
     }
     #[doc = "0xb20..0xbe0 - Device OUT endpoints 1-6"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `OUT_EP1` cluster.</div>"]
     #[inline(always)]
     pub const fn out_ep(&self, n: usize) -> &OUT_EP {
         &self.out_ep[n]
@@ -399,7 +405,7 @@ impl RegisterBlock {
         #[allow(clippy::no_effect)]
         [(); 16][n];
         unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(4096)
                 .add(4096 * n)
@@ -411,7 +417,7 @@ impl RegisterBlock {
     #[inline(always)]
     pub fn fifo_iter(&self) -> impl Iterator<Item = &FIFO> {
         (0..16).map(move |n| unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(4096)
                 .add(4096 * n)
diff --git a/esp32s2/src/usb0/daintmsk.rs b/esp32s2/src/usb0/daintmsk.rs
index 231fa18130..e0075ce733 100644
--- a/esp32s2/src/usb0/daintmsk.rs
+++ b/esp32s2/src/usb0/daintmsk.rs
@@ -138,7 +138,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `INEPMSK0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk(&mut self, n: u8) -> INEPMSK_W<DAINTMSK_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 7][n as usize];
@@ -146,43 +145,36 @@ impl W {
     }
     #[doc = "Bit 0 - INEPMSK0"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk0(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 0)
     }
     #[doc = "Bit 1 - INEPMSK1"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk1(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 1)
     }
     #[doc = "Bit 2 - INEPMSK2"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk2(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 2)
     }
     #[doc = "Bit 3 - INEPMSK3"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk3(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 3)
     }
     #[doc = "Bit 4 - INEPMSK4"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk4(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 4)
     }
     #[doc = "Bit 5 - INEPMSK5"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk5(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 5)
     }
     #[doc = "Bit 6 - INEPMSK6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk6(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 6)
     }
@@ -190,7 +182,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OUTEPMSK0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk(&mut self, n: u8) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 7][n as usize];
@@ -198,43 +189,36 @@ impl W {
     }
     #[doc = "Bit 16 - OUTEPMSK0"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk0(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 16)
     }
     #[doc = "Bit 17 - OUTEPMSK1"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk1(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 17)
     }
     #[doc = "Bit 18 - OUTEPMSK2"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk2(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 18)
     }
     #[doc = "Bit 19 - OUTEPMSK3"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk3(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 19)
     }
     #[doc = "Bit 20 - OUTEPMSK4"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk4(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 20)
     }
     #[doc = "Bit 21 - OUTEPMSK5"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk5(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 21)
     }
     #[doc = "Bit 22 - OUTEPMSK6"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk6(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 22)
     }
diff --git a/esp32s2/src/usb0/dcfg.rs b/esp32s2/src/usb0/dcfg.rs
index a6d0af1184..6488a1b902 100644
--- a/esp32s2/src/usb0/dcfg.rs
+++ b/esp32s2/src/usb0/dcfg.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn nzstsouthshk(&mut self) -> NZSTSOUTHSHK_W<DCFG_SPEC> {
         NZSTSOUTHSHK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ena32khzsusp(&mut self) -> ENA32KHZSUSP_W<DCFG_SPEC> {
         ENA32KHZSUSP_W::new(self, 3)
     }
     #[doc = "Bits 4:10"]
     #[inline(always)]
-    #[must_use]
     pub fn devaddr(&mut self) -> DEVADDR_W<DCFG_SPEC> {
         DEVADDR_W::new(self, 4)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn perfrlint(&mut self) -> PERFRLINT_W<DCFG_SPEC> {
         PERFRLINT_W::new(self, 11)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn endevoutnak(&mut self) -> ENDEVOUTNAK_W<DCFG_SPEC> {
         ENDEVOUTNAK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn xcvrdly(&mut self) -> XCVRDLY_W<DCFG_SPEC> {
         XCVRDLY_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn erraticintmsk(&mut self) -> ERRATICINTMSK_W<DCFG_SPEC> {
         ERRATICINTMSK_W::new(self, 15)
     }
     #[doc = "Bits 18:22"]
     #[inline(always)]
-    #[must_use]
     pub fn epmiscnt(&mut self) -> EPMISCNT_W<DCFG_SPEC> {
         EPMISCNT_W::new(self, 18)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn descdma(&mut self) -> DESCDMA_W<DCFG_SPEC> {
         DESCDMA_W::new(self, 23)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn perschintvl(&mut self) -> PERSCHINTVL_W<DCFG_SPEC> {
         PERSCHINTVL_W::new(self, 24)
     }
     #[doc = "Bits 26:31"]
     #[inline(always)]
-    #[must_use]
     pub fn resvalid(&mut self) -> RESVALID_W<DCFG_SPEC> {
         RESVALID_W::new(self, 26)
     }
diff --git a/esp32s2/src/usb0/dctl.rs b/esp32s2/src/usb0/dctl.rs
index e806259488..ca8528bace 100644
--- a/esp32s2/src/usb0/dctl.rs
+++ b/esp32s2/src/usb0/dctl.rs
@@ -128,79 +128,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rmtwkupsig(&mut self) -> RMTWKUPSIG_W<DCTL_SPEC> {
         RMTWKUPSIG_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sftdiscon(&mut self) -> SFTDISCON_W<DCTL_SPEC> {
         SFTDISCON_W::new(self, 1)
     }
     #[doc = "Bits 4:6"]
     #[inline(always)]
-    #[must_use]
     pub fn tstctl(&mut self) -> TSTCTL_W<DCTL_SPEC> {
         TSTCTL_W::new(self, 4)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sgnpinnak(&mut self) -> SGNPINNAK_W<DCTL_SPEC> {
         SGNPINNAK_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn cgnpinnak(&mut self) -> CGNPINNAK_W<DCTL_SPEC> {
         CGNPINNAK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sgoutnak(&mut self) -> SGOUTNAK_W<DCTL_SPEC> {
         SGOUTNAK_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn cgoutnak(&mut self) -> CGOUTNAK_W<DCTL_SPEC> {
         CGOUTNAK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pwronprgdone(&mut self) -> PWRONPRGDONE_W<DCTL_SPEC> {
         PWRONPRGDONE_W::new(self, 11)
     }
     #[doc = "Bits 13:14"]
     #[inline(always)]
-    #[must_use]
     pub fn gmc(&mut self) -> GMC_W<DCTL_SPEC> {
         GMC_W::new(self, 13)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ignrfrmnum(&mut self) -> IGNRFRMNUM_W<DCTL_SPEC> {
         IGNRFRMNUM_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn nakonbble(&mut self) -> NAKONBBLE_W<DCTL_SPEC> {
         NAKONBBLE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn encountonbna(&mut self) -> ENCOUNTONBNA_W<DCTL_SPEC> {
         ENCOUNTONBNA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn deepsleepbeslreject(&mut self) -> DEEPSLEEPBESLREJECT_W<DCTL_SPEC> {
         DEEPSLEEPBESLREJECT_W::new(self, 18)
     }
diff --git a/esp32s2/src/usb0/diepempmsk.rs b/esp32s2/src/usb0/diepempmsk.rs
index 0f43f3df8c..b9f279ed78 100644
--- a/esp32s2/src/usb0/diepempmsk.rs
+++ b/esp32s2/src/usb0/diepempmsk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn d_ineptxfempmsk(&mut self) -> D_INEPTXFEMPMSK_W<DIEPEMPMSK_SPEC> {
         D_INEPTXFEMPMSK_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/diepmsk.rs b/esp32s2/src/usb0/diepmsk.rs
index 106eb330b5..02c6955f54 100644
--- a/esp32s2/src/usb0/diepmsk.rs
+++ b/esp32s2/src/usb0/diepmsk.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn di_xfercomplmsk(&mut self) -> DI_XFERCOMPLMSK_W<DIEPMSK_SPEC> {
         DI_XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn di_epdisbldmsk(&mut self) -> DI_EPDISBLDMSK_W<DIEPMSK_SPEC> {
         DI_EPDISBLDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn di_ahbermsk(&mut self) -> DI_AHBERMSK_W<DIEPMSK_SPEC> {
         DI_AHBERMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timeoutmsk(&mut self) -> TIMEOUTMSK_W<DIEPMSK_SPEC> {
         TIMEOUTMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn intkntxfempmsk(&mut self) -> INTKNTXFEMPMSK_W<DIEPMSK_SPEC> {
         INTKNTXFEMPMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn intknepmismsk(&mut self) -> INTKNEPMISMSK_W<DIEPMSK_SPEC> {
         INTKNEPMISMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepnakeffmsk(&mut self) -> INEPNAKEFFMSK_W<DIEPMSK_SPEC> {
         INEPNAKEFFMSK_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifoundrnmsk(&mut self) -> TXFIFOUNDRNMSK_W<DIEPMSK_SPEC> {
         TXFIFOUNDRNMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnainintrmsk(&mut self) -> BNAININTRMSK_W<DIEPMSK_SPEC> {
         BNAININTRMSK_W::new(self, 9)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn di_nakmsk(&mut self) -> DI_NAKMSK_W<DIEPMSK_SPEC> {
         DI_NAKMSK_W::new(self, 13)
     }
diff --git a/esp32s2/src/usb0/dieptxf.rs b/esp32s2/src/usb0/dieptxf.rs
index d59c42b2bb..63392a85e3 100644
--- a/esp32s2/src/usb0/dieptxf.rs
+++ b/esp32s2/src/usb0/dieptxf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn inep1txfstaddr(&mut self) -> INEP1TXFSTADDR_W<DIEPTXF_SPEC> {
         INEP1TXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn inep1txfdep(&mut self) -> INEP1TXFDEP_W<DIEPTXF_SPEC> {
         INEP1TXFDEP_W::new(self, 16)
     }
diff --git a/esp32s2/src/usb0/doepmsk.rs b/esp32s2/src/usb0/doepmsk.rs
index 89b209f847..5496a246b0 100644
--- a/esp32s2/src/usb0/doepmsk.rs
+++ b/esp32s2/src/usb0/doepmsk.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<DOEPMSK_SPEC> {
         XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbldmsk(&mut self) -> EPDISBLDMSK_W<DOEPMSK_SPEC> {
         EPDISBLDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbermsk(&mut self) -> AHBERMSK_W<DOEPMSK_SPEC> {
         AHBERMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn setupmsk(&mut self) -> SETUPMSK_W<DOEPMSK_SPEC> {
         SETUPMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn outtknepdismsk(&mut self) -> OUTTKNEPDISMSK_W<DOEPMSK_SPEC> {
         OUTTKNEPDISMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn stsphsercvdmsk(&mut self) -> STSPHSERCVDMSK_W<DOEPMSK_SPEC> {
         STSPHSERCVDMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<DOEPMSK_SPEC> {
         BACK2BACKSETUP_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn outpkterrmsk(&mut self) -> OUTPKTERRMSK_W<DOEPMSK_SPEC> {
         OUTPKTERRMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaoutintrmsk(&mut self) -> BNAOUTINTRMSK_W<DOEPMSK_SPEC> {
         BNAOUTINTRMSK_W::new(self, 9)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerrmsk(&mut self) -> BBLEERRMSK_W<DOEPMSK_SPEC> {
         BBLEERRMSK_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakmsk(&mut self) -> NAKMSK_W<DOEPMSK_SPEC> {
         NAKMSK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetmsk(&mut self) -> NYETMSK_W<DOEPMSK_SPEC> {
         NYETMSK_W::new(self, 14)
     }
diff --git a/esp32s2/src/usb0/dthrctl.rs b/esp32s2/src/usb0/dthrctl.rs
index 9ab009ceb9..e1c5862ed7 100644
--- a/esp32s2/src/usb0/dthrctl.rs
+++ b/esp32s2/src/usb0/dthrctl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn nonisothren(&mut self) -> NONISOTHREN_W<DTHRCTL_SPEC> {
         NONISOTHREN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn isothren(&mut self) -> ISOTHREN_W<DTHRCTL_SPEC> {
         ISOTHREN_W::new(self, 1)
     }
     #[doc = "Bits 2:10"]
     #[inline(always)]
-    #[must_use]
     pub fn txthrlen(&mut self) -> TXTHRLEN_W<DTHRCTL_SPEC> {
         TXTHRLEN_W::new(self, 2)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbthrratio(&mut self) -> AHBTHRRATIO_W<DTHRCTL_SPEC> {
         AHBTHRRATIO_W::new(self, 11)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn rxthren(&mut self) -> RXTHREN_W<DTHRCTL_SPEC> {
         RXTHREN_W::new(self, 16)
     }
     #[doc = "Bits 17:25"]
     #[inline(always)]
-    #[must_use]
     pub fn rxthrlen(&mut self) -> RXTHRLEN_W<DTHRCTL_SPEC> {
         RXTHRLEN_W::new(self, 17)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn arbprken(&mut self) -> ARBPRKEN_W<DTHRCTL_SPEC> {
         ARBPRKEN_W::new(self, 27)
     }
diff --git a/esp32s2/src/usb0/dvbusdis.rs b/esp32s2/src/usb0/dvbusdis.rs
index 0aded180be..75c7ff65cf 100644
--- a/esp32s2/src/usb0/dvbusdis.rs
+++ b/esp32s2/src/usb0/dvbusdis.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn dvbusdis(&mut self) -> DVBUSDIS_W<DVBUSDIS_SPEC> {
         DVBUSDIS_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/dvbuspulse.rs b/esp32s2/src/usb0/dvbuspulse.rs
index e0ad68f11a..34da3344b2 100644
--- a/esp32s2/src/usb0/dvbuspulse.rs
+++ b/esp32s2/src/usb0/dvbuspulse.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn dvbuspulse(&mut self) -> DVBUSPULSE_W<DVBUSPULSE_SPEC> {
         DVBUSPULSE_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/fifo.rs b/esp32s2/src/usb0/fifo.rs
index f5e55135b2..3eb476d958 100644
--- a/esp32s2/src/usb0/fifo.rs
+++ b/esp32s2/src/usb0/fifo.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn word(&mut self) -> WORD_W<FIFO_SPEC> {
         WORD_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/gahbcfg.rs b/esp32s2/src/usb0/gahbcfg.rs
index 23ed6383db..17a6a7368d 100644
--- a/esp32s2/src/usb0/gahbcfg.rs
+++ b/esp32s2/src/usb0/gahbcfg.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn glbllntrmsk(&mut self) -> GLBLLNTRMSK_W<GAHBCFG_SPEC> {
         GLBLLNTRMSK_W::new(self, 0)
     }
     #[doc = "Bits 1:4"]
     #[inline(always)]
-    #[must_use]
     pub fn hbstlen(&mut self) -> HBSTLEN_W<GAHBCFG_SPEC> {
         HBSTLEN_W::new(self, 1)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaen(&mut self) -> DMAEN_W<GAHBCFG_SPEC> {
         DMAEN_W::new(self, 5)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfemplvl(&mut self) -> NPTXFEMPLVL_W<GAHBCFG_SPEC> {
         NPTXFEMPLVL_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfemplvl(&mut self) -> PTXFEMPLVL_W<GAHBCFG_SPEC> {
         PTXFEMPLVL_W::new(self, 8)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn remmemsupp(&mut self) -> REMMEMSUPP_W<GAHBCFG_SPEC> {
         REMMEMSUPP_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn notialldmawrit(&mut self) -> NOTIALLDMAWRIT_W<GAHBCFG_SPEC> {
         NOTIALLDMAWRIT_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbsingle(&mut self) -> AHBSINGLE_W<GAHBCFG_SPEC> {
         AHBSINGLE_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn invdescendianess(&mut self) -> INVDESCENDIANESS_W<GAHBCFG_SPEC> {
         INVDESCENDIANESS_W::new(self, 24)
     }
diff --git a/esp32s2/src/usb0/gdfifocfg.rs b/esp32s2/src/usb0/gdfifocfg.rs
index 6996405a7a..981246c611 100644
--- a/esp32s2/src/usb0/gdfifocfg.rs
+++ b/esp32s2/src/usb0/gdfifocfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gdfifocfg(&mut self) -> GDFIFOCFG_W<GDFIFOCFG_SPEC> {
         GDFIFOCFG_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn epinfobaseaddr(&mut self) -> EPINFOBASEADDR_W<GDFIFOCFG_SPEC> {
         EPINFOBASEADDR_W::new(self, 16)
     }
diff --git a/esp32s2/src/usb0/gintmsk.rs b/esp32s2/src/usb0/gintmsk.rs
index 6b4555f22e..51c75a34e0 100644
--- a/esp32s2/src/usb0/gintmsk.rs
+++ b/esp32s2/src/usb0/gintmsk.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn modemismsk(&mut self) -> MODEMISMSK_W<GINTMSK_SPEC> {
         MODEMISMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn otgintmsk(&mut self) -> OTGINTMSK_W<GINTMSK_SPEC> {
         OTGINTMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sofmsk(&mut self) -> SOFMSK_W<GINTMSK_SPEC> {
         SOFMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn rxflvimsk(&mut self) -> RXFLVIMSK_W<GINTMSK_SPEC> {
         RXFLVIMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfempmsk(&mut self) -> NPTXFEMPMSK_W<GINTMSK_SPEC> {
         NPTXFEMPMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ginnakeffmsk(&mut self) -> GINNAKEFFMSK_W<GINTMSK_SPEC> {
         GINNAKEFFMSK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn goutnackeffmsk(&mut self) -> GOUTNACKEFFMSK_W<GINTMSK_SPEC> {
         GOUTNACKEFFMSK_W::new(self, 7)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn erlysuspmsk(&mut self) -> ERLYSUSPMSK_W<GINTMSK_SPEC> {
         ERLYSUSPMSK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn usbsuspmsk(&mut self) -> USBSUSPMSK_W<GINTMSK_SPEC> {
         USBSUSPMSK_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn usbrstmsk(&mut self) -> USBRSTMSK_W<GINTMSK_SPEC> {
         USBRSTMSK_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn enumdonemsk(&mut self) -> ENUMDONEMSK_W<GINTMSK_SPEC> {
         ENUMDONEMSK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn isooutdropmsk(&mut self) -> ISOOUTDROPMSK_W<GINTMSK_SPEC> {
         ISOOUTDROPMSK_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn eopfmsk(&mut self) -> EOPFMSK_W<GINTMSK_SPEC> {
         EOPFMSK_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn epmismsk(&mut self) -> EPMISMSK_W<GINTMSK_SPEC> {
         EPMISMSK_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn iepintmsk(&mut self) -> IEPINTMSK_W<GINTMSK_SPEC> {
         IEPINTMSK_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn oepintmsk(&mut self) -> OEPINTMSK_W<GINTMSK_SPEC> {
         OEPINTMSK_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn incompisoinmsk(&mut self) -> INCOMPISOINMSK_W<GINTMSK_SPEC> {
         INCOMPISOINMSK_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn incompipmsk(&mut self) -> INCOMPIPMSK_W<GINTMSK_SPEC> {
         INCOMPIPMSK_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fetsuspmsk(&mut self) -> FETSUSPMSK_W<GINTMSK_SPEC> {
         FETSUSPMSK_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn resetdetmsk(&mut self) -> RESETDETMSK_W<GINTMSK_SPEC> {
         RESETDETMSK_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn prtlntmsk(&mut self) -> PRTLNTMSK_W<GINTMSK_SPEC> {
         PRTLNTMSK_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn hchintmsk(&mut self) -> HCHINTMSK_W<GINTMSK_SPEC> {
         HCHINTMSK_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfempmsk(&mut self) -> PTXFEMPMSK_W<GINTMSK_SPEC> {
         PTXFEMPMSK_W::new(self, 26)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn conidstschngmsk(&mut self) -> CONIDSTSCHNGMSK_W<GINTMSK_SPEC> {
         CONIDSTSCHNGMSK_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn disconnintmsk(&mut self) -> DISCONNINTMSK_W<GINTMSK_SPEC> {
         DISCONNINTMSK_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn sessreqintmsk(&mut self) -> SESSREQINTMSK_W<GINTMSK_SPEC> {
         SESSREQINTMSK_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn wkupintmsk(&mut self) -> WKUPINTMSK_W<GINTMSK_SPEC> {
         WKUPINTMSK_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/gintsts.rs b/esp32s2/src/usb0/gintsts.rs
index 62dddd5efc..e84b095398 100644
--- a/esp32s2/src/usb0/gintsts.rs
+++ b/esp32s2/src/usb0/gintsts.rs
@@ -272,103 +272,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn modemis(&mut self) -> MODEMIS_W<GINTSTS_SPEC> {
         MODEMIS_W::new(self, 1)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sof(&mut self) -> SOF_W<GINTSTS_SPEC> {
         SOF_W::new(self, 3)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn erlysusp(&mut self) -> ERLYSUSP_W<GINTSTS_SPEC> {
         ERLYSUSP_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn usbsusp(&mut self) -> USBSUSP_W<GINTSTS_SPEC> {
         USBSUSP_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn usbrst(&mut self) -> USBRST_W<GINTSTS_SPEC> {
         USBRST_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn enumdone(&mut self) -> ENUMDONE_W<GINTSTS_SPEC> {
         ENUMDONE_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn isooutdrop(&mut self) -> ISOOUTDROP_W<GINTSTS_SPEC> {
         ISOOUTDROP_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn eopf(&mut self) -> EOPF_W<GINTSTS_SPEC> {
         EOPF_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn epmis(&mut self) -> EPMIS_W<GINTSTS_SPEC> {
         EPMIS_W::new(self, 17)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn incompisoin(&mut self) -> INCOMPISOIN_W<GINTSTS_SPEC> {
         INCOMPISOIN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn incompip(&mut self) -> INCOMPIP_W<GINTSTS_SPEC> {
         INCOMPIP_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fetsusp(&mut self) -> FETSUSP_W<GINTSTS_SPEC> {
         FETSUSP_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn resetdet(&mut self) -> RESETDET_W<GINTSTS_SPEC> {
         RESETDET_W::new(self, 23)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn conidstschng(&mut self) -> CONIDSTSCHNG_W<GINTSTS_SPEC> {
         CONIDSTSCHNG_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn disconnint(&mut self) -> DISCONNINT_W<GINTSTS_SPEC> {
         DISCONNINT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn sessreqint(&mut self) -> SESSREQINT_W<GINTSTS_SPEC> {
         SESSREQINT_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn wkupint(&mut self) -> WKUPINT_W<GINTSTS_SPEC> {
         WKUPINT_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/gnptxfsiz.rs b/esp32s2/src/usb0/gnptxfsiz.rs
index 64f666b6fe..b6ad1bc036 100644
--- a/esp32s2/src/usb0/gnptxfsiz.rs
+++ b/esp32s2/src/usb0/gnptxfsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfstaddr(&mut self) -> NPTXFSTADDR_W<GNPTXFSIZ_SPEC> {
         NPTXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfdep(&mut self) -> NPTXFDEP_W<GNPTXFSIZ_SPEC> {
         NPTXFDEP_W::new(self, 16)
     }
diff --git a/esp32s2/src/usb0/gotgctl.rs b/esp32s2/src/usb0/gotgctl.rs
index c0500f1604..6b575cd5fb 100644
--- a/esp32s2/src/usb0/gotgctl.rs
+++ b/esp32s2/src/usb0/gotgctl.rs
@@ -200,79 +200,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sesreq(&mut self) -> SESREQ_W<GOTGCTL_SPEC> {
         SESREQ_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn vbvalidoven(&mut self) -> VBVALIDOVEN_W<GOTGCTL_SPEC> {
         VBVALIDOVEN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn vbvalidovval(&mut self) -> VBVALIDOVVAL_W<GOTGCTL_SPEC> {
         VBVALIDOVVAL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn avalidoven(&mut self) -> AVALIDOVEN_W<GOTGCTL_SPEC> {
         AVALIDOVEN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn avalidovval(&mut self) -> AVALIDOVVAL_W<GOTGCTL_SPEC> {
         AVALIDOVVAL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn bvalidoven(&mut self) -> BVALIDOVEN_W<GOTGCTL_SPEC> {
         BVALIDOVEN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn bvalidovval(&mut self) -> BVALIDOVVAL_W<GOTGCTL_SPEC> {
         BVALIDOVVAL_W::new(self, 7)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hnpreq(&mut self) -> HNPREQ_W<GOTGCTL_SPEC> {
         HNPREQ_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn hstsethnpen(&mut self) -> HSTSETHNPEN_W<GOTGCTL_SPEC> {
         HSTSETHNPEN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn devhnpen(&mut self) -> DEVHNPEN_W<GOTGCTL_SPEC> {
         DEVHNPEN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ehen(&mut self) -> EHEN_W<GOTGCTL_SPEC> {
         EHEN_W::new(self, 12)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn dbncefltrbypass(&mut self) -> DBNCEFLTRBYPASS_W<GOTGCTL_SPEC> {
         DBNCEFLTRBYPASS_W::new(self, 15)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn otgver(&mut self) -> OTGVER_W<GOTGCTL_SPEC> {
         OTGVER_W::new(self, 20)
     }
diff --git a/esp32s2/src/usb0/gotgint.rs b/esp32s2/src/usb0/gotgint.rs
index 65bc5f1f82..b588af01dd 100644
--- a/esp32s2/src/usb0/gotgint.rs
+++ b/esp32s2/src/usb0/gotgint.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sesenddet(&mut self) -> SESENDDET_W<GOTGINT_SPEC> {
         SESENDDET_W::new(self, 2)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sesreqsucstschng(&mut self) -> SESREQSUCSTSCHNG_W<GOTGINT_SPEC> {
         SESREQSUCSTSCHNG_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hstnegsucstschng(&mut self) -> HSTNEGSUCSTSCHNG_W<GOTGINT_SPEC> {
         HSTNEGSUCSTSCHNG_W::new(self, 9)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn hstnegdet(&mut self) -> HSTNEGDET_W<GOTGINT_SPEC> {
         HSTNEGDET_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn adevtoutchg(&mut self) -> ADEVTOUTCHG_W<GOTGINT_SPEC> {
         ADEVTOUTCHG_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn dbncedone(&mut self) -> DBNCEDONE_W<GOTGINT_SPEC> {
         DBNCEDONE_W::new(self, 19)
     }
diff --git a/esp32s2/src/usb0/grstctl.rs b/esp32s2/src/usb0/grstctl.rs
index bdd666ef07..83ad580e3e 100644
--- a/esp32s2/src/usb0/grstctl.rs
+++ b/esp32s2/src/usb0/grstctl.rs
@@ -90,37 +90,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn csftrst(&mut self) -> CSFTRST_W<GRSTCTL_SPEC> {
         CSFTRST_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn piufssftrst(&mut self) -> PIUFSSFTRST_W<GRSTCTL_SPEC> {
         PIUFSSFTRST_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frmcntrrst(&mut self) -> FRMCNTRRST_W<GRSTCTL_SPEC> {
         FRMCNTRRST_W::new(self, 2)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfflsh(&mut self) -> RXFFLSH_W<GRSTCTL_SPEC> {
         RXFFLSH_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn txfflsh(&mut self) -> TXFFLSH_W<GRSTCTL_SPEC> {
         TXFFLSH_W::new(self, 5)
     }
     #[doc = "Bits 6:10"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<GRSTCTL_SPEC> {
         TXFNUM_W::new(self, 6)
     }
diff --git a/esp32s2/src/usb0/grxfsiz.rs b/esp32s2/src/usb0/grxfsiz.rs
index 1b3760bac6..6fbfc23f7a 100644
--- a/esp32s2/src/usb0/grxfsiz.rs
+++ b/esp32s2/src/usb0/grxfsiz.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfdep(&mut self) -> RXFDEP_W<GRXFSIZ_SPEC> {
         RXFDEP_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/gusbcfg.rs b/esp32s2/src/usb0/gusbcfg.rs
index 0cda2361ee..1351cb9c67 100644
--- a/esp32s2/src/usb0/gusbcfg.rs
+++ b/esp32s2/src/usb0/gusbcfg.rs
@@ -140,67 +140,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn toutcal(&mut self) -> TOUTCAL_W<GUSBCFG_SPEC> {
         TOUTCAL_W::new(self, 0)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn phyif(&mut self) -> PHYIF_W<GUSBCFG_SPEC> {
         PHYIF_W::new(self, 3)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn fsintf(&mut self) -> FSINTF_W<GUSBCFG_SPEC> {
         FSINTF_W::new(self, 5)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn srpcap(&mut self) -> SRPCAP_W<GUSBCFG_SPEC> {
         SRPCAP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hnpcap(&mut self) -> HNPCAP_W<GUSBCFG_SPEC> {
         HNPCAP_W::new(self, 9)
     }
     #[doc = "Bits 10:13"]
     #[inline(always)]
-    #[must_use]
     pub fn usbtrdtim(&mut self) -> USBTRDTIM_W<GUSBCFG_SPEC> {
         USBTRDTIM_W::new(self, 10)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn termseldlpulse(&mut self) -> TERMSELDLPULSE_W<GUSBCFG_SPEC> {
         TERMSELDLPULSE_W::new(self, 22)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn txenddelay(&mut self) -> TXENDDELAY_W<GUSBCFG_SPEC> {
         TXENDDELAY_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn forcehstmode(&mut self) -> FORCEHSTMODE_W<GUSBCFG_SPEC> {
         FORCEHSTMODE_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn forcedevmode(&mut self) -> FORCEDEVMODE_W<GUSBCFG_SPEC> {
         FORCEDEVMODE_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn corrupttxpkt(&mut self) -> CORRUPTTXPKT_W<GUSBCFG_SPEC> {
         CORRUPTTXPKT_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/haintmsk.rs b/esp32s2/src/usb0/haintmsk.rs
index eed276f53e..6779448c85 100644
--- a/esp32s2/src/usb0/haintmsk.rs
+++ b/esp32s2/src/usb0/haintmsk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn haintmsk(&mut self) -> HAINTMSK_W<HAINTMSK_SPEC> {
         HAINTMSK_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/hc/char.rs b/esp32s2/src/usb0/hc/char.rs
index 8fa3c4a433..906fb5c5ea 100644
--- a/esp32s2/src/usb0/hc/char.rs
+++ b/esp32s2/src/usb0/hc/char.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<CHAR_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bits 11:14"]
     #[inline(always)]
-    #[must_use]
     pub fn epnum(&mut self) -> EPNUM_W<CHAR_SPEC> {
         EPNUM_W::new(self, 11)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn epdir(&mut self) -> EPDIR_W<CHAR_SPEC> {
         EPDIR_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn lspddev(&mut self) -> LSPDDEV_W<CHAR_SPEC> {
         LSPDDEV_W::new(self, 17)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<CHAR_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ec(&mut self) -> EC_W<CHAR_SPEC> {
         EC_W::new(self, 21)
     }
     #[doc = "Bits 22:28"]
     #[inline(always)]
-    #[must_use]
     pub fn devaddr(&mut self) -> DEVADDR_W<CHAR_SPEC> {
         DEVADDR_W::new(self, 22)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn oddfrm(&mut self) -> ODDFRM_W<CHAR_SPEC> {
         ODDFRM_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn chdis(&mut self) -> CHDIS_W<CHAR_SPEC> {
         CHDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn chena(&mut self) -> CHENA_W<CHAR_SPEC> {
         CHENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/hc/dma.rs b/esp32s2/src/usb0/hc/dma.rs
index 43d5d40c9f..8f54073847 100644
--- a/esp32s2/src/usb0/hc/dma.rs
+++ b/esp32s2/src/usb0/hc/dma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/hc/int.rs b/esp32s2/src/usb0/hc/int.rs
index 4b1dea7eae..d8f78296bc 100644
--- a/esp32s2/src/usb0/hc/int.rs
+++ b/esp32s2/src/usb0/hc/int.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<INT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn chhltd(&mut self) -> CHHLTD_W<INT_SPEC> {
         CHHLTD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<INT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<INT_SPEC> {
         STALL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_SPEC> {
         NACK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ack(&mut self) -> ACK_W<INT_SPEC> {
         ACK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn nyet(&mut self) -> NYET_W<INT_SPEC> {
         NYET_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn xacterr(&mut self) -> XACTERR_W<INT_SPEC> {
         XACTERR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn bblerr(&mut self) -> BBLERR_W<INT_SPEC> {
         BBLERR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn frmovrun(&mut self) -> FRMOVRUN_W<INT_SPEC> {
         FRMOVRUN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn datatglerr(&mut self) -> DATATGLERR_W<INT_SPEC> {
         DATATGLERR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<INT_SPEC> {
         BNAINTR_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn xcs_xact_err(&mut self) -> XCS_XACT_ERR_W<INT_SPEC> {
         XCS_XACT_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn desc_lst_rollintr(&mut self) -> DESC_LST_ROLLINTR_W<INT_SPEC> {
         DESC_LST_ROLLINTR_W::new(self, 13)
     }
diff --git a/esp32s2/src/usb0/hc/intmsk.rs b/esp32s2/src/usb0/hc/intmsk.rs
index ad418d26ff..794713f712 100644
--- a/esp32s2/src/usb0/hc/intmsk.rs
+++ b/esp32s2/src/usb0/hc/intmsk.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<INTMSK_SPEC> {
         XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<INTMSK_SPEC> {
         CHHLTDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<INTMSK_SPEC> {
         AHBERRMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn stallmsk(&mut self) -> STALLMSK_W<INTMSK_SPEC> {
         STALLMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn nakmsk(&mut self) -> NAKMSK_W<INTMSK_SPEC> {
         NAKMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ackmsk(&mut self) -> ACKMSK_W<INTMSK_SPEC> {
         ACKMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetmsk(&mut self) -> NYETMSK_W<INTMSK_SPEC> {
         NYETMSK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<INTMSK_SPEC> {
         XACTERRMSK_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<INTMSK_SPEC> {
         BBLERRMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<INTMSK_SPEC> {
         FRMOVRUNMSK_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<INTMSK_SPEC> {
         DATATGLERRMSK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintrmsk(&mut self) -> BNAINTRMSK_W<INTMSK_SPEC> {
         BNAINTRMSK_W::new(self, 11)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn desc_lst_rollintrmsk(&mut self) -> DESC_LST_ROLLINTRMSK_W<INTMSK_SPEC> {
         DESC_LST_ROLLINTRMSK_W::new(self, 13)
     }
diff --git a/esp32s2/src/usb0/hc/tsiz.rs b/esp32s2/src/usb0/hc/tsiz.rs
index c8693b771d..30558700fd 100644
--- a/esp32s2/src/usb0/hc/tsiz.rs
+++ b/esp32s2/src/usb0/hc/tsiz.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<TSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<TSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn pid(&mut self) -> PID_W<TSIZ_SPEC> {
         PID_W::new(self, 29)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn dopng(&mut self) -> DOPNG_W<TSIZ_SPEC> {
         DOPNG_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/hcfg.rs b/esp32s2/src/usb0/hcfg.rs
index a716d5c156..1ca636e59a 100644
--- a/esp32s2/src/usb0/hcfg.rs
+++ b/esp32s2/src/usb0/hcfg.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W<HCFG_SPEC> {
         FSLSPCLKSEL_W::new(self, 0)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn fslssupp(&mut self) -> FSLSSUPP_W<HCFG_SPEC> {
         FSLSSUPP_W::new(self, 2)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ena32khzs(&mut self) -> ENA32KHZS_W<HCFG_SPEC> {
         ENA32KHZS_W::new(self, 7)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn descdma(&mut self) -> DESCDMA_W<HCFG_SPEC> {
         DESCDMA_W::new(self, 23)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn frlisten(&mut self) -> FRLISTEN_W<HCFG_SPEC> {
         FRLISTEN_W::new(self, 24)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn perschedena(&mut self) -> PERSCHEDENA_W<HCFG_SPEC> {
         PERSCHEDENA_W::new(self, 26)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn modechtimen(&mut self) -> MODECHTIMEN_W<HCFG_SPEC> {
         MODECHTIMEN_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/hfir.rs b/esp32s2/src/usb0/hfir.rs
index e8a461ca6f..a9e241d9b8 100644
--- a/esp32s2/src/usb0/hfir.rs
+++ b/esp32s2/src/usb0/hfir.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn frint(&mut self) -> FRINT_W<HFIR_SPEC> {
         FRINT_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn hfirrldctrl(&mut self) -> HFIRRLDCTRL_W<HFIR_SPEC> {
         HFIRRLDCTRL_W::new(self, 16)
     }
diff --git a/esp32s2/src/usb0/hflbaddr.rs b/esp32s2/src/usb0/hflbaddr.rs
index c3545c961f..f49a43e827 100644
--- a/esp32s2/src/usb0/hflbaddr.rs
+++ b/esp32s2/src/usb0/hflbaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn hflbaddr(&mut self) -> HFLBADDR_W<HFLBADDR_SPEC> {
         HFLBADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/hprt.rs b/esp32s2/src/usb0/hprt.rs
index 08371ccc09..1aab1f1fb3 100644
--- a/esp32s2/src/usb0/hprt.rs
+++ b/esp32s2/src/usb0/hprt.rs
@@ -136,55 +136,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn prtconndet(&mut self) -> PRTCONNDET_W<HPRT_SPEC> {
         PRTCONNDET_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn prtena(&mut self) -> PRTENA_W<HPRT_SPEC> {
         PRTENA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn prtenchng(&mut self) -> PRTENCHNG_W<HPRT_SPEC> {
         PRTENCHNG_W::new(self, 3)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn prtovrcurrchng(&mut self) -> PRTOVRCURRCHNG_W<HPRT_SPEC> {
         PRTOVRCURRCHNG_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn prtres(&mut self) -> PRTRES_W<HPRT_SPEC> {
         PRTRES_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn prtsusp(&mut self) -> PRTSUSP_W<HPRT_SPEC> {
         PRTSUSP_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn prtrst(&mut self) -> PRTRST_W<HPRT_SPEC> {
         PRTRST_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn prtpwr(&mut self) -> PRTPWR_W<HPRT_SPEC> {
         PRTPWR_W::new(self, 12)
     }
     #[doc = "Bits 13:16"]
     #[inline(always)]
-    #[must_use]
     pub fn prttstctl(&mut self) -> PRTTSTCTL_W<HPRT_SPEC> {
         PRTTSTCTL_W::new(self, 13)
     }
diff --git a/esp32s2/src/usb0/hptxfsiz.rs b/esp32s2/src/usb0/hptxfsiz.rs
index 33af448539..9e9389cf89 100644
--- a/esp32s2/src/usb0/hptxfsiz.rs
+++ b/esp32s2/src/usb0/hptxfsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfstaddr(&mut self) -> PTXFSTADDR_W<HPTXFSIZ_SPEC> {
         PTXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfsize(&mut self) -> PTXFSIZE_W<HPTXFSIZ_SPEC> {
         PTXFSIZE_W::new(self, 16)
     }
diff --git a/esp32s2/src/usb0/in_ep/diepctl.rs b/esp32s2/src/usb0/in_ep/diepctl.rs
index f1ccc75dc0..3edca046cf 100644
--- a/esp32s2/src/usb0/in_ep/diepctl.rs
+++ b/esp32s2/src/usb0/in_ep/diepctl.rs
@@ -100,67 +100,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DIEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn usbactep(&mut self) -> USBACTEP_W<DIEPCTL_SPEC> {
         USBACTEP_W::new(self, 15)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<DIEPCTL_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DIEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bits 22:25"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<DIEPCTL_SPEC> {
         TXFNUM_W::new(self, 22)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DIEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DIEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn setd0pid(&mut self) -> SETD0PID_W<DIEPCTL_SPEC> {
         SETD0PID_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn setd1pid(&mut self) -> SETD1PID_W<DIEPCTL_SPEC> {
         SETD1PID_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DIEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DIEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/in_ep/dieptsiz.rs b/esp32s2/src/usb0/in_ep/dieptsiz.rs
index b56d094260..d4b0862441 100644
--- a/esp32s2/src/usb0/in_ep/dieptsiz.rs
+++ b/esp32s2/src/usb0/in_ep/dieptsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DIEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DIEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
diff --git a/esp32s2/src/usb0/in_ep0/diepctl.rs b/esp32s2/src/usb0/in_ep0/diepctl.rs
index da2f3f3341..b5fffe659c 100644
--- a/esp32s2/src/usb0/in_ep0/diepctl.rs
+++ b/esp32s2/src/usb0/in_ep0/diepctl.rs
@@ -92,43 +92,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DIEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DIEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bits 22:25"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<DIEPCTL_SPEC> {
         TXFNUM_W::new(self, 22)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DIEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DIEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DIEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DIEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/in_ep0/diepdma.rs b/esp32s2/src/usb0/in_ep0/diepdma.rs
index fda02a27d7..14e7e7eb4e 100644
--- a/esp32s2/src/usb0/in_ep0/diepdma.rs
+++ b/esp32s2/src/usb0/in_ep0/diepdma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DIEPDMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/in_ep0/diepint.rs b/esp32s2/src/usb0/in_ep0/diepint.rs
index 7717febbce..4b88eda259 100644
--- a/esp32s2/src/usb0/in_ep0/diepint.rs
+++ b/esp32s2/src/usb0/in_ep0/diepint.rs
@@ -152,79 +152,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<DIEPINT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbld(&mut self) -> EPDISBLD_W<DIEPINT_SPEC> {
         EPDISBLD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<DIEPINT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timeout(&mut self) -> TIMEOUT_W<DIEPINT_SPEC> {
         TIMEOUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<DIEPINT_SPEC> {
         INTKNTXFEMP_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn intknepmis(&mut self) -> INTKNEPMIS_W<DIEPINT_SPEC> {
         INTKNEPMIS_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<DIEPINT_SPEC> {
         INEPNAKEFF_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<DIEPINT_SPEC> {
         TXFIFOUNDRN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<DIEPINT_SPEC> {
         BNAINTR_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<DIEPINT_SPEC> {
         PKTDRPSTS_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerr(&mut self) -> BBLEERR_W<DIEPINT_SPEC> {
         BBLEERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakintrpt(&mut self) -> NAKINTRPT_W<DIEPINT_SPEC> {
         NAKINTRPT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetintrpt(&mut self) -> NYETINTRPT_W<DIEPINT_SPEC> {
         NYETINTRPT_W::new(self, 14)
     }
diff --git a/esp32s2/src/usb0/in_ep0/dieptsiz.rs b/esp32s2/src/usb0/in_ep0/dieptsiz.rs
index f13b9d4f8c..41e3a4167b 100644
--- a/esp32s2/src/usb0/in_ep0/dieptsiz.rs
+++ b/esp32s2/src/usb0/in_ep0/dieptsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DIEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:20"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DIEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
diff --git a/esp32s2/src/usb0/out_ep/doepctl.rs b/esp32s2/src/usb0/out_ep/doepctl.rs
index 3f72a94784..8383da45f8 100644
--- a/esp32s2/src/usb0/out_ep/doepctl.rs
+++ b/esp32s2/src/usb0/out_ep/doepctl.rs
@@ -100,67 +100,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DOEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn usbactep(&mut self) -> USBACTEP_W<DOEPCTL_SPEC> {
         USBACTEP_W::new(self, 15)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<DOEPCTL_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn snp(&mut self) -> SNP_W<DOEPCTL_SPEC> {
         SNP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DOEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DOEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DOEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn setd0pid(&mut self) -> SETD0PID_W<DOEPCTL_SPEC> {
         SETD0PID_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn setd1pid(&mut self) -> SETD1PID_W<DOEPCTL_SPEC> {
         SETD1PID_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DOEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DOEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/out_ep/doeptsiz.rs b/esp32s2/src/usb0/out_ep/doeptsiz.rs
index d41c10a8e2..b8fd22ab01 100644
--- a/esp32s2/src/usb0/out_ep/doeptsiz.rs
+++ b/esp32s2/src/usb0/out_ep/doeptsiz.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DOEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DOEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn supcnt(&mut self) -> SUPCNT_W<DOEPTSIZ_SPEC> {
         SUPCNT_W::new(self, 29)
     }
diff --git a/esp32s2/src/usb0/out_ep0/doepctl.rs b/esp32s2/src/usb0/out_ep0/doepctl.rs
index 3a49f43156..2df4e16832 100644
--- a/esp32s2/src/usb0/out_ep0/doepctl.rs
+++ b/esp32s2/src/usb0/out_ep0/doepctl.rs
@@ -88,31 +88,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn snp(&mut self) -> SNP_W<DOEPCTL_SPEC> {
         SNP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DOEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DOEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DOEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DOEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb0/out_ep0/doepdma.rs b/esp32s2/src/usb0/out_ep0/doepdma.rs
index 9911f59651..ae7f29bae7 100644
--- a/esp32s2/src/usb0/out_ep0/doepdma.rs
+++ b/esp32s2/src/usb0/out_ep0/doepdma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DOEPDMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/out_ep0/doepdmab.rs b/esp32s2/src/usb0/out_ep0/doepdmab.rs
index 09d2730336..9cd48daf0a 100644
--- a/esp32s2/src/usb0/out_ep0/doepdmab.rs
+++ b/esp32s2/src/usb0/out_ep0/doepdmab.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmabufferaddr(&mut self) -> DMABUFFERADDR_W<DOEPDMAB_SPEC> {
         DMABUFFERADDR_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb0/out_ep0/doepint.rs b/esp32s2/src/usb0/out_ep0/doepint.rs
index 240ab32605..56aa763dba 100644
--- a/esp32s2/src/usb0/out_ep0/doepint.rs
+++ b/esp32s2/src/usb0/out_ep0/doepint.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<DOEPINT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbld(&mut self) -> EPDISBLD_W<DOEPINT_SPEC> {
         EPDISBLD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<DOEPINT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn setup(&mut self) -> SETUP_W<DOEPINT_SPEC> {
         SETUP_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<DOEPINT_SPEC> {
         OUTTKNEPDIS_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<DOEPINT_SPEC> {
         STSPHSERCVD_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<DOEPINT_SPEC> {
         BACK2BACKSETUP_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn outpkterr(&mut self) -> OUTPKTERR_W<DOEPINT_SPEC> {
         OUTPKTERR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<DOEPINT_SPEC> {
         BNAINTR_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<DOEPINT_SPEC> {
         PKTDRPSTS_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerr(&mut self) -> BBLEERR_W<DOEPINT_SPEC> {
         BBLEERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakintrpt(&mut self) -> NAKINTRPT_W<DOEPINT_SPEC> {
         NAKINTRPT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyepintrpt(&mut self) -> NYEPINTRPT_W<DOEPINT_SPEC> {
         NYEPINTRPT_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<DOEPINT_SPEC> {
         STUPPKTRCVD_W::new(self, 15)
     }
diff --git a/esp32s2/src/usb0/out_ep0/doeptsiz.rs b/esp32s2/src/usb0/out_ep0/doeptsiz.rs
index 5224d73bbe..9b13801902 100644
--- a/esp32s2/src/usb0/out_ep0/doeptsiz.rs
+++ b/esp32s2/src/usb0/out_ep0/doeptsiz.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DOEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DOEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn supcnt(&mut self) -> SUPCNT_W<DOEPTSIZ_SPEC> {
         SUPCNT_W::new(self, 29)
     }
diff --git a/esp32s2/src/usb0/pcgcctl.rs b/esp32s2/src/usb0/pcgcctl.rs
index c649b0ccab..06ebb2daad 100644
--- a/esp32s2/src/usb0/pcgcctl.rs
+++ b/esp32s2/src/usb0/pcgcctl.rs
@@ -80,31 +80,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn stoppclk(&mut self) -> STOPPCLK_W<PCGCCTL_SPEC> {
         STOPPCLK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gatehclk(&mut self) -> GATEHCLK_W<PCGCCTL_SPEC> {
         GATEHCLK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pwrclmp(&mut self) -> PWRCLMP_W<PCGCCTL_SPEC> {
         PWRCLMP_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<PCGCCTL_SPEC> {
         RSTPDWNMODULE_W::new(self, 3)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<PCGCCTL_SPEC> {
         RESETAFTERSUSP_W::new(self, 8)
     }
diff --git a/esp32s2/src/usb_wrap/date.rs b/esp32s2/src/usb_wrap/date.rs
index be3aa8c786..cfa07ba774 100644
--- a/esp32s2/src/usb_wrap/date.rs
+++ b/esp32s2/src/usb_wrap/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Date register"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_wrap_date(&mut self) -> USB_WRAP_DATE_W<DATE_SPEC> {
         USB_WRAP_DATE_W::new(self, 0)
     }
diff --git a/esp32s2/src/usb_wrap/otg_conf.rs b/esp32s2/src/usb_wrap/otg_conf.rs
index e0c91f9dd3..c438ca8f25 100644
--- a/esp32s2/src/usb_wrap/otg_conf.rs
+++ b/esp32s2/src/usb_wrap/otg_conf.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
     #[inline(always)]
-    #[must_use]
     pub fn srp_sessend_override(&mut self) -> SRP_SESSEND_OVERRIDE_W<OTG_CONF_SPEC> {
         SRP_SESSEND_OVERRIDE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Software over-ride value of srp session end signal."]
     #[inline(always)]
-    #[must_use]
     pub fn srp_sessend_value(&mut self) -> SRP_SESSEND_VALUE_W<OTG_CONF_SPEC> {
         SRP_SESSEND_VALUE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
     #[inline(always)]
-    #[must_use]
     pub fn phy_sel(&mut self) -> PHY_SEL_W<OTG_CONF_SPEC> {
         PHY_SEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
     #[inline(always)]
-    #[must_use]
     pub fn dfifo_force_pd(&mut self) -> DFIFO_FORCE_PD_W<OTG_CONF_SPEC> {
         DFIFO_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
     #[inline(always)]
-    #[must_use]
     pub fn dbnce_fltr_bypass(&mut self) -> DBNCE_FLTR_BYPASS_W<OTG_CONF_SPEC> {
         DBNCE_FLTR_BYPASS_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W<OTG_CONF_SPEC> {
         EXCHG_PINS_OVERRIDE_W::new(self, 5)
     }
     #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins(&mut self) -> EXCHG_PINS_W<OTG_CONF_SPEC> {
         EXCHG_PINS_W::new(self, 6)
     }
     #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefh(&mut self) -> VREFH_W<OTG_CONF_SPEC> {
         VREFH_W::new(self, 7)
     }
     #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefl(&mut self) -> VREFL_W<OTG_CONF_SPEC> {
         VREFL_W::new(self, 9)
     }
     #[doc = "Bit 11 - Enable software controlle input threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn vref_override(&mut self) -> VREF_OVERRIDE_W<OTG_CONF_SPEC> {
         VREF_OVERRIDE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W<OTG_CONF_SPEC> {
         PAD_PULL_OVERRIDE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Controlle USB D+ pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup(&mut self) -> DP_PULLUP_W<OTG_CONF_SPEC> {
         DP_PULLUP_W::new(self, 13)
     }
     #[doc = "Bit 14 - Controlle USB D+ pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W<OTG_CONF_SPEC> {
         DP_PULLDOWN_W::new(self, 14)
     }
     #[doc = "Bit 15 - Controlle USB D+ pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup(&mut self) -> DM_PULLUP_W<OTG_CONF_SPEC> {
         DM_PULLUP_W::new(self, 15)
     }
     #[doc = "Bit 16 - Controlle USB D+ pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W<OTG_CONF_SPEC> {
         DM_PULLDOWN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
     #[inline(always)]
-    #[must_use]
     pub fn pullup_value(&mut self) -> PULLUP_VALUE_W<OTG_CONF_SPEC> {
         PULLUP_VALUE_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enable USB pad function"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<OTG_CONF_SPEC> {
         USB_PAD_ENABLE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Force ahb clock always on"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_clk_force_on(&mut self) -> AHB_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
         AHB_CLK_FORCE_ON_W::new(self, 19)
     }
     #[doc = "Bit 20 - Force phy clock always on"]
     #[inline(always)]
-    #[must_use]
     pub fn phy_clk_force_on(&mut self) -> PHY_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
         PHY_CLK_FORCE_ON_W::new(self, 20)
     }
     #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W<OTG_CONF_SPEC> {
         PHY_TX_EDGE_SEL_W::new(self, 21)
     }
     #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
     #[inline(always)]
-    #[must_use]
     pub fn dfifo_force_pu(&mut self) -> DFIFO_FORCE_PU_W<OTG_CONF_SPEC> {
         DFIFO_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 31 - Disable auto clock gating of CSR registers"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<OTG_CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s2/src/usb_wrap/test_conf.rs b/esp32s2/src/usb_wrap/test_conf.rs
index 914f0057a7..fafff78a2a 100644
--- a/esp32s2/src/usb_wrap/test_conf.rs
+++ b/esp32s2/src/usb_wrap/test_conf.rs
@@ -78,25 +78,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
-    #[must_use]
     pub fn test_enable(&mut self) -> TEST_ENABLE_W<TEST_CONF_SPEC> {
         TEST_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - USB pad oen in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_usb_oe(&mut self) -> TEST_USB_OE_W<TEST_CONF_SPEC> {
         TEST_USB_OE_W::new(self, 1)
     }
     #[doc = "Bit 2 - USB D+ tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_tx_dp(&mut self) -> TEST_TX_DP_W<TEST_CONF_SPEC> {
         TEST_TX_DP_W::new(self, 2)
     }
     #[doc = "Bit 3 - USB D- tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_tx_dm(&mut self) -> TEST_TX_DM_W<TEST_CONF_SPEC> {
         TEST_TX_DM_W::new(self, 3)
     }
diff --git a/esp32s2/src/xts_aes/destination.rs b/esp32s2/src/xts_aes/destination.rs
index 4d8c170c25..dacc72e2f9 100644
--- a/esp32s2/src/xts_aes/destination.rs
+++ b/esp32s2/src/xts_aes/destination.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn destination(&mut self) -> DESTINATION_W<DESTINATION_SPEC> {
         DESTINATION_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/destroy.rs b/esp32s2/src/xts_aes/destroy.rs
index f7f8ccb7bf..62475a8e18 100644
--- a/esp32s2/src/xts_aes/destroy.rs
+++ b/esp32s2/src/xts_aes/destroy.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DESTROY_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set to destroy encrypted result."]
     #[inline(always)]
-    #[must_use]
     pub fn destroy(&mut self) -> DESTROY_W<DESTROY_SPEC> {
         DESTROY_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/linesize.rs b/esp32s2/src/xts_aes/linesize.rs
index 2ebf935c3e..c109369991 100644
--- a/esp32s2/src/xts_aes/linesize.rs
+++ b/esp32s2/src/xts_aes/linesize.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn linesize(&mut self) -> LINESIZE_W<LINESIZE_SPEC> {
         LINESIZE_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/physical_address.rs b/esp32s2/src/xts_aes/physical_address.rs
index acc6c8443f..65c1fe3899 100644
--- a/esp32s2/src/xts_aes/physical_address.rs
+++ b/esp32s2/src/xts_aes/physical_address.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Physical address."]
     #[inline(always)]
-    #[must_use]
     pub fn physical_address(&mut self) -> PHYSICAL_ADDRESS_W<PHYSICAL_ADDRESS_SPEC> {
         PHYSICAL_ADDRESS_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/plain_.rs b/esp32s2/src/xts_aes/plain_.rs
index 3d49d324de..3ddae08131 100644
--- a/esp32s2/src/xts_aes/plain_.rs
+++ b/esp32s2/src/xts_aes/plain_.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register stores %sth 32-bit piece of plaintext."]
     #[inline(always)]
-    #[must_use]
     pub fn plain(&mut self) -> PLAIN_W<PLAIN__SPEC> {
         PLAIN_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/release.rs b/esp32s2/src/xts_aes/release.rs
index 20faf1a7d4..06b0d91c84 100644
--- a/esp32s2/src/xts_aes/release.rs
+++ b/esp32s2/src/xts_aes/release.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RELEASE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set to grant SPI1 access to encrypted result."]
     #[inline(always)]
-    #[must_use]
     pub fn release(&mut self) -> RELEASE_W<RELEASE_SPEC> {
         RELEASE_W::new(self, 0)
     }
diff --git a/esp32s2/src/xts_aes/trigger.rs b/esp32s2/src/xts_aes/trigger.rs
index 3bd9a045ad..bedf84b8d9 100644
--- a/esp32s2/src/xts_aes/trigger.rs
+++ b/esp32s2/src/xts_aes/trigger.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set to enable manual encryption."]
     #[inline(always)]
-    #[must_use]
     pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
         TRIGGER_W::new(self, 0)
     }
diff --git a/esp32s3/Cargo.toml b/esp32s3/Cargo.toml
index b22c4ece4f..a9750f921c 100644
--- a/esp32s3/Cargo.toml
+++ b/esp32s3/Cargo.toml
@@ -30,7 +30,6 @@ test = false
 [dependencies]
 critical-section = { version = "1.1.3", optional = true }
 vcell = "0.1.3"
-xtensa-lx = "0.9.0"
 defmt = { version = "0.3.8", optional = true }
 
 [features]
diff --git a/esp32s3/src/aes/aad_block_num.rs b/esp32s3/src/aes/aad_block_num.rs
index 69251c94d2..709b31f828 100644
--- a/esp32s3/src/aes/aad_block_num.rs
+++ b/esp32s3/src/aes/aad_block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
-    #[must_use]
     pub fn aad_block_num(&mut self) -> AAD_BLOCK_NUM_W<AAD_BLOCK_NUM_SPEC> {
         AAD_BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/block_mode.rs b/esp32s3/src/aes/block_mode.rs
index a84a99f335..0b4efbf844 100644
--- a/esp32s3/src/aes/block_mode.rs
+++ b/esp32s3/src/aes/block_mode.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn block_mode(&mut self) -> BLOCK_MODE_W<BLOCK_MODE_SPEC> {
         BLOCK_MODE_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/block_num.rs b/esp32s3/src/aes/block_num.rs
index 9b1e2d1721..809053226c 100644
--- a/esp32s3/src/aes/block_num.rs
+++ b/esp32s3/src/aes/block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn block_num(&mut self) -> BLOCK_NUM_W<BLOCK_NUM_SPEC> {
         BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/continue_.rs b/esp32s3/src/aes/continue_.rs
index 05f460517e..cf7b305537 100644
--- a/esp32s3/src/aes/continue_.rs
+++ b/esp32s3/src/aes/continue_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to continue GCM operation."]
     #[inline(always)]
-    #[must_use]
     pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
         CONTINUE_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/date.rs b/esp32s3/src/aes/date.rs
index 2b4485b861..c860c6be83 100644
--- a/esp32s3/src/aes/date.rs
+++ b/esp32s3/src/aes/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - This bits stores the version information of AES."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/dma_enable.rs b/esp32s3/src/aes/dma_enable.rs
index 8ff9f5685b..f39731d5d3 100644
--- a/esp32s3/src/aes/dma_enable.rs
+++ b/esp32s3/src/aes/dma_enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_enable(&mut self) -> DMA_ENABLE_W<DMA_ENABLE_SPEC> {
         DMA_ENABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/dma_exit.rs b/esp32s3/src/aes/dma_exit.rs
index ce69d113a8..c81d2613b4 100644
--- a/esp32s3/src/aes/dma_exit.rs
+++ b/esp32s3/src/aes/dma_exit.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_EXIT_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_exit(&mut self) -> DMA_EXIT_W<DMA_EXIT_SPEC> {
         DMA_EXIT_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/inc_sel.rs b/esp32s3/src/aes/inc_sel.rs
index bb0f756bdd..b0e06b4586 100644
--- a/esp32s3/src/aes/inc_sel.rs
+++ b/esp32s3/src/aes/inc_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
     #[inline(always)]
-    #[must_use]
     pub fn inc_sel(&mut self) -> INC_SEL_W<INC_SEL_SPEC> {
         INC_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/int_clr.rs b/esp32s3/src/aes/int_clr.rs
index c5a1fc0395..6385beb246 100644
--- a/esp32s3/src/aes/int_clr.rs
+++ b/esp32s3/src/aes/int_clr.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to clear AES interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
         INT_CLR_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/int_ena.rs b/esp32s3/src/aes/int_ena.rs
index 7e41ca7506..4aef394f2e 100644
--- a/esp32s3/src/aes/int_ena.rs
+++ b/esp32s3/src/aes/int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
         INT_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/key.rs b/esp32s3/src/aes/key.rs
index 807bd5088c..9b19d6f124 100644
--- a/esp32s3/src/aes/key.rs
+++ b/esp32s3/src/aes/key.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores AES keys."]
     #[inline(always)]
-    #[must_use]
     pub fn key(&mut self) -> KEY_W<KEY_SPEC> {
         KEY_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/mode.rs b/esp32s3/src/aes/mode.rs
index 26f252f07e..6d8c7122de 100644
--- a/esp32s3/src/aes/mode.rs
+++ b/esp32s3/src/aes/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Defines the key length and the encryption/decryption of the AES accelerator."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/remainder_bit_num.rs b/esp32s3/src/aes/remainder_bit_num.rs
index c2a124ab9e..3f20adbc9f 100644
--- a/esp32s3/src/aes/remainder_bit_num.rs
+++ b/esp32s3/src/aes/remainder_bit_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
-    #[must_use]
     pub fn remainder_bit_num(&mut self) -> REMAINDER_BIT_NUM_W<REMAINDER_BIT_NUM_SPEC> {
         REMAINDER_BIT_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/text_in.rs b/esp32s3/src/aes/text_in.rs
index eaa69ee033..9717e2e6e1 100644
--- a/esp32s3/src/aes/text_in.rs
+++ b/esp32s3/src/aes/text_in.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn text_in(&mut self) -> TEXT_IN_W<TEXT_IN_SPEC> {
         TEXT_IN_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/text_out.rs b/esp32s3/src/aes/text_out.rs
index e4c6b3463b..2fd3a65e73 100644
--- a/esp32s3/src/aes/text_out.rs
+++ b/esp32s3/src/aes/text_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn text_out(&mut self) -> TEXT_OUT_W<TEXT_OUT_SPEC> {
         TEXT_OUT_W::new(self, 0)
     }
diff --git a/esp32s3/src/aes/trigger.rs b/esp32s3/src/aes/trigger.rs
index a5fe4605d4..f5109ee10e 100644
--- a/esp32s3/src/aes/trigger.rs
+++ b/esp32s3/src/aes/trigger.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start AES calculation."]
     #[inline(always)]
-    #[must_use]
     pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
         TRIGGER_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/clk_out_en.rs b/esp32s3/src/apb_ctrl/clk_out_en.rs
index 972e4029c5..76d07c65fd 100644
--- a/esp32s3/src/apb_ctrl/clk_out_en.rs
+++ b/esp32s3/src/apb_ctrl/clk_out_en.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk20_oen(&mut self) -> CLK20_OEN_W<CLK_OUT_EN_SPEC> {
         CLK20_OEN_W::new(self, 0)
     }
     #[doc = "Bit 1 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk22_oen(&mut self) -> CLK22_OEN_W<CLK_OUT_EN_SPEC> {
         CLK22_OEN_W::new(self, 1)
     }
     #[doc = "Bit 2 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk44_oen(&mut self) -> CLK44_OEN_W<CLK_OUT_EN_SPEC> {
         CLK44_OEN_W::new(self, 2)
     }
     #[doc = "Bit 3 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_bb_oen(&mut self) -> CLK_BB_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_BB_OEN_W::new(self, 3)
     }
     #[doc = "Bit 4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk80_oen(&mut self) -> CLK80_OEN_W<CLK_OUT_EN_SPEC> {
         CLK80_OEN_W::new(self, 4)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk160_oen(&mut self) -> CLK160_OEN_W<CLK_OUT_EN_SPEC> {
         CLK160_OEN_W::new(self, 5)
     }
     #[doc = "Bit 6 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_320m_oen(&mut self) -> CLK_320M_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_320M_OEN_W::new(self, 6)
     }
     #[doc = "Bit 7 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_adc_inf_oen(&mut self) -> CLK_ADC_INF_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_ADC_INF_OEN_W::new(self, 7)
     }
     #[doc = "Bit 8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_dac_cpu_oen(&mut self) -> CLK_DAC_CPU_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_DAC_CPU_OEN_W::new(self, 8)
     }
     #[doc = "Bit 9 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk40x_bb_oen(&mut self) -> CLK40X_BB_OEN_W<CLK_OUT_EN_SPEC> {
         CLK40X_BB_OEN_W::new(self, 9)
     }
     #[doc = "Bit 10 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_xtal_oen(&mut self) -> CLK_XTAL_OEN_W<CLK_OUT_EN_SPEC> {
         CLK_XTAL_OEN_W::new(self, 10)
     }
diff --git a/esp32s3/src/apb_ctrl/clkgate_force_on.rs b/esp32s3/src/apb_ctrl/clkgate_force_on.rs
index e5aaac236d..c61b40a10c 100644
--- a/esp32s3/src/apb_ctrl/clkgate_force_on.rs
+++ b/esp32s3/src/apb_ctrl/clkgate_force_on.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_clkgate_force_on(&mut self) -> ROM_CLKGATE_FORCE_ON_W<CLKGATE_FORCE_ON_SPEC> {
         ROM_CLKGATE_FORCE_ON_W::new(self, 0)
     }
     #[doc = "Bits 3:13 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_clkgate_force_on(&mut self) -> SRAM_CLKGATE_FORCE_ON_W<CLKGATE_FORCE_ON_SPEC> {
         SRAM_CLKGATE_FORCE_ON_W::new(self, 3)
     }
diff --git a/esp32s3/src/apb_ctrl/date.rs b/esp32s3/src/apb_ctrl/date.rs
index 1f3facbc7a..dc545f0439 100644
--- a/esp32s3/src/apb_ctrl/date.rs
+++ b/esp32s3/src/apb_ctrl/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Version control"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs b/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
index fe3e5cd396..3b37fae8d1 100644
--- a/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
+++ b/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_mem_pms_lock(&mut self) -> EXT_MEM_PMS_LOCK_W<EXT_MEM_PMS_LOCK_SPEC> {
         EXT_MEM_PMS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs b/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
index 191aac7d45..730098428a 100644
--- a/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
+++ b/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
     #[inline(always)]
-    #[must_use]
     pub fn writeback_bypass(&mut self) -> WRITEBACK_BYPASS_W<EXT_MEM_WRITEBACK_BYPASS_SPEC> {
         WRITEBACK_BYPASS_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_addr.rs b/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
index e528fe34b3..a05d28a184 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE0_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_attr.rs b/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
index 30769a57c4..b60b6633d4 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace0_attr(&mut self) -> FLASH_ACE0_ATTR_W<FLASH_ACE0_ATTR_SPEC> {
         FLASH_ACE0_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_size.rs b/esp32s3/src/apb_ctrl/flash_ace0_size.rs
index c1c4043f12..069bc2f9de 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace0_size(&mut self) -> FLASH_ACE0_SIZE_W<FLASH_ACE0_SIZE_SPEC> {
         FLASH_ACE0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_addr.rs b/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
index 6edf0e50d9..8f25efdf51 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE1_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_attr.rs b/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
index 6206c4c13e..d9ea5bc668 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace1_attr(&mut self) -> FLASH_ACE1_ATTR_W<FLASH_ACE1_ATTR_SPEC> {
         FLASH_ACE1_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_size.rs b/esp32s3/src/apb_ctrl/flash_ace1_size.rs
index ccd0c3452f..8e6aa0e2cf 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace1_size(&mut self) -> FLASH_ACE1_SIZE_W<FLASH_ACE1_SIZE_SPEC> {
         FLASH_ACE1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_addr.rs b/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
index 29d7a5c063..1cff867793 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE2_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_attr.rs b/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
index 10839a5b8b..cc97aec7a2 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace2_attr(&mut self) -> FLASH_ACE2_ATTR_W<FLASH_ACE2_ATTR_SPEC> {
         FLASH_ACE2_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_size.rs b/esp32s3/src/apb_ctrl/flash_ace2_size.rs
index e6d3b59901..613f43aa4f 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace2_size(&mut self) -> FLASH_ACE2_SIZE_W<FLASH_ACE2_SIZE_SPEC> {
         FLASH_ACE2_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_addr.rs b/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
index e493744e24..7ab7a90441 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FLASH_ACE3_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_attr.rs b/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
index ee603c1636..ca95a0963a 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace3_attr(&mut self) -> FLASH_ACE3_ATTR_W<FLASH_ACE3_ATTR_SPEC> {
         FLASH_ACE3_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_size.rs b/esp32s3/src/apb_ctrl/flash_ace3_size.rs
index 25723d971e..bbcf1dc1ec 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ace3_size(&mut self) -> FLASH_ACE3_SIZE_W<FLASH_ACE3_SIZE_SPEC> {
         FLASH_ACE3_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/front_end_mem_pd.rs b/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
index 925d272d1f..55c575fe97 100644
--- a/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
+++ b/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pu(&mut self) -> AGC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PU_W::new(self, 0)
     }
     #[doc = "Bit 1 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn agc_mem_force_pd(&mut self) -> AGC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         AGC_MEM_FORCE_PD_W::new(self, 1)
     }
     #[doc = "Bit 2 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pu(&mut self) -> PBUS_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PU_W::new(self, 2)
     }
     #[doc = "Bit 3 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn pbus_mem_force_pd(&mut self) -> PBUS_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         PBUS_MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_mem_force_pu(&mut self) -> DC_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         DC_MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_mem_force_pd(&mut self) -> DC_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         DC_MEM_FORCE_PD_W::new(self, 5)
     }
     #[doc = "Bit 6 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn freq_mem_force_pu(&mut self) -> FREQ_MEM_FORCE_PU_W<FRONT_END_MEM_PD_SPEC> {
         FREQ_MEM_FORCE_PU_W::new(self, 6)
     }
     #[doc = "Bit 7 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn freq_mem_force_pd(&mut self) -> FREQ_MEM_FORCE_PD_W<FRONT_END_MEM_PD_SPEC> {
         FREQ_MEM_FORCE_PD_W::new(self, 7)
     }
diff --git a/esp32s3/src/apb_ctrl/host_inf_sel.rs b/esp32s3/src/apb_ctrl/host_inf_sel.rs
index be642937e3..c2473f9983 100644
--- a/esp32s3/src/apb_ctrl/host_inf_sel.rs
+++ b/esp32s3/src/apb_ctrl/host_inf_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_io_swap(&mut self) -> PERI_IO_SWAP_W<HOST_INF_SEL_SPEC> {
         PERI_IO_SWAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/mem_power_down.rs b/esp32s3/src/apb_ctrl/mem_power_down.rs
index 841504dfce..a467678ff1 100644
--- a/esp32s3/src/apb_ctrl/mem_power_down.rs
+++ b/esp32s3/src/apb_ctrl/mem_power_down.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_power_down(&mut self) -> ROM_POWER_DOWN_W<MEM_POWER_DOWN_SPEC> {
         ROM_POWER_DOWN_W::new(self, 0)
     }
     #[doc = "Bits 3:13 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_power_down(&mut self) -> SRAM_POWER_DOWN_W<MEM_POWER_DOWN_SPEC> {
         SRAM_POWER_DOWN_W::new(self, 3)
     }
diff --git a/esp32s3/src/apb_ctrl/mem_power_up.rs b/esp32s3/src/apb_ctrl/mem_power_up.rs
index 696ebc48c6..fe2df0bc5f 100644
--- a/esp32s3/src/apb_ctrl/mem_power_up.rs
+++ b/esp32s3/src/apb_ctrl/mem_power_up.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn rom_power_up(&mut self) -> ROM_POWER_UP_W<MEM_POWER_UP_SPEC> {
         ROM_POWER_UP_W::new(self, 0)
     }
     #[doc = "Bits 3:13 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_power_up(&mut self) -> SRAM_POWER_UP_W<MEM_POWER_UP_SPEC> {
         SRAM_POWER_UP_W::new(self, 3)
     }
diff --git a/esp32s3/src/apb_ctrl/redcy_sig0.rs b/esp32s3/src/apb_ctrl/redcy_sig0.rs
index 4a9277bbe5..a2771f998a 100644
--- a/esp32s3/src/apb_ctrl/redcy_sig0.rs
+++ b/esp32s3/src/apb_ctrl/redcy_sig0.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:30 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn redcy_sig0(&mut self) -> REDCY_SIG0_W<REDCY_SIG0_SPEC> {
         REDCY_SIG0_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/redcy_sig1.rs b/esp32s3/src/apb_ctrl/redcy_sig1.rs
index 546c91acc8..f91104bcca 100644
--- a/esp32s3/src/apb_ctrl/redcy_sig1.rs
+++ b/esp32s3/src/apb_ctrl/redcy_sig1.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:30 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn redcy_sig1(&mut self) -> REDCY_SIG1_W<REDCY_SIG1_SPEC> {
         REDCY_SIG1_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl.rs b/esp32s3/src/apb_ctrl/retention_ctrl.rs
index 8e02f7e330..c44f15a563 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_cpu_link_addr(&mut self) -> RETENTION_CPU_LINK_ADDR_W<RETENTION_CTRL_SPEC> {
         RETENTION_CPU_LINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 27 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn nobypass_cpu_iso_rst(&mut self) -> NOBYPASS_CPU_ISO_RST_W<RETENTION_CTRL_SPEC> {
         NOBYPASS_CPU_ISO_RST_W::new(self, 27)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl1.rs b/esp32s3/src/apb_ctrl/retention_ctrl1.rs
index e6103ad1bd..35fe5973aa 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl1.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_tag_link_addr(&mut self) -> RETENTION_TAG_LINK_ADDR_W<RETENTION_CTRL1_SPEC> {
         RETENTION_TAG_LINK_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl2.rs b/esp32s3/src/apb_ctrl/retention_ctrl2.rs
index 64a9141f2b..bed975b882 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl2.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl2.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 4:11 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_icache_size(&mut self) -> RET_ICACHE_SIZE_W<RETENTION_CTRL2_SPEC> {
         RET_ICACHE_SIZE_W::new(self, 4)
     }
     #[doc = "Bits 13:20 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_icache_vld_size(&mut self) -> RET_ICACHE_VLD_SIZE_W<RETENTION_CTRL2_SPEC> {
         RET_ICACHE_VLD_SIZE_W::new(self, 13)
     }
     #[doc = "Bits 22:29 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_icache_start_point(&mut self) -> RET_ICACHE_START_POINT_W<RETENTION_CTRL2_SPEC> {
         RET_ICACHE_START_POINT_W::new(self, 22)
     }
     #[doc = "Bit 31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_icache_enable(&mut self) -> RET_ICACHE_ENABLE_W<RETENTION_CTRL2_SPEC> {
         RET_ICACHE_ENABLE_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl3.rs b/esp32s3/src/apb_ctrl/retention_ctrl3.rs
index beb483596f..2f38972ccc 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl3.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 4:12 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_dcache_size(&mut self) -> RET_DCACHE_SIZE_W<RETENTION_CTRL3_SPEC> {
         RET_DCACHE_SIZE_W::new(self, 4)
     }
     #[doc = "Bits 13:21 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_dcache_vld_size(&mut self) -> RET_DCACHE_VLD_SIZE_W<RETENTION_CTRL3_SPEC> {
         RET_DCACHE_VLD_SIZE_W::new(self, 13)
     }
     #[doc = "Bits 22:30 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_dcache_start_point(&mut self) -> RET_DCACHE_START_POINT_W<RETENTION_CTRL3_SPEC> {
         RET_DCACHE_START_POINT_W::new(self, 22)
     }
     #[doc = "Bit 31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ret_dcache_enable(&mut self) -> RET_DCACHE_ENABLE_W<RETENTION_CTRL3_SPEC> {
         RET_DCACHE_ENABLE_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl4.rs b/esp32s3/src/apb_ctrl/retention_ctrl4.rs
index e0794c0b55..1fe2a259b1 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl4.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_inv_cfg(&mut self) -> RETENTION_INV_CFG_W<RETENTION_CTRL4_SPEC> {
         RETENTION_INV_CFG_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl5.rs b/esp32s3/src/apb_ctrl/retention_ctrl5.rs
index 3824f822f8..ff4c00937b 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl5.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_disable(&mut self) -> RETENTION_DISABLE_W<RETENTION_CTRL5_SPEC> {
         RETENTION_DISABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sdio_ctrl.rs b/esp32s3/src/apb_ctrl/sdio_ctrl.rs
index cfce8aea18..e32740d657 100644
--- a/esp32s3/src/apb_ctrl/sdio_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/sdio_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_win_access_en(&mut self) -> SDIO_WIN_ACCESS_EN_W<SDIO_CTRL_SPEC> {
         SDIO_WIN_ACCESS_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs b/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
index 9f3e40984e..debd4a8efc 100644
--- a/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 18:19 - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_page_size(&mut self) -> FLASH_PAGE_SIZE_W<SPI_MEM_ECC_CTRL_SPEC> {
         FLASH_PAGE_SIZE_W::new(self, 18)
     }
     #[doc = "Bits 20:21 - Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_page_size(&mut self) -> SRAM_PAGE_SIZE_W<SPI_MEM_ECC_CTRL_SPEC> {
         SRAM_PAGE_SIZE_W::new(self, 20)
     }
diff --git a/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs b/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
index ae8c8b9e2d..d91ef5ac69 100644
--- a/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_mem_reject_clr(&mut self) -> SPI_MEM_REJECT_CLR_W<SPI_MEM_PMS_CTRL_SPEC> {
         SPI_MEM_REJECT_CLR_W::new(self, 1)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_addr.rs b/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
index 1f723d5cfc..366bee17a3 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE0_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_attr.rs b/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
index ecefa02fd2..8f850d1d9d 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace0_attr(&mut self) -> SRAM_ACE0_ATTR_W<SRAM_ACE0_ATTR_SPEC> {
         SRAM_ACE0_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_size.rs b/esp32s3/src/apb_ctrl/sram_ace0_size.rs
index 1d754be092..a61b3afd20 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace0_size(&mut self) -> SRAM_ACE0_SIZE_W<SRAM_ACE0_SIZE_SPEC> {
         SRAM_ACE0_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_addr.rs b/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
index 9b99139383..d5b26171ce 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE1_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_attr.rs b/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
index 74c3ceb7c1..b75ec4806f 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace1_attr(&mut self) -> SRAM_ACE1_ATTR_W<SRAM_ACE1_ATTR_SPEC> {
         SRAM_ACE1_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_size.rs b/esp32s3/src/apb_ctrl/sram_ace1_size.rs
index c2515c870c..646adb977d 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace1_size(&mut self) -> SRAM_ACE1_SIZE_W<SRAM_ACE1_SIZE_SPEC> {
         SRAM_ACE1_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_addr.rs b/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
index 171fe8058d..56f7fed5b6 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE2_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_attr.rs b/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
index be3012015c..1157a3bb9c 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace2_attr(&mut self) -> SRAM_ACE2_ATTR_W<SRAM_ACE2_ATTR_SPEC> {
         SRAM_ACE2_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_size.rs b/esp32s3/src/apb_ctrl/sram_ace2_size.rs
index d5f30f6985..a7daec90ba 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace2_size(&mut self) -> SRAM_ACE2_SIZE_W<SRAM_ACE2_SIZE_SPEC> {
         SRAM_ACE2_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_addr.rs b/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
index ca24fb22c3..6658c742b8 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SRAM_ACE3_ADDR_SPEC> {
         S_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_attr.rs b/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
index e0d30026e5..15bd0427e2 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace3_attr(&mut self) -> SRAM_ACE3_ATTR_W<SRAM_ACE3_ATTR_SPEC> {
         SRAM_ACE3_ATTR_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_size.rs b/esp32s3/src/apb_ctrl/sram_ace3_size.rs
index 918887c392..81109d54d1 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_ace3_size(&mut self) -> SRAM_ACE3_SIZE_W<SRAM_ACE3_SIZE_SPEC> {
         SRAM_ACE3_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/sysclk_conf.rs b/esp32s3/src/apb_ctrl/sysclk_conf.rs
index 1353569b6b..681e74381d 100644
--- a/esp32s3/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32s3/src/apb_ctrl/sysclk_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
         PRE_DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bit 10 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
         CLK_320M_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
         CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
         RST_TICK_CNT_W::new(self, 12)
     }
diff --git a/esp32s3/src/apb_ctrl/tick_conf.rs b/esp32s3/src/apb_ctrl/tick_conf.rs
index 5763e25286..d31c0923cb 100644
--- a/esp32s3/src/apb_ctrl/tick_conf.rs
+++ b/esp32s3/src/apb_ctrl/tick_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<TICK_CONF_SPEC> {
         XTAL_TICK_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<TICK_CONF_SPEC> {
         CK8M_TICK_NUM_W::new(self, 8)
     }
     #[doc = "Bit 16 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_enable(&mut self) -> TICK_ENABLE_W<TICK_CONF_SPEC> {
         TICK_ENABLE_W::new(self, 16)
     }
diff --git a/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs b/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
index 4a51ba2f81..e275cbc9e4 100644
--- a/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
+++ b/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg(&mut self) -> WIFI_BB_CFG_W<WIFI_BB_CFG_SPEC> {
         WIFI_BB_CFG_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs b/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
index e34c25e775..50227c637c 100644
--- a/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
+++ b/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_bb_cfg_2(&mut self) -> WIFI_BB_CFG_2_W<WIFI_BB_CFG_2_SPEC> {
         WIFI_BB_CFG_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/wifi_clk_en.rs b/esp32s3/src/apb_ctrl/wifi_clk_en.rs
index 1e2e078012..3ca0b94450 100644
--- a/esp32s3/src/apb_ctrl/wifi_clk_en.rs
+++ b/esp32s3/src/apb_ctrl/wifi_clk_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<WIFI_CLK_EN_SPEC> {
         WIFI_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_ctrl/wifi_rst_en.rs b/esp32s3/src/apb_ctrl/wifi_rst_en.rs
index 6963ed6c6c..df87c5d8b1 100644
--- a/esp32s3/src/apb_ctrl/wifi_rst_en.rs
+++ b/esp32s3/src/apb_ctrl/wifi_rst_en.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_rst(&mut self) -> WIFI_RST_W<WIFI_RST_EN_SPEC> {
         WIFI_RST_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/arb_ctrl.rs b/esp32s3/src/apb_saradc/arb_ctrl.rs
index 647deb1e15..e771eab0a6 100644
--- a/esp32s3/src/apb_saradc/arb_ctrl.rs
+++ b/esp32s3/src/apb_saradc/arb_ctrl.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_force(&mut self) -> APB_FORCE_W<ARB_CTRL_SPEC> {
         APB_FORCE_W::new(self, 2)
     }
     #[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_force(&mut self) -> RTC_FORCE_W<ARB_CTRL_SPEC> {
         RTC_FORCE_W::new(self, 3)
     }
     #[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force(&mut self) -> WIFI_FORCE_W<ARB_CTRL_SPEC> {
         WIFI_FORCE_W::new(self, 4)
     }
     #[doc = "Bit 5 - adc2 arbiter force grant"]
     #[inline(always)]
-    #[must_use]
     pub fn grant_force(&mut self) -> GRANT_FORCE_W<ARB_CTRL_SPEC> {
         GRANT_FORCE_W::new(self, 5)
     }
     #[doc = "Bits 6:7 - Set adc2 arbiterapb priority"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_priority(&mut self) -> APB_PRIORITY_W<ARB_CTRL_SPEC> {
         APB_PRIORITY_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_priority(&mut self) -> RTC_PRIORITY_W<ARB_CTRL_SPEC> {
         RTC_PRIORITY_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_priority(&mut self) -> WIFI_PRIORITY_W<ARB_CTRL_SPEC> {
         WIFI_PRIORITY_W::new(self, 10)
     }
     #[doc = "Bit 12 - adc2 arbiter uses fixed priority"]
     #[inline(always)]
-    #[must_use]
     pub fn fix_priority(&mut self) -> FIX_PRIORITY_W<ARB_CTRL_SPEC> {
         FIX_PRIORITY_W::new(self, 12)
     }
diff --git a/esp32s3/src/apb_saradc/clkm_conf.rs b/esp32s3/src/apb_saradc/clkm_conf.rs
index b1c46dee71..ccbd9a656e 100644
--- a/esp32s3/src/apb_saradc/clkm_conf.rs
+++ b/esp32s3/src/apb_saradc/clkm_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Integral clock divider value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
         CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
         CLKM_DIV_B_W::new(self, 8)
     }
     #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
     #[inline(always)]
-    #[must_use]
     pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
         CLKM_DIV_A_W::new(self, 14)
     }
     #[doc = "Bit 20 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
         CLK_EN_W::new(self, 20)
     }
     #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
         CLK_SEL_W::new(self, 21)
     }
diff --git a/esp32s3/src/apb_saradc/ctrl.rs b/esp32s3/src/apb_saradc/ctrl.rs
index 65d253d14d..215dee1682 100644
--- a/esp32s3/src/apb_saradc/ctrl.rs
+++ b/esp32s3/src/apb_saradc/ctrl.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - enable start saradc by sw"]
     #[inline(always)]
-    #[must_use]
     pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
         START_FORCE_W::new(self, 0)
     }
     #[doc = "Bit 1 - start saradc by sw"]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CTRL_SPEC> {
         START_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
     #[inline(always)]
-    #[must_use]
     pub fn work_mode(&mut self) -> WORK_MODE_W<CTRL_SPEC> {
         WORK_MODE_W::new(self, 3)
     }
     #[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sel(&mut self) -> SAR_SEL_W<CTRL_SPEC> {
         SAR_SEL_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
         SAR_CLK_GATED_W::new(self, 6)
     }
     #[doc = "Bits 7:14 - SAR clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
         SAR_CLK_DIV_W::new(self, 7)
     }
     #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<CTRL_SPEC> {
         SAR1_PATT_LEN_W::new(self, 15)
     }
     #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<CTRL_SPEC> {
         SAR2_PATT_LEN_W::new(self, 19)
     }
     #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<CTRL_SPEC> {
         SAR1_PATT_P_CLEAR_W::new(self, 23)
     }
     #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<CTRL_SPEC> {
         SAR2_PATT_P_CLEAR_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<CTRL_SPEC> {
         DATA_SAR_SEL_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<CTRL_SPEC> {
         DATA_TO_I2S_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - force option to xpd sar blocks"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
         XPD_SAR_FORCE_W::new(self, 27)
     }
     #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
     #[inline(always)]
-    #[must_use]
     pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
         WAIT_ARB_CYCLE_W::new(self, 30)
     }
diff --git a/esp32s3/src/apb_saradc/ctrl2.rs b/esp32s3/src/apb_saradc/ctrl2.rs
index 9e59d3755e..199c709e9f 100644
--- a/esp32s3/src/apb_saradc/ctrl2.rs
+++ b/esp32s3/src/apb_saradc/ctrl2.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - enable apb saradc limit the sample num"]
     #[inline(always)]
-    #[must_use]
     pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
         MEAS_NUM_LIMIT_W::new(self, 0)
     }
     #[doc = "Bits 1:8 - max conversion number"]
     #[inline(always)]
-    #[must_use]
     pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
         MAX_MEAS_NUM_W::new(self, 1)
     }
     #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
         SAR1_INV_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
         SAR2_INV_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
         TIMER_SEL_W::new(self, 11)
     }
     #[doc = "Bits 12:23 - to set saradc timer target"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
         TIMER_TARGET_W::new(self, 12)
     }
     #[doc = "Bit 24 - to enable saradc timer trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
         TIMER_EN_W::new(self, 24)
     }
diff --git a/esp32s3/src/apb_saradc/ctrl_date.rs b/esp32s3/src/apb_saradc/ctrl_date.rs
index 2e1255bea7..e394c7231a 100644
--- a/esp32s3/src/apb_saradc/ctrl_date.rs
+++ b/esp32s3/src/apb_saradc/ctrl_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - version"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<CTRL_DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/dma_conf.rs b/esp32s3/src/apb_saradc/dma_conf.rs
index 8558a42cbd..33b2e72f27 100644
--- a/esp32s3/src/apb_saradc/dma_conf.rs
+++ b/esp32s3/src/apb_saradc/dma_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
-    #[must_use]
     pub fn adc_eof_num(&mut self) -> ADC_EOF_NUM_W<DMA_CONF_SPEC> {
         ADC_EOF_NUM_W::new(self, 0)
     }
     #[doc = "Bit 30 - reset_apb_adc_state"]
     #[inline(always)]
-    #[must_use]
     pub fn adc_reset_fsm(&mut self) -> ADC_RESET_FSM_W<DMA_CONF_SPEC> {
         ADC_RESET_FSM_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable apb_adc use spi_dma"]
     #[inline(always)]
-    #[must_use]
     pub fn adc_trans(&mut self) -> ADC_TRANS_W<DMA_CONF_SPEC> {
         ADC_TRANS_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_saradc/filter_ctrl0.rs b/esp32s3/src/apb_saradc/filter_ctrl0.rs
index e64c394cfc..18e7734a58 100644
--- a/esp32s3/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32s3/src/apb_saradc/filter_ctrl0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 14:18 - configure the filter1 channel"]
     #[inline(always)]
-    #[must_use]
     pub fn filter_channel1(&mut self) -> FILTER_CHANNEL1_W<FILTER_CTRL0_SPEC> {
         FILTER_CHANNEL1_W::new(self, 14)
     }
     #[doc = "Bits 19:23 - configure the filter0 channel"]
     #[inline(always)]
-    #[must_use]
     pub fn filter_channel0(&mut self) -> FILTER_CHANNEL0_W<FILTER_CTRL0_SPEC> {
         FILTER_CHANNEL0_W::new(self, 19)
     }
     #[doc = "Bit 31 - enable apb_adc1_filter"]
     #[inline(always)]
-    #[must_use]
     pub fn filter_reset(&mut self) -> FILTER_RESET_W<FILTER_CTRL0_SPEC> {
         FILTER_RESET_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_saradc/filter_ctrl1.rs b/esp32s3/src/apb_saradc/filter_ctrl1.rs
index 9cf29a3d1e..690f608204 100644
--- a/esp32s3/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32s3/src/apb_saradc/filter_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 26:28 - apb saradc factor1"]
     #[inline(always)]
-    #[must_use]
     pub fn filter_factor1(&mut self) -> FILTER_FACTOR1_W<FILTER_CTRL1_SPEC> {
         FILTER_FACTOR1_W::new(self, 26)
     }
     #[doc = "Bits 29:31 - apb saradc factor0"]
     #[inline(always)]
-    #[must_use]
     pub fn filter_factor0(&mut self) -> FILTER_FACTOR0_W<FILTER_CTRL1_SPEC> {
         FILTER_FACTOR0_W::new(self, 29)
     }
diff --git a/esp32s3/src/apb_saradc/fsm_wait.rs b/esp32s3/src/apb_saradc/fsm_wait.rs
index 114ea9433e..531dc62d6d 100644
--- a/esp32s3/src/apb_saradc/fsm_wait.rs
+++ b/esp32s3/src/apb_saradc/fsm_wait.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_wait(&mut self) -> XPD_WAIT_W<FSM_WAIT_SPEC> {
         XPD_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
     #[inline(always)]
-    #[must_use]
     pub fn rstb_wait(&mut self) -> RSTB_WAIT_W<FSM_WAIT_SPEC> {
         RSTB_WAIT_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
     #[inline(always)]
-    #[must_use]
     pub fn standby_wait(&mut self) -> STANDBY_WAIT_W<FSM_WAIT_SPEC> {
         STANDBY_WAIT_W::new(self, 16)
     }
diff --git a/esp32s3/src/apb_saradc/int_clr.rs b/esp32s3/src/apb_saradc/int_clr.rs
index 2847970218..fb0b605a8a 100644
--- a/esp32s3/src/apb_saradc/int_clr.rs
+++ b/esp32s3/src/apb_saradc/int_clr.rs
@@ -21,37 +21,31 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 26 - interrupt of thres1 low"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_CLR_SPEC> {
         THRES1_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27 - interrupt of thres0 low"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_CLR_SPEC> {
         THRES0_LOW_W::new(self, 27)
     }
     #[doc = "Bit 28 - interrupt of thres1 high"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_CLR_SPEC> {
         THRES1_HIGH_W::new(self, 28)
     }
     #[doc = "Bit 29 - interrupt of thres0 high"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_CLR_SPEC> {
         THRES0_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30 - interrupt of sar2 done"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
         ADC2_DONE_W::new(self, 30)
     }
     #[doc = "Bit 31 - interrupt of sar1 done"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
         ADC1_DONE_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_saradc/int_ena.rs b/esp32s3/src/apb_saradc/int_ena.rs
index 363912d5ac..c717e04201 100644
--- a/esp32s3/src/apb_saradc/int_ena.rs
+++ b/esp32s3/src/apb_saradc/int_ena.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 26 - interrupt of thres1 low"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_ENA_SPEC> {
         THRES1_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27 - interrupt of thres0 low"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_ENA_SPEC> {
         THRES0_LOW_W::new(self, 27)
     }
     #[doc = "Bit 28 - interrupt of thres1 high"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_ENA_SPEC> {
         THRES1_HIGH_W::new(self, 28)
     }
     #[doc = "Bit 29 - interrupt of thres0 high"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_ENA_SPEC> {
         THRES0_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30 - interrupt of sar2 done"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_ENA_SPEC> {
         ADC2_DONE_W::new(self, 30)
     }
     #[doc = "Bit 31 - interrupt of sar1 done"]
     #[inline(always)]
-    #[must_use]
     pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_ENA_SPEC> {
         ADC1_DONE_W::new(self, 31)
     }
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab1.rs b/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
index 0395c76804..e36b095f1a 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab1(&mut self) -> SAR1_PATT_TAB1_W<SAR1_PATT_TAB1_SPEC> {
         SAR1_PATT_TAB1_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab2.rs b/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
index cf0e133c16..52d985c81f 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab2(&mut self) -> SAR1_PATT_TAB2_W<SAR1_PATT_TAB2_SPEC> {
         SAR1_PATT_TAB2_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab3.rs b/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
index 7e8bc0bf9e..2fa6a23dde 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab3(&mut self) -> SAR1_PATT_TAB3_W<SAR1_PATT_TAB3_SPEC> {
         SAR1_PATT_TAB3_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab4.rs b/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
index 32b50abdf9..af50627cdb 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_patt_tab4(&mut self) -> SAR1_PATT_TAB4_W<SAR1_PATT_TAB4_SPEC> {
         SAR1_PATT_TAB4_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab1.rs b/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
index df7f3295d4..386a6d8238 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab1(&mut self) -> SAR2_PATT_TAB1_W<SAR2_PATT_TAB1_SPEC> {
         SAR2_PATT_TAB1_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab2.rs b/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
index f2f3b2b684..1dc64f3c59 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab2(&mut self) -> SAR2_PATT_TAB2_W<SAR2_PATT_TAB2_SPEC> {
         SAR2_PATT_TAB2_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab3.rs b/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
index 2099a55aab..a6499b8f9a 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab3(&mut self) -> SAR2_PATT_TAB3_W<SAR2_PATT_TAB3_SPEC> {
         SAR2_PATT_TAB3_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab4.rs b/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
index b693e81771..4d055f4b73 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_patt_tab4(&mut self) -> SAR2_PATT_TAB4_W<SAR2_PATT_TAB4_SPEC> {
         SAR2_PATT_TAB4_W::new(self, 0)
     }
diff --git a/esp32s3/src/apb_saradc/thres0_ctrl.rs b/esp32s3/src/apb_saradc/thres0_ctrl.rs
index a3937a9fff..adb2e81c8d 100644
--- a/esp32s3/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres0_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_channel(&mut self) -> THRES0_CHANNEL_W<THRES0_CTRL_SPEC> {
         THRES0_CHANNEL_W::new(self, 0)
     }
     #[doc = "Bits 5:17 - thres0 monitor high thres"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_high(&mut self) -> THRES0_HIGH_W<THRES0_CTRL_SPEC> {
         THRES0_HIGH_W::new(self, 5)
     }
     #[doc = "Bits 18:30 - thres0 monitor low thres"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_low(&mut self) -> THRES0_LOW_W<THRES0_CTRL_SPEC> {
         THRES0_LOW_W::new(self, 18)
     }
diff --git a/esp32s3/src/apb_saradc/thres1_ctrl.rs b/esp32s3/src/apb_saradc/thres1_ctrl.rs
index 498c1be17b..b19699ad79 100644
--- a/esp32s3/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres1_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_channel(&mut self) -> THRES1_CHANNEL_W<THRES1_CTRL_SPEC> {
         THRES1_CHANNEL_W::new(self, 0)
     }
     #[doc = "Bits 5:17 - thres1 monitor high thres"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_high(&mut self) -> THRES1_HIGH_W<THRES1_CTRL_SPEC> {
         THRES1_HIGH_W::new(self, 5)
     }
     #[doc = "Bits 18:30 - thres1 monitor low thres"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_low(&mut self) -> THRES1_LOW_W<THRES1_CTRL_SPEC> {
         THRES1_LOW_W::new(self, 18)
     }
diff --git a/esp32s3/src/apb_saradc/thres_ctrl.rs b/esp32s3/src/apb_saradc/thres_ctrl.rs
index f5f311164e..c64b0cc6ff 100644
--- a/esp32s3/src/apb_saradc/thres_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres_ctrl.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 27 - enable thres0 to monitor all channel"]
     #[inline(always)]
-    #[must_use]
     pub fn thres_all_en(&mut self) -> THRES_ALL_EN_W<THRES_CTRL_SPEC> {
         THRES_ALL_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn thres3_en(&mut self) -> THRES3_EN_W<THRES_CTRL_SPEC> {
         THRES3_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn thres2_en(&mut self) -> THRES2_EN_W<THRES_CTRL_SPEC> {
         THRES2_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable thres1"]
     #[inline(always)]
-    #[must_use]
     pub fn thres1_en(&mut self) -> THRES1_EN_W<THRES_CTRL_SPEC> {
         THRES1_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable thres0"]
     #[inline(always)]
-    #[must_use]
     pub fn thres0_en(&mut self) -> THRES0_EN_W<THRES_CTRL_SPEC> {
         THRES0_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
index 3ab8a734bd..16dd89b99c 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_max(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_MAX_W<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
index 759d767566..c9de513bea 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_min(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_MIN_W<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
index 18d6fec0d8..1cd2b1757b 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_max(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_MAX_W<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
index 30e80919a6..a7a7e14eed 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_min(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_MIN_W<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs b/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
index 5bcdfb25f7..61602cca8c 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_max(&mut self) -> CORE_0_AREA_PIF_0_MAX_W<CORE_0_AREA_PIF_0_MAX_SPEC> {
         CORE_0_AREA_PIF_0_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs b/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
index f613bb8608..3ecdfc7ac3 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_min(&mut self) -> CORE_0_AREA_PIF_0_MIN_W<CORE_0_AREA_PIF_0_MIN_SPEC> {
         CORE_0_AREA_PIF_0_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs b/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
index 2da306da5d..16410a8f09 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_max(&mut self) -> CORE_0_AREA_PIF_1_MAX_W<CORE_0_AREA_PIF_1_MAX_SPEC> {
         CORE_0_AREA_PIF_1_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs b/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
index fd5cb131f7..1a8d405597 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_min(&mut self) -> CORE_0_AREA_PIF_1_MIN_W<CORE_0_AREA_PIF_1_MIN_SPEC> {
         CORE_0_AREA_PIF_1_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_intr_clr.rs b/esp32s3/src/assist_debug/core_0_intr_clr.rs
index 6ac791627d..458d9493ed 100644
--- a/esp32s3/src/assist_debug/core_0_intr_clr.rs
+++ b/esp32s3/src/assist_debug/core_0_intr_clr.rs
@@ -152,7 +152,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_rd_clr(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
@@ -160,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_wr_clr(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
@@ -168,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_rd_clr(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
@@ -176,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_wr_clr(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
@@ -184,43 +180,36 @@ impl W {
     }
     #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_rd_clr(&mut self) -> CORE_0_AREA_PIF_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_AREA_PIF_0_RD_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_wr_clr(&mut self) -> CORE_0_AREA_PIF_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_AREA_PIF_0_WR_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_rd_clr(&mut self) -> CORE_0_AREA_PIF_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_AREA_PIF_1_RD_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_wr_clr(&mut self) -> CORE_0_AREA_PIF_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_AREA_PIF_1_WR_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_min_clr(&mut self) -> CORE_0_SP_SPILL_MIN_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_SP_SPILL_MIN_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_max_clr(&mut self) -> CORE_0_SP_SPILL_MAX_CLR_W<CORE_0_INTR_CLR_SPEC> {
         CORE_0_SP_SPILL_MAX_CLR_W::new(self, 9)
     }
     #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_exception_monitor_clr(
         &mut self,
     ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
@@ -228,7 +217,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_exception_monitor_clr(
         &mut self,
     ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_intr_ena.rs b/esp32s3/src/assist_debug/core_0_intr_ena.rs
index e94b4e81c1..853373c11c 100644
--- a/esp32s3/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32s3/src/assist_debug/core_0_intr_ena.rs
@@ -174,7 +174,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_rd_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -182,7 +181,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_wr_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -190,7 +188,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_rd_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -198,7 +195,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_wr_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -206,7 +202,6 @@ impl W {
     }
     #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_rd_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_0_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -214,7 +209,6 @@ impl W {
     }
     #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_wr_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_0_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -222,7 +216,6 @@ impl W {
     }
     #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_rd_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_1_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -230,7 +223,6 @@ impl W {
     }
     #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_wr_intr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_1_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -238,7 +230,6 @@ impl W {
     }
     #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_min_intr_ena(
         &mut self,
     ) -> CORE_0_SP_SPILL_MIN_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -246,7 +237,6 @@ impl W {
     }
     #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_max_intr_ena(
         &mut self,
     ) -> CORE_0_SP_SPILL_MAX_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -254,7 +244,6 @@ impl W {
     }
     #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_exception_monitor_intr_ena(
         &mut self,
     ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
@@ -262,7 +251,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_exception_monitor_intr_ena(
         &mut self,
     ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_montr_ena.rs b/esp32s3/src/assist_debug/core_0_montr_ena.rs
index c586fb4691..a4c4378997 100644
--- a/esp32s3/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32s3/src/assist_debug/core_0_montr_ena.rs
@@ -152,7 +152,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_rd_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -160,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_0_wr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -168,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_rd_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -176,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_dram0_1_wr_ena(
         &mut self,
     ) -> CORE_0_AREA_DRAM0_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -184,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_rd_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -192,7 +187,6 @@ impl W {
     }
     #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_0_wr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -200,7 +194,6 @@ impl W {
     }
     #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_rd_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -208,7 +201,6 @@ impl W {
     }
     #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_area_pif_1_wr_ena(
         &mut self,
     ) -> CORE_0_AREA_PIF_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -216,19 +208,16 @@ impl W {
     }
     #[doc = "Bit 8 - Core0 stackpoint overflow monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W<CORE_0_MONTR_ENA_SPEC> {
         CORE_0_SP_SPILL_MIN_ENA_W::new(self, 8)
     }
     #[doc = "Bit 9 - Core0 stackpoint underflow monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W<CORE_0_MONTR_ENA_SPEC> {
         CORE_0_SP_SPILL_MAX_ENA_W::new(self, 9)
     }
     #[doc = "Bit 10 - IBUS busy monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_exception_monitor_ena(
         &mut self,
     ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
@@ -236,7 +225,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor enbale"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_exception_monitor_ena(
         &mut self,
     ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
index 5e71fc8bfa..3fd43f8973 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_rcd_pdebugenable(
         &mut self,
     ) -> CORE_0_RCD_PDEBUGENABLE_W<CORE_0_RCD_PDEBUGENABLE_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_recording.rs b/esp32s3/src/assist_debug/core_0_rcd_recording.rs
index b91fdd4480..d7e59b21cf 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_recording.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_recording.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_rcd_recording(&mut self) -> CORE_0_RCD_RECORDING_W<CORE_0_RCD_RECORDING_SPEC> {
         CORE_0_RCD_RECORDING_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_sp_max.rs b/esp32s3/src/assist_debug/core_0_sp_max.rs
index 882510bd45..0cb5a47ee1 100644
--- a/esp32s3/src/assist_debug/core_0_sp_max.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stack max value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_max(&mut self) -> CORE_0_SP_MAX_W<CORE_0_SP_MAX_SPEC> {
         CORE_0_SP_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_sp_min.rs b/esp32s3/src/assist_debug/core_0_sp_min.rs
index 7aaf63da61..ff421fbf13 100644
--- a/esp32s3/src/assist_debug/core_0_sp_min.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stack min value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_min(&mut self) -> CORE_0_SP_MIN_W<CORE_0_SP_MIN_SPEC> {
         CORE_0_SP_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_0_sp_unstable.rs b/esp32s3/src/assist_debug/core_0_sp_unstable.rs
index 44db9348a4..a6f063a310 100644
--- a/esp32s3/src/assist_debug/core_0_sp_unstable.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_unstable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_sp_unstable(&mut self) -> CORE_0_SP_UNSTABLE_W<CORE_0_SP_UNSTABLE_SPEC> {
         CORE_0_SP_UNSTABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs b/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
index 28609c85ee..96ed4d1311 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_max(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_MAX_W<CORE_1_AREA_DRAM0_0_MAX_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs b/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
index b675ad5a36..1ef66cbf62 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_min(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_MIN_W<CORE_1_AREA_DRAM0_0_MIN_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs b/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
index 24a1f92a97..dd40c934ee 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_max(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_MAX_W<CORE_1_AREA_DRAM0_1_MAX_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs b/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
index 546b178cad..accdb9a2f3 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_min(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_MIN_W<CORE_1_AREA_DRAM0_1_MIN_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs b/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
index 7fb43e8db1..94ecaca4c2 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_max(&mut self) -> CORE_1_AREA_PIF_0_MAX_W<CORE_1_AREA_PIF_0_MAX_SPEC> {
         CORE_1_AREA_PIF_0_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs b/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
index c34d9af137..0d494f2610 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_min(&mut self) -> CORE_1_AREA_PIF_0_MIN_W<CORE_1_AREA_PIF_0_MIN_SPEC> {
         CORE_1_AREA_PIF_0_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs b/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
index 753799daa1..ea6d3f439a 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_max(&mut self) -> CORE_1_AREA_PIF_1_MAX_W<CORE_1_AREA_PIF_1_MAX_SPEC> {
         CORE_1_AREA_PIF_1_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs b/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
index 987ea9a032..8ed27abd98 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_min(&mut self) -> CORE_1_AREA_PIF_1_MIN_W<CORE_1_AREA_PIF_1_MIN_SPEC> {
         CORE_1_AREA_PIF_1_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_intr_clr.rs b/esp32s3/src/assist_debug/core_1_intr_clr.rs
index 8941f86f1d..4fa03c481b 100644
--- a/esp32s3/src/assist_debug/core_1_intr_clr.rs
+++ b/esp32s3/src/assist_debug/core_1_intr_clr.rs
@@ -152,7 +152,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_rd_clr(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
@@ -160,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_wr_clr(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
@@ -168,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_rd_clr(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
@@ -176,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_wr_clr(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
@@ -184,43 +180,36 @@ impl W {
     }
     #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_rd_clr(&mut self) -> CORE_1_AREA_PIF_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_AREA_PIF_0_RD_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_wr_clr(&mut self) -> CORE_1_AREA_PIF_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_AREA_PIF_0_WR_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_rd_clr(&mut self) -> CORE_1_AREA_PIF_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_AREA_PIF_1_RD_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_wr_clr(&mut self) -> CORE_1_AREA_PIF_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_AREA_PIF_1_WR_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_min_clr(&mut self) -> CORE_1_SP_SPILL_MIN_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_SP_SPILL_MIN_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_max_clr(&mut self) -> CORE_1_SP_SPILL_MAX_CLR_W<CORE_1_INTR_CLR_SPEC> {
         CORE_1_SP_SPILL_MAX_CLR_W::new(self, 9)
     }
     #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_exception_monitor_clr(
         &mut self,
     ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
@@ -228,7 +217,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_exception_monitor_clr(
         &mut self,
     ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_intr_ena.rs b/esp32s3/src/assist_debug/core_1_intr_ena.rs
index 03208a3169..2f164e56ca 100644
--- a/esp32s3/src/assist_debug/core_1_intr_ena.rs
+++ b/esp32s3/src/assist_debug/core_1_intr_ena.rs
@@ -174,7 +174,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_rd_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -182,7 +181,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_wr_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -190,7 +188,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_rd_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -198,7 +195,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_wr_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -206,7 +202,6 @@ impl W {
     }
     #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_rd_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_0_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -214,7 +209,6 @@ impl W {
     }
     #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_wr_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_0_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -222,7 +216,6 @@ impl W {
     }
     #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_rd_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_1_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -230,7 +223,6 @@ impl W {
     }
     #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_wr_intr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_1_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -238,7 +230,6 @@ impl W {
     }
     #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_min_intr_ena(
         &mut self,
     ) -> CORE_1_SP_SPILL_MIN_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -246,7 +237,6 @@ impl W {
     }
     #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_max_intr_ena(
         &mut self,
     ) -> CORE_1_SP_SPILL_MAX_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -254,7 +244,6 @@ impl W {
     }
     #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_exception_monitor_intr_ena(
         &mut self,
     ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
@@ -262,7 +251,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_exception_monitor_intr_ena(
         &mut self,
     ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_montr_ena.rs b/esp32s3/src/assist_debug/core_1_montr_ena.rs
index 4167808781..b171e581c3 100644
--- a/esp32s3/src/assist_debug/core_1_montr_ena.rs
+++ b/esp32s3/src/assist_debug/core_1_montr_ena.rs
@@ -152,7 +152,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_rd_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -160,7 +159,6 @@ impl W {
     }
     #[doc = "Bit 1 - Core1 dram0 area0 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_0_wr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_0_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -168,7 +166,6 @@ impl W {
     }
     #[doc = "Bit 2 - Core1 dram0 area1 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_rd_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -176,7 +173,6 @@ impl W {
     }
     #[doc = "Bit 3 - Core1 dram0 area1 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_dram0_1_wr_ena(
         &mut self,
     ) -> CORE_1_AREA_DRAM0_1_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -184,7 +180,6 @@ impl W {
     }
     #[doc = "Bit 4 - Core1 PIF area0 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_rd_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_0_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -192,7 +187,6 @@ impl W {
     }
     #[doc = "Bit 5 - Core1 PIF area0 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_0_wr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_0_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -200,7 +194,6 @@ impl W {
     }
     #[doc = "Bit 6 - Core1 PIF area1 read monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_rd_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_1_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -208,7 +201,6 @@ impl W {
     }
     #[doc = "Bit 7 - Core1 PIF area1 write monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_area_pif_1_wr_ena(
         &mut self,
     ) -> CORE_1_AREA_PIF_1_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -216,19 +208,16 @@ impl W {
     }
     #[doc = "Bit 8 - Core1 stackpoint overflow monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_min_ena(&mut self) -> CORE_1_SP_SPILL_MIN_ENA_W<CORE_1_MONTR_ENA_SPEC> {
         CORE_1_SP_SPILL_MIN_ENA_W::new(self, 8)
     }
     #[doc = "Bit 9 - Core1 stackpoint underflow monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_spill_max_ena(&mut self) -> CORE_1_SP_SPILL_MAX_ENA_W<CORE_1_MONTR_ENA_SPEC> {
         CORE_1_SP_SPILL_MAX_ENA_W::new(self, 9)
     }
     #[doc = "Bit 10 - IBUS busy monitor enable"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_exception_monitor_ena(
         &mut self,
     ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
@@ -236,7 +225,6 @@ impl W {
     }
     #[doc = "Bit 11 - DBUS busy monitor enbale"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_exception_monitor_ena(
         &mut self,
     ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
index bd4c8af783..9d7c76f337 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_rcd_pdebugenable(
         &mut self,
     ) -> CORE_1_RCD_PDEBUGENABLE_W<CORE_1_RCD_PDEBUGENABLE_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_recording.rs b/esp32s3/src/assist_debug/core_1_rcd_recording.rs
index feff662605..8121073bf9 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_recording.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_recording.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_rcd_recording(&mut self) -> CORE_1_RCD_RECORDING_W<CORE_1_RCD_RECORDING_SPEC> {
         CORE_1_RCD_RECORDING_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_sp_max.rs b/esp32s3/src/assist_debug/core_1_sp_max.rs
index adf62942a0..0db4de0c78 100644
--- a/esp32s3/src/assist_debug/core_1_sp_max.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stack max value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_max(&mut self) -> CORE_1_SP_MAX_W<CORE_1_SP_MAX_SPEC> {
         CORE_1_SP_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_sp_min.rs b/esp32s3/src/assist_debug/core_1_sp_min.rs
index 5f409eceb5..47e3e1b8f7 100644
--- a/esp32s3/src/assist_debug/core_1_sp_min.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stack min value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_min(&mut self) -> CORE_1_SP_MIN_W<CORE_1_SP_MIN_SPEC> {
         CORE_1_SP_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_1_sp_unstable.rs b/esp32s3/src/assist_debug/core_1_sp_unstable.rs
index bdd4130d14..29b6dbe7ca 100644
--- a/esp32s3/src/assist_debug/core_1_sp_unstable.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_unstable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_sp_unstable(&mut self) -> CORE_1_SP_UNSTABLE_W<CORE_1_SP_UNSTABLE_SPEC> {
         CORE_1_SP_UNSTABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 49c90bbcfe..e389d924c2 100644
--- a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - busy monitor window cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_limit_cycle_0(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index 8261c7d7f6..903a876d59 100644
--- a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_limit_cycle_1(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/assist_debug/date.rs b/esp32s3/src/assist_debug/date.rs
index 59663eb5e4..bf12654a29 100644
--- a/esp32s3/src/assist_debug/date.rs
+++ b/esp32s3/src/assist_debug/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_data_0.rs b/esp32s3/src/assist_debug/log_data_0.rs
index 5941e0da20..1ce3be31a7 100644
--- a/esp32s3/src/assist_debug/log_data_0.rs
+++ b/esp32s3/src/assist_debug/log_data_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check data0"]
     #[inline(always)]
-    #[must_use]
     pub fn log_data_0(&mut self) -> LOG_DATA_0_W<LOG_DATA_0_SPEC> {
         LOG_DATA_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_data_1.rs b/esp32s3/src/assist_debug/log_data_1.rs
index 80568933db..2aca66e050 100644
--- a/esp32s3/src/assist_debug/log_data_1.rs
+++ b/esp32s3/src/assist_debug/log_data_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check data1"]
     #[inline(always)]
-    #[must_use]
     pub fn log_data_1(&mut self) -> LOG_DATA_1_W<LOG_DATA_1_SPEC> {
         LOG_DATA_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_data_2.rs b/esp32s3/src/assist_debug/log_data_2.rs
index 086707d971..accb063e59 100644
--- a/esp32s3/src/assist_debug/log_data_2.rs
+++ b/esp32s3/src/assist_debug/log_data_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check data2"]
     #[inline(always)]
-    #[must_use]
     pub fn log_data_2(&mut self) -> LOG_DATA_2_W<LOG_DATA_2_SPEC> {
         LOG_DATA_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_data_3.rs b/esp32s3/src/assist_debug/log_data_3.rs
index e05d29da63..5b83205f23 100644
--- a/esp32s3/src/assist_debug/log_data_3.rs
+++ b/esp32s3/src/assist_debug/log_data_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check data3"]
     #[inline(always)]
-    #[must_use]
     pub fn log_data_3(&mut self) -> LOG_DATA_3_W<LOG_DATA_3_SPEC> {
         LOG_DATA_3_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_data_mask.rs b/esp32s3/src/assist_debug/log_data_mask.rs
index a77e7aa67a..9f17a7ab7f 100644
--- a/esp32s3/src/assist_debug/log_data_mask.rs
+++ b/esp32s3/src/assist_debug/log_data_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - data mask"]
     #[inline(always)]
-    #[must_use]
     pub fn log_data_size(&mut self) -> LOG_DATA_SIZE_W<LOG_DATA_MASK_SPEC> {
         LOG_DATA_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_max.rs b/esp32s3/src/assist_debug/log_max.rs
index 98e56cec63..d141bf5714 100644
--- a/esp32s3/src/assist_debug/log_max.rs
+++ b/esp32s3/src/assist_debug/log_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check region max addr"]
     #[inline(always)]
-    #[must_use]
     pub fn log_max(&mut self) -> LOG_MAX_W<LOG_MAX_SPEC> {
         LOG_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_mem_end.rs b/esp32s3/src/assist_debug/log_mem_end.rs
index b74804229a..9c75e4f74c 100644
--- a/esp32s3/src/assist_debug/log_mem_end.rs
+++ b/esp32s3/src/assist_debug/log_mem_end.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - mem end addr"]
     #[inline(always)]
-    #[must_use]
     pub fn log_mem_end(&mut self) -> LOG_MEM_END_W<LOG_MEM_END_SPEC> {
         LOG_MEM_END_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_mem_full_flag.rs b/esp32s3/src/assist_debug/log_mem_full_flag.rs
index 9cd92dfbd9..a2e2358904 100644
--- a/esp32s3/src/assist_debug/log_mem_full_flag.rs
+++ b/esp32s3/src/assist_debug/log_mem_full_flag.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - when it's 1,show that mem write loop morte than one time."]
     #[inline(always)]
-    #[must_use]
     pub fn log_mem_full_flag(&mut self) -> LOG_MEM_FULL_FLAG_W<LOG_MEM_FULL_FLAG_SPEC> {
         LOG_MEM_FULL_FLAG_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_mem_start.rs b/esp32s3/src/assist_debug/log_mem_start.rs
index 041aa30956..ee56f3a6d7 100644
--- a/esp32s3/src/assist_debug/log_mem_start.rs
+++ b/esp32s3/src/assist_debug/log_mem_start.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - mem start addr"]
     #[inline(always)]
-    #[must_use]
     pub fn log_mem_start(&mut self) -> LOG_MEM_START_W<LOG_MEM_START_SPEC> {
         LOG_MEM_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_min.rs b/esp32s3/src/assist_debug/log_min.rs
index 91e063e529..1e1c9c7bee 100644
--- a/esp32s3/src/assist_debug/log_min.rs
+++ b/esp32s3/src/assist_debug/log_min.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - check region min addr"]
     #[inline(always)]
-    #[must_use]
     pub fn log_min(&mut self) -> LOG_MIN_W<LOG_MIN_SPEC> {
         LOG_MIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/assist_debug/log_setting.rs b/esp32s3/src/assist_debug/log_setting.rs
index d135e9ca05..b47fb6567f 100644
--- a/esp32s3/src/assist_debug/log_setting.rs
+++ b/esp32s3/src/assist_debug/log_setting.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
     #[inline(always)]
-    #[must_use]
     pub fn log_ena(&mut self) -> LOG_ENA_W<LOG_SETTING_SPEC> {
         LOG_ENA_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word"]
     #[inline(always)]
-    #[must_use]
     pub fn log_mode(&mut self) -> LOG_MODE_W<LOG_SETTING_SPEC> {
         LOG_MODE_W::new(self, 3)
     }
     #[doc = "Bit 6 - mem_loop enable,1 means that loop write"]
     #[inline(always)]
-    #[must_use]
     pub fn log_mem_loop_enable(&mut self) -> LOG_MEM_LOOP_ENABLE_W<LOG_SETTING_SPEC> {
         LOG_MEM_LOOP_ENABLE_W::new(self, 6)
     }
diff --git a/esp32s3/src/bb/bbpd_ctrl.rs b/esp32s3/src/bb/bbpd_ctrl.rs
index 968dce20ce..6de8322c9b 100644
--- a/esp32s3/src/bb/bbpd_ctrl.rs
+++ b/esp32s3/src/bb/bbpd_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pd(&mut self) -> DC_EST_FORCE_PD_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn dc_est_force_pu(&mut self) -> DC_EST_FORCE_PU_W<BBPD_CTRL_SPEC> {
         DC_EST_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pd(&mut self) -> FFT_FORCE_PD_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn fft_force_pu(&mut self) -> FFT_FORCE_PU_W<BBPD_CTRL_SPEC> {
         FFT_FORCE_PU_W::new(self, 3)
     }
diff --git a/esp32s3/src/dma.rs b/esp32s3/src/dma.rs
index d9b0e04cb6..f974e6a247 100644
--- a/esp32s3/src/dma.rs
+++ b/esp32s3/src/dma.rs
@@ -51,7 +51,7 @@ impl RegisterBlock {
         #[allow(clippy::no_effect)]
         [(); 5][n];
         unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(972)
                 .add(8 * n)
@@ -63,7 +63,7 @@ impl RegisterBlock {
     #[inline(always)]
     pub fn in_sram_size_ch_iter(&self) -> impl Iterator<Item = &IN_SRAM_SIZE_CH> {
         (0..5).map(move |n| unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(972)
                 .add(8 * n)
@@ -76,7 +76,7 @@ impl RegisterBlock {
         #[allow(clippy::no_effect)]
         [(); 5][n];
         unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(976)
                 .add(8 * n)
@@ -88,7 +88,7 @@ impl RegisterBlock {
     #[inline(always)]
     pub fn out_sram_size_ch_iter(&self) -> impl Iterator<Item = &OUT_SRAM_SIZE_CH> {
         (0..5).map(move |n| unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(976)
                 .add(8 * n)
diff --git a/esp32s3/src/dma/ahb_test.rs b/esp32s3/src/dma/ahb_test.rs
index aed39b9b4b..267c4d1c67 100644
--- a/esp32s3/src/dma/ahb_test.rs
+++ b/esp32s3/src/dma/ahb_test.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
         AHB_TESTMODE_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
         AHB_TESTADDR_W::new(self, 4)
     }
diff --git a/esp32s3/src/dma/ch/in_conf0.rs b/esp32s3/src/dma/ch/in_conf0.rs
index 5c5bfac39e..a73282b5fa 100644
--- a/esp32s3/src/dma/ch/in_conf0.rs
+++ b/esp32s3/src/dma/ch/in_conf0.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn in_rst(&mut self) -> IN_RST_W<IN_CONF0_SPEC> {
         IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<IN_CONF0_SPEC> {
         IN_LOOP_TEST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<IN_CONF0_SPEC> {
         INDSCR_BURST_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<IN_CONF0_SPEC> {
         IN_DATA_BURST_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<IN_CONF0_SPEC> {
         MEM_TRANS_EN_W::new(self, 4)
     }
diff --git a/esp32s3/src/dma/ch/in_conf1.rs b/esp32s3/src/dma/ch/in_conf1.rs
index a79b686ea7..0e6ebdd558 100644
--- a/esp32s3/src/dma/ch/in_conf1.rs
+++ b/esp32s3/src/dma/ch/in_conf1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<IN_CONF1_SPEC> {
         DMA_INFIFO_FULL_THRS_W::new(self, 0)
     }
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<IN_CONF1_SPEC> {
         IN_CHECK_OWNER_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn in_ext_mem_bk_size(&mut self) -> IN_EXT_MEM_BK_SIZE_W<IN_CONF1_SPEC> {
         IN_EXT_MEM_BK_SIZE_W::new(self, 13)
     }
diff --git a/esp32s3/src/dma/ch/in_int/clr.rs b/esp32s3/src/dma/ch/in_int/clr.rs
index b3514726ff..a8cce21302 100644
--- a/esp32s3/src/dma/ch/in_int/clr.rs
+++ b/esp32s3/src/dma/ch/in_int/clr.rs
@@ -29,61 +29,51 @@ impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<CLR_SPEC> {
         IN_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<CLR_SPEC> {
         IN_SUC_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<CLR_SPEC> {
         IN_ERR_EOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<CLR_SPEC> {
         IN_DSCR_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<CLR_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<CLR_SPEC> {
         DMA_INFIFO_FULL_WM_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<CLR_SPEC> {
         INFIFO_OVF_L1_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<CLR_SPEC> {
         INFIFO_UDF_L1_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<CLR_SPEC> {
         INFIFO_OVF_L3_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<CLR_SPEC> {
         INFIFO_UDF_L3_W::new(self, 9)
     }
diff --git a/esp32s3/src/dma/ch/in_int/ena.rs b/esp32s3/src/dma/ch/in_int/ena.rs
index ea4e010d02..f7eeea3b4b 100644
--- a/esp32s3/src/dma/ch/in_int/ena.rs
+++ b/esp32s3/src/dma/ch/in_int/ena.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<ENA_SPEC> {
         IN_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<ENA_SPEC> {
         IN_SUC_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<ENA_SPEC> {
         IN_ERR_EOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<ENA_SPEC> {
         IN_DSCR_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<ENA_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<ENA_SPEC> {
         INFIFO_FULL_WM_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<ENA_SPEC> {
         INFIFO_OVF_L1_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<ENA_SPEC> {
         INFIFO_UDF_L1_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<ENA_SPEC> {
         INFIFO_OVF_L3_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<ENA_SPEC> {
         INFIFO_UDF_L3_W::new(self, 9)
     }
diff --git a/esp32s3/src/dma/ch/in_int/raw.rs b/esp32s3/src/dma/ch/in_int/raw.rs
index 3df6c5cda8..32e83decbc 100644
--- a/esp32s3/src/dma/ch/in_int/raw.rs
+++ b/esp32s3/src/dma/ch/in_int/raw.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn in_done(&mut self) -> IN_DONE_W<RAW_SPEC> {
         IN_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<RAW_SPEC> {
         IN_SUC_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<RAW_SPEC> {
         IN_ERR_EOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<RAW_SPEC> {
         IN_DSCR_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<RAW_SPEC> {
         IN_DSCR_EMPTY_W::new(self, 4)
     }
     #[doc = "Bit 5 - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<RAW_SPEC> {
         INFIFO_FULL_WM_W::new(self, 5)
     }
     #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<RAW_SPEC> {
         INFIFO_OVF_L1_W::new(self, 6)
     }
     #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<RAW_SPEC> {
         INFIFO_UDF_L1_W::new(self, 7)
     }
     #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<RAW_SPEC> {
         INFIFO_OVF_L3_W::new(self, 8)
     }
     #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<RAW_SPEC> {
         INFIFO_UDF_L3_W::new(self, 9)
     }
diff --git a/esp32s3/src/dma/ch/in_link.rs b/esp32s3/src/dma/ch/in_link.rs
index bf9fbcb3e9..b0c1657016 100644
--- a/esp32s3/src/dma/ch/in_link.rs
+++ b/esp32s3/src/dma/ch/in_link.rs
@@ -72,31 +72,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<IN_LINK_SPEC> {
         INLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<IN_LINK_SPEC> {
         INLINK_AUTO_RET_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_stop(&mut self) -> INLINK_STOP_W<IN_LINK_SPEC> {
         INLINK_STOP_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_start(&mut self) -> INLINK_START_W<IN_LINK_SPEC> {
         INLINK_START_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<IN_LINK_SPEC> {
         INLINK_RESTART_W::new(self, 23)
     }
diff --git a/esp32s3/src/dma/ch/in_peri_sel.rs b/esp32s3/src/dma/ch/in_peri_sel.rs
index be69a9d718..ab2de18a62 100644
--- a/esp32s3/src/dma/ch/in_peri_sel.rs
+++ b/esp32s3/src/dma/ch/in_peri_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
     #[inline(always)]
-    #[must_use]
     pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<IN_PERI_SEL_SPEC> {
         PERI_IN_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/ch/in_pop.rs b/esp32s3/src/dma/ch/in_pop.rs
index a70e43a4b5..158d3e4ab0 100644
--- a/esp32s3/src/dma/ch/in_pop.rs
+++ b/esp32s3/src/dma/ch/in_pop.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn infifo_pop(&mut self) -> INFIFO_POP_W<IN_POP_SPEC> {
         INFIFO_POP_W::new(self, 12)
     }
diff --git a/esp32s3/src/dma/ch/in_pri.rs b/esp32s3/src/dma/ch/in_pri.rs
index 740f8df3cd..38e76ef287 100644
--- a/esp32s3/src/dma/ch/in_pri.rs
+++ b/esp32s3/src/dma/ch/in_pri.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pri(&mut self) -> RX_PRI_W<IN_PRI_SPEC> {
         RX_PRI_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/ch/in_wight.rs b/esp32s3/src/dma/ch/in_wight.rs
index dcb8605638..b143136b84 100644
--- a/esp32s3/src/dma/ch/in_wight.rs
+++ b/esp32s3/src/dma/ch/in_wight.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:11 - The weight of Rx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_weight(&mut self) -> RX_WEIGHT_W<IN_WIGHT_SPEC> {
         RX_WEIGHT_W::new(self, 8)
     }
diff --git a/esp32s3/src/dma/ch/out_conf0.rs b/esp32s3/src/dma/ch/out_conf0.rs
index 19497e03f8..6439e0039c 100644
--- a/esp32s3/src/dma/ch/out_conf0.rs
+++ b/esp32s3/src/dma/ch/out_conf0.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rst(&mut self) -> OUT_RST_W<OUT_CONF0_SPEC> {
         OUT_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<OUT_CONF0_SPEC> {
         OUT_LOOP_TEST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
     #[inline(always)]
-    #[must_use]
     pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<OUT_CONF0_SPEC> {
         OUT_AUTO_WRBACK_W::new(self, 2)
     }
     #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<OUT_CONF0_SPEC> {
         OUT_EOF_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<OUT_CONF0_SPEC> {
         OUTDSCR_BURST_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<OUT_CONF0_SPEC> {
         OUT_DATA_BURST_EN_W::new(self, 5)
     }
diff --git a/esp32s3/src/dma/ch/out_conf1.rs b/esp32s3/src/dma/ch/out_conf1.rs
index 67262e8da7..61edccad83 100644
--- a/esp32s3/src/dma/ch/out_conf1.rs
+++ b/esp32s3/src/dma/ch/out_conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
-    #[must_use]
     pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<OUT_CONF1_SPEC> {
         OUT_CHECK_OWNER_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn out_ext_mem_bk_size(&mut self) -> OUT_EXT_MEM_BK_SIZE_W<OUT_CONF1_SPEC> {
         OUT_EXT_MEM_BK_SIZE_W::new(self, 13)
     }
diff --git a/esp32s3/src/dma/ch/out_int/clr.rs b/esp32s3/src/dma/ch/out_int/clr.rs
index bc91ec6c31..e9bcdc0388 100644
--- a/esp32s3/src/dma/ch/out_int/clr.rs
+++ b/esp32s3/src/dma/ch/out_int/clr.rs
@@ -25,49 +25,41 @@ impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<CLR_SPEC> {
         OUT_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<CLR_SPEC> {
         OUT_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<CLR_SPEC> {
         OUT_DSCR_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<CLR_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<CLR_SPEC> {
         OUTFIFO_OVF_L1_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<CLR_SPEC> {
         OUTFIFO_UDF_L1_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<CLR_SPEC> {
         OUTFIFO_OVF_L3_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<CLR_SPEC> {
         OUTFIFO_UDF_L3_W::new(self, 7)
     }
diff --git a/esp32s3/src/dma/ch/out_int/ena.rs b/esp32s3/src/dma/ch/out_int/ena.rs
index 3d92059e7f..405a78c6ef 100644
--- a/esp32s3/src/dma/ch/out_int/ena.rs
+++ b/esp32s3/src/dma/ch/out_int/ena.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<ENA_SPEC> {
         OUT_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<ENA_SPEC> {
         OUT_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<ENA_SPEC> {
         OUT_DSCR_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<ENA_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<ENA_SPEC> {
         OUTFIFO_OVF_L1_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<ENA_SPEC> {
         OUTFIFO_UDF_L1_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<ENA_SPEC> {
         OUTFIFO_OVF_L3_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<ENA_SPEC> {
         OUTFIFO_UDF_L3_W::new(self, 7)
     }
diff --git a/esp32s3/src/dma/ch/out_int/raw.rs b/esp32s3/src/dma/ch/out_int/raw.rs
index d5d746c5f1..7bf1926da0 100644
--- a/esp32s3/src/dma/ch/out_int/raw.rs
+++ b/esp32s3/src/dma/ch/out_int/raw.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn out_done(&mut self) -> OUT_DONE_W<RAW_SPEC> {
         OUT_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<RAW_SPEC> {
         OUT_EOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<RAW_SPEC> {
         OUT_DSCR_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<RAW_SPEC> {
         OUT_TOTAL_EOF_W::new(self, 3)
     }
     #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<RAW_SPEC> {
         OUTFIFO_OVF_L1_W::new(self, 4)
     }
     #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<RAW_SPEC> {
         OUTFIFO_UDF_L1_W::new(self, 5)
     }
     #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<RAW_SPEC> {
         OUTFIFO_OVF_L3_W::new(self, 6)
     }
     #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<RAW_SPEC> {
         OUTFIFO_UDF_L3_W::new(self, 7)
     }
diff --git a/esp32s3/src/dma/ch/out_link.rs b/esp32s3/src/dma/ch/out_link.rs
index 18e90ef418..652a9622b8 100644
--- a/esp32s3/src/dma/ch/out_link.rs
+++ b/esp32s3/src/dma/ch/out_link.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<OUT_LINK_SPEC> {
         OUTLINK_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<OUT_LINK_SPEC> {
         OUTLINK_STOP_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_start(&mut self) -> OUTLINK_START_W<OUT_LINK_SPEC> {
         OUTLINK_START_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<OUT_LINK_SPEC> {
         OUTLINK_RESTART_W::new(self, 22)
     }
diff --git a/esp32s3/src/dma/ch/out_peri_sel.rs b/esp32s3/src/dma/ch/out_peri_sel.rs
index a1c3ba422c..aa0f4aeee9 100644
--- a/esp32s3/src/dma/ch/out_peri_sel.rs
+++ b/esp32s3/src/dma/ch/out_peri_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
     #[inline(always)]
-    #[must_use]
     pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<OUT_PERI_SEL_SPEC> {
         PERI_OUT_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/ch/out_pri.rs b/esp32s3/src/dma/ch/out_pri.rs
index 215bd1ef1e..554b24e4cd 100644
--- a/esp32s3/src/dma/ch/out_pri.rs
+++ b/esp32s3/src/dma/ch/out_pri.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pri(&mut self) -> TX_PRI_W<OUT_PRI_SPEC> {
         TX_PRI_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/ch/out_push.rs b/esp32s3/src/dma/ch/out_push.rs
index ea1185c8df..ca913c3847 100644
--- a/esp32s3/src/dma/ch/out_push.rs
+++ b/esp32s3/src/dma/ch/out_push.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<OUT_PUSH_SPEC> {
         OUTFIFO_WDATA_W::new(self, 0)
     }
     #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<OUT_PUSH_SPEC> {
         OUTFIFO_PUSH_W::new(self, 9)
     }
diff --git a/esp32s3/src/dma/ch/out_wight.rs b/esp32s3/src/dma/ch/out_wight.rs
index d4bb2a1611..2fcaa3b2c5 100644
--- a/esp32s3/src/dma/ch/out_wight.rs
+++ b/esp32s3/src/dma/ch/out_wight.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:11 - The weight of Tx channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_weight(&mut self) -> TX_WEIGHT_W<OUT_WIGHT_SPEC> {
         TX_WEIGHT_W::new(self, 8)
     }
diff --git a/esp32s3/src/dma/date.rs b/esp32s3/src/dma/date.rs
index bc7cab1b15..409b614404 100644
--- a/esp32s3/src/dma/date.rs
+++ b/esp32s3/src/dma/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/extmem_reject_int_clr.rs b/esp32s3/src/dma/extmem_reject_int_clr.rs
index 48d2b64857..b07a26522a 100644
--- a/esp32s3/src/dma/extmem_reject_int_clr.rs
+++ b/esp32s3/src/dma/extmem_reject_int_clr.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the EXTMEM_REJECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn extmem_reject_int_clr(&mut self) -> EXTMEM_REJECT_INT_CLR_W<EXTMEM_REJECT_INT_CLR_SPEC> {
         EXTMEM_REJECT_INT_CLR_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/extmem_reject_int_ena.rs b/esp32s3/src/dma/extmem_reject_int_ena.rs
index 0c436bf543..e4ce5fbf1f 100644
--- a/esp32s3/src/dma/extmem_reject_int_ena.rs
+++ b/esp32s3/src/dma/extmem_reject_int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn extmem_reject_int_ena(&mut self) -> EXTMEM_REJECT_INT_ENA_W<EXTMEM_REJECT_INT_ENA_SPEC> {
         EXTMEM_REJECT_INT_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/extmem_reject_int_raw.rs b/esp32s3/src/dma/extmem_reject_int_raw.rs
index 805b4d3cd8..625cf4b94a 100644
--- a/esp32s3/src/dma/extmem_reject_int_raw.rs
+++ b/esp32s3/src/dma/extmem_reject_int_raw.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
     #[inline(always)]
-    #[must_use]
     pub fn extmem_reject_int_raw(&mut self) -> EXTMEM_REJECT_INT_RAW_W<EXTMEM_REJECT_INT_RAW_SPEC> {
         EXTMEM_REJECT_INT_RAW_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/in_sram_size_ch.rs b/esp32s3/src/dma/in_sram_size_ch.rs
index 0e30aff208..012387ae3e 100644
--- a/esp32s3/src/dma/in_sram_size_ch.rs
+++ b/esp32s3/src/dma/in_sram_size_ch.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn in_size(&mut self) -> IN_SIZE_W<IN_SRAM_SIZE_CH_SPEC> {
         IN_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/misc_conf.rs b/esp32s3/src/dma/misc_conf.rs
index b446f6300c..a25ae0eba0 100644
--- a/esp32s3/src/dma/misc_conf.rs
+++ b/esp32s3/src/dma/misc_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst_inter(&mut self) -> AHBM_RST_INTER_W<MISC_CONF_SPEC> {
         AHBM_RST_INTER_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit, then clear this bit to reset the external ahb FSM."]
     #[inline(always)]
-    #[must_use]
     pub fn ahbm_rst_exter(&mut self) -> AHBM_RST_EXTER_W<MISC_CONF_SPEC> {
         AHBM_RST_EXTER_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
     #[inline(always)]
-    #[must_use]
     pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W<MISC_CONF_SPEC> {
         ARB_PRI_DIS_W::new(self, 2)
     }
     #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
         CLK_EN_W::new(self, 4)
     }
diff --git a/esp32s3/src/dma/out_sram_size_ch.rs b/esp32s3/src/dma/out_sram_size_ch.rs
index 2b83b9da34..080588fe8f 100644
--- a/esp32s3/src/dma/out_sram_size_ch.rs
+++ b/esp32s3/src/dma/out_sram_size_ch.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn out_size(&mut self) -> OUT_SIZE_W<OUT_SRAM_SIZE_CH_SPEC> {
         OUT_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/dma/pd_conf.rs b/esp32s3/src/dma/pd_conf.rs
index 81b9bb0b01..3d6bd6bffd 100644
--- a/esp32s3/src/dma/pd_conf.rs
+++ b/esp32s3/src/dma/pd_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 4 - Set this bit to force power down DMA internal memory."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_force_pd(&mut self) -> DMA_RAM_FORCE_PD_W<PD_CONF_SPEC> {
         DMA_RAM_FORCE_PD_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to force power up DMA internal memory"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_force_pu(&mut self) -> DMA_RAM_FORCE_PU_W<PD_CONF_SPEC> {
         DMA_RAM_FORCE_PU_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_ram_clk_fo(&mut self) -> DMA_RAM_CLK_FO_W<PD_CONF_SPEC> {
         DMA_RAM_CLK_FO_W::new(self, 6)
     }
diff --git a/esp32s3/src/ds/date.rs b/esp32s3/src/ds/date.rs
index 2af9611b50..db49879ad1 100644
--- a/esp32s3/src/ds/date.rs
+++ b/esp32s3/src/ds/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - ds version information"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/ds/iv_.rs b/esp32s3/src/ds/iv_.rs
index 32f4e0550c..442461fc79 100644
--- a/esp32s3/src/ds/iv_.rs
+++ b/esp32s3/src/ds/iv_.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores IV block data"]
     #[inline(always)]
-    #[must_use]
     pub fn iv(&mut self) -> IV_W<IV__SPEC> {
         IV_W::new(self, 0)
     }
diff --git a/esp32s3/src/ds/set_finish.rs b/esp32s3/src/ds/set_finish.rs
index 438f904447..7c92f1c4ac 100644
--- a/esp32s3/src/ds/set_finish.rs
+++ b/esp32s3/src/ds/set_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to end DS operation."]
     #[inline(always)]
-    #[must_use]
     pub fn set_finish(&mut self) -> SET_FINISH_W<SET_FINISH_SPEC> {
         SET_FINISH_W::new(self, 0)
     }
diff --git a/esp32s3/src/ds/set_me.rs b/esp32s3/src/ds/set_me.rs
index 0648c538e8..b60b3df552 100644
--- a/esp32s3/src/ds/set_me.rs
+++ b/esp32s3/src/ds/set_me.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_ME_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to start DS operation."]
     #[inline(always)]
-    #[must_use]
     pub fn set_me(&mut self) -> SET_ME_W<SET_ME_SPEC> {
         SET_ME_W::new(self, 0)
     }
diff --git a/esp32s3/src/ds/set_start.rs b/esp32s3/src/ds/set_start.rs
index a6e4457868..273b988697 100644
--- a/esp32s3/src/ds/set_start.rs
+++ b/esp32s3/src/ds/set_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to this register to active the DS peripheral"]
     #[inline(always)]
-    #[must_use]
     pub fn set_start(&mut self) -> SET_START_W<SET_START_SPEC> {
         SET_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/clk.rs b/esp32s3/src/efuse/clk.rs
index 54fe331005..f9d86ac18a 100644
--- a/esp32s3/src/efuse/clk.rs
+++ b/esp32s3/src/efuse/clk.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_mem_force_pd(&mut self) -> EFUSE_MEM_FORCE_PD_W<CLK_SPEC> {
         EFUSE_MEM_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit and force to activate clock signal of eFuse SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<CLK_SPEC> {
         MEM_CLK_FORCE_ON_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to force eFuse SRAM into working mode."]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_mem_force_pu(&mut self) -> EFUSE_MEM_FORCE_PU_W<CLK_SPEC> {
         EFUSE_MEM_FORCE_PU_W::new(self, 2)
     }
     #[doc = "Bit 16 - Set this bit and force to enable clock signal of eFuse memory."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CLK_SPEC> {
         EN_W::new(self, 16)
     }
diff --git a/esp32s3/src/efuse/cmd.rs b/esp32s3/src/efuse/cmd.rs
index baaf4145e4..fe0688f848 100644
--- a/esp32s3/src/efuse/cmd.rs
+++ b/esp32s3/src/efuse/cmd.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
-    #[must_use]
     pub fn read_cmd(&mut self) -> READ_CMD_W<CMD_SPEC> {
         READ_CMD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to send programming command."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_cmd(&mut self) -> PGM_CMD_W<CMD_SPEC> {
         PGM_CMD_W::new(self, 1)
     }
     #[doc = "Bits 2:5 - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn blk_num(&mut self) -> BLK_NUM_W<CMD_SPEC> {
         BLK_NUM_W::new(self, 2)
     }
diff --git a/esp32s3/src/efuse/conf.rs b/esp32s3/src/efuse/conf.rs
index b5fdc4c1ad..68c5c3c6e9 100644
--- a/esp32s3/src/efuse/conf.rs
+++ b/esp32s3/src/efuse/conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command 0x5AA5: Operate read command."]
     #[inline(always)]
-    #[must_use]
     pub fn op_code(&mut self) -> OP_CODE_W<CONF_SPEC> {
         OP_CODE_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/dac_conf.rs b/esp32s3/src/efuse/dac_conf.rs
index 386dc3b935..dbc17b47fc 100644
--- a/esp32s3/src/efuse/dac_conf.rs
+++ b/esp32s3/src/efuse/dac_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_div(&mut self) -> DAC_CLK_DIV_W<DAC_CONF_SPEC> {
         DAC_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bit 8 - Don't care."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_clk_pad_sel(&mut self) -> DAC_CLK_PAD_SEL_W<DAC_CONF_SPEC> {
         DAC_CLK_PAD_SEL_W::new(self, 8)
     }
     #[doc = "Bits 9:16 - Controls the rising period of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn dac_num(&mut self) -> DAC_NUM_W<DAC_CONF_SPEC> {
         DAC_NUM_W::new(self, 9)
     }
     #[doc = "Bit 17 - Reduces the power supply of the programming voltage."]
     #[inline(always)]
-    #[must_use]
     pub fn oe_clr(&mut self) -> OE_CLR_W<DAC_CONF_SPEC> {
         OE_CLR_W::new(self, 17)
     }
diff --git a/esp32s3/src/efuse/date.rs b/esp32s3/src/efuse/date.rs
index d866b2c4c3..a0b894a1d3 100644
--- a/esp32s3/src/efuse/date.rs
+++ b/esp32s3/src/efuse/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Stores eFuse version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/int_clr.rs b/esp32s3/src/efuse/int_clr.rs
index 670d58f7e5..230f4356f1 100644
--- a/esp32s3/src/efuse/int_clr.rs
+++ b/esp32s3/src/efuse/int_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The clear signal for read_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_CLR_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear signal for pgm_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_CLR_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32s3/src/efuse/int_ena.rs b/esp32s3/src/efuse/int_ena.rs
index 424c4f079d..3d4c9086ee 100644
--- a/esp32s3/src/efuse/int_ena.rs
+++ b/esp32s3/src/efuse/int_ena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_ENA_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable signal for pgm_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_ENA_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32s3/src/efuse/int_raw.rs b/esp32s3/src/efuse/int_raw.rs
index 6bfa5bd172..a187c9e496 100644
--- a/esp32s3/src/efuse/int_raw.rs
+++ b/esp32s3/src/efuse/int_raw.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw bit signal for read_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn read_done(&mut self) -> READ_DONE_W<INT_RAW_SPEC> {
         READ_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw bit signal for pgm_done interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_done(&mut self) -> PGM_DONE_W<INT_RAW_SPEC> {
         PGM_DONE_W::new(self, 1)
     }
diff --git a/esp32s3/src/efuse/pgm_check_value0.rs b/esp32s3/src/efuse/pgm_check_value0.rs
index bed5588bf9..165a5a55b2 100644
--- a/esp32s3/src/efuse/pgm_check_value0.rs
+++ b/esp32s3/src/efuse/pgm_check_value0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_rs_data_0(&mut self) -> PGM_RS_DATA_0_W<PGM_CHECK_VALUE0_SPEC> {
         PGM_RS_DATA_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_check_value1.rs b/esp32s3/src/efuse/pgm_check_value1.rs
index 585f92eb55..0d04132207 100644
--- a/esp32s3/src/efuse/pgm_check_value1.rs
+++ b/esp32s3/src/efuse/pgm_check_value1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_rs_data_1(&mut self) -> PGM_RS_DATA_1_W<PGM_CHECK_VALUE1_SPEC> {
         PGM_RS_DATA_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_check_value2.rs b/esp32s3/src/efuse/pgm_check_value2.rs
index d3c0a50f20..bb85d3697c 100644
--- a/esp32s3/src/efuse/pgm_check_value2.rs
+++ b/esp32s3/src/efuse/pgm_check_value2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_rs_data_2(&mut self) -> PGM_RS_DATA_2_W<PGM_CHECK_VALUE2_SPEC> {
         PGM_RS_DATA_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data0.rs b/esp32s3/src/efuse/pgm_data0.rs
index 2676c1f6a5..9691777d12 100644
--- a/esp32s3/src/efuse/pgm_data0.rs
+++ b/esp32s3/src/efuse/pgm_data0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_0(&mut self) -> PGM_DATA_0_W<PGM_DATA0_SPEC> {
         PGM_DATA_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data1.rs b/esp32s3/src/efuse/pgm_data1.rs
index b3802bb980..4ce4c4339d 100644
--- a/esp32s3/src/efuse/pgm_data1.rs
+++ b/esp32s3/src/efuse/pgm_data1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_1(&mut self) -> PGM_DATA_1_W<PGM_DATA1_SPEC> {
         PGM_DATA_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data2.rs b/esp32s3/src/efuse/pgm_data2.rs
index fe05569e67..49e46b4e7e 100644
--- a/esp32s3/src/efuse/pgm_data2.rs
+++ b/esp32s3/src/efuse/pgm_data2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_2(&mut self) -> PGM_DATA_2_W<PGM_DATA2_SPEC> {
         PGM_DATA_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data3.rs b/esp32s3/src/efuse/pgm_data3.rs
index 721be6b07a..53270d76fc 100644
--- a/esp32s3/src/efuse/pgm_data3.rs
+++ b/esp32s3/src/efuse/pgm_data3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 3rd 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_3(&mut self) -> PGM_DATA_3_W<PGM_DATA3_SPEC> {
         PGM_DATA_3_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data4.rs b/esp32s3/src/efuse/pgm_data4.rs
index 84f78f4284..db5f011b1c 100644
--- a/esp32s3/src/efuse/pgm_data4.rs
+++ b/esp32s3/src/efuse/pgm_data4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 4th 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_4(&mut self) -> PGM_DATA_4_W<PGM_DATA4_SPEC> {
         PGM_DATA_4_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data5.rs b/esp32s3/src/efuse/pgm_data5.rs
index ce70e5d5d6..8a7df71c5e 100644
--- a/esp32s3/src/efuse/pgm_data5.rs
+++ b/esp32s3/src/efuse/pgm_data5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 5th 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_5(&mut self) -> PGM_DATA_5_W<PGM_DATA5_SPEC> {
         PGM_DATA_5_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data6.rs b/esp32s3/src/efuse/pgm_data6.rs
index 0f8ed00121..e1d3392919 100644
--- a/esp32s3/src/efuse/pgm_data6.rs
+++ b/esp32s3/src/efuse/pgm_data6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 6th 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_6(&mut self) -> PGM_DATA_6_W<PGM_DATA6_SPEC> {
         PGM_DATA_6_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/pgm_data7.rs b/esp32s3/src/efuse/pgm_data7.rs
index 0c5227677f..4294c78bcd 100644
--- a/esp32s3/src/efuse/pgm_data7.rs
+++ b/esp32s3/src/efuse/pgm_data7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The content of the 7th 32-bit data to be programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn pgm_data_7(&mut self) -> PGM_DATA_7_W<PGM_DATA7_SPEC> {
         PGM_DATA_7_W::new(self, 0)
     }
diff --git a/esp32s3/src/efuse/rd_tim_conf.rs b/esp32s3/src/efuse/rd_tim_conf.rs
index 11a8af2a0f..3b1e957a8c 100644
--- a/esp32s3/src/efuse/rd_tim_conf.rs
+++ b/esp32s3/src/efuse/rd_tim_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 24:31 - Configures the initial read time of eFuse."]
     #[inline(always)]
-    #[must_use]
     pub fn read_init_num(&mut self) -> READ_INIT_NUM_W<RD_TIM_CONF_SPEC> {
         READ_INIT_NUM_W::new(self, 24)
     }
diff --git a/esp32s3/src/efuse/wr_tim_conf1.rs b/esp32s3/src/efuse/wr_tim_conf1.rs
index 72073fd384..33c12e0d31 100644
--- a/esp32s3/src/efuse/wr_tim_conf1.rs
+++ b/esp32s3/src/efuse/wr_tim_conf1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:23 - Configures the power up time for VDDQ."]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_on_num(&mut self) -> PWR_ON_NUM_W<WR_TIM_CONF1_SPEC> {
         PWR_ON_NUM_W::new(self, 8)
     }
diff --git a/esp32s3/src/efuse/wr_tim_conf2.rs b/esp32s3/src/efuse/wr_tim_conf2.rs
index 5a9d903776..e9b9424ef6 100644
--- a/esp32s3/src/efuse/wr_tim_conf2.rs
+++ b/esp32s3/src/efuse/wr_tim_conf2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_off_num(&mut self) -> PWR_OFF_NUM_W<WR_TIM_CONF2_SPEC> {
         PWR_OFF_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_acs_cnt_clr.rs b/esp32s3/src/extmem/cache_acs_cnt_clr.rs
index 395ec8e704..e44e103fa4 100644
--- a/esp32s3/src/extmem/cache_acs_cnt_clr.rs
+++ b/esp32s3/src/extmem/cache_acs_cnt_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<CACHE_ACS_CNT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear dcache counter."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_acs_cnt_clr(&mut self) -> DCACHE_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
         DCACHE_ACS_CNT_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to clear icache counter."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_acs_cnt_clr(&mut self) -> ICACHE_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
         ICACHE_ACS_CNT_CLR_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs b/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
index 003bf9f2f9..ff696dbef2 100644
--- a/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
+++ b/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn alloc_wb_hold_arbiter(
         &mut self,
     ) -> ALLOC_WB_HOLD_ARBITER_W<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/cache_conf_misc.rs b/esp32s3/src/extmem/cache_conf_misc.rs
index 0cfc214bc4..969ae7d8ce 100644
--- a/esp32s3/src/extmem/cache_conf_misc.rs
+++ b/esp32s3/src/extmem/cache_conf_misc.rs
@@ -50,7 +50,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ignore_preload_mmu_entry_fault(
         &mut self,
     ) -> CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
@@ -58,7 +57,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ignore_sync_mmu_entry_fault(
         &mut self,
     ) -> CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
@@ -66,7 +64,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to enable cache trace function."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_trace_ena(&mut self) -> CACHE_TRACE_ENA_W<CACHE_CONF_MISC_SPEC> {
         CACHE_TRACE_ENA_W::new(self, 2)
     }
diff --git a/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index 58c3dc6847..bd89e22395 100644
--- a/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -47,7 +47,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_manual_crypt(
         &mut self,
     ) -> CLK_FORCE_ON_MANUAL_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
@@ -55,7 +54,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_auto_crypt(
         &mut self,
     ) -> CLK_FORCE_ON_AUTO_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
@@ -63,7 +61,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_force_on_crypt(
         &mut self,
     ) -> CLK_FORCE_ON_CRYPT_W<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
diff --git a/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
index 38b570d534..9483bdf512 100644
--- a/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn record_disable_db_encrypt(
         &mut self,
     ) -> RECORD_DISABLE_DB_ENCRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn record_disable_g0cb_decrypt(
         &mut self,
     ) -> RECORD_DISABLE_G0CB_DECRYPT_W<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
diff --git a/esp32s3/src/extmem/cache_ilg_int_clr.rs b/esp32s3/src/extmem/cache_ilg_int_clr.rs
index e7fba0b487..8aa1601db4 100644
--- a/esp32s3/src/extmem/cache_ilg_int_clr.rs
+++ b/esp32s3/src/extmem/cache_ilg_int_clr.rs
@@ -27,55 +27,46 @@ impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt by sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
         ICACHE_SYNC_OP_FAULT_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to clear interrupt by preload configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
         ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to clear interrupt by sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
         DCACHE_SYNC_OP_FAULT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to clear interrupt by preload configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
         DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
     }
     #[doc = "Bit 4 - The bit is used to clear interrupt by dcache trying to write flash."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_CLR_SPEC> {
         DCACHE_WRITE_FLASH_W::new(self, 4)
     }
     #[doc = "Bit 5 - The bit is used to clear interrupt by mmu entry fault."]
     #[inline(always)]
-    #[must_use]
     pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
         MMU_ENTRY_FAULT_W::new(self, 5)
     }
     #[doc = "Bit 6 - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_CLR_SPEC> {
         DCACHE_OCCUPY_EXC_W::new(self, 6)
     }
     #[doc = "Bit 7 - The bit is used to clear interrupt by ibus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
         IBUS_CNT_OVF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The bit is used to clear interrupt by dbus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
         DBUS_CNT_OVF_W::new(self, 8)
     }
diff --git a/esp32s3/src/extmem/cache_ilg_int_ena.rs b/esp32s3/src/extmem/cache_ilg_int_ena.rs
index 108121168d..70814da7a7 100644
--- a/esp32s3/src/extmem/cache_ilg_int_ena.rs
+++ b/esp32s3/src/extmem/cache_ilg_int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
         ICACHE_SYNC_OP_FAULT_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
         ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to enable interrupt by sync configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
         DCACHE_SYNC_OP_FAULT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to enable interrupt by preload configurations fault."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
         DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
     }
     #[doc = "Bit 4 - The bit is used to enable interrupt by dcache trying to write flash."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_ENA_SPEC> {
         DCACHE_WRITE_FLASH_W::new(self, 4)
     }
     #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
     #[inline(always)]
-    #[must_use]
     pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
         MMU_ENTRY_FAULT_W::new(self, 5)
     }
     #[doc = "Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_ENA_SPEC> {
         DCACHE_OCCUPY_EXC_W::new(self, 6)
     }
     #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
         IBUS_CNT_OVF_W::new(self, 7)
     }
     #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
         DBUS_CNT_OVF_W::new(self, 8)
     }
diff --git a/esp32s3/src/extmem/cache_mmu_owner.rs b/esp32s3/src/extmem/cache_mmu_owner.rs
index 19c275d00a..6f0d3850e4 100644
--- a/esp32s3/src/extmem/cache_mmu_owner.rs
+++ b/esp32s3/src/extmem/cache_mmu_owner.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_owner(&mut self) -> CACHE_MMU_OWNER_W<CACHE_MMU_OWNER_SPEC> {
         CACHE_MMU_OWNER_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_mmu_power_ctrl.rs b/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
index 186a6046c8..cb050e5451 100644
--- a/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
+++ b/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
@@ -44,7 +44,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_mem_force_on(
         &mut self,
     ) -> CACHE_MMU_MEM_FORCE_ON_W<CACHE_MMU_POWER_CTRL_SPEC> {
@@ -52,7 +51,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_mem_force_pd(
         &mut self,
     ) -> CACHE_MMU_MEM_FORCE_PD_W<CACHE_MMU_POWER_CTRL_SPEC> {
@@ -60,7 +58,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_mem_force_pu(
         &mut self,
     ) -> CACHE_MMU_MEM_FORCE_PU_W<CACHE_MMU_POWER_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/cache_preload_int_ctrl.rs b/esp32s3/src/extmem/cache_preload_int_ctrl.rs
index 7a0a0dfc09..422f7f0d08 100644
--- a/esp32s3/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32s3/src/extmem/cache_preload_int_ctrl.rs
@@ -54,19 +54,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
         ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to clear the interrupt by icache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn clr(&mut self) -> CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
         CLR_W::new(self, 2)
     }
     #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_int_ena(
         &mut self,
     ) -> DCACHE_PRELOAD_INT_ENA_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
@@ -74,7 +71,6 @@ impl W {
     }
     #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache pre-load done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_int_clr(
         &mut self,
     ) -> DCACHE_PRELOAD_INT_CLR_W<CACHE_PRELOAD_INT_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/cache_request.rs b/esp32s3/src/extmem/cache_request.rs
index a2594a7718..59a40cb91a 100644
--- a/esp32s3/src/extmem/cache_request.rs
+++ b/esp32s3/src/extmem/cache_request.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
     #[inline(always)]
-    #[must_use]
     pub fn bypass(&mut self) -> BYPASS_W<CACHE_REQUEST_SPEC> {
         BYPASS_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_sync_int_ctrl.rs b/esp32s3/src/extmem/cache_sync_int_ctrl.rs
index 8ae053daf9..332f7677ba 100644
--- a/esp32s3/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32s3/src/extmem/cache_sync_int_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
         ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to clear the interrupt by icache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn clr(&mut self) -> CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
         CLR_W::new(self, 2)
     }
     #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_int_ena(&mut self) -> DCACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
         DCACHE_SYNC_INT_ENA_W::new(self, 4)
     }
     #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache sync done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_int_clr(&mut self) -> DCACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
         DCACHE_SYNC_INT_CLR_W::new(self, 5)
     }
diff --git a/esp32s3/src/extmem/cache_tag_content.rs b/esp32s3/src/extmem/cache_tag_content.rs
index 467309d66e..eb409d4fe5 100644
--- a/esp32s3/src/extmem/cache_tag_content.rs
+++ b/esp32s3/src/extmem/cache_tag_content.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_tag_content(&mut self) -> CACHE_TAG_CONTENT_W<CACHE_TAG_CONTENT_SPEC> {
         CACHE_TAG_CONTENT_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_tag_object_ctrl.rs b/esp32s3/src/extmem/cache_tag_object_ctrl.rs
index 2fba1b0008..7599357687 100644
--- a/esp32s3/src/extmem/cache_tag_object_ctrl.rs
+++ b/esp32s3/src/extmem/cache_tag_object_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_tag_object(&mut self) -> ICACHE_TAG_OBJECT_W<CACHE_TAG_OBJECT_CTRL_SPEC> {
         ICACHE_TAG_OBJECT_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_tag_object(&mut self) -> DCACHE_TAG_OBJECT_W<CACHE_TAG_OBJECT_CTRL_SPEC> {
         DCACHE_TAG_OBJECT_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/cache_tag_way_object.rs b/esp32s3/src/extmem/cache_tag_way_object.rs
index d271f65003..9c40d5e753 100644
--- a/esp32s3/src/extmem/cache_tag_way_object.rs
+++ b/esp32s3/src/extmem/cache_tag_way_object.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_tag_way_object(&mut self) -> CACHE_TAG_WAY_OBJECT_W<CACHE_TAG_WAY_OBJECT_SPEC> {
         CACHE_TAG_WAY_OBJECT_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_vaddr.rs b/esp32s3/src/extmem/cache_vaddr.rs
index 5fc6eab56d..e6bb47e653 100644
--- a/esp32s3/src/extmem/cache_vaddr.rs
+++ b/esp32s3/src/extmem/cache_vaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_vaddr(&mut self) -> CACHE_VADDR_W<CACHE_VADDR_SPEC> {
         CACHE_VADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/cache_wrap_around_ctrl.rs b/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
index 66e3663c6c..d8240e8bd7 100644
--- a/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
+++ b/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
@@ -37,7 +37,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_flash_wrap_around(
         &mut self,
     ) -> CACHE_FLASH_WRAP_AROUND_W<CACHE_WRAP_AROUND_CTRL_SPEC> {
@@ -45,7 +44,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to enable wrap around mode when read data from spiram."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_rd_wrap_around(
         &mut self,
     ) -> CACHE_SRAM_RD_WRAP_AROUND_W<CACHE_WRAP_AROUND_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/clock_gate.rs b/esp32s3/src/extmem/clock_gate.rs
index 3b0224dcef..ca2fbc422c 100644
--- a/esp32s3/src/extmem/clock_gate.rs
+++ b/esp32s3/src/extmem/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/core0_acs_cache_int_clr.rs b/esp32s3/src/extmem/core0_acs_cache_int_clr.rs
index b4598570d3..414e76a9ed 100644
--- a/esp32s3/src/extmem/core0_acs_cache_int_clr.rs
+++ b/esp32s3/src/extmem/core0_acs_cache_int_clr.rs
@@ -19,7 +19,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_acs_msk_ic(
         &mut self,
     ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
@@ -27,19 +26,16 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to clear interrupt by ibus trying to write icache"]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
         CORE0_IBUS_WR_IC_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
         CORE0_IBUS_REJECT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_dbus_acs_msk_dc(
         &mut self,
     ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
@@ -47,7 +43,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
         CORE0_DBUS_REJECT_W::new(self, 4)
     }
diff --git a/esp32s3/src/extmem/core0_acs_cache_int_ena.rs b/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
index eaea588981..a94829c317 100644
--- a/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
+++ b/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
@@ -64,7 +64,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_acs_msk_ic(
         &mut self,
     ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
@@ -72,19 +71,16 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
         CORE0_IBUS_WR_IC_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
         CORE0_IBUS_REJECT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_dbus_acs_msk_dc(
         &mut self,
     ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
@@ -92,7 +88,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
         CORE0_DBUS_REJECT_W::new(self, 4)
     }
diff --git a/esp32s3/src/extmem/core1_acs_cache_int_clr.rs b/esp32s3/src/extmem/core1_acs_cache_int_clr.rs
index 7de919edfc..9983030b72 100644
--- a/esp32s3/src/extmem/core1_acs_cache_int_clr.rs
+++ b/esp32s3/src/extmem/core1_acs_cache_int_clr.rs
@@ -19,7 +19,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE1_ACS_CACHE_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_acs_msk_ic_int_clr(
         &mut self,
     ) -> CORE1_IBUS_ACS_MSK_IC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
@@ -27,7 +26,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to clear interrupt by ibus trying to write icache"]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_wr_ic_int_clr(
         &mut self,
     ) -> CORE1_IBUS_WR_IC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
@@ -35,7 +33,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_reject_int_clr(
         &mut self,
     ) -> CORE1_IBUS_REJECT_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
@@ -43,7 +40,6 @@ impl W {
     }
     #[doc = "Bit 3 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_dbus_acs_msk_dc_int_clr(
         &mut self,
     ) -> CORE1_DBUS_ACS_MSK_DC_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
@@ -51,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_dbus_reject_int_clr(
         &mut self,
     ) -> CORE1_DBUS_REJECT_INT_CLR_W<CORE1_ACS_CACHE_INT_CLR_SPEC> {
diff --git a/esp32s3/src/extmem/core1_acs_cache_int_ena.rs b/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
index 869469645e..a2051a762b 100644
--- a/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
+++ b/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
@@ -76,7 +76,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_acs_msk_ic_int_ena(
         &mut self,
     ) -> CORE1_IBUS_ACS_MSK_IC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
@@ -84,7 +83,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_wr_ic_int_ena(
         &mut self,
     ) -> CORE1_IBUS_WR_IC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
@@ -92,7 +90,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_ibus_reject_int_ena(
         &mut self,
     ) -> CORE1_IBUS_REJECT_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
@@ -100,7 +97,6 @@ impl W {
     }
     #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_dbus_acs_msk_dc_int_ena(
         &mut self,
     ) -> CORE1_DBUS_ACS_MSK_DC_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
@@ -108,7 +104,6 @@ impl W {
     }
     #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_dbus_reject_int_ena(
         &mut self,
     ) -> CORE1_DBUS_REJECT_INT_ENA_W<CORE1_ACS_CACHE_INT_ENA_SPEC> {
diff --git a/esp32s3/src/extmem/date.rs b/esp32s3/src/extmem/date.rs
index 5203d8c454..03e188a274 100644
--- a/esp32s3/src/extmem/date.rs
+++ b/esp32s3/src/extmem/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version information."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs b/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
index b6380ab449..882aec0028 100644
--- a/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
+++ b/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_to_flash_end_vaddr(
         &mut self,
     ) -> DBUS_TO_FLASH_END_VADDR_W<DBUS_TO_FLASH_END_VADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs b/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
index 81a517ccd3..56d365cb84 100644
--- a/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
+++ b/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
-    #[must_use]
     pub fn dbus_to_flash_start_vaddr(
         &mut self,
     ) -> DBUS_TO_FLASH_START_VADDR_W<DBUS_TO_FLASH_START_VADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_atomic_operate_ena.rs b/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
index 46eb31cf94..14afec1e8f 100644
--- a/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
+++ b/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_atomic_operate_ena(
         &mut self,
     ) -> DCACHE_ATOMIC_OPERATE_ENA_W<DCACHE_ATOMIC_OPERATE_ENA_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_autoload_ctrl.rs b/esp32s3/src/extmem/dcache_autoload_ctrl.rs
index 42aaf6ee5b..fc1b09dbcc 100644
--- a/esp32s3/src/extmem/dcache_autoload_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_autoload_ctrl.rs
@@ -95,7 +95,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct0_ena(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT0_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
@@ -103,7 +102,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct1_ena(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT1_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
@@ -111,31 +109,26 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_ena(&mut self) -> DCACHE_AUTOLOAD_ENA_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
         DCACHE_AUTOLOAD_ENA_W::new(self, 2)
     }
     #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_order(&mut self) -> DCACHE_AUTOLOAD_ORDER_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
         DCACHE_AUTOLOAD_ORDER_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_rqst(&mut self) -> DCACHE_AUTOLOAD_RQST_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
         DCACHE_AUTOLOAD_RQST_W::new(self, 5)
     }
     #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_size(&mut self) -> DCACHE_AUTOLOAD_SIZE_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
         DCACHE_AUTOLOAD_SIZE_W::new(self, 7)
     }
     #[doc = "Bit 9 - The bit is used to clear autoload buffer in dcache."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_buffer_clear(
         &mut self,
     ) -> DCACHE_AUTOLOAD_BUFFER_CLEAR_W<DCACHE_AUTOLOAD_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs b/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
index 21e9db1c95..3f075c1c1e 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct0_addr(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT0_ADDR_W<DCACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_autoload_sct0_size.rs b/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
index 6d882079f2..a0bd9505b2 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct0_size(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT0_SIZE_W<DCACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs b/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
index 3dcd1a15a8..bd692369c3 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct1_addr(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT1_ADDR_W<DCACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_autoload_sct1_size.rs b/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
index dd0aeb3037..a1187e2e92 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_autoload_sct1_size(
         &mut self,
     ) -> DCACHE_AUTOLOAD_SCT1_SIZE_W<DCACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_ctrl.rs b/esp32s3/src/extmem/dcache_ctrl.rs
index 4c0b98acb7..ef30bc37be 100644
--- a/esp32s3/src/extmem/dcache_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_enable(&mut self) -> DCACHE_ENABLE_W<DCACHE_CTRL_SPEC> {
         DCACHE_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 32KB, 1: 64KB"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_size_mode(&mut self) -> DCACHE_SIZE_MODE_W<DCACHE_CTRL_SPEC> {
         DCACHE_SIZE_MODE_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_blocksize_mode(&mut self) -> DCACHE_BLOCKSIZE_MODE_W<DCACHE_CTRL_SPEC> {
         DCACHE_BLOCKSIZE_MODE_W::new(self, 3)
     }
diff --git a/esp32s3/src/extmem/dcache_ctrl1.rs b/esp32s3/src/extmem/dcache_ctrl1.rs
index f94ba34321..75b8b10780 100644
--- a/esp32s3/src/extmem/dcache_ctrl1.rs
+++ b/esp32s3/src/extmem/dcache_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_shut_core0_bus(&mut self) -> DCACHE_SHUT_CORE0_BUS_W<DCACHE_CTRL1_SPEC> {
         DCACHE_SHUT_CORE0_BUS_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to disable core1 dbus, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_shut_core1_bus(&mut self) -> DCACHE_SHUT_CORE1_BUS_W<DCACHE_CTRL1_SPEC> {
         DCACHE_SHUT_CORE1_BUS_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/dcache_freeze.rs b/esp32s3/src/extmem/dcache_freeze.rs
index 43a28244d7..7d79904e10 100644
--- a/esp32s3/src/extmem/dcache_freeze.rs
+++ b/esp32s3/src/extmem/dcache_freeze.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable dcache freeze mode"]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<DCACHE_FREEZE_SPEC> {
         ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<DCACHE_FREEZE_SPEC> {
         MODE_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/dcache_lock_addr.rs b/esp32s3/src/extmem/dcache_lock_addr.rs
index 908f9104ef..6beea6f2ee 100644
--- a/esp32s3/src/extmem/dcache_lock_addr.rs
+++ b/esp32s3/src/extmem/dcache_lock_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_lock_addr(&mut self) -> DCACHE_LOCK_ADDR_W<DCACHE_LOCK_ADDR_SPEC> {
         DCACHE_LOCK_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_lock_ctrl.rs b/esp32s3/src/extmem/dcache_lock_ctrl.rs
index b84c635a99..70a1927839 100644
--- a/esp32s3/src/extmem/dcache_lock_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_lock_ctrl.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_lock_ena(&mut self) -> DCACHE_LOCK_ENA_W<DCACHE_LOCK_CTRL_SPEC> {
         DCACHE_LOCK_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_unlock_ena(&mut self) -> DCACHE_UNLOCK_ENA_W<DCACHE_LOCK_CTRL_SPEC> {
         DCACHE_UNLOCK_ENA_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/dcache_lock_size.rs b/esp32s3/src/extmem/dcache_lock_size.rs
index 1ecb01c389..0802b53575 100644
--- a/esp32s3/src/extmem/dcache_lock_size.rs
+++ b/esp32s3/src/extmem/dcache_lock_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_lock_size(&mut self) -> DCACHE_LOCK_SIZE_W<DCACHE_LOCK_SIZE_SPEC> {
         DCACHE_LOCK_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_occupy_addr.rs b/esp32s3/src/extmem/dcache_occupy_addr.rs
index f8ede71d05..96873d180a 100644
--- a/esp32s3/src/extmem/dcache_occupy_addr.rs
+++ b/esp32s3/src/extmem/dcache_occupy_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_occupy_addr(&mut self) -> DCACHE_OCCUPY_ADDR_W<DCACHE_OCCUPY_ADDR_SPEC> {
         DCACHE_OCCUPY_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_occupy_ctrl.rs b/esp32s3/src/extmem/dcache_occupy_ctrl.rs
index f7233742a4..583114afd0 100644
--- a/esp32s3/src/extmem/dcache_occupy_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_occupy_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_occupy_ena(&mut self) -> DCACHE_OCCUPY_ENA_W<DCACHE_OCCUPY_CTRL_SPEC> {
         DCACHE_OCCUPY_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_occupy_size.rs b/esp32s3/src/extmem/dcache_occupy_size.rs
index 840b7fc359..e8c45f3bb3 100644
--- a/esp32s3/src/extmem/dcache_occupy_size.rs
+++ b/esp32s3/src/extmem/dcache_occupy_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_occupy_size(&mut self) -> DCACHE_OCCUPY_SIZE_W<DCACHE_OCCUPY_SIZE_SPEC> {
         DCACHE_OCCUPY_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_preload_addr.rs b/esp32s3/src/extmem/dcache_preload_addr.rs
index 88080b07f4..dba5d223ce 100644
--- a/esp32s3/src/extmem/dcache_preload_addr.rs
+++ b/esp32s3/src/extmem/dcache_preload_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_addr(&mut self) -> DCACHE_PRELOAD_ADDR_W<DCACHE_PRELOAD_ADDR_SPEC> {
         DCACHE_PRELOAD_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_preload_ctrl.rs b/esp32s3/src/extmem/dcache_preload_ctrl.rs
index 391a74d672..3b7fab96df 100644
--- a/esp32s3/src/extmem/dcache_preload_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_preload_ctrl.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_ena(&mut self) -> DCACHE_PRELOAD_ENA_W<DCACHE_PRELOAD_CTRL_SPEC> {
         DCACHE_PRELOAD_ENA_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_order(&mut self) -> DCACHE_PRELOAD_ORDER_W<DCACHE_PRELOAD_CTRL_SPEC> {
         DCACHE_PRELOAD_ORDER_W::new(self, 2)
     }
diff --git a/esp32s3/src/extmem/dcache_preload_size.rs b/esp32s3/src/extmem/dcache_preload_size.rs
index f963ab576e..dd1c92fc13 100644
--- a/esp32s3/src/extmem/dcache_preload_size.rs
+++ b/esp32s3/src/extmem/dcache_preload_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_size(&mut self) -> DCACHE_PRELOAD_SIZE_W<DCACHE_PRELOAD_SIZE_SPEC> {
         DCACHE_PRELOAD_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_prelock_ctrl.rs b/esp32s3/src/extmem/dcache_prelock_ctrl.rs
index a7bf877802..1167ab214e 100644
--- a/esp32s3/src/extmem/dcache_prelock_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_prelock_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct0_en(&mut self) -> DCACHE_PRELOCK_SCT0_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
         DCACHE_PRELOCK_SCT0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct1_en(&mut self) -> DCACHE_PRELOCK_SCT1_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
         DCACHE_PRELOCK_SCT1_EN_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs b/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
index 835f74cb52..06fde71d34 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct0_addr(
         &mut self,
     ) -> DCACHE_PRELOCK_SCT0_ADDR_W<DCACHE_PRELOCK_SCT0_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs b/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
index eb5f82f025..7ee11844dc 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct1_addr(
         &mut self,
     ) -> DCACHE_PRELOCK_SCT1_ADDR_W<DCACHE_PRELOCK_SCT1_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_prelock_sct_size.rs b/esp32s3/src/extmem/dcache_prelock_sct_size.rs
index 498862df20..0b11972132 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct_size.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct_size.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct1_size(
         &mut self,
     ) -> DCACHE_PRELOCK_SCT1_SIZE_W<DCACHE_PRELOCK_SCT_SIZE_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_prelock_sct0_size(
         &mut self,
     ) -> DCACHE_PRELOCK_SCT0_SIZE_W<DCACHE_PRELOCK_SCT_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/dcache_sync_addr.rs b/esp32s3/src/extmem/dcache_sync_addr.rs
index 80b4eb50fe..89c4f93cca 100644
--- a/esp32s3/src/extmem/dcache_sync_addr.rs
+++ b/esp32s3/src/extmem/dcache_sync_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_addr(&mut self) -> DCACHE_SYNC_ADDR_W<DCACHE_SYNC_ADDR_SPEC> {
         DCACHE_SYNC_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_sync_ctrl.rs b/esp32s3/src/extmem/dcache_sync_ctrl.rs
index 3a9226bc9d..d0576d4a8e 100644
--- a/esp32s3/src/extmem/dcache_sync_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_sync_ctrl.rs
@@ -52,19 +52,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_invalidate_ena(&mut self) -> DCACHE_INVALIDATE_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
         DCACHE_INVALIDATE_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_writeback_ena(&mut self) -> DCACHE_WRITEBACK_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
         DCACHE_WRITEBACK_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_clean_ena(&mut self) -> DCACHE_CLEAN_ENA_W<DCACHE_SYNC_CTRL_SPEC> {
         DCACHE_CLEAN_ENA_W::new(self, 2)
     }
diff --git a/esp32s3/src/extmem/dcache_sync_size.rs b/esp32s3/src/extmem/dcache_sync_size.rs
index 1b23c5949b..9b5c4ea44b 100644
--- a/esp32s3/src/extmem/dcache_sync_size.rs
+++ b/esp32s3/src/extmem/dcache_sync_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_size(&mut self) -> DCACHE_SYNC_SIZE_W<DCACHE_SYNC_SIZE_SPEC> {
         DCACHE_SYNC_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/dcache_tag_power_ctrl.rs b/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
index d5dcc4b76f..acdd68d0b0 100644
--- a/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
@@ -44,7 +44,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_tag_mem_force_on(
         &mut self,
     ) -> DCACHE_TAG_MEM_FORCE_ON_W<DCACHE_TAG_POWER_CTRL_SPEC> {
@@ -52,7 +51,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_tag_mem_force_pd(
         &mut self,
     ) -> DCACHE_TAG_MEM_FORCE_PD_W<DCACHE_TAG_POWER_CTRL_SPEC> {
@@ -60,7 +58,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_tag_mem_force_pu(
         &mut self,
     ) -> DCACHE_TAG_MEM_FORCE_PU_W<DCACHE_TAG_POWER_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs b/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
index 442ba02fd4..8057427af0 100644
--- a/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
+++ b/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_to_flash_end_vaddr(
         &mut self,
     ) -> IBUS_TO_FLASH_END_VADDR_W<IBUS_TO_FLASH_END_VADDR_SPEC> {
diff --git a/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs b/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
index 412606bcab..777634a3bf 100644
--- a/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
+++ b/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
-    #[must_use]
     pub fn ibus_to_flash_start_vaddr(
         &mut self,
     ) -> IBUS_TO_FLASH_START_VADDR_W<IBUS_TO_FLASH_START_VADDR_SPEC> {
diff --git a/esp32s3/src/extmem/icache_atomic_operate_ena.rs b/esp32s3/src/extmem/icache_atomic_operate_ena.rs
index 61dc2f17c4..a89fbadcc0 100644
--- a/esp32s3/src/extmem/icache_atomic_operate_ena.rs
+++ b/esp32s3/src/extmem/icache_atomic_operate_ena.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_atomic_operate_ena(
         &mut self,
     ) -> ICACHE_ATOMIC_OPERATE_ENA_W<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
diff --git a/esp32s3/src/extmem/icache_autoload_ctrl.rs b/esp32s3/src/extmem/icache_autoload_ctrl.rs
index f57285f71f..8fac1e8777 100644
--- a/esp32s3/src/extmem/icache_autoload_ctrl.rs
+++ b/esp32s3/src/extmem/icache_autoload_ctrl.rs
@@ -95,7 +95,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct0_ena(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT0_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
@@ -103,7 +102,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bits are used to enable the second section for autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct1_ena(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT1_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
@@ -111,31 +109,26 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_ena(&mut self) -> ICACHE_AUTOLOAD_ENA_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
         ICACHE_AUTOLOAD_ENA_W::new(self, 2)
     }
     #[doc = "Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_order(&mut self) -> ICACHE_AUTOLOAD_ORDER_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
         ICACHE_AUTOLOAD_ORDER_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_rqst(&mut self) -> ICACHE_AUTOLOAD_RQST_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
         ICACHE_AUTOLOAD_RQST_W::new(self, 5)
     }
     #[doc = "Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_size(&mut self) -> ICACHE_AUTOLOAD_SIZE_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
         ICACHE_AUTOLOAD_SIZE_W::new(self, 7)
     }
     #[doc = "Bit 9 - The bit is used to clear autoload buffer in icache."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_buffer_clear(
         &mut self,
     ) -> ICACHE_AUTOLOAD_BUFFER_CLEAR_W<ICACHE_AUTOLOAD_CTRL_SPEC> {
diff --git a/esp32s3/src/extmem/icache_autoload_sct0_addr.rs b/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
index 5a873714fd..4e4badc0cb 100644
--- a/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct0_addr(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT0_ADDR_W<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/icache_autoload_sct0_size.rs b/esp32s3/src/extmem/icache_autoload_sct0_size.rs
index 81bb8be9c4..c7de23f82a 100644
--- a/esp32s3/src/extmem/icache_autoload_sct0_size.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct0_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct0_size(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT0_SIZE_W<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/icache_autoload_sct1_addr.rs b/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
index a69bdddb38..8c8efa7eb5 100644
--- a/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct1_addr(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT1_ADDR_W<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/icache_autoload_sct1_size.rs b/esp32s3/src/extmem/icache_autoload_sct1_size.rs
index 5fc624c355..d478ae9084 100644
--- a/esp32s3/src/extmem/icache_autoload_sct1_size.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct1_size.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_autoload_sct1_size(
         &mut self,
     ) -> ICACHE_AUTOLOAD_SCT1_SIZE_W<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/icache_ctrl.rs b/esp32s3/src/extmem/icache_ctrl.rs
index 0f29c56d5d..7420c35153 100644
--- a/esp32s3/src/extmem/icache_ctrl.rs
+++ b/esp32s3/src/extmem/icache_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W<ICACHE_CTRL_SPEC> {
         ICACHE_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_way_mode(&mut self) -> ICACHE_WAY_MODE_W<ICACHE_CTRL_SPEC> {
         ICACHE_WAY_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_size_mode(&mut self) -> ICACHE_SIZE_MODE_W<ICACHE_CTRL_SPEC> {
         ICACHE_SIZE_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_blocksize_mode(&mut self) -> ICACHE_BLOCKSIZE_MODE_W<ICACHE_CTRL_SPEC> {
         ICACHE_BLOCKSIZE_MODE_W::new(self, 3)
     }
diff --git a/esp32s3/src/extmem/icache_ctrl1.rs b/esp32s3/src/extmem/icache_ctrl1.rs
index 5b055bf5e3..613dc1c7a6 100644
--- a/esp32s3/src/extmem/icache_ctrl1.rs
+++ b/esp32s3/src/extmem/icache_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_shut_core0_bus(&mut self) -> ICACHE_SHUT_CORE0_BUS_W<ICACHE_CTRL1_SPEC> {
         ICACHE_SHUT_CORE0_BUS_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_shut_core1_bus(&mut self) -> ICACHE_SHUT_CORE1_BUS_W<ICACHE_CTRL1_SPEC> {
         ICACHE_SHUT_CORE1_BUS_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/icache_freeze.rs b/esp32s3/src/extmem/icache_freeze.rs
index 5cd7830a92..e612af1f88 100644
--- a/esp32s3/src/extmem/icache_freeze.rs
+++ b/esp32s3/src/extmem/icache_freeze.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<ICACHE_FREEZE_SPEC> {
         ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<ICACHE_FREEZE_SPEC> {
         MODE_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/icache_lock_addr.rs b/esp32s3/src/extmem/icache_lock_addr.rs
index f685cd581a..27e59a80f1 100644
--- a/esp32s3/src/extmem/icache_lock_addr.rs
+++ b/esp32s3/src/extmem/icache_lock_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_lock_addr(&mut self) -> ICACHE_LOCK_ADDR_W<ICACHE_LOCK_ADDR_SPEC> {
         ICACHE_LOCK_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_lock_ctrl.rs b/esp32s3/src/extmem/icache_lock_ctrl.rs
index c45c4dcf56..99e3da8c0c 100644
--- a/esp32s3/src/extmem/icache_lock_ctrl.rs
+++ b/esp32s3/src/extmem/icache_lock_ctrl.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_lock_ena(&mut self) -> ICACHE_LOCK_ENA_W<ICACHE_LOCK_CTRL_SPEC> {
         ICACHE_LOCK_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_unlock_ena(&mut self) -> ICACHE_UNLOCK_ENA_W<ICACHE_LOCK_CTRL_SPEC> {
         ICACHE_UNLOCK_ENA_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/icache_lock_size.rs b/esp32s3/src/extmem/icache_lock_size.rs
index 399fa8deee..000e23ab1e 100644
--- a/esp32s3/src/extmem/icache_lock_size.rs
+++ b/esp32s3/src/extmem/icache_lock_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_lock_size(&mut self) -> ICACHE_LOCK_SIZE_W<ICACHE_LOCK_SIZE_SPEC> {
         ICACHE_LOCK_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_preload_addr.rs b/esp32s3/src/extmem/icache_preload_addr.rs
index 03bd8693e3..c820054142 100644
--- a/esp32s3/src/extmem/icache_preload_addr.rs
+++ b/esp32s3/src/extmem/icache_preload_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_addr(&mut self) -> ICACHE_PRELOAD_ADDR_W<ICACHE_PRELOAD_ADDR_SPEC> {
         ICACHE_PRELOAD_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_preload_ctrl.rs b/esp32s3/src/extmem/icache_preload_ctrl.rs
index 27985adcfa..38ab00dd88 100644
--- a/esp32s3/src/extmem/icache_preload_ctrl.rs
+++ b/esp32s3/src/extmem/icache_preload_ctrl.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_ena(&mut self) -> ICACHE_PRELOAD_ENA_W<ICACHE_PRELOAD_CTRL_SPEC> {
         ICACHE_PRELOAD_ENA_W::new(self, 0)
     }
     #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 1: descending, 0: ascending."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_order(&mut self) -> ICACHE_PRELOAD_ORDER_W<ICACHE_PRELOAD_CTRL_SPEC> {
         ICACHE_PRELOAD_ORDER_W::new(self, 2)
     }
diff --git a/esp32s3/src/extmem/icache_preload_size.rs b/esp32s3/src/extmem/icache_preload_size.rs
index a031fa8f04..d64257db6e 100644
--- a/esp32s3/src/extmem/icache_preload_size.rs
+++ b/esp32s3/src/extmem/icache_preload_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_size(&mut self) -> ICACHE_PRELOAD_SIZE_W<ICACHE_PRELOAD_SIZE_SPEC> {
         ICACHE_PRELOAD_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_prelock_ctrl.rs b/esp32s3/src/extmem/icache_prelock_ctrl.rs
index 0de1163ce6..43b76d48af 100644
--- a/esp32s3/src/extmem/icache_prelock_ctrl.rs
+++ b/esp32s3/src/extmem/icache_prelock_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct0_en(&mut self) -> ICACHE_PRELOCK_SCT0_EN_W<ICACHE_PRELOCK_CTRL_SPEC> {
         ICACHE_PRELOCK_SCT0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct1_en(&mut self) -> ICACHE_PRELOCK_SCT1_EN_W<ICACHE_PRELOCK_CTRL_SPEC> {
         ICACHE_PRELOCK_SCT1_EN_W::new(self, 1)
     }
diff --git a/esp32s3/src/extmem/icache_prelock_sct0_addr.rs b/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
index a62539bfed..10b878c4cd 100644
--- a/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct0_addr(
         &mut self,
     ) -> ICACHE_PRELOCK_SCT0_ADDR_W<ICACHE_PRELOCK_SCT0_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/icache_prelock_sct1_addr.rs b/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
index ece0baded4..17ba6000de 100644
--- a/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct1_addr(
         &mut self,
     ) -> ICACHE_PRELOCK_SCT1_ADDR_W<ICACHE_PRELOCK_SCT1_ADDR_SPEC> {
diff --git a/esp32s3/src/extmem/icache_prelock_sct_size.rs b/esp32s3/src/extmem/icache_prelock_sct_size.rs
index a178e2b645..bd12091491 100644
--- a/esp32s3/src/extmem/icache_prelock_sct_size.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct_size.rs
@@ -34,7 +34,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct1_size(
         &mut self,
     ) -> ICACHE_PRELOCK_SCT1_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
@@ -42,7 +41,6 @@ impl W {
     }
     #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_prelock_sct0_size(
         &mut self,
     ) -> ICACHE_PRELOCK_SCT0_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
diff --git a/esp32s3/src/extmem/icache_sync_addr.rs b/esp32s3/src/extmem/icache_sync_addr.rs
index 6f8c7f226a..5af0978a28 100644
--- a/esp32s3/src/extmem/icache_sync_addr.rs
+++ b/esp32s3/src/extmem/icache_sync_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_addr(&mut self) -> ICACHE_SYNC_ADDR_W<ICACHE_SYNC_ADDR_SPEC> {
         ICACHE_SYNC_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_sync_ctrl.rs b/esp32s3/src/extmem/icache_sync_ctrl.rs
index 928803e71c..416083e743 100644
--- a/esp32s3/src/extmem/icache_sync_ctrl.rs
+++ b/esp32s3/src/extmem/icache_sync_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_invalidate_ena(&mut self) -> ICACHE_INVALIDATE_ENA_W<ICACHE_SYNC_CTRL_SPEC> {
         ICACHE_INVALIDATE_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_sync_size.rs b/esp32s3/src/extmem/icache_sync_size.rs
index a054a9e795..45a7636354 100644
--- a/esp32s3/src/extmem/icache_sync_size.rs
+++ b/esp32s3/src/extmem/icache_sync_size.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_size(&mut self) -> ICACHE_SYNC_SIZE_W<ICACHE_SYNC_SIZE_SPEC> {
         ICACHE_SYNC_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/extmem/icache_tag_power_ctrl.rs b/esp32s3/src/extmem/icache_tag_power_ctrl.rs
index 6c0a388b62..d2b2a17294 100644
--- a/esp32s3/src/extmem/icache_tag_power_ctrl.rs
+++ b/esp32s3/src/extmem/icache_tag_power_ctrl.rs
@@ -44,7 +44,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
-    #[must_use]
     pub fn icache_tag_mem_force_on(
         &mut self,
     ) -> ICACHE_TAG_MEM_FORCE_ON_W<ICACHE_TAG_POWER_CTRL_SPEC> {
@@ -52,7 +51,6 @@ impl W {
     }
     #[doc = "Bit 1 - The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_tag_mem_force_pd(
         &mut self,
     ) -> ICACHE_TAG_MEM_FORCE_PD_W<ICACHE_TAG_POWER_CTRL_SPEC> {
@@ -60,7 +58,6 @@ impl W {
     }
     #[doc = "Bit 2 - The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_tag_mem_force_pu(
         &mut self,
     ) -> ICACHE_TAG_MEM_FORCE_PU_W<ICACHE_TAG_POWER_CTRL_SPEC> {
diff --git a/esp32s3/src/fe/gen_ctrl.rs b/esp32s3/src/fe/gen_ctrl.rs
index b0d00836ae..00fcd0ce83 100644
--- a/esp32s3/src/fe/gen_ctrl.rs
+++ b/esp32s3/src/fe/gen_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 4 - Force Power Down for IQ Estimation"]
     #[inline(always)]
-    #[must_use]
     pub fn iq_est_force_pd(&mut self) -> IQ_EST_FORCE_PD_W<GEN_CTRL_SPEC> {
         IQ_EST_FORCE_PD_W::new(self, 4)
     }
     #[doc = "Bit 5 - Force Power Up for IQ Estimation"]
     #[inline(always)]
-    #[must_use]
     pub fn iq_est_force_pu(&mut self) -> IQ_EST_FORCE_PU_W<GEN_CTRL_SPEC> {
         IQ_EST_FORCE_PU_W::new(self, 5)
     }
diff --git a/esp32s3/src/fe2/tx_interp_ctrl.rs b/esp32s3/src/fe2/tx_interp_ctrl.rs
index c019b49ecc..badc771101 100644
--- a/esp32s3/src/fe2/tx_interp_ctrl.rs
+++ b/esp32s3/src/fe2/tx_interp_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9 - Force Power Down field"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_inf_force_pd(&mut self) -> TX_INF_FORCE_PD_W<TX_INTERP_CTRL_SPEC> {
         TX_INF_FORCE_PD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Force Power Up field"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_inf_force_pu(&mut self) -> TX_INF_FORCE_PU_W<TX_INTERP_CTRL_SPEC> {
         TX_INF_FORCE_PU_W::new(self, 10)
     }
diff --git a/esp32s3/src/generic.rs b/esp32s3/src/generic.rs
index d57106cb27..a7cb020aef 100644
--- a/esp32s3/src/generic.rs
+++ b/esp32s3/src/generic.rs
@@ -524,18 +524,60 @@ impl<REG: Resettable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " In the latter case, other fields will be set to their reset value."]
     #[inline(always)]
-    pub fn write<F>(&self, f: F)
+    pub fn write<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes bits to a `Writable` register and produce a value."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[doc = ""]
+    #[doc = " Values can be returned from the closure:"]
+    #[doc = " ```ignore"]
+    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn from_write<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Writable> Reg<REG> {
@@ -547,17 +589,37 @@ impl<REG: Writable> Reg<REG> {
     #[doc = ""]
     #[doc = " Unsafe to use with registers which don't allow to write 0."]
     #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F)
+    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::Ux::default(),
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes 0 to a `Writable` register and produces a value."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable + Writable> Reg<REG> {
@@ -587,25 +649,75 @@ impl<REG: Readable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " Other fields will have the value they had before the call to `modify`."]
     #[inline(always)]
-    pub fn modify<F>(&self, f: F)
+    pub fn modify<F>(&self, f: F) -> REG::Ux
     where
         for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
     {
         let bits = self.register.get();
-        self.register.set(
-            f(
-                &R {
-                    bits,
-                    _reg: marker::PhantomData,
-                },
-                &mut W {
-                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                    _reg: marker::PhantomData,
-                },
-            )
-            .bits,
+        let value = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut W {
+                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            },
+        )
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Modifies the contents of the register by reading and then writing it"]
+    #[doc = " and produces a value."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.modify(|r, w| {"]
+    #[doc = "     let new_bits = r.bits() | 3;"]
+    #[doc = "     unsafe {"]
+    #[doc = "         w.bits(new_bits);"]
+    #[doc = "     }"]
+    #[doc = ""]
+    #[doc = "     new_bits"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn from_modify<F, T>(&self, f: F) -> T
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+    {
+        let bits = self.register.get();
+        let mut writer = W {
+            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut writer,
         );
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
diff --git a/esp32s3/src/generic/raw.rs b/esp32s3/src/generic/raw.rs
index 81f5779524..d60a23a7cc 100644
--- a/esp32s3/src/generic/raw.rs
+++ b/esp32s3/src/generic/raw.rs
@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
         }
     }
 }
+#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
         }
     }
 }
+#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s3/src/gpio/bt_select.rs b/esp32s3/src/gpio/bt_select.rs
index d7b1c5cbd7..1207e6041d 100644
--- a/esp32s3/src/gpio/bt_select.rs
+++ b/esp32s3/src/gpio/bt_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_sel(&mut self) -> BT_SEL_W<BT_SELECT_SPEC> {
         BT_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/clock_gate.rs b/esp32s3/src/gpio/clock_gate.rs
index dc08365f35..fcb38c1911 100644
--- a/esp32s3/src/gpio/clock_gate.rs
+++ b/esp32s3/src/gpio/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable.rs b/esp32s3/src/gpio/enable.rs
index f88ac51742..ec0fef1ced 100644
--- a/esp32s3/src/gpio/enable.rs
+++ b/esp32s3/src/gpio/enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable1.rs b/esp32s3/src/gpio/enable1.rs
index 24c17fb387..4766ebfb43 100644
--- a/esp32s3/src/gpio/enable1.rs
+++ b/esp32s3/src/gpio/enable1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO output enable register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<ENABLE1_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable1_w1tc.rs b/esp32s3/src/gpio/enable1_w1tc.rs
index 6300cd3707..66d7c1c2f1 100644
--- a/esp32s3/src/gpio/enable1_w1tc.rs
+++ b/esp32s3/src/gpio/enable1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO output enable clear register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_w1tc(&mut self) -> ENABLE1_W1TC_W<ENABLE1_W1TC_SPEC> {
         ENABLE1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable1_w1ts.rs b/esp32s3/src/gpio/enable1_w1ts.rs
index 1aa292c867..6fb4bde334 100644
--- a/esp32s3/src/gpio/enable1_w1ts.rs
+++ b/esp32s3/src/gpio/enable1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO output enable set register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn enable1_w1ts(&mut self) -> ENABLE1_W1TS_W<ENABLE1_W1TS_SPEC> {
         ENABLE1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable_w1tc.rs b/esp32s3/src/gpio/enable_w1tc.rs
index 2430ef3d46..2b4f6b45f4 100644
--- a/esp32s3/src/gpio/enable_w1tc.rs
+++ b/esp32s3/src/gpio/enable_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable clear register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/enable_w1ts.rs b/esp32s3/src/gpio/enable_w1ts.rs
index 6078292c22..b282747b2c 100644
--- a/esp32s3/src/gpio/enable_w1ts.rs
+++ b/esp32s3/src/gpio/enable_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable set register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1ts(&mut self) -> ENABLE_W1TS_W<ENABLE_W1TS_SPEC> {
         ENABLE_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/func_in_sel_cfg.rs b/esp32s3/src/gpio/func_in_sel_cfg.rs
index 5172202aa6..8e71235145 100644
--- a/esp32s3/src/gpio/func_in_sel_cfg.rs
+++ b/esp32s3/src/gpio/func_in_sel_cfg.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - set this value: s=0-53: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
-    #[must_use]
     pub fn in_sel(&mut self) -> IN_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_SEL_W::new(self, 0)
     }
     #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."]
     #[inline(always)]
-    #[must_use]
     pub fn in_inv_sel(&mut self) -> IN_INV_SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         IN_INV_SEL_W::new(self, 6)
     }
     #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<FUNC_IN_SEL_CFG_SPEC> {
         SEL_W::new(self, 7)
     }
diff --git a/esp32s3/src/gpio/func_out_sel_cfg.rs b/esp32s3/src/gpio/func_out_sel_cfg.rs
index 6c364aa736..554163795a 100644
--- a/esp32s3/src/gpio/func_out_sel_cfg.rs
+++ b/esp32s3/src/gpio/func_out_sel_cfg.rs
@@ -2,9 +2,9 @@
 pub type R = crate::R<FUNC_OUT_SEL_CFG_SPEC>;
 #[doc = "Register `FUNC%s_OUT_SEL_CFG` writer"]
 pub type W = crate::W<FUNC_OUT_SEL_CFG_SPEC>;
-#[doc = "Field `OUT_SEL` reader - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
+#[doc = "Field `OUT_SEL` reader - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
 pub type OUT_SEL_R = crate::FieldReader<u16>;
-#[doc = "Field `OUT_SEL` writer - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
+#[doc = "Field `OUT_SEL` writer - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
 pub type OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
 #[doc = "Field `INV_SEL` reader - set this bit to invert output signal.1:invert.0:not invert."]
 pub type INV_SEL_R = crate::BitReader;
@@ -19,7 +19,7 @@ pub type OEN_INV_SEL_R = crate::BitReader;
 #[doc = "Field `OEN_INV_SEL` writer - set this bit to invert output enable signal.1:invert.0:not invert."]
 pub type OEN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
+    #[doc = "Bits 0:8 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
     pub fn out_sel(&self) -> OUT_SEL_R {
         OUT_SEL_R::new((self.bits & 0x01ff) as u16)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
+    #[doc = "Bits 0:8 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn out_sel(&mut self) -> OUT_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OUT_SEL_W::new(self, 0)
     }
     #[doc = "Bit 9 - set this bit to invert output signal.1:invert.0:not invert."]
     #[inline(always)]
-    #[must_use]
     pub fn inv_sel(&mut self) -> INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         INV_SEL_W::new(self, 9)
     }
     #[doc = "Bit 10 - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn oen_sel(&mut self) -> OEN_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_SEL_W::new(self, 10)
     }
     #[doc = "Bit 11 - set this bit to invert output enable signal.1:invert.0:not invert."]
     #[inline(always)]
-    #[must_use]
     pub fn oen_inv_sel(&mut self) -> OEN_INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
         OEN_INV_SEL_W::new(self, 11)
     }
diff --git a/esp32s3/src/gpio/in1.rs b/esp32s3/src/gpio/in1.rs
index 49eb9de7e1..18ef519557 100644
--- a/esp32s3/src/gpio/in1.rs
+++ b/esp32s3/src/gpio/in1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO input register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn data_next(&mut self) -> DATA_NEXT_W<IN1_SPEC> {
         DATA_NEXT_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/in_.rs b/esp32s3/src/gpio/in_.rs
index 014742f43a..98fd5bd0e6 100644
--- a/esp32s3/src/gpio/in_.rs
+++ b/esp32s3/src/gpio/in_.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO input register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn data_next(&mut self) -> DATA_NEXT_W<IN_SPEC> {
         DATA_NEXT_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out.rs b/esp32s3/src/gpio/out.rs
index 4e8b7d0b21..f52f2a8c9e 100644
--- a/esp32s3/src/gpio/out.rs
+++ b/esp32s3/src/gpio/out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn data_orig(&mut self) -> DATA_ORIG_W<OUT_SPEC> {
         DATA_ORIG_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out1.rs b/esp32s3/src/gpio/out1.rs
index de373d2cae..0fac9b51cf 100644
--- a/esp32s3/src/gpio/out1.rs
+++ b/esp32s3/src/gpio/out1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO output register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn data_orig(&mut self) -> DATA_ORIG_W<OUT1_SPEC> {
         DATA_ORIG_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out1_w1tc.rs b/esp32s3/src/gpio/out1_w1tc.rs
index b2bfd08d06..d3b8a94440 100644
--- a/esp32s3/src/gpio/out1_w1tc.rs
+++ b/esp32s3/src/gpio/out1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO output clear register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn out1_w1tc(&mut self) -> OUT1_W1TC_W<OUT1_W1TC_SPEC> {
         OUT1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out1_w1ts.rs b/esp32s3/src/gpio/out1_w1ts.rs
index a078ba4cdd..3f70f05b0d 100644
--- a/esp32s3/src/gpio/out1_w1ts.rs
+++ b/esp32s3/src/gpio/out1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO output set register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn out1_w1ts(&mut self) -> OUT1_W1TS_W<OUT1_W1TS_SPEC> {
         OUT1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out_w1tc.rs b/esp32s3/src/gpio/out_w1tc.rs
index a0260c53ec..a4a932319a 100644
--- a/esp32s3/src/gpio/out_w1tc.rs
+++ b/esp32s3/src/gpio/out_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO output clear register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn out_w1tc(&mut self) -> OUT_W1TC_W<OUT_W1TC_SPEC> {
         OUT_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/out_w1ts.rs b/esp32s3/src/gpio/out_w1ts.rs
index 70c7af6b7e..33b86ce3b3 100644
--- a/esp32s3/src/gpio/out_w1ts.rs
+++ b/esp32s3/src/gpio/out_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<OUT_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO output set register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn out_w1ts(&mut self) -> OUT_W1TS_W<OUT_W1TS_SPEC> {
         OUT_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/pin.rs b/esp32s3/src/gpio/pin.rs
index 28a30e66af..5bad7dea08 100644
--- a/esp32s3/src/gpio/pin.rs
+++ b/esp32s3/src/gpio/pin.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn sync2_bypass(&mut self) -> SYNC2_BYPASS_W<PIN_SPEC> {
         SYNC2_BYPASS_W::new(self, 0)
     }
     #[doc = "Bit 2 - set this bit to select pad driver. 1:open-drain. 0:normal."]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn sync1_bypass(&mut self) -> SYNC1_BYPASS_W<PIN_SPEC> {
         SYNC1_BYPASS_W::new(self, 3)
     }
     #[doc = "Bits 7:9 - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
         INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
         WAKEUP_ENABLE_W::new(self, 10)
     }
     #[doc = "Bits 11:12 - reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn config(&mut self) -> CONFIG_W<PIN_SPEC> {
         CONFIG_W::new(self, 11)
     }
     #[doc = "Bits 13:17 - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<PIN_SPEC> {
         INT_ENA_W::new(self, 13)
     }
diff --git a/esp32s3/src/gpio/reg_date.rs b/esp32s3/src/gpio/reg_date.rs
index 8e5d5b504d..cb3551f992 100644
--- a/esp32s3/src/gpio/reg_date.rs
+++ b/esp32s3/src/gpio/reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn reg_date(&mut self) -> REG_DATE_W<REG_DATE_SPEC> {
         REG_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/sdio_select.rs b/esp32s3/src/gpio/sdio_select.rs
index 4099035e5f..20bb242683 100644
--- a/esp32s3/src/gpio/sdio_select.rs
+++ b/esp32s3/src/gpio/sdio_select.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_sel(&mut self) -> SDIO_SEL_W<SDIO_SELECT_SPEC> {
         SDIO_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status.rs b/esp32s3/src/gpio/status.rs
index c98aa95035..d09aa5f9bd 100644
--- a/esp32s3/src/gpio/status.rs
+++ b/esp32s3/src/gpio/status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt(&mut self) -> INTERRUPT_W<STATUS_SPEC> {
         INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status1.rs b/esp32s3/src/gpio/status1.rs
index 9076b9933f..75ffb9e47e 100644
--- a/esp32s3/src/gpio/status1.rs
+++ b/esp32s3/src/gpio/status1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - GPIO interrupt status register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt(&mut self) -> INTERRUPT_W<STATUS1_SPEC> {
         INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status1_w1tc.rs b/esp32s3/src/gpio/status1_w1tc.rs
index 352c92a65f..a468cc75c3 100644
--- a/esp32s3/src/gpio/status1_w1tc.rs
+++ b/esp32s3/src/gpio/status1_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO interrupt status clear register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn status1_w1tc(&mut self) -> STATUS1_W1TC_W<STATUS1_W1TC_SPEC> {
         STATUS1_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status1_w1ts.rs b/esp32s3/src/gpio/status1_w1ts.rs
index 66a43cca16..2d00c925b1 100644
--- a/esp32s3/src/gpio/status1_w1ts.rs
+++ b/esp32s3/src/gpio/status1_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:21 - GPIO interrupt status set register for GPIO32-53"]
     #[inline(always)]
-    #[must_use]
     pub fn status1_w1ts(&mut self) -> STATUS1_W1TS_W<STATUS1_W1TS_SPEC> {
         STATUS1_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status_w1tc.rs b/esp32s3/src/gpio/status_w1tc.rs
index 823616fd36..2d8a58ef2a 100644
--- a/esp32s3/src/gpio/status_w1tc.rs
+++ b/esp32s3/src/gpio/status_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status clear register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn status_w1tc(&mut self) -> STATUS_W1TC_W<STATUS_W1TC_SPEC> {
         STATUS_W1TC_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio/status_w1ts.rs b/esp32s3/src/gpio/status_w1ts.rs
index 0baee1a8e9..b915c312f0 100644
--- a/esp32s3/src/gpio/status_w1ts.rs
+++ b/esp32s3/src/gpio/status_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status set register for GPIO0-31"]
     #[inline(always)]
-    #[must_use]
     pub fn status_w1ts(&mut self) -> STATUS_W1TS_W<STATUS_W1TS_SPEC> {
         STATUS_W1TS_W::new(self, 0)
     }
diff --git a/esp32s3/src/gpio_sd/clock_gate.rs b/esp32s3/src/gpio_sd/clock_gate.rs
index c260e2a103..49ae0f928c 100644
--- a/esp32s3/src/gpio_sd/clock_gate.rs
+++ b/esp32s3/src/gpio_sd/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/gpio_sd/sigmadelta.rs b/esp32s3/src/gpio_sd/sigmadelta.rs
index 38e02d27b9..aed653d231 100644
--- a/esp32s3/src/gpio_sd/sigmadelta.rs
+++ b/esp32s3/src/gpio_sd/sigmadelta.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
-    #[must_use]
     pub fn in_(&mut self) -> IN_W<SIGMADELTA_SPEC> {
         IN_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<SIGMADELTA_SPEC> {
         PRESCALE_W::new(self, 8)
     }
diff --git a/esp32s3/src/gpio_sd/sigmadelta_misc.rs b/esp32s3/src/gpio_sd/sigmadelta_misc.rs
index 4ab13a96f5..3f7dca6ec7 100644
--- a/esp32s3/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32s3/src/gpio_sd/sigmadelta_misc.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
-    #[must_use]
     pub fn function_clk_en(&mut self) -> FUNCTION_CLK_EN_W<SIGMADELTA_MISC_SPEC> {
         FUNCTION_CLK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_swap(&mut self) -> SPI_SWAP_W<SIGMADELTA_MISC_SPEC> {
         SPI_SWAP_W::new(self, 31)
     }
diff --git a/esp32s3/src/gpio_sd/version.rs b/esp32s3/src/gpio_sd/version.rs
index 103f2cef59..5fe213d85f 100644
--- a/esp32s3/src/gpio_sd/version.rs
+++ b/esp32s3/src/gpio_sd/version.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W<VERSION_SPEC> {
         GPIO_SD_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/date.rs b/esp32s3/src/hmac/date.rs
index c0b9917083..92e7e72977 100644
--- a/esp32s3/src/hmac/date.rs
+++ b/esp32s3/src/hmac/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Hmac date information/ hmac version information."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/one_block.rs b/esp32s3/src/hmac/one_block.rs
index b43566689f..b4035ad8b6 100644
--- a/esp32s3/src/hmac/one_block.rs
+++ b/esp32s3/src/hmac/one_block.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ONE_BLOCK_SPEC> {
 impl W {
     #[doc = "Bit 0 - Don't have to do padding."]
     #[inline(always)]
-    #[must_use]
     pub fn set_one_block(&mut self) -> SET_ONE_BLOCK_W<ONE_BLOCK_SPEC> {
         SET_ONE_BLOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_invalidate_ds.rs b/esp32s3/src/hmac/set_invalidate_ds.rs
index 111bcc4282..407f746e9e 100644
--- a/esp32s3/src/hmac/set_invalidate_ds.rs
+++ b/esp32s3/src/hmac/set_invalidate_ds.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_INVALIDATE_DS_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clear result from hmac downstream DS."]
     #[inline(always)]
-    #[must_use]
     pub fn set_invalidate_ds(&mut self) -> SET_INVALIDATE_DS_W<SET_INVALIDATE_DS_SPEC> {
         SET_INVALIDATE_DS_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_invalidate_jtag.rs b/esp32s3/src/hmac/set_invalidate_jtag.rs
index d3506d5640..82a7427c4a 100644
--- a/esp32s3/src/hmac/set_invalidate_jtag.rs
+++ b/esp32s3/src/hmac/set_invalidate_jtag.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_INVALIDATE_JTAG_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clear result from hmac downstream JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn set_invalidate_jtag(&mut self) -> SET_INVALIDATE_JTAG_W<SET_INVALIDATE_JTAG_SPEC> {
         SET_INVALIDATE_JTAG_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_message_end.rs b/esp32s3/src/hmac/set_message_end.rs
index 3ae43ef9c8..7006fb27f4 100644
--- a/esp32s3/src/hmac/set_message_end.rs
+++ b/esp32s3/src/hmac/set_message_end.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_END_SPEC> {
 impl W {
     #[doc = "Bit 0 - Start hardware padding."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_end(&mut self) -> SET_TEXT_END_W<SET_MESSAGE_END_SPEC> {
         SET_TEXT_END_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_message_ing.rs b/esp32s3/src/hmac/set_message_ing.rs
index c325d92c32..663dbe540f 100644
--- a/esp32s3/src/hmac/set_message_ing.rs
+++ b/esp32s3/src/hmac/set_message_ing.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_ING_SPEC> {
 impl W {
     #[doc = "Bit 0 - Continue typical hmac."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_ing(&mut self) -> SET_TEXT_ING_W<SET_MESSAGE_ING_SPEC> {
         SET_TEXT_ING_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_message_one.rs b/esp32s3/src/hmac/set_message_one.rs
index 8ef37f11db..d32eb2efd1 100644
--- a/esp32s3/src/hmac/set_message_one.rs
+++ b/esp32s3/src/hmac/set_message_one.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_ONE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Call SHA to calculate one message block."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_one(&mut self) -> SET_TEXT_ONE_W<SET_MESSAGE_ONE_SPEC> {
         SET_TEXT_ONE_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_message_pad.rs b/esp32s3/src/hmac/set_message_pad.rs
index 8739d11add..8877ee730d 100644
--- a/esp32s3/src/hmac/set_message_pad.rs
+++ b/esp32s3/src/hmac/set_message_pad.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_MESSAGE_PAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Start software padding."]
     #[inline(always)]
-    #[must_use]
     pub fn set_text_pad(&mut self) -> SET_TEXT_PAD_W<SET_MESSAGE_PAD_SPEC> {
         SET_TEXT_PAD_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_para_finish.rs b/esp32s3/src/hmac/set_para_finish.rs
index 66cbaa057f..15257695f6 100644
--- a/esp32s3/src/hmac/set_para_finish.rs
+++ b/esp32s3/src/hmac/set_para_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - Finish hmac configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn set_para_end(&mut self) -> SET_PARA_END_W<SET_PARA_FINISH_SPEC> {
         SET_PARA_END_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_para_key.rs b/esp32s3/src/hmac/set_para_key.rs
index 0bbde55d9d..fe4e62547a 100644
--- a/esp32s3/src/hmac/set_para_key.rs
+++ b/esp32s3/src/hmac/set_para_key.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_KEY_SPEC> {
 impl W {
     #[doc = "Bits 0:2 - Set hmac parameter key."]
     #[inline(always)]
-    #[must_use]
     pub fn key_set(&mut self) -> KEY_SET_W<SET_PARA_KEY_SPEC> {
         KEY_SET_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_para_purpose.rs b/esp32s3/src/hmac/set_para_purpose.rs
index eafe6bc3e7..fc78aa1598 100644
--- a/esp32s3/src/hmac/set_para_purpose.rs
+++ b/esp32s3/src/hmac/set_para_purpose.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_PARA_PURPOSE_SPEC> {
 impl W {
     #[doc = "Bits 0:3 - Set hmac parameter purpose."]
     #[inline(always)]
-    #[must_use]
     pub fn purpose_set(&mut self) -> PURPOSE_SET_W<SET_PARA_PURPOSE_SPEC> {
         PURPOSE_SET_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_result_finish.rs b/esp32s3/src/hmac/set_result_finish.rs
index ed02cedec4..430f5290fb 100644
--- a/esp32s3/src/hmac/set_result_finish.rs
+++ b/esp32s3/src/hmac/set_result_finish.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_RESULT_FINISH_SPEC> {
 impl W {
     #[doc = "Bit 0 - After read result from upstream, then let hmac back to idle."]
     #[inline(always)]
-    #[must_use]
     pub fn set_result_end(&mut self) -> SET_RESULT_END_W<SET_RESULT_FINISH_SPEC> {
         SET_RESULT_END_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/set_start.rs b/esp32s3/src/hmac/set_start.rs
index 293497a4fd..e8e873ce29 100644
--- a/esp32s3/src/hmac/set_start.rs
+++ b/esp32s3/src/hmac/set_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SET_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Start hmac operation."]
     #[inline(always)]
-    #[must_use]
     pub fn set_start(&mut self) -> SET_START_W<SET_START_SPEC> {
         SET_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/soft_jtag_ctrl.rs b/esp32s3/src/hmac/soft_jtag_ctrl.rs
index 9c7ec8ae3d..368f294e81 100644
--- a/esp32s3/src/hmac/soft_jtag_ctrl.rs
+++ b/esp32s3/src/hmac/soft_jtag_ctrl.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<SOFT_JTAG_CTRL_SPEC> {
 impl W {
     #[doc = "Bit 0 - Turn on JTAG verification."]
     #[inline(always)]
-    #[must_use]
     pub fn soft_jtag_ctrl(&mut self) -> SOFT_JTAG_CTRL_W<SOFT_JTAG_CTRL_SPEC> {
         SOFT_JTAG_CTRL_W::new(self, 0)
     }
diff --git a/esp32s3/src/hmac/wr_jtag.rs b/esp32s3/src/hmac/wr_jtag.rs
index 98c5adab47..e1bfccc0b9 100644
--- a/esp32s3/src/hmac/wr_jtag.rs
+++ b/esp32s3/src/hmac/wr_jtag.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WR_JTAG_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - 32-bit of key to be compared."]
     #[inline(always)]
-    #[must_use]
     pub fn wr_jtag(&mut self) -> WR_JTAG_W<WR_JTAG_SPEC> {
         WR_JTAG_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/clk_conf.rs b/esp32s3/src/i2c0/clk_conf.rs
index 8232389a17..4a33df6cf5 100644
--- a/esp32s3/src/i2c0/clk_conf.rs
+++ b/esp32s3/src/i2c0/clk_conf.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<CLK_CONF_SPEC> {
         SCLK_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<CLK_CONF_SPEC> {
         SCLK_DIV_A_W::new(self, 8)
     }
     #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<CLK_CONF_SPEC> {
         SCLK_DIV_B_W::new(self, 14)
     }
     #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL;1-CLK_8MHz."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_sel(&mut self) -> SCLK_SEL_W<CLK_CONF_SPEC> {
         SCLK_SEL_W::new(self, 20)
     }
     #[doc = "Bit 21 - The clock switch for i2c module"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<CLK_CONF_SPEC> {
         SCLK_ACTIVE_W::new(self, 21)
     }
diff --git a/esp32s3/src/i2c0/comd.rs b/esp32s3/src/i2c0/comd.rs
index bb55c194e6..7dbcd9c95a 100644
--- a/esp32s3/src/i2c0/comd.rs
+++ b/esp32s3/src/i2c0/comd.rs
@@ -170,37 +170,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Number of bytes to be sent or received for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_num(&mut self) -> BYTE_NUM_W<COMD_SPEC> {
         BYTE_NUM_W::new(self, 0)
     }
     #[doc = "Bit 8 - Acknowledge check enable for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_check_en(&mut self) -> ACK_CHECK_EN_W<COMD_SPEC> {
         ACK_CHECK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Acknowledge expected for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_exp(&mut self) -> ACK_EXP_W<COMD_SPEC> {
         ACK_EXP_W::new(self, 9)
     }
     #[doc = "Bit 10 - Acknowledge value for command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_value(&mut self) -> ACK_VALUE_W<COMD_SPEC> {
         ACK_VALUE_W::new(self, 10)
     }
     #[doc = "Bits 11:13 - Opcode part of command %s."]
     #[inline(always)]
-    #[must_use]
     pub fn opcode(&mut self) -> OPCODE_W<COMD_SPEC> {
         OPCODE_W::new(self, 11)
     }
     #[doc = "Bit 31 - When command 0 is done in I2C Master mode, this bit changes to high level."]
     #[inline(always)]
-    #[must_use]
     pub fn command_done(&mut self) -> COMMAND_DONE_W<COMD_SPEC> {
         COMMAND_DONE_W::new(self, 31)
     }
diff --git a/esp32s3/src/i2c0/ctr.rs b/esp32s3/src/i2c0/ctr.rs
index c83b48c9d6..ec45213987 100644
--- a/esp32s3/src/i2c0/ctr.rs
+++ b/esp32s3/src/i2c0/ctr.rs
@@ -140,91 +140,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 0: direct output; 1: open drain output."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - 0: direct output; 1: open drain output."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
     #[inline(always)]
-    #[must_use]
     pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
         SAMPLE_SCL_LEVEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
         RX_FULL_ACK_LEVEL_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave."]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
         MS_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
         TRANS_START_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit; 0: send data from the most significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
         TX_LSB_FIRST_W::new(self, 6)
     }
     #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit; 0: receive data from the most significant bit."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
         RX_LSB_FIRST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
         CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
         ARBITRATION_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - This register is used to reset the scl FMS."]
     #[inline(always)]
-    #[must_use]
     pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
         FSM_RST_W::new(self, 10)
     }
     #[doc = "Bit 11 - synchronization bit"]
     #[inline(always)]
-    #[must_use]
     pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<CTR_SPEC> {
         CONF_UPGATE_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for slave to send data automatically"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_tx_auto_start_en(&mut self) -> SLV_TX_AUTO_START_EN_W<CTR_SPEC> {
         SLV_TX_AUTO_START_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol"]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_rw_check_en(&mut self) -> ADDR_10BIT_RW_CHECK_EN_W<CTR_SPEC> {
         ADDR_10BIT_RW_CHECK_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit to support the 7bit general call function."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_broadcasting_en(&mut self) -> ADDR_BROADCASTING_EN_W<CTR_SPEC> {
         ADDR_BROADCASTING_EN_W::new(self, 14)
     }
diff --git a/esp32s3/src/i2c0/data.rs b/esp32s3/src/i2c0/data.rs
index 7b61d0c9b4..85e1cbdac8 100644
--- a/esp32s3/src/i2c0/data.rs
+++ b/esp32s3/src/i2c0/data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_rdata(&mut self) -> FIFO_RDATA_W<DATA_SPEC> {
         FIFO_RDATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/date.rs b/esp32s3/src/i2c0/date.rs
index d5b4a1c04c..a2cb39465c 100644
--- a/esp32s3/src/i2c0/date.rs
+++ b/esp32s3/src/i2c0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/fifo_conf.rs b/esp32s3/src/i2c0/fifo_conf.rs
index 9f814ec804..178ec5c82b 100644
--- a/esp32s3/src/i2c0/fifo_conf.rs
+++ b/esp32s3/src/i2c0/fifo_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
         RXFIFO_WM_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[4:0\\], reg_txfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
         TXFIFO_WM_THRHD_W::new(self, 5)
     }
     #[doc = "Bit 10 - Set this bit to enable APB nonfifo access."]
     #[inline(always)]
-    #[must_use]
     pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<FIFO_CONF_SPEC> {
         NONFIFO_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W<FIFO_CONF_SPEC> {
         FIFO_ADDR_CFG_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to reset rx-fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<FIFO_CONF_SPEC> {
         RX_FIFO_RST_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to reset tx-fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<FIFO_CONF_SPEC> {
         TX_FIFO_RST_W::new(self, 13)
     }
     #[doc = "Bit 14 - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W<FIFO_CONF_SPEC> {
         FIFO_PRT_EN_W::new(self, 14)
     }
diff --git a/esp32s3/src/i2c0/filter_cfg.rs b/esp32s3/src/i2c0/filter_cfg.rs
index bfac5394cd..03c1bda7ac 100644
--- a/esp32s3/src/i2c0/filter_cfg.rs
+++ b/esp32s3/src/i2c0/filter_cfg.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<FILTER_CFG_SPEC> {
         SCL_FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<FILTER_CFG_SPEC> {
         SDA_FILTER_THRES_W::new(self, 4)
     }
     #[doc = "Bit 8 - This is the filter enable bit for SCL."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<FILTER_CFG_SPEC> {
         SCL_FILTER_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the filter enable bit for SDA."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<FILTER_CFG_SPEC> {
         SDA_FILTER_EN_W::new(self, 9)
     }
diff --git a/esp32s3/src/i2c0/int_clr.rs b/esp32s3/src/i2c0/int_clr.rs
index 6006d600c1..a78b0e4966 100644
--- a/esp32s3/src/i2c0/int_clr.rs
+++ b/esp32s3/src/i2c0/int_clr.rs
@@ -45,109 +45,91 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
         RXFIFO_WM_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
         TXFIFO_WM_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
         BYTE_TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
         MST_TXFIFO_UDF_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
         TXFIFO_OVF_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
         RXFIFO_UDF_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
         SCL_ST_TO_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
         SCL_MAIN_ST_TO_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
         DET_START_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_CLR_SPEC> {
         SLAVE_STRETCH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit for I2C_GENARAL_CALL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_CLR_SPEC> {
         GENERAL_CALL_W::new(self, 17)
     }
diff --git a/esp32s3/src/i2c0/int_ena.rs b/esp32s3/src/i2c0/int_ena.rs
index 1597503f2a..3ba842f856 100644
--- a/esp32s3/src/i2c0/int_ena.rs
+++ b/esp32s3/src/i2c0/int_ena.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_ENA_SPEC> {
         RXFIFO_WM_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_ENA_SPEC> {
         TXFIFO_WM_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
         END_DETECT_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_ENA_SPEC> {
         BYTE_TRANS_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
         ARBITRATION_LOST_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_ENA_SPEC> {
         MST_TXFIFO_UDF_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
         TRANS_COMPLETE_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
         TIME_OUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
         TRANS_START_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
         NACK_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_ENA_SPEC> {
         TXFIFO_OVF_W::new(self, 11)
     }
     #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_ENA_SPEC> {
         RXFIFO_UDF_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_ENA_SPEC> {
         SCL_ST_TO_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_ENA_SPEC> {
         SCL_MAIN_ST_TO_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn det_start(&mut self) -> DET_START_W<INT_ENA_SPEC> {
         DET_START_W::new(self, 15)
     }
     #[doc = "Bit 16 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_ENA_SPEC> {
         SLAVE_STRETCH_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_ENA_SPEC> {
         GENERAL_CALL_W::new(self, 17)
     }
diff --git a/esp32s3/src/i2c0/scl_high_period.rs b/esp32s3/src/i2c0/scl_high_period.rs
index de59a22f03..7f223ad3d7 100644
--- a/esp32s3/src/i2c0/scl_high_period.rs
+++ b/esp32s3/src/i2c0/scl_high_period.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_HIGH_PERIOD_W::new(self, 0)
     }
     #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
         SCL_WAIT_HIGH_PERIOD_W::new(self, 9)
     }
diff --git a/esp32s3/src/i2c0/scl_low_period.rs b/esp32s3/src/i2c0/scl_low_period.rs
index f8d802b480..9874b6f962 100644
--- a/esp32s3/src/i2c0/scl_low_period.rs
+++ b/esp32s3/src/i2c0/scl_low_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<SCL_LOW_PERIOD_SPEC> {
         SCL_LOW_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_main_st_time_out.rs b/esp32s3/src/i2c0/scl_main_st_time_out.rs
index 4b94a84d01..c96787154f 100644
--- a/esp32s3/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32s3/src/i2c0/scl_main_st_time_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_main_st_to_i2c(&mut self) -> SCL_MAIN_ST_TO_I2C_W<SCL_MAIN_ST_TIME_OUT_SPEC> {
         SCL_MAIN_ST_TO_I2C_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_rstart_setup.rs b/esp32s3/src/i2c0/scl_rstart_setup.rs
index c1a7053eec..203436a57b 100644
--- a/esp32s3/src/i2c0/scl_rstart_setup.rs
+++ b/esp32s3/src/i2c0/scl_rstart_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_RSTART_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_sp_conf.rs b/esp32s3/src/i2c0/scl_sp_conf.rs
index ed2452044b..dbc65b04e9 100644
--- a/esp32s3/src/i2c0/scl_sp_conf.rs
+++ b/esp32s3/src/i2c0/scl_sp_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W<SCL_SP_CONF_SPEC> {
         SCL_RST_SLV_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W<SCL_SP_CONF_SPEC> {
         SCL_RST_SLV_NUM_W::new(self, 1)
     }
     #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."]
     #[inline(always)]
-    #[must_use]
     pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W<SCL_SP_CONF_SPEC> {
         SCL_PD_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W<SCL_SP_CONF_SPEC> {
         SDA_PD_EN_W::new(self, 7)
     }
diff --git a/esp32s3/src/i2c0/scl_st_time_out.rs b/esp32s3/src/i2c0/scl_st_time_out.rs
index 5d5bb0cdf0..2c4ef3d12d 100644
--- a/esp32s3/src/i2c0/scl_st_time_out.rs
+++ b/esp32s3/src/i2c0/scl_st_time_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_st_to_i2c(&mut self) -> SCL_ST_TO_I2C_W<SCL_ST_TIME_OUT_SPEC> {
         SCL_ST_TO_I2C_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_start_hold.rs b/esp32s3/src/i2c0/scl_start_hold.rs
index 9c5229f113..efdfbc194d 100644
--- a/esp32s3/src/i2c0/scl_start_hold.rs
+++ b/esp32s3/src/i2c0/scl_start_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_START_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_stop_hold.rs b/esp32s3/src/i2c0/scl_stop_hold.rs
index da01c0553d..df2ba1ff1a 100644
--- a/esp32s3/src/i2c0/scl_stop_hold.rs
+++ b/esp32s3/src/i2c0/scl_stop_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_stop_setup.rs b/esp32s3/src/i2c0/scl_stop_setup.rs
index cfa05ff67e..d1db579730 100644
--- a/esp32s3/src/i2c0/scl_stop_setup.rs
+++ b/esp32s3/src/i2c0/scl_stop_setup.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SCL_STOP_SETUP_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/scl_stretch_conf.rs b/esp32s3/src/i2c0/scl_stretch_conf.rs
index 729b74ea69..8b037fc596 100644
--- a/esp32s3/src/i2c0/scl_stretch_conf.rs
+++ b/esp32s3/src/i2c0/scl_stretch_conf.rs
@@ -56,31 +56,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
-    #[must_use]
     pub fn stretch_protect_num(&mut self) -> STRETCH_PROTECT_NUM_W<SCL_STRETCH_CONF_SPEC> {
         STRETCH_PROTECT_NUM_W::new(self, 0)
     }
     #[doc = "Bit 10 - The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_scl_stretch_en(&mut self) -> SLAVE_SCL_STRETCH_EN_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_SCL_STRETCH_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the I2C slave SCL stretch function."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_scl_stretch_clr(&mut self) -> SLAVE_SCL_STRETCH_CLR_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_SCL_STRETCH_CLR_W::new(self, 11)
     }
     #[doc = "Bit 12 - The enable bit for slave to control ACK level function."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_byte_ack_ctl_en(&mut self) -> SLAVE_BYTE_ACK_CTL_EN_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_BYTE_ACK_CTL_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set the ACK level when slave controlling ACK level function enables."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_byte_ack_lvl(&mut self) -> SLAVE_BYTE_ACK_LVL_W<SCL_STRETCH_CONF_SPEC> {
         SLAVE_BYTE_ACK_LVL_W::new(self, 13)
     }
diff --git a/esp32s3/src/i2c0/sda_hold.rs b/esp32s3/src/i2c0/sda_hold.rs
index a0d78acbb9..4a67e2222b 100644
--- a/esp32s3/src/i2c0/sda_hold.rs
+++ b/esp32s3/src/i2c0/sda_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_HOLD_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/sda_sample.rs b/esp32s3/src/i2c0/sda_sample.rs
index b03e34e366..b211168b11 100644
--- a/esp32s3/src/i2c0/sda_sample.rs
+++ b/esp32s3/src/i2c0/sda_sample.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time(&mut self) -> TIME_W<SDA_SAMPLE_SPEC> {
         TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2c0/slave_addr.rs b/esp32s3/src/i2c0/slave_addr.rs
index ee01a15ed5..1b27ba5ce3 100644
--- a/esp32s3/src/i2c0/slave_addr.rs
+++ b/esp32s3/src/i2c0/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - This field is used to enable the slave 10-bit addressing mode in master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
         ADDR_10BIT_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/i2c0/to.rs b/esp32s3/src/i2c0/to.rs
index 9b92f1f93a..aa23944258 100644
--- a/esp32s3/src/i2c0/to.rs
+++ b/esp32s3/src/i2c0/to.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out_value(&mut self) -> TIME_OUT_VALUE_W<TO_SPEC> {
         TIME_OUT_VALUE_W::new(self, 0)
     }
     #[doc = "Bit 5 - This is the enable bit for time out control."]
     #[inline(always)]
-    #[must_use]
     pub fn time_out_en(&mut self) -> TIME_OUT_EN_W<TO_SPEC> {
         TIME_OUT_EN_W::new(self, 5)
     }
diff --git a/esp32s3/src/i2s0/conf_sigle_data.rs b/esp32s3/src/i2s0/conf_sigle_data.rs
index 50a4d005f8..27ac6bf4a9 100644
--- a/esp32s3/src/i2s0/conf_sigle_data.rs
+++ b/esp32s3/src/i2s0/conf_sigle_data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
-    #[must_use]
     pub fn single_data(&mut self) -> SINGLE_DATA_W<CONF_SIGLE_DATA_SPEC> {
         SINGLE_DATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s0/date.rs b/esp32s3/src/i2s0/date.rs
index 89b709c15e..77a462fc9e 100644
--- a/esp32s3/src/i2s0/date.rs
+++ b/esp32s3/src/i2s0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - I2S version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s0/int_clr.rs b/esp32s3/src/i2s0/int_clr.rs
index c3a99c694f..1719a408f1 100644
--- a/esp32s3/src/i2s0/int_clr.rs
+++ b/esp32s3/src/i2s0/int_clr.rs
@@ -17,25 +17,21 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_done(&mut self) -> RX_DONE_W<INT_CLR_SPEC> {
         RX_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the i2s_tx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
         TX_DONE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the i2s_rx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the i2s_tx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
diff --git a/esp32s3/src/i2s0/int_ena.rs b/esp32s3/src/i2s0/int_ena.rs
index 0f2bb7d8e0..c87530a8a6 100644
--- a/esp32s3/src/i2s0/int_ena.rs
+++ b/esp32s3/src/i2s0/int_ena.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_done(&mut self) -> RX_DONE_W<INT_ENA_SPEC> {
         RX_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
         TX_DONE_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
diff --git a/esp32s3/src/i2s0/lc_hung_conf.rs b/esp32s3/src/i2s0/lc_hung_conf.rs
index 187de6aa6f..323187c7df 100644
--- a/esp32s3/src/i2s0/lc_hung_conf.rs
+++ b/esp32s3/src/i2s0/lc_hung_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - The enable bit for FIFO timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
     }
diff --git a/esp32s3/src/i2s0/rx_clkm_conf.rs b/esp32s3/src/i2s0/rx_clkm_conf.rs
index 89f45bca23..140e2179d1 100644
--- a/esp32s3/src/i2s0/rx_clkm_conf.rs
+++ b/esp32s3/src/i2s0/rx_clkm_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_num(&mut self) -> RX_CLKM_DIV_NUM_W<RX_CLKM_CONF_SPEC> {
         RX_CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bit 26 - I2S Rx module clock enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clk_active(&mut self) -> RX_CLK_ACTIVE_W<RX_CLKM_CONF_SPEC> {
         RX_CLK_ACTIVE_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clk_sel(&mut self) -> RX_CLK_SEL_W<RX_CLKM_CONF_SPEC> {
         RX_CLK_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
     #[inline(always)]
-    #[must_use]
     pub fn mclk_sel(&mut self) -> MCLK_SEL_W<RX_CLKM_CONF_SPEC> {
         MCLK_SEL_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s0/rx_clkm_div_conf.rs b/esp32s3/src/i2s0/rx_clkm_div_conf.rs
index 8ebfa2b7d2..c14256acfa 100644
--- a/esp32s3/src/i2s0/rx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s0/rx_clkm_div_conf.rs
@@ -2,39 +2,39 @@
 pub type R = crate::R<RX_CLKM_DIV_CONF_SPEC>;
 #[doc = "Register `RX_CLKM_DIV_CONF` writer"]
 pub type W = crate::W<RX_CLKM_DIV_CONF_SPEC>;
-#[doc = "Field `RX_CLKM_DIV_Z` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `RX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
 pub type RX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_Z` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `RX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
 pub type RX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_Y` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `RX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
 pub type RX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_Y` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `RX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
 pub type RX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_X` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `RX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type RX_CLKM_DIV_X_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_X` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `RX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type RX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_YN1` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `RX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
 pub type RX_CLKM_DIV_YN1_R = crate::BitReader;
-#[doc = "Field `RX_CLKM_DIV_YN1` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `RX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
 pub type RX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
     pub fn rx_clkm_div_z(&self) -> RX_CLKM_DIV_Z_R {
         RX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
     pub fn rx_clkm_div_y(&self) -> RX_CLKM_DIV_Y_R {
         RX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
     pub fn rx_clkm_div_x(&self) -> RX_CLKM_DIV_X_R {
         RX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
     pub fn rx_clkm_div_yn1(&self) -> RX_CLKM_DIV_YN1_R {
         RX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_z(&mut self) -> RX_CLKM_DIV_Z_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_Z_W::new(self, 0)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_y(&mut self) -> RX_CLKM_DIV_Y_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_Y_W::new(self, 9)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_x(&mut self) -> RX_CLKM_DIV_X_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_X_W::new(self, 18)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_yn1(&mut self) -> RX_CLKM_DIV_YN1_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_YN1_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s0/rx_conf.rs b/esp32s3/src/i2s0/rx_conf.rs
index 85cd6d23dc..d1c9dc20bb 100644
--- a/esp32s3/src/i2s0/rx_conf.rs
+++ b/esp32s3/src/i2s0/rx_conf.rs
@@ -30,9 +30,9 @@ pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type RX_MONO_FST_VLD_R = crate::BitReader;
 #[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
 pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type RX_PCM_CONF_R = crate::FieldReader;
-#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 #[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."]
 pub type RX_PCM_BYPASS_R = crate::BitReader;
@@ -105,7 +105,7 @@ impl R {
     pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R {
         RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
     pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R {
         RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
@@ -188,115 +188,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_reset(&mut self) -> RX_RESET_W<RX_CONF_SPEC> {
         RX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<RX_CONF_SPEC> {
         RX_FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to start receiving data"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<RX_CONF_SPEC> {
         RX_START_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<RX_CONF_SPEC> {
         RX_SLAVE_MOD_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono(&mut self) -> RX_MONO_W<RX_CONF_SPEC> {
         RX_MONO_W::new(self, 5)
     }
     #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<RX_CONF_SPEC> {
         RX_BIG_ENDIAN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_update(&mut self) -> RX_UPDATE_W<RX_CONF_SPEC> {
         RX_UPDATE_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W<RX_CONF_SPEC> {
         RX_MONO_FST_VLD_W::new(self, 9)
     }
-    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<RX_CONF_SPEC> {
         RX_PCM_CONF_W::new(self, 10)
     }
     #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<RX_CONF_SPEC> {
         RX_PCM_BYPASS_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W<RX_CONF_SPEC> {
         RX_STOP_MODE_W::new(self, 13)
     }
     #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W<RX_CONF_SPEC> {
         RX_LEFT_ALIGN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W<RX_CONF_SPEC> {
         RX_24_FILL_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W<RX_CONF_SPEC> {
         RX_WS_IDLE_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W<RX_CONF_SPEC> {
         RX_BIT_ORDER_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W<RX_CONF_SPEC> {
         RX_TDM_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<RX_CONF_SPEC> {
         RX_PDM_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: Enable PDM2PCM RX mode. 0: DIsable."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm2pcm_en(&mut self) -> RX_PDM2PCM_EN_W<RX_CONF_SPEC> {
         RX_PDM2PCM_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W<RX_CONF_SPEC> {
         RX_PDM_SINC_DSR_16_EN_W::new(self, 22)
     }
diff --git a/esp32s3/src/i2s0/rx_conf1.rs b/esp32s3/src/i2s0/rx_conf1.rs
index d3795df6cb..ba9590de00 100644
--- a/esp32s3/src/i2s0/rx_conf1.rs
+++ b/esp32s3/src/i2s0/rx_conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W<RX_CONF1_SPEC> {
         RX_TDM_WS_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<RX_CONF1_SPEC> {
         RX_BCK_DIV_NUM_W::new(self, 7)
     }
     #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<RX_CONF1_SPEC> {
         RX_BITS_MOD_W::new(self, 13)
     }
     #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W<RX_CONF1_SPEC> {
         RX_HALF_SAMPLE_BITS_W::new(self, 18)
     }
     #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W<RX_CONF1_SPEC> {
         RX_TDM_CHAN_BITS_W::new(self, 24)
     }
     #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<RX_CONF1_SPEC> {
         RX_MSB_SHIFT_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s0/rx_tdm_ctrl.rs b/esp32s3/src/i2s0/rx_tdm_ctrl.rs
index 145b893140..430d8487d3 100644
--- a/esp32s3/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s0/rx_tdm_ctrl.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan0_en(&mut self) -> RX_TDM_PDM_CHAN0_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan1_en(&mut self) -> RX_TDM_PDM_CHAN1_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan2_en(&mut self) -> RX_TDM_PDM_CHAN2_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan3_en(&mut self) -> RX_TDM_PDM_CHAN3_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN3_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan4_en(&mut self) -> RX_TDM_PDM_CHAN4_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN4_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan5_en(&mut self) -> RX_TDM_PDM_CHAN5_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN5_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan6_en(&mut self) -> RX_TDM_PDM_CHAN6_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN6_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan7_en(&mut self) -> RX_TDM_PDM_CHAN7_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN7_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan8_en(&mut self) -> RX_TDM_CHAN8_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN8_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan9_en(&mut self) -> RX_TDM_CHAN9_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN9_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan10_en(&mut self) -> RX_TDM_CHAN10_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN10_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan11_en(&mut self) -> RX_TDM_CHAN11_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN11_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan12_en(&mut self) -> RX_TDM_CHAN12_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN12_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan13_en(&mut self) -> RX_TDM_CHAN13_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN13_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan14_en(&mut self) -> RX_TDM_CHAN14_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN14_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan15_en(&mut self) -> RX_TDM_CHAN15_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN15_EN_W::new(self, 15)
     }
     #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_tot_chan_num(&mut self) -> RX_TDM_TOT_CHAN_NUM_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_TOT_CHAN_NUM_W::new(self, 16)
     }
diff --git a/esp32s3/src/i2s0/rx_timing.rs b/esp32s3/src/i2s0/rx_timing.rs
index dc2281880d..ae2f911f0f 100644
--- a/esp32s3/src/i2s0/rx_timing.rs
+++ b/esp32s3/src/i2s0/rx_timing.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W<RX_TIMING_SPEC> {
         RX_SD_IN_DM_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd1_in_dm(&mut self) -> RX_SD1_IN_DM_W<RX_TIMING_SPEC> {
         RX_SD1_IN_DM_W::new(self, 4)
     }
     #[doc = "Bits 8:9 - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd2_in_dm(&mut self) -> RX_SD2_IN_DM_W<RX_TIMING_SPEC> {
         RX_SD2_IN_DM_W::new(self, 8)
     }
     #[doc = "Bits 12:13 - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd3_in_dm(&mut self) -> RX_SD3_IN_DM_W<RX_TIMING_SPEC> {
         RX_SD3_IN_DM_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W<RX_TIMING_SPEC> {
         RX_WS_OUT_DM_W::new(self, 16)
     }
     #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W<RX_TIMING_SPEC> {
         RX_BCK_OUT_DM_W::new(self, 20)
     }
     #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W<RX_TIMING_SPEC> {
         RX_WS_IN_DM_W::new(self, 24)
     }
     #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W<RX_TIMING_SPEC> {
         RX_BCK_IN_DM_W::new(self, 28)
     }
diff --git a/esp32s3/src/i2s0/rxeof_num.rs b/esp32s3/src/i2s0/rxeof_num.rs
index 3cc1cab6bd..e06f8c3e0d 100644
--- a/esp32s3/src/i2s0/rxeof_num.rs
+++ b/esp32s3/src/i2s0/rxeof_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<RXEOF_NUM_SPEC> {
         RX_EOF_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s0/tx_clkm_conf.rs b/esp32s3/src/i2s0/tx_clkm_conf.rs
index 24561dcbc6..af8d613b56 100644
--- a/esp32s3/src/i2s0/tx_clkm_conf.rs
+++ b/esp32s3/src/i2s0/tx_clkm_conf.rs
@@ -2,9 +2,9 @@
 pub type R = crate::R<TX_CLKM_CONF_SPEC>;
 #[doc = "Register `TX_CLKM_CONF` writer"]
 pub type W = crate::W<TX_CLKM_CONF_SPEC>;
-#[doc = "Field `TX_CLKM_DIV_NUM` reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+#[doc = "Field `TX_CLKM_DIV_NUM` reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
 pub type TX_CLKM_DIV_NUM_R = crate::FieldReader;
-#[doc = "Field `TX_CLKM_DIV_NUM` writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+#[doc = "Field `TX_CLKM_DIV_NUM` writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
 pub type TX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 #[doc = "Field `TX_CLK_ACTIVE` reader - I2S Tx module clock enable signal."]
 pub type TX_CLK_ACTIVE_R = crate::BitReader;
@@ -19,7 +19,7 @@ pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"]
 pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
     pub fn tx_clkm_div_num(&self) -> TX_CLKM_DIV_NUM_R {
         TX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_num(&mut self) -> TX_CLKM_DIV_NUM_W<TX_CLKM_CONF_SPEC> {
         TX_CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bit 26 - I2S Tx module clock enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clk_active(&mut self) -> TX_CLK_ACTIVE_W<TX_CLKM_CONF_SPEC> {
         TX_CLK_ACTIVE_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clk_sel(&mut self) -> TX_CLK_SEL_W<TX_CLKM_CONF_SPEC> {
         TX_CLK_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - Set this bit to enable clk gate"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<TX_CLKM_CONF_SPEC> {
         CLK_EN_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s0/tx_clkm_div_conf.rs b/esp32s3/src/i2s0/tx_clkm_div_conf.rs
index e7b9c46e13..f8c04d20cf 100644
--- a/esp32s3/src/i2s0/tx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s0/tx_clkm_div_conf.rs
@@ -2,39 +2,39 @@
 pub type R = crate::R<TX_CLKM_DIV_CONF_SPEC>;
 #[doc = "Register `TX_CLKM_DIV_CONF` writer"]
 pub type W = crate::W<TX_CLKM_DIV_CONF_SPEC>;
-#[doc = "Field `TX_CLKM_DIV_Z` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `TX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
 pub type TX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_Z` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `TX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
 pub type TX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_Y` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `TX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
 pub type TX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_Y` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `TX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
 pub type TX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_X` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `TX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type TX_CLKM_DIV_X_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_X` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `TX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type TX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_YN1` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `TX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
 pub type TX_CLKM_DIV_YN1_R = crate::BitReader;
-#[doc = "Field `TX_CLKM_DIV_YN1` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `TX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
 pub type TX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
     pub fn tx_clkm_div_z(&self) -> TX_CLKM_DIV_Z_R {
         TX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
     pub fn tx_clkm_div_y(&self) -> TX_CLKM_DIV_Y_R {
         TX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
     pub fn tx_clkm_div_x(&self) -> TX_CLKM_DIV_X_R {
         TX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
     pub fn tx_clkm_div_yn1(&self) -> TX_CLKM_DIV_YN1_R {
         TX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_z(&mut self) -> TX_CLKM_DIV_Z_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_Z_W::new(self, 0)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_y(&mut self) -> TX_CLKM_DIV_Y_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_Y_W::new(self, 9)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_x(&mut self) -> TX_CLKM_DIV_X_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_X_W::new(self, 18)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_yn1(&mut self) -> TX_CLKM_DIV_YN1_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_YN1_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s0/tx_conf.rs b/esp32s3/src/i2s0/tx_conf.rs
index 48f6449414..628e4fb80d 100644
--- a/esp32s3/src/i2s0/tx_conf.rs
+++ b/esp32s3/src/i2s0/tx_conf.rs
@@ -34,9 +34,9 @@ pub type TX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type TX_MONO_FST_VLD_R = crate::BitReader;
 #[doc = "Field `TX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
 pub type TX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type TX_PCM_CONF_R = crate::FieldReader;
-#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type TX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 #[doc = "Field `TX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for transmitted data."]
 pub type TX_PCM_BYPASS_R = crate::BitReader;
@@ -114,7 +114,7 @@ impl R {
     pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R {
         TX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
     pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R {
         TX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
@@ -198,121 +198,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_reset(&mut self) -> TX_RESET_W<TX_CONF_SPEC> {
         TX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset Tx AFIFO"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<TX_CONF_SPEC> {
         TX_FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to start transmitting data"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<TX_CONF_SPEC> {
         TX_START_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<TX_CONF_SPEC> {
         TX_SLAVE_MOD_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono(&mut self) -> TX_MONO_W<TX_CONF_SPEC> {
         TX_MONO_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_equal(&mut self) -> TX_CHAN_EQUAL_W<TX_CONF_SPEC> {
         TX_CHAN_EQUAL_W::new(self, 6)
     }
     #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W<TX_CONF_SPEC> {
         TX_BIG_ENDIAN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_update(&mut self) -> TX_UPDATE_W<TX_CONF_SPEC> {
         TX_UPDATE_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono_fst_vld(&mut self) -> TX_MONO_FST_VLD_W<TX_CONF_SPEC> {
         TX_MONO_FST_VLD_W::new(self, 9)
     }
-    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<TX_CONF_SPEC> {
         TX_PCM_CONF_W::new(self, 10)
     }
     #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<TX_CONF_SPEC> {
         TX_PCM_BYPASS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<TX_CONF_SPEC> {
         TX_STOP_EN_W::new(self, 13)
     }
     #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_left_align(&mut self) -> TX_LEFT_ALIGN_W<TX_CONF_SPEC> {
         TX_LEFT_ALIGN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_24_fill_en(&mut self) -> TX_24_FILL_EN_W<TX_CONF_SPEC> {
         TX_24_FILL_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_idle_pol(&mut self) -> TX_WS_IDLE_POL_W<TX_CONF_SPEC> {
         TX_WS_IDLE_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bit_order(&mut self) -> TX_BIT_ORDER_W<TX_CONF_SPEC> {
         TX_BIT_ORDER_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_en(&mut self) -> TX_TDM_EN_W<TX_CONF_SPEC> {
         TX_TDM_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<TX_CONF_SPEC> {
         TX_PDM_EN_W::new(self, 20)
     }
     #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<TX_CONF_SPEC> {
         TX_CHAN_MOD_W::new(self, 24)
     }
     #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<TX_CONF_SPEC> {
         SIG_LOOPBACK_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s0/tx_conf1.rs b/esp32s3/src/i2s0/tx_conf1.rs
index 196c16c060..ca317bc3f4 100644
--- a/esp32s3/src/i2s0/tx_conf1.rs
+++ b/esp32s3/src/i2s0/tx_conf1.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W<TX_CONF1_SPEC> {
         TX_TDM_WS_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<TX_CONF1_SPEC> {
         TX_BCK_DIV_NUM_W::new(self, 7)
     }
     #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<TX_CONF1_SPEC> {
         TX_BITS_MOD_W::new(self, 13)
     }
     #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W<TX_CONF1_SPEC> {
         TX_HALF_SAMPLE_BITS_W::new(self, 18)
     }
     #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W<TX_CONF1_SPEC> {
         TX_TDM_CHAN_BITS_W::new(self, 24)
     }
     #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<TX_CONF1_SPEC> {
         TX_MSB_SHIFT_W::new(self, 29)
     }
     #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W<TX_CONF1_SPEC> {
         TX_BCK_NO_DLY_W::new(self, 30)
     }
diff --git a/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs b/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
index efaddb2ef6..b58b16a1ad 100644
--- a/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
@@ -140,43 +140,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_hp_bypass(&mut self) -> TX_PDM_HP_BYPASS_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_HP_BYPASS_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - I2S TX PDM OSR2 value"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sinc_osr2(&mut self) -> TX_PDM_SINC_OSR2_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_SINC_OSR2_W::new(self, 1)
     }
     #[doc = "Bits 5:12 - I2S TX PDM prescale for sigmadelta"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_prescale(&mut self) -> TX_PDM_PRESCALE_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_PRESCALE_W::new(self, 5)
     }
     #[doc = "Bits 13:14 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_hp_in_shift(&mut self) -> TX_PDM_HP_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_HP_IN_SHIFT_W::new(self, 13)
     }
     #[doc = "Bits 15:16 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_lp_in_shift(&mut self) -> TX_PDM_LP_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_LP_IN_SHIFT_W::new(self, 15)
     }
     #[doc = "Bits 17:18 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sinc_in_shift(&mut self) -> TX_PDM_SINC_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_SINC_IN_SHIFT_W::new(self, 17)
     }
     #[doc = "Bits 19:20 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sigmadelta_in_shift(
         &mut self,
     ) -> TX_PDM_SIGMADELTA_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
@@ -184,7 +177,6 @@ impl W {
     }
     #[doc = "Bit 21 - I2S TX PDM sigmadelta dither2 value"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sigmadelta_dither2(
         &mut self,
     ) -> TX_PDM_SIGMADELTA_DITHER2_W<TX_PCM2PDM_CONF_SPEC> {
@@ -192,25 +184,21 @@ impl W {
     }
     #[doc = "Bit 22 - I2S TX PDM sigmadelta dither value"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_sigmadelta_dither(&mut self) -> TX_PDM_SIGMADELTA_DITHER_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_SIGMADELTA_DITHER_W::new(self, 22)
     }
     #[doc = "Bit 23 - I2S TX PDM dac mode enable"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_dac_2out_en(&mut self) -> TX_PDM_DAC_2OUT_EN_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_DAC_2OUT_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - I2S TX PDM dac 2channel enable"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_dac_mode_en(&mut self) -> TX_PDM_DAC_MODE_EN_W<TX_PCM2PDM_CONF_SPEC> {
         TX_PDM_DAC_MODE_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - I2S TX PDM Converter enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pcm2pdm_conv_en(&mut self) -> PCM2PDM_CONV_EN_W<TX_PCM2PDM_CONF_SPEC> {
         PCM2PDM_CONV_EN_W::new(self, 25)
     }
diff --git a/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
index 7f58eb3572..6ae1a8208e 100644
--- a/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_fp(&mut self) -> TX_PDM_FP_W<TX_PCM2PDM_CONF1_SPEC> {
         TX_PDM_FP_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - I2S TX PDM Fs"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_fs(&mut self) -> TX_PDM_FS_W<TX_PCM2PDM_CONF1_SPEC> {
         TX_PDM_FS_W::new(self, 10)
     }
     #[doc = "Bits 20:22 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_iir_hp_mult12_5(&mut self) -> TX_IIR_HP_MULT12_5_W<TX_PCM2PDM_CONF1_SPEC> {
         TX_IIR_HP_MULT12_5_W::new(self, 20)
     }
     #[doc = "Bits 23:25 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_iir_hp_mult12_0(&mut self) -> TX_IIR_HP_MULT12_0_W<TX_PCM2PDM_CONF1_SPEC> {
         TX_IIR_HP_MULT12_0_W::new(self, 23)
     }
diff --git a/esp32s3/src/i2s0/tx_tdm_ctrl.rs b/esp32s3/src/i2s0/tx_tdm_ctrl.rs
index 9d5efa9df7..859510cb36 100644
--- a/esp32s3/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s0/tx_tdm_ctrl.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan0_en(&mut self) -> TX_TDM_CHAN0_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan1_en(&mut self) -> TX_TDM_CHAN1_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan2_en(&mut self) -> TX_TDM_CHAN2_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan3_en(&mut self) -> TX_TDM_CHAN3_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN3_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan4_en(&mut self) -> TX_TDM_CHAN4_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN4_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan5_en(&mut self) -> TX_TDM_CHAN5_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN5_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan6_en(&mut self) -> TX_TDM_CHAN6_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN6_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan7_en(&mut self) -> TX_TDM_CHAN7_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN7_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan8_en(&mut self) -> TX_TDM_CHAN8_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN8_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan9_en(&mut self) -> TX_TDM_CHAN9_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN9_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan10_en(&mut self) -> TX_TDM_CHAN10_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN10_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan11_en(&mut self) -> TX_TDM_CHAN11_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN11_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan12_en(&mut self) -> TX_TDM_CHAN12_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN12_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan13_en(&mut self) -> TX_TDM_CHAN13_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN13_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan14_en(&mut self) -> TX_TDM_CHAN14_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN14_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan15_en(&mut self) -> TX_TDM_CHAN15_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN15_EN_W::new(self, 15)
     }
     #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_tot_chan_num(&mut self) -> TX_TDM_TOT_CHAN_NUM_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_TOT_CHAN_NUM_W::new(self, 16)
     }
     #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_skip_msk_en(&mut self) -> TX_TDM_SKIP_MSK_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_SKIP_MSK_EN_W::new(self, 20)
     }
diff --git a/esp32s3/src/i2s0/tx_timing.rs b/esp32s3/src/i2s0/tx_timing.rs
index 82d20256cd..a9e6a29856 100644
--- a/esp32s3/src/i2s0/tx_timing.rs
+++ b/esp32s3/src/i2s0/tx_timing.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<TX_TIMING_SPEC> {
         TX_SD_OUT_DM_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<TX_TIMING_SPEC> {
         TX_SD1_OUT_DM_W::new(self, 4)
     }
     #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<TX_TIMING_SPEC> {
         TX_WS_OUT_DM_W::new(self, 16)
     }
     #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<TX_TIMING_SPEC> {
         TX_BCK_OUT_DM_W::new(self, 20)
     }
     #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<TX_TIMING_SPEC> {
         TX_WS_IN_DM_W::new(self, 24)
     }
     #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<TX_TIMING_SPEC> {
         TX_BCK_IN_DM_W::new(self, 28)
     }
diff --git a/esp32s3/src/i2s1/conf_sigle_data.rs b/esp32s3/src/i2s1/conf_sigle_data.rs
index 50a4d005f8..27ac6bf4a9 100644
--- a/esp32s3/src/i2s1/conf_sigle_data.rs
+++ b/esp32s3/src/i2s1/conf_sigle_data.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
-    #[must_use]
     pub fn single_data(&mut self) -> SINGLE_DATA_W<CONF_SIGLE_DATA_SPEC> {
         SINGLE_DATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s1/date.rs b/esp32s3/src/i2s1/date.rs
index 89b709c15e..77a462fc9e 100644
--- a/esp32s3/src/i2s1/date.rs
+++ b/esp32s3/src/i2s1/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - I2S version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s1/int_clr.rs b/esp32s3/src/i2s1/int_clr.rs
index c3a99c694f..1719a408f1 100644
--- a/esp32s3/src/i2s1/int_clr.rs
+++ b/esp32s3/src/i2s1/int_clr.rs
@@ -17,25 +17,21 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_done(&mut self) -> RX_DONE_W<INT_CLR_SPEC> {
         RX_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the i2s_tx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
         TX_DONE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the i2s_rx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the i2s_tx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
diff --git a/esp32s3/src/i2s1/int_ena.rs b/esp32s3/src/i2s1/int_ena.rs
index 0f2bb7d8e0..c87530a8a6 100644
--- a/esp32s3/src/i2s1/int_ena.rs
+++ b/esp32s3/src/i2s1/int_ena.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_done(&mut self) -> RX_DONE_W<INT_ENA_SPEC> {
         RX_DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
         TX_DONE_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
diff --git a/esp32s3/src/i2s1/lc_hung_conf.rs b/esp32s3/src/i2s1/lc_hung_conf.rs
index 187de6aa6f..323187c7df 100644
--- a/esp32s3/src/i2s1/lc_hung_conf.rs
+++ b/esp32s3/src/i2s1/lc_hung_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - The enable bit for FIFO timeout"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
         LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
     }
diff --git a/esp32s3/src/i2s1/rx_clkm_conf.rs b/esp32s3/src/i2s1/rx_clkm_conf.rs
index 89f45bca23..140e2179d1 100644
--- a/esp32s3/src/i2s1/rx_clkm_conf.rs
+++ b/esp32s3/src/i2s1/rx_clkm_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_num(&mut self) -> RX_CLKM_DIV_NUM_W<RX_CLKM_CONF_SPEC> {
         RX_CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bit 26 - I2S Rx module clock enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clk_active(&mut self) -> RX_CLK_ACTIVE_W<RX_CLKM_CONF_SPEC> {
         RX_CLK_ACTIVE_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clk_sel(&mut self) -> RX_CLK_SEL_W<RX_CLKM_CONF_SPEC> {
         RX_CLK_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
     #[inline(always)]
-    #[must_use]
     pub fn mclk_sel(&mut self) -> MCLK_SEL_W<RX_CLKM_CONF_SPEC> {
         MCLK_SEL_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s1/rx_clkm_div_conf.rs b/esp32s3/src/i2s1/rx_clkm_div_conf.rs
index 8ebfa2b7d2..c14256acfa 100644
--- a/esp32s3/src/i2s1/rx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s1/rx_clkm_div_conf.rs
@@ -2,39 +2,39 @@
 pub type R = crate::R<RX_CLKM_DIV_CONF_SPEC>;
 #[doc = "Register `RX_CLKM_DIV_CONF` writer"]
 pub type W = crate::W<RX_CLKM_DIV_CONF_SPEC>;
-#[doc = "Field `RX_CLKM_DIV_Z` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `RX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
 pub type RX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_Z` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `RX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
 pub type RX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_Y` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `RX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
 pub type RX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_Y` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `RX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
 pub type RX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_X` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `RX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type RX_CLKM_DIV_X_R = crate::FieldReader<u16>;
-#[doc = "Field `RX_CLKM_DIV_X` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `RX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type RX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `RX_CLKM_DIV_YN1` reader - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `RX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
 pub type RX_CLKM_DIV_YN1_R = crate::BitReader;
-#[doc = "Field `RX_CLKM_DIV_YN1` writer - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `RX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
 pub type RX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
     pub fn rx_clkm_div_z(&self) -> RX_CLKM_DIV_Z_R {
         RX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
     pub fn rx_clkm_div_y(&self) -> RX_CLKM_DIV_Y_R {
         RX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
     pub fn rx_clkm_div_x(&self) -> RX_CLKM_DIV_X_R {
         RX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
     pub fn rx_clkm_div_yn1(&self) -> RX_CLKM_DIV_YN1_R {
         RX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_z(&mut self) -> RX_CLKM_DIV_Z_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_Z_W::new(self, 0)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_y(&mut self) -> RX_CLKM_DIV_Y_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_Y_W::new(self, 9)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_x(&mut self) -> RX_CLKM_DIV_X_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_X_W::new(self, 18)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_clkm_div_yn1(&mut self) -> RX_CLKM_DIV_YN1_W<RX_CLKM_DIV_CONF_SPEC> {
         RX_CLKM_DIV_YN1_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s1/rx_conf.rs b/esp32s3/src/i2s1/rx_conf.rs
index edaa8a1a29..0e70426ffc 100644
--- a/esp32s3/src/i2s1/rx_conf.rs
+++ b/esp32s3/src/i2s1/rx_conf.rs
@@ -30,9 +30,9 @@ pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type RX_MONO_FST_VLD_R = crate::BitReader;
 #[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
 pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type RX_PCM_CONF_R = crate::FieldReader;
-#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 #[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."]
 pub type RX_PCM_BYPASS_R = crate::BitReader;
@@ -97,7 +97,7 @@ impl R {
     pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R {
         RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
     pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R {
         RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
@@ -168,103 +168,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_reset(&mut self) -> RX_RESET_W<RX_CONF_SPEC> {
         RX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<RX_CONF_SPEC> {
         RX_FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to start receiving data"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<RX_CONF_SPEC> {
         RX_START_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<RX_CONF_SPEC> {
         RX_SLAVE_MOD_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono(&mut self) -> RX_MONO_W<RX_CONF_SPEC> {
         RX_MONO_W::new(self, 5)
     }
     #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<RX_CONF_SPEC> {
         RX_BIG_ENDIAN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_update(&mut self) -> RX_UPDATE_W<RX_CONF_SPEC> {
         RX_UPDATE_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W<RX_CONF_SPEC> {
         RX_MONO_FST_VLD_W::new(self, 9)
     }
-    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<RX_CONF_SPEC> {
         RX_PCM_CONF_W::new(self, 10)
     }
     #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<RX_CONF_SPEC> {
         RX_PCM_BYPASS_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W<RX_CONF_SPEC> {
         RX_STOP_MODE_W::new(self, 13)
     }
     #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W<RX_CONF_SPEC> {
         RX_LEFT_ALIGN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W<RX_CONF_SPEC> {
         RX_24_FILL_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W<RX_CONF_SPEC> {
         RX_WS_IDLE_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W<RX_CONF_SPEC> {
         RX_BIT_ORDER_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W<RX_CONF_SPEC> {
         RX_TDM_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<RX_CONF_SPEC> {
         RX_PDM_EN_W::new(self, 20)
     }
diff --git a/esp32s3/src/i2s1/rx_conf1.rs b/esp32s3/src/i2s1/rx_conf1.rs
index d3795df6cb..ba9590de00 100644
--- a/esp32s3/src/i2s1/rx_conf1.rs
+++ b/esp32s3/src/i2s1/rx_conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W<RX_CONF1_SPEC> {
         RX_TDM_WS_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<RX_CONF1_SPEC> {
         RX_BCK_DIV_NUM_W::new(self, 7)
     }
     #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<RX_CONF1_SPEC> {
         RX_BITS_MOD_W::new(self, 13)
     }
     #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W<RX_CONF1_SPEC> {
         RX_HALF_SAMPLE_BITS_W::new(self, 18)
     }
     #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W<RX_CONF1_SPEC> {
         RX_TDM_CHAN_BITS_W::new(self, 24)
     }
     #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<RX_CONF1_SPEC> {
         RX_MSB_SHIFT_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s1/rx_tdm_ctrl.rs b/esp32s3/src/i2s1/rx_tdm_ctrl.rs
index 145b893140..430d8487d3 100644
--- a/esp32s3/src/i2s1/rx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s1/rx_tdm_ctrl.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan0_en(&mut self) -> RX_TDM_PDM_CHAN0_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan1_en(&mut self) -> RX_TDM_PDM_CHAN1_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan2_en(&mut self) -> RX_TDM_PDM_CHAN2_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan3_en(&mut self) -> RX_TDM_PDM_CHAN3_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN3_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan4_en(&mut self) -> RX_TDM_PDM_CHAN4_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN4_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan5_en(&mut self) -> RX_TDM_PDM_CHAN5_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN5_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan6_en(&mut self) -> RX_TDM_PDM_CHAN6_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN6_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_pdm_chan7_en(&mut self) -> RX_TDM_PDM_CHAN7_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_PDM_CHAN7_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan8_en(&mut self) -> RX_TDM_CHAN8_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN8_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan9_en(&mut self) -> RX_TDM_CHAN9_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN9_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan10_en(&mut self) -> RX_TDM_CHAN10_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN10_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan11_en(&mut self) -> RX_TDM_CHAN11_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN11_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan12_en(&mut self) -> RX_TDM_CHAN12_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN12_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan13_en(&mut self) -> RX_TDM_CHAN13_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN13_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan14_en(&mut self) -> RX_TDM_CHAN14_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN14_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_chan15_en(&mut self) -> RX_TDM_CHAN15_EN_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_CHAN15_EN_W::new(self, 15)
     }
     #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tdm_tot_chan_num(&mut self) -> RX_TDM_TOT_CHAN_NUM_W<RX_TDM_CTRL_SPEC> {
         RX_TDM_TOT_CHAN_NUM_W::new(self, 16)
     }
diff --git a/esp32s3/src/i2s1/rx_timing.rs b/esp32s3/src/i2s1/rx_timing.rs
index bb9ba20b42..bcf0d0e4ce 100644
--- a/esp32s3/src/i2s1/rx_timing.rs
+++ b/esp32s3/src/i2s1/rx_timing.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W<RX_TIMING_SPEC> {
         RX_SD_IN_DM_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W<RX_TIMING_SPEC> {
         RX_WS_OUT_DM_W::new(self, 16)
     }
     #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W<RX_TIMING_SPEC> {
         RX_BCK_OUT_DM_W::new(self, 20)
     }
     #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W<RX_TIMING_SPEC> {
         RX_WS_IN_DM_W::new(self, 24)
     }
     #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W<RX_TIMING_SPEC> {
         RX_BCK_IN_DM_W::new(self, 28)
     }
diff --git a/esp32s3/src/i2s1/rxeof_num.rs b/esp32s3/src/i2s1/rxeof_num.rs
index 3cc1cab6bd..e06f8c3e0d 100644
--- a/esp32s3/src/i2s1/rxeof_num.rs
+++ b/esp32s3/src/i2s1/rxeof_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<RXEOF_NUM_SPEC> {
         RX_EOF_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/i2s1/tx_clkm_conf.rs b/esp32s3/src/i2s1/tx_clkm_conf.rs
index 24561dcbc6..af8d613b56 100644
--- a/esp32s3/src/i2s1/tx_clkm_conf.rs
+++ b/esp32s3/src/i2s1/tx_clkm_conf.rs
@@ -2,9 +2,9 @@
 pub type R = crate::R<TX_CLKM_CONF_SPEC>;
 #[doc = "Register `TX_CLKM_CONF` writer"]
 pub type W = crate::W<TX_CLKM_CONF_SPEC>;
-#[doc = "Field `TX_CLKM_DIV_NUM` reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+#[doc = "Field `TX_CLKM_DIV_NUM` reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
 pub type TX_CLKM_DIV_NUM_R = crate::FieldReader;
-#[doc = "Field `TX_CLKM_DIV_NUM` writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+#[doc = "Field `TX_CLKM_DIV_NUM` writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
 pub type TX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 #[doc = "Field `TX_CLK_ACTIVE` reader - I2S Tx module clock enable signal."]
 pub type TX_CLK_ACTIVE_R = crate::BitReader;
@@ -19,7 +19,7 @@ pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"]
 pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
     pub fn tx_clkm_div_num(&self) -> TX_CLKM_DIV_NUM_R {
         TX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_num(&mut self) -> TX_CLKM_DIV_NUM_W<TX_CLKM_CONF_SPEC> {
         TX_CLKM_DIV_NUM_W::new(self, 0)
     }
     #[doc = "Bit 26 - I2S Tx module clock enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clk_active(&mut self) -> TX_CLK_ACTIVE_W<TX_CLKM_CONF_SPEC> {
         TX_CLK_ACTIVE_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clk_sel(&mut self) -> TX_CLK_SEL_W<TX_CLKM_CONF_SPEC> {
         TX_CLK_SEL_W::new(self, 27)
     }
     #[doc = "Bit 29 - Set this bit to enable clk gate"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<TX_CLKM_CONF_SPEC> {
         CLK_EN_W::new(self, 29)
     }
diff --git a/esp32s3/src/i2s1/tx_clkm_div_conf.rs b/esp32s3/src/i2s1/tx_clkm_div_conf.rs
index e7b9c46e13..f8c04d20cf 100644
--- a/esp32s3/src/i2s1/tx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s1/tx_clkm_div_conf.rs
@@ -2,39 +2,39 @@
 pub type R = crate::R<TX_CLKM_DIV_CONF_SPEC>;
 #[doc = "Register `TX_CLKM_DIV_CONF` writer"]
 pub type W = crate::W<TX_CLKM_DIV_CONF_SPEC>;
-#[doc = "Field `TX_CLKM_DIV_Z` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `TX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
 pub type TX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_Z` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+#[doc = "Field `TX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
 pub type TX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_Y` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `TX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
 pub type TX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_Y` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+#[doc = "Field `TX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
 pub type TX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_X` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `TX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type TX_CLKM_DIV_X_R = crate::FieldReader<u16>;
-#[doc = "Field `TX_CLKM_DIV_X` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+#[doc = "Field `TX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
 pub type TX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
-#[doc = "Field `TX_CLKM_DIV_YN1` reader - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `TX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
 pub type TX_CLKM_DIV_YN1_R = crate::BitReader;
-#[doc = "Field `TX_CLKM_DIV_YN1` writer - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+#[doc = "Field `TX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
 pub type TX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
     pub fn tx_clkm_div_z(&self) -> TX_CLKM_DIV_Z_R {
         TX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
     pub fn tx_clkm_div_y(&self) -> TX_CLKM_DIV_Y_R {
         TX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
     pub fn tx_clkm_div_x(&self) -> TX_CLKM_DIV_X_R {
         TX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
     pub fn tx_clkm_div_yn1(&self) -> TX_CLKM_DIV_YN1_R {
         TX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
@@ -52,27 +52,23 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_z(&mut self) -> TX_CLKM_DIV_Z_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_Z_W::new(self, 0)
     }
-    #[doc = "Bits 9:17 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_y(&mut self) -> TX_CLKM_DIV_Y_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_Y_W::new(self, 9)
     }
-    #[doc = "Bits 18:26 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_x(&mut self) -> TX_CLKM_DIV_X_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_X_W::new(self, 18)
     }
-    #[doc = "Bit 27 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_clkm_div_yn1(&mut self) -> TX_CLKM_DIV_YN1_W<TX_CLKM_DIV_CONF_SPEC> {
         TX_CLKM_DIV_YN1_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s1/tx_conf.rs b/esp32s3/src/i2s1/tx_conf.rs
index 48f6449414..628e4fb80d 100644
--- a/esp32s3/src/i2s1/tx_conf.rs
+++ b/esp32s3/src/i2s1/tx_conf.rs
@@ -34,9 +34,9 @@ pub type TX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type TX_MONO_FST_VLD_R = crate::BitReader;
 #[doc = "Field `TX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
 pub type TX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type TX_PCM_CONF_R = crate::FieldReader;
-#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
 pub type TX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 #[doc = "Field `TX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for transmitted data."]
 pub type TX_PCM_BYPASS_R = crate::BitReader;
@@ -114,7 +114,7 @@ impl R {
     pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R {
         TX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
     pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R {
         TX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
@@ -198,121 +198,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_reset(&mut self) -> TX_RESET_W<TX_CONF_SPEC> {
         TX_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset Tx AFIFO"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<TX_CONF_SPEC> {
         TX_FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to start transmitting data"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<TX_CONF_SPEC> {
         TX_START_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<TX_CONF_SPEC> {
         TX_SLAVE_MOD_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono(&mut self) -> TX_MONO_W<TX_CONF_SPEC> {
         TX_MONO_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_equal(&mut self) -> TX_CHAN_EQUAL_W<TX_CONF_SPEC> {
         TX_CHAN_EQUAL_W::new(self, 6)
     }
     #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W<TX_CONF_SPEC> {
         TX_BIG_ENDIAN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_update(&mut self) -> TX_UPDATE_W<TX_CONF_SPEC> {
         TX_UPDATE_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_mono_fst_vld(&mut self) -> TX_MONO_FST_VLD_W<TX_CONF_SPEC> {
         TX_MONO_FST_VLD_W::new(self, 9)
     }
-    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;"]
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<TX_CONF_SPEC> {
         TX_PCM_CONF_W::new(self, 10)
     }
     #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<TX_CONF_SPEC> {
         TX_PCM_BYPASS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<TX_CONF_SPEC> {
         TX_STOP_EN_W::new(self, 13)
     }
     #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_left_align(&mut self) -> TX_LEFT_ALIGN_W<TX_CONF_SPEC> {
         TX_LEFT_ALIGN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_24_fill_en(&mut self) -> TX_24_FILL_EN_W<TX_CONF_SPEC> {
         TX_24_FILL_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_idle_pol(&mut self) -> TX_WS_IDLE_POL_W<TX_CONF_SPEC> {
         TX_WS_IDLE_POL_W::new(self, 17)
     }
     #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bit_order(&mut self) -> TX_BIT_ORDER_W<TX_CONF_SPEC> {
         TX_BIT_ORDER_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_en(&mut self) -> TX_TDM_EN_W<TX_CONF_SPEC> {
         TX_TDM_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<TX_CONF_SPEC> {
         TX_PDM_EN_W::new(self, 20)
     }
     #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<TX_CONF_SPEC> {
         TX_CHAN_MOD_W::new(self, 24)
     }
     #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<TX_CONF_SPEC> {
         SIG_LOOPBACK_W::new(self, 27)
     }
diff --git a/esp32s3/src/i2s1/tx_conf1.rs b/esp32s3/src/i2s1/tx_conf1.rs
index 196c16c060..ca317bc3f4 100644
--- a/esp32s3/src/i2s1/tx_conf1.rs
+++ b/esp32s3/src/i2s1/tx_conf1.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W<TX_CONF1_SPEC> {
         TX_TDM_WS_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<TX_CONF1_SPEC> {
         TX_BCK_DIV_NUM_W::new(self, 7)
     }
     #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<TX_CONF1_SPEC> {
         TX_BITS_MOD_W::new(self, 13)
     }
     #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W<TX_CONF1_SPEC> {
         TX_HALF_SAMPLE_BITS_W::new(self, 18)
     }
     #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W<TX_CONF1_SPEC> {
         TX_TDM_CHAN_BITS_W::new(self, 24)
     }
     #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<TX_CONF1_SPEC> {
         TX_MSB_SHIFT_W::new(self, 29)
     }
     #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W<TX_CONF1_SPEC> {
         TX_BCK_NO_DLY_W::new(self, 30)
     }
diff --git a/esp32s3/src/i2s1/tx_tdm_ctrl.rs b/esp32s3/src/i2s1/tx_tdm_ctrl.rs
index 9d5efa9df7..859510cb36 100644
--- a/esp32s3/src/i2s1/tx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s1/tx_tdm_ctrl.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan0_en(&mut self) -> TX_TDM_CHAN0_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan1_en(&mut self) -> TX_TDM_CHAN1_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan2_en(&mut self) -> TX_TDM_CHAN2_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan3_en(&mut self) -> TX_TDM_CHAN3_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN3_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan4_en(&mut self) -> TX_TDM_CHAN4_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN4_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan5_en(&mut self) -> TX_TDM_CHAN5_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN5_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan6_en(&mut self) -> TX_TDM_CHAN6_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN6_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan7_en(&mut self) -> TX_TDM_CHAN7_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN7_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan8_en(&mut self) -> TX_TDM_CHAN8_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN8_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan9_en(&mut self) -> TX_TDM_CHAN9_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN9_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan10_en(&mut self) -> TX_TDM_CHAN10_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN10_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan11_en(&mut self) -> TX_TDM_CHAN11_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN11_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan12_en(&mut self) -> TX_TDM_CHAN12_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN12_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan13_en(&mut self) -> TX_TDM_CHAN13_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN13_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan14_en(&mut self) -> TX_TDM_CHAN14_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN14_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_chan15_en(&mut self) -> TX_TDM_CHAN15_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_CHAN15_EN_W::new(self, 15)
     }
     #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_tot_chan_num(&mut self) -> TX_TDM_TOT_CHAN_NUM_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_TOT_CHAN_NUM_W::new(self, 16)
     }
     #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tdm_skip_msk_en(&mut self) -> TX_TDM_SKIP_MSK_EN_W<TX_TDM_CTRL_SPEC> {
         TX_TDM_SKIP_MSK_EN_W::new(self, 20)
     }
diff --git a/esp32s3/src/i2s1/tx_timing.rs b/esp32s3/src/i2s1/tx_timing.rs
index 82d20256cd..a9e6a29856 100644
--- a/esp32s3/src/i2s1/tx_timing.rs
+++ b/esp32s3/src/i2s1/tx_timing.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<TX_TIMING_SPEC> {
         TX_SD_OUT_DM_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<TX_TIMING_SPEC> {
         TX_SD1_OUT_DM_W::new(self, 4)
     }
     #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<TX_TIMING_SPEC> {
         TX_WS_OUT_DM_W::new(self, 16)
     }
     #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<TX_TIMING_SPEC> {
         TX_BCK_OUT_DM_W::new(self, 20)
     }
     #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<TX_TIMING_SPEC> {
         TX_WS_IN_DM_W::new(self, 24)
     }
     #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<TX_TIMING_SPEC> {
         TX_BCK_IN_DM_W::new(self, 28)
     }
diff --git a/esp32s3/src/interrupt_core0/aes_int_map.rs b/esp32s3/src/interrupt_core0/aes_int_map.rs
index 320bab6650..f534a25d50 100644
--- a/esp32s3/src/interrupt_core0/aes_int_map.rs
+++ b/esp32s3/src/interrupt_core0/aes_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map aes interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn aes_int_map(&mut self) -> AES_INT_MAP_W<AES_INT_MAP_SPEC> {
         AES_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/apb_adc_int_map.rs b/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
index 654bc94698..df646617c2 100644
--- a/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
+++ b/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map apb_adc interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_adc_int_map(&mut self) -> APB_ADC_INT_MAP_W<APB_ADC_INT_MAP_SPEC> {
         APB_ADC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs b/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
index dc23015574..babb89a014 100644
--- a/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map assist_debug interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn assist_debug_intr_map(&mut self) -> ASSIST_DEBUG_INTR_MAP_W<ASSIST_DEBUG_INTR_MAP_SPEC> {
         ASSIST_DEBUG_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs b/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
index bb0b60f71a..7b1d997b9b 100644
--- a/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn backup_pms_violate_intr_map(
         &mut self,
     ) -> BACKUP_PMS_VIOLATE_INTR_MAP_W<BACKUP_PMS_VIOLATE_INTR_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/bb_int_map.rs b/esp32s3/src/interrupt_core0/bb_int_map.rs
index 829b3dd533..34a10950b2 100644
--- a/esp32s3/src/interrupt_core0/bb_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_int_map(&mut self) -> BB_INT_MAP_W<BB_INT_MAP_SPEC> {
         BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/bt_bb_int_map.rs b/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
index d39ab7ef15..0835bfbcf3 100644
--- a/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bt_bb interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_bb_int_map(&mut self) -> BT_BB_INT_MAP_W<BT_BB_INT_MAP_SPEC> {
         BT_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
index 0a4352fd8b..e4f800f8ba 100644
--- a/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_bt_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_bb_nmi_map(&mut self) -> BT_BB_NMI_MAP_W<BT_BB_NMI_MAP_SPEC> {
         BT_BB_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/bt_mac_int_map.rs b/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
index 3f15ca1a7c..3d8dc1b3ef 100644
--- a/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_mac interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_mac_int_map(&mut self) -> BT_MAC_INT_MAP_W<BT_MAC_INT_MAP_SPEC> {
         BT_MAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs b/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
index e78394fe2d..5ed0ae5293 100644
--- a/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core0_acs interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_core0_acs_int_map(
         &mut self,
     ) -> CACHE_CORE0_ACS_INT_MAP_W<CACHE_CORE0_ACS_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs b/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
index 324f339612..a062eae17e 100644
--- a/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core1_acs interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_core1_acs_int_map(
         &mut self,
     ) -> CACHE_CORE1_ACS_INT_MAP_W<CACHE_CORE1_ACS_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/cache_ia_int_map.rs b/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
index 7a6dfe82fe..dbd0f5ebb7 100644
--- a/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_ia interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_map(&mut self) -> CACHE_IA_INT_MAP_W<CACHE_IA_INT_MAP_SPEC> {
         CACHE_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/can_int_map.rs b/esp32s3/src/interrupt_core0/can_int_map.rs
index aeea5203ed..6d49fc7bd5 100644
--- a/esp32s3/src/interrupt_core0/can_int_map.rs
+++ b/esp32s3/src/interrupt_core0/can_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map can interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn can_int_map(&mut self) -> CAN_INT_MAP_W<CAN_INT_MAP_SPEC> {
         CAN_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/clock_gate.rs b/esp32s3/src/interrupt_core0/clock_gate.rs
index 4a690814e9..25eff3a07d 100644
--- a/esp32s3/src/interrupt_core0/clock_gate.rs
+++ b/esp32s3/src/interrupt_core0/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - this register uesd to control clock-gating interupt martrix"]
     #[inline(always)]
-    #[must_use]
     pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W<CLOCK_GATE_SPEC> {
         REG_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
index 5a2f36412f..003a584f5a 100644
--- a/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
index 4476ae82de..78c10ec5ae 100644
--- a/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
index fe3a679487..aa3dd744eb 100644
--- a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
index c8d10aa93a..ad8592dc6e 100644
--- a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_size_intr_map(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_W<
diff --git a/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
index abd2cebed3..fe7d3e3f55 100644
--- a/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
index 79bdebcf22..5a810dbff0 100644
--- a/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
index da876d8e57..0d15db6d67 100644
--- a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
index 09c6563acd..1931eeb325 100644
--- a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_size_intr_map(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_W<
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index 10e0fdf307..e03c0665b8 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_0_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_0_MAP_W<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index 082c6e902f..c6b818c02a 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_1_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_1_MAP_W<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index d8bff27f7b..094b7c4873 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_2_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_2_MAP_W<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index 430b731f6b..acfc2b7440 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_3_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_3_MAP_W<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/date.rs b/esp32s3/src/interrupt_core0/date.rs
index f74f7f28fd..8e8133a1c2 100644
--- a/esp32s3/src/interrupt_core0/date.rs
+++ b/esp32s3/src/interrupt_core0/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_reg_date(&mut self) -> INTERRUPT_REG_DATE_W<DATE_SPEC> {
         INTERRUPT_REG_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs b/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
index cf78046195..df82086ef6 100644
--- a/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_prelaod interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_int_map(
         &mut self,
     ) -> DCACHE_PRELOAD_INT_MAP_W<DCACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs b/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
index 5899f31542..5d79d38907 100644
--- a/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_sync interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_int_map(&mut self) -> DCACHE_SYNC_INT_MAP_W<DCACHE_SYNC_INT_MAP_SPEC> {
         DCACHE_SYNC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
index 67f0081102..63ca6d7cf9 100644
--- a/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_pms_monitor_violate_intr_map(
         &mut self,
     ) -> DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_W<DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs b/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
index baf35678fa..646d40ab3f 100644
--- a/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_extmem_reject interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_extmem_reject_int_map(
         &mut self,
     ) -> DMA_EXTMEM_REJECT_INT_MAP_W<DMA_EXTMEM_REJECT_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
index 8782c20c89..52f2da688d 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch0_int_map(&mut self) -> DMA_IN_CH0_INT_MAP_W<DMA_IN_CH0_INT_MAP_SPEC> {
         DMA_IN_CH0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
index 232c62216d..985d041029 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch1_int_map(&mut self) -> DMA_IN_CH1_INT_MAP_W<DMA_IN_CH1_INT_MAP_SPEC> {
         DMA_IN_CH1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
index 761e313f9a..84e783076a 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch2_int_map(&mut self) -> DMA_IN_CH2_INT_MAP_W<DMA_IN_CH2_INT_MAP_SPEC> {
         DMA_IN_CH2_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
index 08265f5d45..dfbf1aeac5 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch3_int_map(&mut self) -> DMA_IN_CH3_INT_MAP_W<DMA_IN_CH3_INT_MAP_SPEC> {
         DMA_IN_CH3_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
index 74f8198518..684bdd1a32 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch4_int_map(&mut self) -> DMA_IN_CH4_INT_MAP_W<DMA_IN_CH4_INT_MAP_SPEC> {
         DMA_IN_CH4_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
index 7b36f36d55..9ee01e51bd 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch0_int_map(&mut self) -> DMA_OUT_CH0_INT_MAP_W<DMA_OUT_CH0_INT_MAP_SPEC> {
         DMA_OUT_CH0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
index 12834727e7..87411b79b1 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch1_int_map(&mut self) -> DMA_OUT_CH1_INT_MAP_W<DMA_OUT_CH1_INT_MAP_SPEC> {
         DMA_OUT_CH1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
index 9b77cfd110..7a9b343944 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch2_int_map(&mut self) -> DMA_OUT_CH2_INT_MAP_W<DMA_OUT_CH2_INT_MAP_SPEC> {
         DMA_OUT_CH2_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
index 597f5a32e2..23201ee4f0 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch3_int_map(&mut self) -> DMA_OUT_CH3_INT_MAP_W<DMA_OUT_CH3_INT_MAP_SPEC> {
         DMA_OUT_CH3_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
index 742bab5135..2cd2daf301 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch4_int_map(&mut self) -> DMA_OUT_CH4_INT_MAP_W<DMA_OUT_CH4_INT_MAP_SPEC> {
         DMA_OUT_CH4_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/efuse_int_map.rs b/esp32s3/src/interrupt_core0/efuse_int_map.rs
index ad9cb018b7..e5debe119d 100644
--- a/esp32s3/src/interrupt_core0/efuse_int_map.rs
+++ b/esp32s3/src/interrupt_core0/efuse_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map efuse interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_int_map(&mut self) -> EFUSE_INT_MAP_W<EFUSE_INT_MAP_SPEC> {
         EFUSE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
index 9570dbc819..efe4eb2dce 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_app_map(
         &mut self,
     ) -> GPIO_INTERRUPT_APP_MAP_W<GPIO_INTERRUPT_APP_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
index 3ab39b23dd..894b9834db 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_app_nmi_map(
         &mut self,
     ) -> GPIO_INTERRUPT_APP_NMI_MAP_W<GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
index 1b543c7e5d..a0d1bf80ac 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_pro_map(
         &mut self,
     ) -> GPIO_INTERRUPT_PRO_MAP_W<GPIO_INTERRUPT_PRO_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index adc7844782..3d22adf543 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_pro_nmi_map(
         &mut self,
     ) -> GPIO_INTERRUPT_PRO_NMI_MAP_W<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
index b0becf30f4..76481b7b80 100644
--- a/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_intr_map(&mut self) -> I2C_EXT0_INTR_MAP_W<I2C_EXT0_INTR_MAP_SPEC> {
         I2C_EXT0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs b/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
index a28cabdc33..537910a21a 100644
--- a/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_intr_map(&mut self) -> I2C_EXT1_INTR_MAP_W<I2C_EXT1_INTR_MAP_SPEC> {
         I2C_EXT1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs b/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
index 416c7d0384..3d461879f4 100644
--- a/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_mst interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_mst_int_map(&mut self) -> I2C_MST_INT_MAP_W<I2C_MST_INT_MAP_SPEC> {
         I2C_MST_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/i2s0_int_map.rs b/esp32s3/src/interrupt_core0/i2s0_int_map.rs
index 281cbd8837..7d1800ea23 100644
--- a/esp32s3/src/interrupt_core0/i2s0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2s0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_int_map(&mut self) -> I2S0_INT_MAP_W<I2S0_INT_MAP_SPEC> {
         I2S0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/i2s1_int_map.rs b/esp32s3/src/interrupt_core0/i2s1_int_map.rs
index 245611620b..d3967a497a 100644
--- a/esp32s3/src/interrupt_core0/i2s1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2s1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_int_map(&mut self) -> I2S1_INT_MAP_W<I2S1_INT_MAP_SPEC> {
         I2S1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/icache_preload_int_map.rs b/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
index a8a76702a0..039a283085 100644
--- a/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_preload interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_int_map(
         &mut self,
     ) -> ICACHE_PRELOAD_INT_MAP_W<ICACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/icache_sync_int_map.rs b/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
index cb95f8f69c..d27f10d7ab 100644
--- a/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_sync interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_int_map(&mut self) -> ICACHE_SYNC_INT_MAP_W<ICACHE_SYNC_INT_MAP_SPEC> {
         ICACHE_SYNC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs b/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
index 0a11252140..ecea8f0b8a 100644
--- a/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
+++ b/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map lcd_cam interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cam_int_map(&mut self) -> LCD_CAM_INT_MAP_W<LCD_CAM_INT_MAP_SPEC> {
         LCD_CAM_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/ledc_int_map.rs b/esp32s3/src/interrupt_core0/ledc_int_map.rs
index 1347610e6c..443601b38e 100644
--- a/esp32s3/src/interrupt_core0/ledc_int_map.rs
+++ b/esp32s3/src/interrupt_core0/ledc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map ledc interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_int_map(&mut self) -> LEDC_INT_MAP_W<LEDC_INT_MAP_SPEC> {
         LEDC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/mac_nmi_map.rs b/esp32s3/src/interrupt_core0/mac_nmi_map.rs
index 6a75e9e92d..a78c0a2634 100644
--- a/esp32s3/src/interrupt_core0/mac_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/mac_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn mac_nmi_map(&mut self) -> MAC_NMI_MAP_W<MAC_NMI_MAP_SPEC> {
         MAC_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pcnt_intr_map.rs b/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
index 0a434f0545..c65241d5db 100644
--- a/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pcnt interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_intr_map(&mut self) -> PCNT_INTR_MAP_W<PCNT_INTR_MAP_SPEC> {
         PCNT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/peri_backup_int_map.rs b/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
index 4721f1a35b..1e753f653a 100644
--- a/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
+++ b/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map peri_backup interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_backup_int_map(&mut self) -> PERI_BACKUP_INT_MAP_W<PERI_BACKUP_INT_MAP_SPEC> {
         PERI_BACKUP_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs b/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
index 0bc2531f00..6b5bfad42b 100644
--- a/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn mac_intr_map(&mut self) -> MAC_INTR_MAP_W<PRO_MAC_INTR_MAP_SPEC> {
         MAC_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pwm0_intr_map.rs b/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
index 98b4139112..aa0be2c307 100644
--- a/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_intr_map(&mut self) -> PWM0_INTR_MAP_W<PWM0_INTR_MAP_SPEC> {
         PWM0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pwm1_intr_map.rs b/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
index 19fa011b6b..9b0681d122 100644
--- a/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_intr_map(&mut self) -> PWM1_INTR_MAP_W<PWM1_INTR_MAP_SPEC> {
         PWM1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pwm2_intr_map.rs b/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
index 13514efe9f..cb698b3cd9 100644
--- a/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_intr_map(&mut self) -> PWM2_INTR_MAP_W<PWM2_INTR_MAP_SPEC> {
         PWM2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pwm3_intr_map.rs b/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
index 8b8c4fa5ee..9275cf6c70 100644
--- a/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_intr_map(&mut self) -> PWM3_INTR_MAP_W<PWM3_INTR_MAP_SPEC> {
         PWM3_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/pwr_intr_map.rs b/esp32s3/src/interrupt_core0/pwr_intr_map.rs
index 319c922f03..913c60e54c 100644
--- a/esp32s3/src/interrupt_core0/pwr_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwr_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwr interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_intr_map(&mut self) -> PWR_INTR_MAP_W<PWR_INTR_MAP_SPEC> {
         PWR_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rmt_intr_map.rs b/esp32s3/src/interrupt_core0/rmt_intr_map.rs
index b4d90c4f3b..53f645a912 100644
--- a/esp32s3/src/interrupt_core0/rmt_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/rmt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rmt interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_intr_map(&mut self) -> RMT_INTR_MAP_W<RMT_INTR_MAP_SPEC> {
         RMT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rsa_int_map.rs b/esp32s3/src/interrupt_core0/rsa_int_map.rs
index 949dfb8414..771194a00b 100644
--- a/esp32s3/src/interrupt_core0/rsa_int_map.rs
+++ b/esp32s3/src/interrupt_core0/rsa_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rsa interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_int_map(&mut self) -> RSA_INT_MAP_W<RSA_INT_MAP_SPEC> {
         RSA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs b/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
index 050cd51640..73f6e5b9d3 100644
--- a/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rtc_core interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_core_intr_map(&mut self) -> RTC_CORE_INTR_MAP_W<RTC_CORE_INTR_MAP_SPEC> {
         RTC_CORE_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rwble_irq_map.rs b/esp32s3/src/interrupt_core0/rwble_irq_map.rs
index 048efd70d9..7163ba5536 100644
--- a/esp32s3/src/interrupt_core0/rwble_irq_map.rs
+++ b/esp32s3/src/interrupt_core0/rwble_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_irq interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwble_irq_map(&mut self) -> RWBLE_IRQ_MAP_W<RWBLE_IRQ_MAP_SPEC> {
         RWBLE_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rwble_nmi_map.rs b/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
index 2185a56a5c..5350485322 100644
--- a/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwble_nmi_map(&mut self) -> RWBLE_NMI_MAP_W<RWBLE_NMI_MAP_SPEC> {
         RWBLE_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rwbt_irq_map.rs b/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
index 7db01c79f6..cab911b3ad 100644
--- a/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
+++ b/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_irq interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwbt_irq_map(&mut self) -> RWBT_IRQ_MAP_W<RWBT_IRQ_MAP_SPEC> {
         RWBT_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs b/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
index 7a30c09fe1..37908e03af 100644
--- a/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac rwbt_nmi to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwbt_nmi_map(&mut self) -> RWBT_NMI_MAP_W<RWBT_NMI_MAP_SPEC> {
         RWBT_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs b/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
index 6a1d914200..a41fabc035 100644
--- a/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
+++ b/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map sdio_host interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_host_interrupt_map(
         &mut self,
     ) -> SDIO_HOST_INTERRUPT_MAP_W<SDIO_HOST_INTERRUPT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/sha_int_map.rs b/esp32s3/src/interrupt_core0/sha_int_map.rs
index 7edca6d1c3..58d76e5c8e 100644
--- a/esp32s3/src/interrupt_core0/sha_int_map.rs
+++ b/esp32s3/src/interrupt_core0/sha_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map sha interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sha_int_map(&mut self) -> SHA_INT_MAP_W<SHA_INT_MAP_SPEC> {
         SHA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/slc0_intr_map.rs b/esp32s3/src/interrupt_core0/slc0_intr_map.rs
index cf9ee30f41..2092b67667 100644
--- a/esp32s3/src/interrupt_core0/slc0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/slc0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_intr_map(&mut self) -> SLC0_INTR_MAP_W<SLC0_INTR_MAP_SPEC> {
         SLC0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/slc1_intr_map.rs b/esp32s3/src/interrupt_core0/slc1_intr_map.rs
index 7e4d28571b..57f3febb07 100644
--- a/esp32s3/src/interrupt_core0/slc1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/slc1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_intr_map(&mut self) -> SLC1_INTR_MAP_W<SLC1_INTR_MAP_SPEC> {
         SLC1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
index 3010e86e3b..0c172dec83 100644
--- a/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi2_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_int_map(&mut self) -> SPI2_DMA_INT_MAP_W<SPI2_DMA_INT_MAP_SPEC> {
         SPI2_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
index f524539d4f..5dbbb85da5 100644
--- a/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi3_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_int_map(&mut self) -> SPI3_DMA_INT_MAP_W<SPI3_DMA_INT_MAP_SPEC> {
         SPI3_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
index 3af08da8cd..456bed237c 100644
--- a/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi4_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_dma_int_map(&mut self) -> SPI4_DMA_INT_MAP_W<SPI4_DMA_INT_MAP_SPEC> {
         SPI4_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi_intr_1_map.rs b/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
index 3c29e86933..b2baf672df 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_1_map(&mut self) -> SPI_INTR_1_MAP_W<SPI_INTR_1_MAP_SPEC> {
         SPI_INTR_1_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi_intr_2_map.rs b/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
index 3d671d41b9..c9b98603bd 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_2_map(&mut self) -> SPI_INTR_2_MAP_W<SPI_INTR_2_MAP_SPEC> {
         SPI_INTR_2_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi_intr_3_map.rs b/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
index 2da2f81a72..e83b2bcbf7 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_3_map(&mut self) -> SPI_INTR_3_MAP_W<SPI_INTR_3_MAP_SPEC> {
         SPI_INTR_3_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi_intr_4_map.rs b/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
index 9add05d1db..f2154f3d55 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_4_map(&mut self) -> SPI_INTR_4_MAP_W<SPI_INTR_4_MAP_SPEC> {
         SPI_INTR_4_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs b/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
index 6d4f89fbca..284cdb2b6f 100644
--- a/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_mem_reject interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_mem_reject_intr_map(
         &mut self,
     ) -> SPI_MEM_REJECT_INTR_MAP_W<SPI_MEM_REJECT_INTR_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
index 58a4b9e335..69c27a8cdf 100644
--- a/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target0_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET0_INT_MAP_W<SYSTIMER_TARGET0_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
index b992ce2bea..70b48c913e 100644
--- a/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target1_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET1_INT_MAP_W<SYSTIMER_TARGET1_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
index 8fcecd5797..37eaab6d20 100644
--- a/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target2_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET2_INT_MAP_W<SYSTIMER_TARGET2_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs b/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
index 968bf94d2d..e463f5fe54 100644
--- a/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_t0_int_map(&mut self) -> TG1_T0_INT_MAP_W<TG1_T0_INT_MAP_SPEC> {
         TG1_T0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs b/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
index 3d877111fa..214bb56709 100644
--- a/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_t1_int_map(&mut self) -> TG1_T1_INT_MAP_W<TG1_T1_INT_MAP_SPEC> {
         TG1_T1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs b/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
index 8c904d9c33..66ed59e198 100644
--- a/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_wdt interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_wdt_int_map(&mut self) -> TG1_WDT_INT_MAP_W<TG1_WDT_INT_MAP_SPEC> {
         TG1_WDT_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/tg_t0_int_map.rs b/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
index 6bceea37af..534d633089 100644
--- a/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_t0_int_map(&mut self) -> TG_T0_INT_MAP_W<TG_T0_INT_MAP_SPEC> {
         TG_T0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/tg_t1_int_map.rs b/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
index 5779245213..13b8d32443 100644
--- a/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_t1_int_map(&mut self) -> TG_T1_INT_MAP_W<TG_T1_INT_MAP_SPEC> {
         TG_T1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs b/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
index 6067f78171..fa306cd4bf 100644
--- a/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rg_wdt interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_wdt_int_map(&mut self) -> TG_WDT_INT_MAP_W<TG_WDT_INT_MAP_SPEC> {
         TG_WDT_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/timer_int1_map.rs b/esp32s3/src/interrupt_core0/timer_int1_map.rs
index fa19caffc3..8ab84c774c 100644
--- a/esp32s3/src/interrupt_core0/timer_int1_map.rs
+++ b/esp32s3/src/interrupt_core0/timer_int1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_int1_map(&mut self) -> TIMER_INT1_MAP_W<TIMER_INT1_MAP_SPEC> {
         TIMER_INT1_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/timer_int2_map.rs b/esp32s3/src/interrupt_core0/timer_int2_map.rs
index 657300379c..ca951eb9cb 100644
--- a/esp32s3/src/interrupt_core0/timer_int2_map.rs
+++ b/esp32s3/src/interrupt_core0/timer_int2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_int2_map(&mut self) -> TIMER_INT2_MAP_W<TIMER_INT2_MAP_SPEC> {
         TIMER_INT2_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/uart1_intr_map.rs b/esp32s3/src/interrupt_core0/uart1_intr_map.rs
index 4e90a6cb1e..c43abb8150 100644
--- a/esp32s3/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_intr_map(&mut self) -> UART1_INTR_MAP_W<UART1_INTR_MAP_SPEC> {
         UART1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/uart2_intr_map.rs b/esp32s3/src/interrupt_core0/uart2_intr_map.rs
index ffecc62582..3c8b15a1be 100644
--- a/esp32s3/src/interrupt_core0/uart2_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_intr_map(&mut self) -> UART2_INTR_MAP_W<UART2_INTR_MAP_SPEC> {
         UART2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/uart_intr_map.rs b/esp32s3/src/interrupt_core0/uart_intr_map.rs
index 431b862c48..f1793b8a2b 100644
--- a/esp32s3/src/interrupt_core0/uart_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_intr_map(&mut self) -> UART_INTR_MAP_W<UART_INTR_MAP_SPEC> {
         UART_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/uhci0_intr_map.rs b/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
index 24127435c1..96362abb3b 100644
--- a/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_intr_map(&mut self) -> UHCI0_INTR_MAP_W<UHCI0_INTR_MAP_SPEC> {
         UHCI0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/uhci1_intr_map.rs b/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
index 5ca1dc8243..c2936038d8 100644
--- a/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_intr_map(&mut self) -> UHCI1_INTR_MAP_W<UHCI1_INTR_MAP_SPEC> {
         UHCI1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/usb_device_int_map.rs b/esp32s3/src/interrupt_core0/usb_device_int_map.rs
index 43cd0aff6f..d6367b2680 100644
--- a/esp32s3/src/interrupt_core0/usb_device_int_map.rs
+++ b/esp32s3/src/interrupt_core0/usb_device_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb_device interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_device_int_map(&mut self) -> USB_DEVICE_INT_MAP_W<USB_DEVICE_INT_MAP_SPEC> {
         USB_DEVICE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/usb_intr_map.rs b/esp32s3/src/interrupt_core0/usb_intr_map.rs
index 5dc113a06d..50fffd8763 100644
--- a/esp32s3/src/interrupt_core0/usb_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/usb_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_intr_map(&mut self) -> USB_INTR_MAP_W<USB_INTR_MAP_SPEC> {
         USB_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core0/wdg_int_map.rs b/esp32s3/src/interrupt_core0/wdg_int_map.rs
index 26bbed5d70..80f41b91de 100644
--- a/esp32s3/src/interrupt_core0/wdg_int_map.rs
+++ b/esp32s3/src/interrupt_core0/wdg_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map wdg interrupt to one of core0's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_int_map(&mut self) -> WDG_INT_MAP_W<WDG_INT_MAP_SPEC> {
         WDG_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/aes_int_map.rs b/esp32s3/src/interrupt_core1/aes_int_map.rs
index 734c93d7d1..94cd7def6e 100644
--- a/esp32s3/src/interrupt_core1/aes_int_map.rs
+++ b/esp32s3/src/interrupt_core1/aes_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map aes interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn aes_int_map(&mut self) -> AES_INT_MAP_W<AES_INT_MAP_SPEC> {
         AES_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/apb_adc_int_map.rs b/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
index c97c6c9c03..757e5bd722 100644
--- a/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
+++ b/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map apb_adc interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_adc_int_map(&mut self) -> APB_ADC_INT_MAP_W<APB_ADC_INT_MAP_SPEC> {
         APB_ADC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/app_mac_intr_map.rs b/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
index 44f0d66518..05f26df1fb 100644
--- a/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn mac_intr_map(&mut self) -> MAC_INTR_MAP_W<APP_MAC_INTR_MAP_SPEC> {
         MAC_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs b/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
index f0b07360ab..5d75b29d7d 100644
--- a/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map assist_debug interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn assist_debug_intr_map(&mut self) -> ASSIST_DEBUG_INTR_MAP_W<ASSIST_DEBUG_INTR_MAP_SPEC> {
         ASSIST_DEBUG_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs b/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
index ea805d447e..7129165dbb 100644
--- a/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn backup_pms_violate_intr_map(
         &mut self,
     ) -> BACKUP_PMS_VIOLATE_INTR_MAP_W<BACKUP_PMS_VIOLATE_INTR_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/bb_int_map.rs b/esp32s3/src/interrupt_core1/bb_int_map.rs
index a7a1a53e8e..964744c9bf 100644
--- a/esp32s3/src/interrupt_core1/bb_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_int_map(&mut self) -> BB_INT_MAP_W<BB_INT_MAP_SPEC> {
         BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/bt_bb_int_map.rs b/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
index 765fa53343..2b95c8c2d2 100644
--- a/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bt_bb interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_bb_int_map(&mut self) -> BT_BB_INT_MAP_W<BT_BB_INT_MAP_SPEC> {
         BT_BB_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs b/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
index f9e24b3cec..c7e336b4f6 100644
--- a/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_bt_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_bb_nmi_map(&mut self) -> BT_BB_NMI_MAP_W<BT_BB_NMI_MAP_SPEC> {
         BT_BB_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/bt_mac_int_map.rs b/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
index 4b3b718b4f..767a60bb28 100644
--- a/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_mac interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_mac_int_map(&mut self) -> BT_MAC_INT_MAP_W<BT_MAC_INT_MAP_SPEC> {
         BT_MAC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs b/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
index 428288a1a3..d12fb1d06b 100644
--- a/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core0_acs interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_core0_acs_int_map(
         &mut self,
     ) -> CACHE_CORE0_ACS_INT_MAP_W<CACHE_CORE0_ACS_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs b/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
index f466dabf02..dfb9baec40 100644
--- a/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core1_acs interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_core1_acs_int_map(
         &mut self,
     ) -> CACHE_CORE1_ACS_INT_MAP_W<CACHE_CORE1_ACS_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/cache_ia_int_map.rs b/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
index 2ea21ecddf..677eee7641 100644
--- a/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_ia interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cache_ia_int_map(&mut self) -> CACHE_IA_INT_MAP_W<CACHE_IA_INT_MAP_SPEC> {
         CACHE_IA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/can_int_map.rs b/esp32s3/src/interrupt_core1/can_int_map.rs
index f3f7d113ff..c19db9e728 100644
--- a/esp32s3/src/interrupt_core1/can_int_map.rs
+++ b/esp32s3/src/interrupt_core1/can_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map can interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn can_int_map(&mut self) -> CAN_INT_MAP_W<CAN_INT_MAP_SPEC> {
         CAN_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/clock_gate.rs b/esp32s3/src/interrupt_core1/clock_gate.rs
index 4a690814e9..25eff3a07d 100644
--- a/esp32s3/src/interrupt_core1/clock_gate.rs
+++ b/esp32s3/src/interrupt_core1/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - this register uesd to control clock-gating interupt martrix"]
     #[inline(always)]
-    #[must_use]
     pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W<CLOCK_GATE_SPEC> {
         REG_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
index 302f665942..0fc21636e4 100644
--- a/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
index f4f9271b51..4b3dae6349 100644
--- a/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
index f061d5ab8a..11104f31da 100644
--- a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
index e401a3c240..718b26712a 100644
--- a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_size_intr_map(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_W<
diff --git a/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
index cf0706d06a..df7cc4b222 100644
--- a/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
index aae10abd9a..9df2bcc366 100644
--- a/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
index 037e3d6341..39fbd93e37 100644
--- a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_intr_map(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_W<CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
index 883fb4f92b..1a31501312 100644
--- a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_size_intr_map(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_W<
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
index da42adcea5..e8fe2ee3d7 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_0_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_0_MAP_W<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
index 6c3f0c5886..a947705ca6 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_1_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_1_MAP_W<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
index 16cac30f3a..76259d5918 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_2_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_2_MAP_W<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
index d026b8e3c8..c4ff70dd6b 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_3_map(
         &mut self,
     ) -> CPU_INTR_FROM_CPU_3_MAP_W<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/date.rs b/esp32s3/src/interrupt_core1/date.rs
index cbf91ad085..97e1364031 100644
--- a/esp32s3/src/interrupt_core1/date.rs
+++ b/esp32s3/src/interrupt_core1/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_date(&mut self) -> INTERRUPT_DATE_W<DATE_SPEC> {
         INTERRUPT_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs b/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
index d5f52469c9..2a353eb65d 100644
--- a/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_prelaod interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_preload_int_map(
         &mut self,
     ) -> DCACHE_PRELOAD_INT_MAP_W<DCACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs b/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
index 233fb1c0b7..797fcdd5e2 100644
--- a/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_sync interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_sync_int_map(&mut self) -> DCACHE_SYNC_INT_MAP_W<DCACHE_SYNC_INT_MAP_SPEC> {
         DCACHE_SYNC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
index 732a19b5e2..ffd444495f 100644
--- a/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_pms_monitor_violate_intr_map(
         &mut self,
     ) -> DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_W<DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC>
diff --git a/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs b/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
index b868201b1b..ff53070bfe 100644
--- a/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_extmem_reject interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_extmem_reject_int_map(
         &mut self,
     ) -> DMA_EXTMEM_REJECT_INT_MAP_W<DMA_EXTMEM_REJECT_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
index 47beabb89a..65ce666997 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch0_int_map(&mut self) -> DMA_IN_CH0_INT_MAP_W<DMA_IN_CH0_INT_MAP_SPEC> {
         DMA_IN_CH0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
index ffa7b70e71..b16f662e16 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch1_int_map(&mut self) -> DMA_IN_CH1_INT_MAP_W<DMA_IN_CH1_INT_MAP_SPEC> {
         DMA_IN_CH1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
index d73b5edb9a..1c707d45c0 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch2_int_map(&mut self) -> DMA_IN_CH2_INT_MAP_W<DMA_IN_CH2_INT_MAP_SPEC> {
         DMA_IN_CH2_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
index ede4239de9..ced13df8ea 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch3_int_map(&mut self) -> DMA_IN_CH3_INT_MAP_W<DMA_IN_CH3_INT_MAP_SPEC> {
         DMA_IN_CH3_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
index 409c7fe4fa..8401d796b4 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_in_ch4_int_map(&mut self) -> DMA_IN_CH4_INT_MAP_W<DMA_IN_CH4_INT_MAP_SPEC> {
         DMA_IN_CH4_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
index 43aa8a91fc..375f2e1a9a 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch0_int_map(&mut self) -> DMA_OUT_CH0_INT_MAP_W<DMA_OUT_CH0_INT_MAP_SPEC> {
         DMA_OUT_CH0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
index 85dbf089c5..89e2e85188 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch1_int_map(&mut self) -> DMA_OUT_CH1_INT_MAP_W<DMA_OUT_CH1_INT_MAP_SPEC> {
         DMA_OUT_CH1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
index 6d56d21068..b32a532919 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch2_int_map(&mut self) -> DMA_OUT_CH2_INT_MAP_W<DMA_OUT_CH2_INT_MAP_SPEC> {
         DMA_OUT_CH2_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
index 93499d5fdc..7d74b7d6a0 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch3_int_map(&mut self) -> DMA_OUT_CH3_INT_MAP_W<DMA_OUT_CH3_INT_MAP_SPEC> {
         DMA_OUT_CH3_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
index 251dda9005..08061f88c1 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_out_ch4_int_map(&mut self) -> DMA_OUT_CH4_INT_MAP_W<DMA_OUT_CH4_INT_MAP_SPEC> {
         DMA_OUT_CH4_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/efuse_int_map.rs b/esp32s3/src/interrupt_core1/efuse_int_map.rs
index 95c263a60a..dfad5a89e2 100644
--- a/esp32s3/src/interrupt_core1/efuse_int_map.rs
+++ b/esp32s3/src/interrupt_core1/efuse_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map efuse interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_int_map(&mut self) -> EFUSE_INT_MAP_W<EFUSE_INT_MAP_SPEC> {
         EFUSE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
index 916bc0a584..5c89c5cbfc 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_app_map(
         &mut self,
     ) -> GPIO_INTERRUPT_APP_MAP_W<GPIO_INTERRUPT_APP_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
index e9e34a8165..9073514d68 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_app_nmi_map(
         &mut self,
     ) -> GPIO_INTERRUPT_APP_NMI_MAP_W<GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
index cf4420766d..92b2528138 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_pro_map(
         &mut self,
     ) -> GPIO_INTERRUPT_PRO_MAP_W<GPIO_INTERRUPT_PRO_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
index 8d8f50bff5..740a7d4031 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_interrupt_pro_nmi_map(
         &mut self,
     ) -> GPIO_INTERRUPT_PRO_NMI_MAP_W<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs b/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
index bf30731a9e..ee3bdabc2b 100644
--- a/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_intr_map(&mut self) -> I2C_EXT0_INTR_MAP_W<I2C_EXT0_INTR_MAP_SPEC> {
         I2C_EXT0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs b/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
index f4e5ce06b4..b74ca19922 100644
--- a/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_intr_map(&mut self) -> I2C_EXT1_INTR_MAP_W<I2C_EXT1_INTR_MAP_SPEC> {
         I2C_EXT1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs b/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
index eb3c816058..6c4ea04e3c 100644
--- a/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_mst interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_mst_int_map(&mut self) -> I2C_MST_INT_MAP_W<I2C_MST_INT_MAP_SPEC> {
         I2C_MST_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/i2s0_int_map.rs b/esp32s3/src/interrupt_core1/i2s0_int_map.rs
index 0527a67eac..67ff89bf22 100644
--- a/esp32s3/src/interrupt_core1/i2s0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2s0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_int_map(&mut self) -> I2S0_INT_MAP_W<I2S0_INT_MAP_SPEC> {
         I2S0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/i2s1_int_map.rs b/esp32s3/src/interrupt_core1/i2s1_int_map.rs
index 855946f17e..6669e65a26 100644
--- a/esp32s3/src/interrupt_core1/i2s1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2s1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_int_map(&mut self) -> I2S1_INT_MAP_W<I2S1_INT_MAP_SPEC> {
         I2S1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/icache_preload_int_map.rs b/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
index 9aeed942ec..e6d5fdb80c 100644
--- a/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_preload interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_preload_int_map(
         &mut self,
     ) -> ICACHE_PRELOAD_INT_MAP_W<ICACHE_PRELOAD_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/icache_sync_int_map.rs b/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
index de4ae17948..7f69a8de56 100644
--- a/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_sync interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_sync_int_map(&mut self) -> ICACHE_SYNC_INT_MAP_W<ICACHE_SYNC_INT_MAP_SPEC> {
         ICACHE_SYNC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs b/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
index 8724724f32..fa9719aaf4 100644
--- a/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
+++ b/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map lcd_cam interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cam_int_map(&mut self) -> LCD_CAM_INT_MAP_W<LCD_CAM_INT_MAP_SPEC> {
         LCD_CAM_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/ledc_int_map.rs b/esp32s3/src/interrupt_core1/ledc_int_map.rs
index 17bb6241a7..be7f9fce6c 100644
--- a/esp32s3/src/interrupt_core1/ledc_int_map.rs
+++ b/esp32s3/src/interrupt_core1/ledc_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map ledc interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_int_map(&mut self) -> LEDC_INT_MAP_W<LEDC_INT_MAP_SPEC> {
         LEDC_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/mac_nmi_map.rs b/esp32s3/src/interrupt_core1/mac_nmi_map.rs
index 0b385b8ee7..9ba894c8ba 100644
--- a/esp32s3/src/interrupt_core1/mac_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/mac_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn mac_nmi_map(&mut self) -> MAC_NMI_MAP_W<MAC_NMI_MAP_SPEC> {
         MAC_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pcnt_intr_map.rs b/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
index e09d3b9553..aaa946ae17 100644
--- a/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pcnt interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_intr_map(&mut self) -> PCNT_INTR_MAP_W<PCNT_INTR_MAP_SPEC> {
         PCNT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/peri_backup_int_map.rs b/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
index 4cdec1b001..e04e7d0cca 100644
--- a/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
+++ b/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map peri_backup interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_backup_int_map(&mut self) -> PERI_BACKUP_INT_MAP_W<PERI_BACKUP_INT_MAP_SPEC> {
         PERI_BACKUP_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pwm0_intr_map.rs b/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
index 03f44715dd..d159ecc993 100644
--- a/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_intr_map(&mut self) -> PWM0_INTR_MAP_W<PWM0_INTR_MAP_SPEC> {
         PWM0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pwm1_intr_map.rs b/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
index b3e3b34c60..26092718b3 100644
--- a/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_intr_map(&mut self) -> PWM1_INTR_MAP_W<PWM1_INTR_MAP_SPEC> {
         PWM1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pwm2_intr_map.rs b/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
index 5e4969d363..bee4e9f162 100644
--- a/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_intr_map(&mut self) -> PWM2_INTR_MAP_W<PWM2_INTR_MAP_SPEC> {
         PWM2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pwm3_intr_map.rs b/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
index 0a748c8eb4..e61d465ff4 100644
--- a/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_intr_map(&mut self) -> PWM3_INTR_MAP_W<PWM3_INTR_MAP_SPEC> {
         PWM3_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/pwr_intr_map.rs b/esp32s3/src/interrupt_core1/pwr_intr_map.rs
index ded55ce46d..a8f39986a9 100644
--- a/esp32s3/src/interrupt_core1/pwr_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwr_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwr interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pwr_intr_map(&mut self) -> PWR_INTR_MAP_W<PWR_INTR_MAP_SPEC> {
         PWR_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rmt_intr_map.rs b/esp32s3/src/interrupt_core1/rmt_intr_map.rs
index 99ff83b01d..9f4838f1d2 100644
--- a/esp32s3/src/interrupt_core1/rmt_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/rmt_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rmt interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_intr_map(&mut self) -> RMT_INTR_MAP_W<RMT_INTR_MAP_SPEC> {
         RMT_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rsa_int_map.rs b/esp32s3/src/interrupt_core1/rsa_int_map.rs
index a4417f9b89..5ce36e79a3 100644
--- a/esp32s3/src/interrupt_core1/rsa_int_map.rs
+++ b/esp32s3/src/interrupt_core1/rsa_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rsa interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_int_map(&mut self) -> RSA_INT_MAP_W<RSA_INT_MAP_SPEC> {
         RSA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs b/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
index 8fd306d08a..06858e49c5 100644
--- a/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rtc_core interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_core_intr_map(&mut self) -> RTC_CORE_INTR_MAP_W<RTC_CORE_INTR_MAP_SPEC> {
         RTC_CORE_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rwble_irq_map.rs b/esp32s3/src/interrupt_core1/rwble_irq_map.rs
index 32ac79262d..75ff4f6ce6 100644
--- a/esp32s3/src/interrupt_core1/rwble_irq_map.rs
+++ b/esp32s3/src/interrupt_core1/rwble_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_irq interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwble_irq_map(&mut self) -> RWBLE_IRQ_MAP_W<RWBLE_IRQ_MAP_SPEC> {
         RWBLE_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rwble_nmi_map.rs b/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
index 35c242faa9..68bc51f4b7 100644
--- a/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwble_nmi_map(&mut self) -> RWBLE_NMI_MAP_W<RWBLE_NMI_MAP_SPEC> {
         RWBLE_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rwbt_irq_map.rs b/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
index 582a133087..c2874bbfd5 100644
--- a/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
+++ b/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_irq interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwbt_irq_map(&mut self) -> RWBT_IRQ_MAP_W<RWBT_IRQ_MAP_SPEC> {
         RWBT_IRQ_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs b/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
index e817966156..3c5c9d21a7 100644
--- a/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_nmi interupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rwbt_nmi_map(&mut self) -> RWBT_NMI_MAP_W<RWBT_NMI_MAP_SPEC> {
         RWBT_NMI_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs b/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
index 14e3381e21..2f81e47c74 100644
--- a/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
+++ b/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map sdio_host interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_host_interrupt_map(
         &mut self,
     ) -> SDIO_HOST_INTERRUPT_MAP_W<SDIO_HOST_INTERRUPT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/sha_int_map.rs b/esp32s3/src/interrupt_core1/sha_int_map.rs
index 7a4e57f775..b3fcab4918 100644
--- a/esp32s3/src/interrupt_core1/sha_int_map.rs
+++ b/esp32s3/src/interrupt_core1/sha_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map sha interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sha_int_map(&mut self) -> SHA_INT_MAP_W<SHA_INT_MAP_SPEC> {
         SHA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/slc0_intr_map.rs b/esp32s3/src/interrupt_core1/slc0_intr_map.rs
index d727fb6be2..ae15206f97 100644
--- a/esp32s3/src/interrupt_core1/slc0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/slc0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slc0_intr_map(&mut self) -> SLC0_INTR_MAP_W<SLC0_INTR_MAP_SPEC> {
         SLC0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/slc1_intr_map.rs b/esp32s3/src/interrupt_core1/slc1_intr_map.rs
index fa12f870b1..35831e2e24 100644
--- a/esp32s3/src/interrupt_core1/slc1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/slc1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slc1_intr_map(&mut self) -> SLC1_INTR_MAP_W<SLC1_INTR_MAP_SPEC> {
         SLC1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
index 50926b1156..7f52b015c7 100644
--- a/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi2_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_int_map(&mut self) -> SPI2_DMA_INT_MAP_W<SPI2_DMA_INT_MAP_SPEC> {
         SPI2_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
index e0c7ba9291..daa3c4e77b 100644
--- a/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi3_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_int_map(&mut self) -> SPI3_DMA_INT_MAP_W<SPI3_DMA_INT_MAP_SPEC> {
         SPI3_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
index e98152c671..c93b212172 100644
--- a/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi4_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_dma_int_map(&mut self) -> SPI4_DMA_INT_MAP_W<SPI4_DMA_INT_MAP_SPEC> {
         SPI4_DMA_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi_intr_1_map.rs b/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
index 419dd3c67d..4904e4e31b 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_1_map(&mut self) -> SPI_INTR_1_MAP_W<SPI_INTR_1_MAP_SPEC> {
         SPI_INTR_1_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi_intr_2_map.rs b/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
index a494e9563f..1b8724a950 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_2_map(&mut self) -> SPI_INTR_2_MAP_W<SPI_INTR_2_MAP_SPEC> {
         SPI_INTR_2_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi_intr_3_map.rs b/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
index b04798cf47..2cef07ee98 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_3_map(&mut self) -> SPI_INTR_3_MAP_W<SPI_INTR_3_MAP_SPEC> {
         SPI_INTR_3_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi_intr_4_map.rs b/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
index adb09e781b..0dcb4fa76f 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_intr_4_map(&mut self) -> SPI_INTR_4_MAP_W<SPI_INTR_4_MAP_SPEC> {
         SPI_INTR_4_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs b/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
index a89a7cac3f..faf1a8e352 100644
--- a/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_mem_reject interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_mem_reject_intr_map(
         &mut self,
     ) -> SPI_MEM_REJECT_INTR_MAP_W<SPI_MEM_REJECT_INTR_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
index 84e7bc07bf..1e78697396 100644
--- a/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target0_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET0_INT_MAP_W<SYSTIMER_TARGET0_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
index e644f0e437..3af60633fb 100644
--- a/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target1_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET1_INT_MAP_W<SYSTIMER_TARGET1_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
index 66a16fe379..f2de743ba2 100644
--- a/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_target2_int_map(
         &mut self,
     ) -> SYSTIMER_TARGET2_INT_MAP_W<SYSTIMER_TARGET2_INT_MAP_SPEC> {
diff --git a/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs b/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
index d5794a0a87..4e353d1d8c 100644
--- a/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_t0_int_map(&mut self) -> TG1_T0_INT_MAP_W<TG1_T0_INT_MAP_SPEC> {
         TG1_T0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs b/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
index af238fcf80..9c28d5b231 100644
--- a/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_t1_int_map(&mut self) -> TG1_T1_INT_MAP_W<TG1_T1_INT_MAP_SPEC> {
         TG1_T1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs b/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
index bf8f5fb3cd..98b72ff223 100644
--- a/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_wdt interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg1_wdt_int_map(&mut self) -> TG1_WDT_INT_MAP_W<TG1_WDT_INT_MAP_SPEC> {
         TG1_WDT_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/tg_t0_int_map.rs b/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
index d2d33e6f1b..3906b99d6c 100644
--- a/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_t0_int_map(&mut self) -> TG_T0_INT_MAP_W<TG_T0_INT_MAP_SPEC> {
         TG_T0_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/tg_t1_int_map.rs b/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
index 4247537127..7c2502433b 100644
--- a/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_t1_int_map(&mut self) -> TG_T1_INT_MAP_W<TG_T1_INT_MAP_SPEC> {
         TG_T1_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs b/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
index 93f0adba31..76cbcd9cab 100644
--- a/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map rg_wdt interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tg_wdt_int_map(&mut self) -> TG_WDT_INT_MAP_W<TG_WDT_INT_MAP_SPEC> {
         TG_WDT_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/timer_int1_map.rs b/esp32s3/src/interrupt_core1/timer_int1_map.rs
index 03607d017e..371454e7fd 100644
--- a/esp32s3/src/interrupt_core1/timer_int1_map.rs
+++ b/esp32s3/src/interrupt_core1/timer_int1_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_int1_map(&mut self) -> TIMER_INT1_MAP_W<TIMER_INT1_MAP_SPEC> {
         TIMER_INT1_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/timer_int2_map.rs b/esp32s3/src/interrupt_core1/timer_int2_map.rs
index 692a86846f..0401ad86e2 100644
--- a/esp32s3/src/interrupt_core1/timer_int2_map.rs
+++ b/esp32s3/src/interrupt_core1/timer_int2_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_int2_map(&mut self) -> TIMER_INT2_MAP_W<TIMER_INT2_MAP_SPEC> {
         TIMER_INT2_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/uart1_intr_map.rs b/esp32s3/src/interrupt_core1/uart1_intr_map.rs
index e698af468c..aa47826c93 100644
--- a/esp32s3/src/interrupt_core1/uart1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_intr_map(&mut self) -> UART1_INTR_MAP_W<UART1_INTR_MAP_SPEC> {
         UART1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/uart2_intr_map.rs b/esp32s3/src/interrupt_core1/uart2_intr_map.rs
index 84a11330b6..f8a01a93cd 100644
--- a/esp32s3/src/interrupt_core1/uart2_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart2_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_intr_map(&mut self) -> UART2_INTR_MAP_W<UART2_INTR_MAP_SPEC> {
         UART2_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/uart_intr_map.rs b/esp32s3/src/interrupt_core1/uart_intr_map.rs
index 20bea25ac7..f5ceb08be4 100644
--- a/esp32s3/src/interrupt_core1/uart_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_intr_map(&mut self) -> UART_INTR_MAP_W<UART_INTR_MAP_SPEC> {
         UART_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/uhci0_intr_map.rs b/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
index 2a5fe7b34a..c520cbdd40 100644
--- a/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_intr_map(&mut self) -> UHCI0_INTR_MAP_W<UHCI0_INTR_MAP_SPEC> {
         UHCI0_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/uhci1_intr_map.rs b/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
index 468d32c306..7f61f7918b 100644
--- a/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_intr_map(&mut self) -> UHCI1_INTR_MAP_W<UHCI1_INTR_MAP_SPEC> {
         UHCI1_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/usb_device_int_map.rs b/esp32s3/src/interrupt_core1/usb_device_int_map.rs
index 5d912ea14a..3dd93cc2be 100644
--- a/esp32s3/src/interrupt_core1/usb_device_int_map.rs
+++ b/esp32s3/src/interrupt_core1/usb_device_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb_device interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_device_int_map(&mut self) -> USB_DEVICE_INT_MAP_W<USB_DEVICE_INT_MAP_SPEC> {
         USB_DEVICE_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/usb_intr_map.rs b/esp32s3/src/interrupt_core1/usb_intr_map.rs
index 6f34830e0d..81831dadae 100644
--- a/esp32s3/src/interrupt_core1/usb_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/usb_intr_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_intr_map(&mut self) -> USB_INTR_MAP_W<USB_INTR_MAP_SPEC> {
         USB_INTR_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/interrupt_core1/wdg_int_map.rs b/esp32s3/src/interrupt_core1/wdg_int_map.rs
index 6078a2bdb1..fd2333e4d3 100644
--- a/esp32s3/src/interrupt_core1/wdg_int_map.rs
+++ b/esp32s3/src/interrupt_core1/wdg_int_map.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - this register used to map wdg interrupt to one of core1's external interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_int_map(&mut self) -> WDG_INT_MAP_W<WDG_INT_MAP_SPEC> {
         WDG_INT_MAP_W::new(self, 0)
     }
diff --git a/esp32s3/src/io_mux/date.rs b/esp32s3/src/io_mux/date.rs
index 300b86f722..163ad3376a 100644
--- a/esp32s3/src/io_mux/date.rs
+++ b/esp32s3/src/io_mux/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn reg_date(&mut self) -> REG_DATE_W<DATE_SPEC> {
         REG_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/io_mux/gpio.rs b/esp32s3/src/io_mux/gpio.rs
index b1424f23f7..5da75dbe0d 100644
--- a/esp32s3/src/io_mux/gpio.rs
+++ b/esp32s3/src/io_mux/gpio.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_oe(&mut self) -> MCU_OE_W<GPIO_SPEC> {
         MCU_OE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sleep mode selection of this pad. Set to 1 to put the pad in pad mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<GPIO_SPEC> {
         SLP_SEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpd(&mut self) -> MCU_WPD_W<GPIO_SPEC> {
         MCU_WPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_wpu(&mut self) -> MCU_WPU_W<GPIO_SPEC> {
         MCU_WPU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_ie(&mut self) -> MCU_IE_W<GPIO_SPEC> {
         MCU_IE_W::new(self, 4)
     }
     #[doc = "Bit 7 - Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpd(&mut self) -> FUN_WPD_W<GPIO_SPEC> {
         FUN_WPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_wpu(&mut self) -> FUN_WPU_W<GPIO_SPEC> {
         FUN_WPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - Input enable of the pad. 1: input enabled; 0: input disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<GPIO_SPEC> {
         FUN_IE_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA."]
     #[inline(always)]
-    #[must_use]
     pub fn fun_drv(&mut self) -> FUN_DRV_W<GPIO_SPEC> {
         FUN_DRV_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc."]
     #[inline(always)]
-    #[must_use]
     pub fn mcu_sel(&mut self) -> MCU_SEL_W<GPIO_SPEC> {
         MCU_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<GPIO_SPEC> {
         FILTER_EN_W::new(self, 15)
     }
diff --git a/esp32s3/src/io_mux/pin_ctrl.rs b/esp32s3/src/io_mux/pin_ctrl.rs
index c42f8b637c..ff6d6809e9 100644
--- a/esp32s3/src/io_mux/pin_ctrl.rs
+++ b/esp32s3/src/io_mux/pin_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_out1(&mut self) -> CLK_OUT1_W<PIN_CTRL_SPEC> {
         CLK_OUT1_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_out2(&mut self) -> CLK_OUT2_W<PIN_CTRL_SPEC> {
         CLK_OUT2_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_out3(&mut self) -> CLK_OUT3_W<PIN_CTRL_SPEC> {
         CLK_OUT3_W::new(self, 8)
     }
diff --git a/esp32s3/src/lcd_cam/cam_ctrl.rs b/esp32s3/src/lcd_cam/cam_ctrl.rs
index 75655c39ac..7ac5912a20 100644
--- a/esp32s3/src/lcd_cam/cam_ctrl.rs
+++ b/esp32s3/src/lcd_cam/cam_ctrl.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_stop_en(&mut self) -> CAM_STOP_EN_W<CAM_CTRL_SPEC> {
         CAM_STOP_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:3 - Filter threshold value for CAM_VSYNC signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vsync_filter_thres(&mut self) -> CAM_VSYNC_FILTER_THRES_W<CAM_CTRL_SPEC> {
         CAM_VSYNC_FILTER_THRES_W::new(self, 1)
     }
     #[doc = "Bit 4 - 1: Update camera registers. This bit is cleared by hardware. 0: Do not care."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_update(&mut self) -> CAM_UPDATE_W<CAM_CTRL_SPEC> {
         CAM_UPDATE_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W<CAM_CTRL_SPEC> {
         CAM_BYTE_ORDER_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W<CAM_CTRL_SPEC> {
         CAM_BIT_ORDER_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_line_int_en(&mut self) -> CAM_LINE_INT_EN_W<CAM_CTRL_SPEC> {
         CAM_LINE_INT_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vs_eof_en(&mut self) -> CAM_VS_EOF_EN_W<CAM_CTRL_SPEC> {
         CAM_VS_EOF_EN_W::new(self, 8)
     }
     #[doc = "Bits 9:16 - Integral camera clock divider value."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clkm_div_num(&mut self) -> CAM_CLKM_DIV_NUM_W<CAM_CTRL_SPEC> {
         CAM_CLKM_DIV_NUM_W::new(self, 9)
     }
     #[doc = "Bits 17:22 - Fractional clock divider numerator value."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clkm_div_b(&mut self) -> CAM_CLKM_DIV_B_W<CAM_CTRL_SPEC> {
         CAM_CLKM_DIV_B_W::new(self, 17)
     }
     #[doc = "Bits 23:28 - Fractional clock divider denominator value."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clkm_div_a(&mut self) -> CAM_CLKM_DIV_A_W<CAM_CTRL_SPEC> {
         CAM_CLKM_DIV_A_W::new(self, 23)
     }
     #[doc = "Bits 29:30 - Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clk_sel(&mut self) -> CAM_CLK_SEL_W<CAM_CTRL_SPEC> {
         CAM_CLK_SEL_W::new(self, 29)
     }
diff --git a/esp32s3/src/lcd_cam/cam_ctrl1.rs b/esp32s3/src/lcd_cam/cam_ctrl1.rs
index 0ef6800ac6..ca9933496c 100644
--- a/esp32s3/src/lcd_cam/cam_ctrl1.rs
+++ b/esp32s3/src/lcd_cam/cam_ctrl1.rs
@@ -118,73 +118,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_rec_data_bytelen(&mut self) -> CAM_REC_DATA_BYTELEN_W<CAM_CTRL1_SPEC> {
         CAM_REC_DATA_BYTELEN_W::new(self, 0)
     }
     #[doc = "Bits 16:21 - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_line_int_num(&mut self) -> CAM_LINE_INT_NUM_W<CAM_CTRL1_SPEC> {
         CAM_LINE_INT_NUM_W::new(self, 16)
     }
     #[doc = "Bit 22 - 1: Invert the input signal CAM_PCLK. 0: Do not invert."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_clk_inv(&mut self) -> CAM_CLK_INV_W<CAM_CTRL1_SPEC> {
         CAM_CLK_INV_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: Enable CAM_VSYNC filter function. 0: Bypass."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vsync_filter_en(&mut self) -> CAM_VSYNC_FILTER_EN_W<CAM_CTRL1_SPEC> {
         CAM_VSYNC_FILTER_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_2byte_en(&mut self) -> CAM_2BYTE_EN_W<CAM_CTRL1_SPEC> {
         CAM_2BYTE_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - CAM_DE invert enable signal, valid in high level."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_de_inv(&mut self) -> CAM_DE_INV_W<CAM_CTRL1_SPEC> {
         CAM_DE_INV_W::new(self, 25)
     }
     #[doc = "Bit 26 - CAM_HSYNC invert enable signal, valid in high level."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_hsync_inv(&mut self) -> CAM_HSYNC_INV_W<CAM_CTRL1_SPEC> {
         CAM_HSYNC_INV_W::new(self, 26)
     }
     #[doc = "Bit 27 - CAM_VSYNC invert enable signal, valid in high level."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vsync_inv(&mut self) -> CAM_VSYNC_INV_W<CAM_CTRL1_SPEC> {
         CAM_VSYNC_INV_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same time."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vh_de_mode_en(&mut self) -> CAM_VH_DE_MODE_EN_W<CAM_CTRL1_SPEC> {
         CAM_VH_DE_MODE_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - Camera module start signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_start(&mut self) -> CAM_START_W<CAM_CTRL1_SPEC> {
         CAM_START_W::new(self, 29)
     }
     #[doc = "Bit 30 - Camera module reset signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_reset(&mut self) -> CAM_RESET_W<CAM_CTRL1_SPEC> {
         CAM_RESET_W::new(self, 30)
     }
     #[doc = "Bit 31 - Camera Async Rx FIFO reset signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_afifo_reset(&mut self) -> CAM_AFIFO_RESET_W<CAM_CTRL1_SPEC> {
         CAM_AFIFO_RESET_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/cam_rgb_yuv.rs b/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
index c2ca1152ae..78493eec59 100644
--- a/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
+++ b/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 21 - Swap every two 8-bit input data. 1: Enabled. 0: Disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_8bits_data_inv(&mut self) -> CAM_CONV_8BITS_DATA_INV_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_8BITS_DATA_INV_W::new(self, 21)
     }
     #[doc = "Bits 22:23 - In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_yuv2yuv_mode(&mut self) -> CAM_CONV_YUV2YUV_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_YUV2YUV_MODE_W::new(self, 22)
     }
     #[doc = "Bits 24:25 - In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_yuv_mode(&mut self) -> CAM_CONV_YUV_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_YUV_MODE_W::new(self, 24)
     }
     #[doc = "Bit 26 - 0: BT601. 1: BT709."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_protocol_mode(&mut self) -> CAM_CONV_PROTOCOL_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_PROTOCOL_MODE_W::new(self, 26)
     }
     #[doc = "Bit 27 - Configure color range for output data. 0: limited color range. 1: full color range."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_data_out_mode(&mut self) -> CAM_CONV_DATA_OUT_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_DATA_OUT_MODE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Configure color range for input data. 0: limited color range. 1: full color range."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_data_in_mode(&mut self) -> CAM_CONV_DATA_IN_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_DATA_IN_MODE_W::new(self, 28)
     }
     #[doc = "Bit 29 - 0: 16-bit mode. 1: 8-bit mode."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_mode_8bits_on(&mut self) -> CAM_CONV_MODE_8BITS_ON_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_MODE_8BITS_ON_W::new(self, 29)
     }
     #[doc = "Bit 30 - 0: converted to RGB format. 1: converted to YUV format."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_trans_mode(&mut self) -> CAM_CONV_TRANS_MODE_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_TRANS_MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_conv_bypass(&mut self) -> CAM_CONV_BYPASS_W<CAM_RGB_YUV_SPEC> {
         CAM_CONV_BYPASS_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/lc_dma_int_clr.rs b/esp32s3/src/lcd_cam/lc_dma_int_clr.rs
index 4f7e6241c7..409c4e5f03 100644
--- a/esp32s3/src/lcd_cam/lc_dma_int_clr.rs
+++ b/esp32s3/src/lcd_cam/lc_dma_int_clr.rs
@@ -17,25 +17,21 @@ impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_int_clr(&mut self) -> LCD_VSYNC_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
         LCD_VSYNC_INT_CLR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_trans_done_int_clr(&mut self) -> LCD_TRANS_DONE_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
         LCD_TRANS_DONE_INT_CLR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vsync_int_clr(&mut self) -> CAM_VSYNC_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
         CAM_VSYNC_INT_CLR_W::new(self, 2)
     }
     #[doc = "Bit 3 - The clear bit for LCD_CAM_CAM_HS_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_hs_int_clr(&mut self) -> CAM_HS_INT_CLR_W<LC_DMA_INT_CLR_SPEC> {
         CAM_HS_INT_CLR_W::new(self, 3)
     }
diff --git a/esp32s3/src/lcd_cam/lc_dma_int_ena.rs b/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
index 3a249404d6..5020357783 100644
--- a/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
+++ b/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_int_ena(&mut self) -> LCD_VSYNC_INT_ENA_W<LC_DMA_INT_ENA_SPEC> {
         LCD_VSYNC_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_trans_done_int_ena(&mut self) -> LCD_TRANS_DONE_INT_ENA_W<LC_DMA_INT_ENA_SPEC> {
         LCD_TRANS_DONE_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_vsync_int_ena(&mut self) -> CAM_VSYNC_INT_ENA_W<LC_DMA_INT_ENA_SPEC> {
         CAM_VSYNC_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for LCD_CAM_CAM_HS_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cam_hs_int_ena(&mut self) -> CAM_HS_INT_ENA_W<LC_DMA_INT_ENA_SPEC> {
         CAM_HS_INT_ENA_W::new(self, 3)
     }
diff --git a/esp32s3/src/lcd_cam/lc_reg_date.rs b/esp32s3/src/lcd_cam/lc_reg_date.rs
index 982c6cbd3e..cd1ab14b60 100644
--- a/esp32s3/src/lcd_cam/lc_reg_date.rs
+++ b/esp32s3/src/lcd_cam/lc_reg_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn lc_date(&mut self) -> LC_DATE_W<LC_REG_DATE_SPEC> {
         LC_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_clock.rs b/esp32s3/src/lcd_cam/lcd_clock.rs
index 9ae8fd4e09..252eb23698 100644
--- a/esp32s3/src/lcd_cam/lcd_clock.rs
+++ b/esp32s3/src/lcd_cam/lcd_clock.rs
@@ -2,13 +2,13 @@
 pub type R = crate::R<LCD_CLOCK_SPEC>;
 #[doc = "Register `LCD_CLOCK` writer"]
 pub type W = crate::W<LCD_CLOCK_SPEC>;
-#[doc = "Field `LCD_CLKCNT_N` reader - f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
+#[doc = "Field `LCD_CLKCNT_N` reader - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
 pub type LCD_CLKCNT_N_R = crate::FieldReader;
-#[doc = "Field `LCD_CLKCNT_N` writer - f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
+#[doc = "Field `LCD_CLKCNT_N` writer - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
 pub type LCD_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
-#[doc = "Field `LCD_CLK_EQU_SYSCLK` reader - 1: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>. 0: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
+#[doc = "Field `LCD_CLK_EQU_SYSCLK` reader - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
 pub type LCD_CLK_EQU_SYSCLK_R = crate::BitReader;
-#[doc = "Field `LCD_CLK_EQU_SYSCLK` writer - 1: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>. 0: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
+#[doc = "Field `LCD_CLK_EQU_SYSCLK` writer - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
 pub type LCD_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `LCD_CK_IDLE_EDGE` reader - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
 pub type LCD_CK_IDLE_EDGE_R = crate::BitReader;
@@ -39,12 +39,12 @@ pub type CLK_EN_R = crate::BitReader;
 #[doc = "Field `CLK_EN` writer - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
 pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:5 - f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
+    #[doc = "Bits 0:5 - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
     #[inline(always)]
     pub fn lcd_clkcnt_n(&self) -> LCD_CLKCNT_N_R {
         LCD_CLKCNT_N_R::new((self.bits & 0x3f) as u8)
     }
-    #[doc = "Bit 6 - 1: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>. 0: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
+    #[doc = "Bit 6 - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
     #[inline(always)]
     pub fn lcd_clk_equ_sysclk(&self) -> LCD_CLK_EQU_SYSCLK_R {
         LCD_CLK_EQU_SYSCLK_R::new(((self.bits >> 6) & 1) != 0)
@@ -102,57 +102,48 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {
-    #[doc = "Bits 0:5 - f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
+    #[doc = "Bits 0:5 - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clkcnt_n(&mut self) -> LCD_CLKCNT_N_W<LCD_CLOCK_SPEC> {
         LCD_CLKCNT_N_W::new(self, 0)
     }
-    #[doc = "Bit 6 - 1: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>. 0: f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
+    #[doc = "Bit 6 - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clk_equ_sysclk(&mut self) -> LCD_CLK_EQU_SYSCLK_W<LCD_CLOCK_SPEC> {
         LCD_CLK_EQU_SYSCLK_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ck_idle_edge(&mut self) -> LCD_CK_IDLE_EDGE_W<LCD_CLOCK_SPEC> {
         LCD_CK_IDLE_EDGE_W::new(self, 7)
     }
     #[doc = "Bit 8 - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ck_out_edge(&mut self) -> LCD_CK_OUT_EDGE_W<LCD_CLOCK_SPEC> {
         LCD_CK_OUT_EDGE_W::new(self, 8)
     }
     #[doc = "Bits 9:16 - Integral LCD clock divider value."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clkm_div_num(&mut self) -> LCD_CLKM_DIV_NUM_W<LCD_CLOCK_SPEC> {
         LCD_CLKM_DIV_NUM_W::new(self, 9)
     }
     #[doc = "Bits 17:22 - Fractional clock divider numerator value."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clkm_div_b(&mut self) -> LCD_CLKM_DIV_B_W<LCD_CLOCK_SPEC> {
         LCD_CLKM_DIV_B_W::new(self, 17)
     }
     #[doc = "Bits 23:28 - Fractional clock divider denominator value."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clkm_div_a(&mut self) -> LCD_CLKM_DIV_A_W<LCD_CLOCK_SPEC> {
         LCD_CLKM_DIV_A_W::new(self, 23)
     }
     #[doc = "Bits 29:30 - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W<LCD_CLOCK_SPEC> {
         LCD_CLK_SEL_W::new(self, 29)
     }
     #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<LCD_CLOCK_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_cmd_val.rs b/esp32s3/src/lcd_cam/lcd_cmd_val.rs
index e2923ffc09..7a4fcc72d6 100644
--- a/esp32s3/src/lcd_cam/lcd_cmd_val.rs
+++ b/esp32s3/src/lcd_cam/lcd_cmd_val.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The LCD write command value."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cmd_value(&mut self) -> LCD_CMD_VALUE_W<LCD_CMD_VAL_SPEC> {
         LCD_CMD_VALUE_W::new(self, 0)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl.rs b/esp32s3/src/lcd_cam/lcd_ctrl.rs
index 374901b9ba..8bb912ed45 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hb_front(&mut self) -> LCD_HB_FRONT_W<LCD_CTRL_SPEC> {
         LCD_HB_FRONT_W::new(self, 0)
     }
     #[doc = "Bits 11:20 - It is the vertical active height of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_va_height(&mut self) -> LCD_VA_HEIGHT_W<LCD_CTRL_SPEC> {
         LCD_VA_HEIGHT_W::new(self, 11)
     }
     #[doc = "Bits 21:30 - It is the vertical total height of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vt_height(&mut self) -> LCD_VT_HEIGHT_W<LCD_CTRL_SPEC> {
         LCD_VT_HEIGHT_W::new(self, 21)
     }
     #[doc = "Bit 31 - 1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_rgb_mode_en(&mut self) -> LCD_RGB_MODE_EN_W<LCD_CTRL_SPEC> {
         LCD_RGB_MODE_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl1.rs b/esp32s3/src/lcd_cam/lcd_ctrl1.rs
index f3e9048ec1..be8980abb9 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl1.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vb_front(&mut self) -> LCD_VB_FRONT_W<LCD_CTRL1_SPEC> {
         LCD_VB_FRONT_W::new(self, 0)
     }
     #[doc = "Bits 8:19 - It is the horizontal active width of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ha_width(&mut self) -> LCD_HA_WIDTH_W<LCD_CTRL1_SPEC> {
         LCD_HA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bits 20:31 - It is the horizontal total width of a frame."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_ht_width(&mut self) -> LCD_HT_WIDTH_W<LCD_CTRL1_SPEC> {
         LCD_HT_WIDTH_W::new(self, 20)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl2.rs b/esp32s3/src/lcd_cam/lcd_ctrl2.rs
index 918db38b56..2c0b09b928 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl2.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl2.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - It is the width of LCD_VSYNC active pulse in a line."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_width(&mut self) -> LCD_VSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
         LCD_VSYNC_WIDTH_W::new(self, 0)
     }
     #[doc = "Bit 7 - It is the idle value of LCD_VSYNC."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_idle_pol(&mut self) -> LCD_VSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
         LCD_VSYNC_IDLE_POL_W::new(self, 7)
     }
     #[doc = "Bit 8 - It is the idle value of LCD_DE."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_de_idle_pol(&mut self) -> LCD_DE_IDLE_POL_W<LCD_CTRL2_SPEC> {
         LCD_DE_IDLE_POL_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hs_blank_en(&mut self) -> LCD_HS_BLANK_EN_W<LCD_CTRL2_SPEC> {
         LCD_HS_BLANK_EN_W::new(self, 9)
     }
     #[doc = "Bits 16:22 - It is the width of LCD_HSYNC active pulse in a line."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_width(&mut self) -> LCD_HSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
         LCD_HSYNC_WIDTH_W::new(self, 16)
     }
     #[doc = "Bit 23 - It is the idle value of LCD_HSYNC."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_idle_pol(&mut self) -> LCD_HSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
         LCD_HSYNC_IDLE_POL_W::new(self, 23)
     }
     #[doc = "Bits 24:31 - It is the position of LCD_HSYNC active pulse in a line."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_position(&mut self) -> LCD_HSYNC_POSITION_W<LCD_CTRL2_SPEC> {
         LCD_HSYNC_POSITION_W::new(self, 24)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs b/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
index 055fc2f4b1..89725d6dc9 100644
--- a/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
+++ b/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
@@ -201,7 +201,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DOUT0_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn dout_mode(&mut self, n: u8) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 16][n as usize];
@@ -209,97 +208,81 @@ impl W {
     }
     #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout0_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout1_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout2_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout3_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout4_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout5_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout6_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout7_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout8_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout9_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 18)
     }
     #[doc = "Bits 20:21 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout10_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout11_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 22)
     }
     #[doc = "Bits 24:25 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout12_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 24)
     }
     #[doc = "Bits 26:27 - The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout13_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 26)
     }
     #[doc = "Bits 28:29 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout14_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn dout15_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
         DOUT_MODE_W::new(self, 30)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_dly_mode.rs b/esp32s3/src/lcd_cam/lcd_dly_mode.rs
index 9c3c570044..057a87aac3 100644
--- a/esp32s3/src/lcd_cam/lcd_dly_mode.rs
+++ b/esp32s3/src/lcd_cam/lcd_dly_mode.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cd_mode(&mut self) -> LCD_CD_MODE_W<LCD_DLY_MODE_SPEC> {
         LCD_CD_MODE_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_de_mode(&mut self) -> LCD_DE_MODE_W<LCD_DLY_MODE_SPEC> {
         LCD_DE_MODE_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_hsync_mode(&mut self) -> LCD_HSYNC_MODE_W<LCD_DLY_MODE_SPEC> {
         LCD_HSYNC_MODE_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vsync_mode(&mut self) -> LCD_VSYNC_MODE_W<LCD_DLY_MODE_SPEC> {
         LCD_VSYNC_MODE_W::new(self, 6)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_misc.rs b/esp32s3/src/lcd_cam/lcd_misc.rs
index a9dfc8d452..7259e34a2c 100644
--- a/esp32s3/src/lcd_cam/lcd_misc.rs
+++ b/esp32s3/src/lcd_cam/lcd_misc.rs
@@ -106,61 +106,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:5 - Set the threshold for Async Tx FIFO full event."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_afifo_threshold_num(&mut self) -> LCD_AFIFO_THRESHOLD_NUM_W<LCD_MISC_SPEC> {
         LCD_AFIFO_THRESHOLD_NUM_W::new(self, 1)
     }
     #[doc = "Bits 6:11 - Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vfk_cyclelen(&mut self) -> LCD_VFK_CYCLELEN_W<LCD_MISC_SPEC> {
         LCD_VFK_CYCLELEN_W::new(self, 6)
     }
     #[doc = "Bits 12:24 - Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_vbk_cyclelen(&mut self) -> LCD_VBK_CYCLELEN_W<LCD_MISC_SPEC> {
         LCD_VBK_CYCLELEN_W::new(self, 12)
     }
     #[doc = "Bit 25 - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_next_frame_en(&mut self) -> LCD_NEXT_FRAME_EN_W<LCD_MISC_SPEC> {
         LCD_NEXT_FRAME_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: Enable blank region when LCD sends data out. 0: No blank region."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_bk_en(&mut self) -> LCD_BK_EN_W<LCD_MISC_SPEC> {
         LCD_BK_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Async Tx FIFO reset signal."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_afifo_reset(&mut self) -> LCD_AFIFO_RESET_W<LCD_MISC_SPEC> {
         LCD_AFIFO_RESET_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cd_data_set(&mut self) -> LCD_CD_DATA_SET_W<LCD_MISC_SPEC> {
         LCD_CD_DATA_SET_W::new(self, 28)
     }
     #[doc = "Bit 29 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cd_dummy_set(&mut self) -> LCD_CD_DUMMY_SET_W<LCD_MISC_SPEC> {
         LCD_CD_DUMMY_SET_W::new(self, 29)
     }
     #[doc = "Bit 30 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cd_cmd_set(&mut self) -> LCD_CD_CMD_SET_W<LCD_MISC_SPEC> {
         LCD_CD_CMD_SET_W::new(self, 30)
     }
     #[doc = "Bit 31 - The default value of LCD_CD."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cd_idle_edge(&mut self) -> LCD_CD_IDLE_EDGE_W<LCD_MISC_SPEC> {
         LCD_CD_IDLE_EDGE_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs b/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
index 3c83d5cafb..6b3e6e38d2 100644
--- a/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
+++ b/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20 - Swap every two 8-bit input data. 1: Enabled. 0: Disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_8bits_data_inv(&mut self) -> LCD_CONV_8BITS_DATA_INV_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_8BITS_DATA_INV_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_yuv2yuv_mode(&mut self) -> LCD_CONV_YUV2YUV_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_YUV2YUV_MODE_W::new(self, 22)
     }
     #[doc = "Bits 24:25 - In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_yuv_mode(&mut self) -> LCD_CONV_YUV_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_YUV_MODE_W::new(self, 24)
     }
     #[doc = "Bit 26 - 0: BT601. 1: BT709."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_protocol_mode(&mut self) -> LCD_CONV_PROTOCOL_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_PROTOCOL_MODE_W::new(self, 26)
     }
     #[doc = "Bit 27 - Configure color range for output data. 0: limited color range. 1: full color range."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_data_out_mode(&mut self) -> LCD_CONV_DATA_OUT_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_DATA_OUT_MODE_W::new(self, 27)
     }
     #[doc = "Bit 28 - Configure color range for input data. 0: limited color range. 1: full color range."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_data_in_mode(&mut self) -> LCD_CONV_DATA_IN_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_DATA_IN_MODE_W::new(self, 28)
     }
     #[doc = "Bit 29 - 0: 16-bit mode. 1: 8-bit mode."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_mode_8bits_on(&mut self) -> LCD_CONV_MODE_8BITS_ON_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_MODE_8BITS_ON_W::new(self, 29)
     }
     #[doc = "Bit 30 - 0: converted to RGB format. 1: converted to YUV format."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_trans_mode(&mut self) -> LCD_CONV_TRANS_MODE_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_TRANS_MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_conv_bypass(&mut self) -> LCD_CONV_BYPASS_W<LCD_RGB_YUV_SPEC> {
         LCD_CONV_BYPASS_W::new(self, 31)
     }
diff --git a/esp32s3/src/lcd_cam/lcd_user.rs b/esp32s3/src/lcd_cam/lcd_user.rs
index 31099270ac..8a0ef1b0f5 100644
--- a/esp32s3/src/lcd_cam/lcd_user.rs
+++ b/esp32s3/src/lcd_cam/lcd_user.rs
@@ -146,85 +146,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:12 - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_dout_cyclelen(&mut self) -> LCD_DOUT_CYCLELEN_W<LCD_USER_SPEC> {
         LCD_DOUT_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bit 13 - LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_always_out_en(&mut self) -> LCD_ALWAYS_OUT_EN_W<LCD_USER_SPEC> {
         LCD_ALWAYS_OUT_EN_W::new(self, 13)
     }
     #[doc = "Bit 19 - 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_8bits_order(&mut self) -> LCD_8BITS_ORDER_W<LCD_USER_SPEC> {
         LCD_8BITS_ORDER_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: Update LCD registers. This bit is cleared by hardware. 0: Do not care."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_update(&mut self) -> LCD_UPDATE_W<LCD_USER_SPEC> {
         LCD_UPDATE_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: Change data bit order. Change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_bit_order(&mut self) -> LCD_BIT_ORDER_W<LCD_USER_SPEC> {
         LCD_BIT_ORDER_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_byte_order(&mut self) -> LCD_BYTE_ORDER_W<LCD_USER_SPEC> {
         LCD_BYTE_ORDER_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_2byte_en(&mut self) -> LCD_2BYTE_EN_W<LCD_USER_SPEC> {
         LCD_2BYTE_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_dout(&mut self) -> LCD_DOUT_W<LCD_USER_SPEC> {
         LCD_DOUT_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_dummy(&mut self) -> LCD_DUMMY_W<LCD_USER_SPEC> {
         LCD_DUMMY_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cmd(&mut self) -> LCD_CMD_W<LCD_USER_SPEC> {
         LCD_CMD_W::new(self, 26)
     }
     #[doc = "Bit 27 - LCD starts sending data enable signal, valid in high level."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_start(&mut self) -> LCD_START_W<LCD_USER_SPEC> {
         LCD_START_W::new(self, 27)
     }
     #[doc = "Bit 28 - Reset LCD module."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_reset(&mut self) -> LCD_RESET_W<LCD_USER_SPEC> {
         LCD_RESET_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - Configure DUMMY cycles. DUMMY cycles = this value + 1."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_dummy_cyclelen(&mut self) -> LCD_DUMMY_CYCLELEN_W<LCD_USER_SPEC> {
         LCD_DUMMY_CYCLELEN_W::new(self, 29)
     }
     #[doc = "Bit 31 - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cmd_2_cycle_en(&mut self) -> LCD_CMD_2_CYCLE_EN_W<LCD_USER_SPEC> {
         LCD_CMD_2_CYCLE_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/ledc/ch/conf0.rs b/esp32s3/src/ledc/ch/conf0.rs
index fd6c77666a..02b98b686f 100644
--- a/esp32s3/src/ledc/ch/conf0.rs
+++ b/esp32s3/src/ledc/ch/conf0.rs
@@ -78,49 +78,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sel(&mut self) -> TIMER_SEL_W<CONF0_SPEC> {
         TIMER_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - Set this bit to enable signal output on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<CONF0_SPEC> {
         SIG_OUT_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_lv(&mut self) -> IDLE_LV_W<CONF0_SPEC> {
         IDLE_LV_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF0_SPEC> {
         PARA_UP_W::new(self, 4)
     }
     #[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_num(&mut self) -> OVF_NUM_W<CONF0_SPEC> {
         OVF_NUM_W::new(self, 5)
     }
     #[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_en(&mut self) -> OVF_CNT_EN_W<CONF0_SPEC> {
         OVF_CNT_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to reset the ovf_cnt of channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_reset(&mut self) -> OVF_CNT_RESET_W<CONF0_SPEC> {
         OVF_CNT_RESET_W::new(self, 16)
     }
     #[doc = "Bit 17 - This is the status bit of LEDC_OVF_CNT_RESET_CH%s."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_reset_st(&mut self) -> OVF_CNT_RESET_ST_W<CONF0_SPEC> {
         OVF_CNT_RESET_ST_W::new(self, 17)
     }
diff --git a/esp32s3/src/ledc/ch/conf1.rs b/esp32s3/src/ledc/ch/conf1.rs
index 6e9b61ddc4..e4c99f9987 100644
--- a/esp32s3/src/ledc/ch/conf1.rs
+++ b/esp32s3/src/ledc/ch/conf1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_scale(&mut self) -> DUTY_SCALE_W<CONF1_SPEC> {
         DUTY_SCALE_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_cycle(&mut self) -> DUTY_CYCLE_W<CONF1_SPEC> {
         DUTY_CYCLE_W::new(self, 10)
     }
     #[doc = "Bits 20:29 - This register is used to control the number of times the duty cycle will be changed."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_num(&mut self) -> DUTY_NUM_W<CONF1_SPEC> {
         DUTY_NUM_W::new(self, 20)
     }
     #[doc = "Bit 30 - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_inc(&mut self) -> DUTY_INC_W<CONF1_SPEC> {
         DUTY_INC_W::new(self, 30)
     }
     #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_start(&mut self) -> DUTY_START_W<CONF1_SPEC> {
         DUTY_START_W::new(self, 31)
     }
diff --git a/esp32s3/src/ledc/ch/duty.rs b/esp32s3/src/ledc/ch/duty.rs
index 37070b8030..5f06a74543 100644
--- a/esp32s3/src/ledc/ch/duty.rs
+++ b/esp32s3/src/ledc/ch/duty.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<DUTY_SPEC> {
         DUTY_W::new(self, 0)
     }
diff --git a/esp32s3/src/ledc/ch/hpoint.rs b/esp32s3/src/ledc/ch/hpoint.rs
index 6e7c457c81..e5ae51d75e 100644
--- a/esp32s3/src/ledc/ch/hpoint.rs
+++ b/esp32s3/src/ledc/ch/hpoint.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
-    #[must_use]
     pub fn hpoint(&mut self) -> HPOINT_W<HPOINT_SPEC> {
         HPOINT_W::new(self, 0)
     }
diff --git a/esp32s3/src/ledc/conf.rs b/esp32s3/src/ledc/conf.rs
index eca3d54c26..4210ff9bdc 100644
--- a/esp32s3/src/ledc/conf.rs
+++ b/esp32s3/src/ledc/conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<CONF_SPEC> {
         APB_CLK_SEL_W::new(self, 0)
     }
     #[doc = "Bit 31 - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/ledc/date.rs b/esp32s3/src/ledc/date.rs
index 4b02f1b38e..7b6676a006 100644
--- a/esp32s3/src/ledc/date.rs
+++ b/esp32s3/src/ledc/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/ledc/int_clr.rs b/esp32s3/src/ledc/int_clr.rs
index 12605167b4..4f57e66a51 100644
--- a/esp32s3/src/ledc/int_clr.rs
+++ b/esp32s3/src/ledc/int_clr.rs
@@ -17,7 +17,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -25,25 +24,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the TIMER0_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the TIMER1_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the TIMER2_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the TIMER3_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -51,7 +46,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -59,49 +53,41 @@ impl W {
     }
     #[doc = "Bit 4 - Set this bit to clear the DUTY_CHNG_END_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the DUTY_CHNG_END_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the DUTY_CHNG_END_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the DUTY_CHNG_END_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the DUTY_CHNG_END_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the DUTY_CHNG_END_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the DUTY_CHNG_END_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the DUTY_CHNG_END_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -109,7 +95,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -117,49 +102,41 @@ impl W {
     }
     #[doc = "Bit 12 - Set this bit to clear the OVF_CNT_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the OVF_CNT_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the OVF_CNT_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the OVF_CNT_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear the OVF_CNT_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the OVF_CNT_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the OVF_CNT_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear the OVF_CNT_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
@@ -173,7 +150,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1011;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s3/src/ledc/int_ena.rs b/esp32s3/src/ledc/int_ena.rs
index bf0c9a05b1..660ac7dc23 100644
--- a/esp32s3/src/ledc/int_ena.rs
+++ b/esp32s3/src/ledc/int_ena.rs
@@ -193,7 +193,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -201,25 +200,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -227,7 +222,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -235,49 +229,41 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for the DUTY_CHNG_END_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for the DUTY_CHNG_END_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -285,7 +271,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -293,49 +278,41 @@ impl W {
     }
     #[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt enable bit for the OVF_CNT_CH6 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt enable bit for the OVF_CNT_CH7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
diff --git a/esp32s3/src/ledc/int_raw.rs b/esp32s3/src/ledc/int_raw.rs
index 265bd1febb..da91e6e8eb 100644
--- a/esp32s3/src/ledc/int_raw.rs
+++ b/esp32s3/src/ledc/int_raw.rs
@@ -193,7 +193,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -201,25 +200,21 @@ impl W {
     }
     #[doc = "Bit 0 - Triggered when the timer0 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 0)
     }
     #[doc = "Bit 1 - Triggered when the timer1 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Triggered when the timer2 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Triggered when the timer3 has reached its maximum counter value."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
         TIMER_OVF_W::new(self, 3)
     }
@@ -227,7 +222,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -235,49 +229,41 @@ impl W {
     }
     #[doc = "Bit 4 - Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 7)
     }
     #[doc = "Bit 8 - Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 8)
     }
     #[doc = "Bit 9 - Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 9)
     }
     #[doc = "Bit 10 - Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 10)
     }
     #[doc = "Bit 11 - Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
         DUTY_CHNG_END_CH_W::new(self, 11)
     }
@@ -285,7 +271,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -293,49 +278,41 @@ impl W {
     }
     #[doc = "Bit 12 - Interrupt raw bit for channel 0. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 12)
     }
     #[doc = "Bit 13 - Interrupt raw bit for channel 1. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 13)
     }
     #[doc = "Bit 14 - Interrupt raw bit for channel 2. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 14)
     }
     #[doc = "Bit 15 - Interrupt raw bit for channel 3. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 15)
     }
     #[doc = "Bit 16 - Interrupt raw bit for channel 4. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Interrupt raw bit for channel 5. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Interrupt raw bit for channel 6. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Interrupt raw bit for channel 7. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
         OVF_CNT_CH_W::new(self, 19)
     }
diff --git a/esp32s3/src/ledc/timer/conf.rs b/esp32s3/src/ledc/timer/conf.rs
index 0932ec402d..9812cbaabe 100644
--- a/esp32s3/src/ledc/timer/conf.rs
+++ b/esp32s3/src/ledc/timer/conf.rs
@@ -66,37 +66,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
-    #[must_use]
     pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
         DUTY_RES_W::new(self, 0)
     }
     #[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_div(&mut self) -> CLK_DIV_W<CONF_SPEC> {
         CLK_DIV_W::new(self, 4)
     }
     #[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
     #[inline(always)]
-    #[must_use]
     pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
         PAUSE_W::new(self, 22)
     }
     #[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
     #[inline(always)]
-    #[must_use]
     pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
         RST_W::new(self, 23)
     }
     #[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
     #[inline(always)]
-    #[must_use]
     pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
         TICK_SEL_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
     #[inline(always)]
-    #[must_use]
     pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
         PARA_UP_W::new(self, 25)
     }
diff --git a/esp32s3/src/lib.rs b/esp32s3/src/lib.rs
index ef50fa3b38..7751ffb2c9 100644
--- a/esp32s3/src/lib.rs
+++ b/esp32s3/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S3 microcontrollers (generated using svd2rust v0.33.4 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S3 microcontrollers (generated using svd2rust v0.33.5 (bfe48e2 2024-11-05))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.5/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
@@ -512,13 +512,8 @@ pub enum Interrupt {
     #[doc = "98 - DMA_EXTMEM_REJECT"]
     DMA_EXTMEM_REJECT = 98,
 }
-unsafe impl xtensa_lx::interrupt::InterruptNumber for Interrupt {
-    #[inline(always)]
-    fn number(self) -> u16 {
-        self as u16
-    }
-}
 #[doc = r" TryFromInterruptError"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[derive(Debug, Copy, Clone)]
 pub struct TryFromInterruptError(());
 impl Interrupt {
diff --git a/esp32s3/src/mcpwm0/cap_ch_cfg.rs b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
index 2eed80ddd9..2d665ef82f 100644
--- a/esp32s3/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
@@ -56,31 +56,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CAP_CH_CFG_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<CAP_CH_CFG_SPEC> {
         MODE_W::new(self, 1)
     }
     #[doc = "Bits 3:10 - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CAP_CH_CFG_SPEC> {
         PRESCALE_W::new(self, 3)
     }
     #[doc = "Bit 11 - when set, CAP0 form GPIO matrix is inverted before prescale"]
     #[inline(always)]
-    #[must_use]
     pub fn in_invert(&mut self) -> IN_INVERT_W<CAP_CH_CFG_SPEC> {
         IN_INVERT_W::new(self, 11)
     }
     #[doc = "Bit 12 - Write 1 will trigger a software forced capture on channel 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sw(&mut self) -> SW_W<CAP_CH_CFG_SPEC> {
         SW_W::new(self, 12)
     }
diff --git a/esp32s3/src/mcpwm0/cap_timer_cfg.rs b/esp32s3/src/mcpwm0/cap_timer_cfg.rs
index c8616618ca..2528a984d1 100644
--- a/esp32s3/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32s3/src/mcpwm0/cap_timer_cfg.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<CAP_TIMER_CFG_SPEC> {
         CAP_TIMER_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - When set, capture timer sync is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNCI_EN_W::new(self, 1)
     }
     #[doc = "Bits 2:4 - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNCI_SEL_W::new(self, 2)
     }
     #[doc = "Bit 5 - Write 1 will force a capture timer sync, capture timer is loaded with value in phase register."]
     #[inline(always)]
-    #[must_use]
     pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<CAP_TIMER_CFG_SPEC> {
         CAP_SYNC_SW_W::new(self, 5)
     }
diff --git a/esp32s3/src/mcpwm0/cap_timer_phase.rs b/esp32s3/src/mcpwm0/cap_timer_phase.rs
index bfe38b6fbd..128ee1214f 100644
--- a/esp32s3/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32s3/src/mcpwm0/cap_timer_phase.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
     #[inline(always)]
-    #[must_use]
     pub fn cap_phase(&mut self) -> CAP_PHASE_W<CAP_TIMER_PHASE_SPEC> {
         CAP_PHASE_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/ch.rs b/esp32s3/src/mcpwm0/ch.rs
index 944dd8936e..65b564c7e8 100644
--- a/esp32s3/src/mcpwm0/ch.rs
+++ b/esp32s3/src/mcpwm0/ch.rs
@@ -43,6 +43,8 @@ impl CH {
         &self.gen_force
     }
     #[doc = "0x14..0x1c - Actions triggered by events on PWMx%s"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `GENA` register.</div>"]
     #[inline(always)]
     pub const fn gen(&self, n: usize) -> &GEN {
         &self.gen[n]
diff --git a/esp32s3/src/mcpwm0/ch/chopper_cfg.rs b/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
index a1be70f8a1..3b25a07d88 100644
--- a/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CHOPPER_CFG_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CHOPPER_CFG_SPEC> {
         PRESCALE_W::new(self, 1)
     }
     #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"]
     #[inline(always)]
-    #[must_use]
     pub fn duty(&mut self) -> DUTY_W<CHOPPER_CFG_SPEC> {
         DUTY_W::new(self, 5)
     }
     #[doc = "Bits 8:11 - width of the fist pulse in number of periods of the carrier"]
     #[inline(always)]
-    #[must_use]
     pub fn oshtwth(&mut self) -> OSHTWTH_W<CHOPPER_CFG_SPEC> {
         OSHTWTH_W::new(self, 8)
     }
     #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"]
     #[inline(always)]
-    #[must_use]
     pub fn out_invert(&mut self) -> OUT_INVERT_W<CHOPPER_CFG_SPEC> {
         OUT_INVERT_W::new(self, 12)
     }
     #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"]
     #[inline(always)]
-    #[must_use]
     pub fn in_invert(&mut self) -> IN_INVERT_W<CHOPPER_CFG_SPEC> {
         IN_INVERT_W::new(self, 13)
     }
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs b/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
index aa9d3a1eae..505da8f2a0 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
     #[inline(always)]
-    #[must_use]
     pub fn a_upmethod(&mut self) -> A_UPMETHOD_W<CMPR_CFG_SPEC> {
         A_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
     #[inline(always)]
-    #[must_use]
     pub fn b_upmethod(&mut self) -> B_UPMETHOD_W<CMPR_CFG_SPEC> {
         B_UPMETHOD_W::new(self, 4)
     }
     #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"]
     #[inline(always)]
-    #[must_use]
     pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W<CMPR_CFG_SPEC> {
         A_SHDW_FULL_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"]
     #[inline(always)]
-    #[must_use]
     pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W<CMPR_CFG_SPEC> {
         B_SHDW_FULL_W::new(self, 9)
     }
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_value0.rs b/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
index d23e3a8b4c..d7b071ec99 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"]
     #[inline(always)]
-    #[must_use]
     pub fn a(&mut self) -> A_W<CMPR_VALUE0_SPEC> {
         A_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_value1.rs b/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
index 48250eabe7..61d07cc76f 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"]
     #[inline(always)]
-    #[must_use]
     pub fn b(&mut self) -> B_W<CMPR_VALUE1_SPEC> {
         B_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/ch/db_cfg.rs b/esp32s3/src/mcpwm0/ch/db_cfg.rs
index c411e46d65..32f7e8f0ef 100644
--- a/esp32s3/src/mcpwm0/ch/db_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_cfg.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W<DB_CFG_SPEC> {
         FED_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
     #[inline(always)]
-    #[must_use]
     pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W<DB_CFG_SPEC> {
         RED_UPMETHOD_W::new(self, 4)
     }
     #[doc = "Bit 8 - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
     #[inline(always)]
-    #[must_use]
     pub fn deb_mode(&mut self) -> DEB_MODE_W<DB_CFG_SPEC> {
         DEB_MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - S6 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn a_outswap(&mut self) -> A_OUTSWAP_W<DB_CFG_SPEC> {
         A_OUTSWAP_W::new(self, 9)
     }
     #[doc = "Bit 10 - S7 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn b_outswap(&mut self) -> B_OUTSWAP_W<DB_CFG_SPEC> {
         B_OUTSWAP_W::new(self, 10)
     }
     #[doc = "Bit 11 - S4 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn red_insel(&mut self) -> RED_INSEL_W<DB_CFG_SPEC> {
         RED_INSEL_W::new(self, 11)
     }
     #[doc = "Bit 12 - S5 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_insel(&mut self) -> FED_INSEL_W<DB_CFG_SPEC> {
         FED_INSEL_W::new(self, 12)
     }
     #[doc = "Bit 13 - S2 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W<DB_CFG_SPEC> {
         RED_OUTINVERT_W::new(self, 13)
     }
     #[doc = "Bit 14 - S3 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W<DB_CFG_SPEC> {
         FED_OUTINVERT_W::new(self, 14)
     }
     #[doc = "Bit 15 - S1 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W<DB_CFG_SPEC> {
         A_OUTBYPASS_W::new(self, 15)
     }
     #[doc = "Bit 16 - S0 in documentation"]
     #[inline(always)]
-    #[must_use]
     pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W<DB_CFG_SPEC> {
         B_OUTBYPASS_W::new(self, 16)
     }
     #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sel(&mut self) -> CLK_SEL_W<DB_CFG_SPEC> {
         CLK_SEL_W::new(self, 17)
     }
diff --git a/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs b/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
index 4cddd5e449..c323d02b90 100644
--- a/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Shadow register for FED"]
     #[inline(always)]
-    #[must_use]
     pub fn fed(&mut self) -> FED_W<DB_FED_CFG_SPEC> {
         FED_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/ch/db_red_cfg.rs b/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
index 95b9183a57..138023daa7 100644
--- a/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Shadow register for RED"]
     #[inline(always)]
-    #[must_use]
     pub fn red(&mut self) -> RED_W<DB_RED_CFG_SPEC> {
         RED_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/ch/gen.rs b/esp32s3/src/mcpwm0/ch/gen.rs
index 14cc231d33..86886c7611 100644
--- a/esp32s3/src/mcpwm0/ch/gen.rs
+++ b/esp32s3/src/mcpwm0/ch/gen.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn utez(&mut self) -> UTEZ_W<GEN_SPEC> {
         UTEZ_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Action on PWM0A triggered by event TEP when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn utep(&mut self) -> UTEP_W<GEN_SPEC> {
         UTEP_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Action on PWM0A triggered by event TEA when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn utea(&mut self) -> UTEA_W<GEN_SPEC> {
         UTEA_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Action on PWM0A triggered by event TEB when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn uteb(&mut self) -> UTEB_W<GEN_SPEC> {
         UTEB_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Action on PWM0A triggered by event_t0 when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn ut0(&mut self) -> UT0_W<GEN_SPEC> {
         UT0_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Action on PWM0A triggered by event_t1 when timer increasing"]
     #[inline(always)]
-    #[must_use]
     pub fn ut1(&mut self) -> UT1_W<GEN_SPEC> {
         UT1_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Action on PWM0A triggered by event TEZ when timer decreasing"]
     #[inline(always)]
-    #[must_use]
     pub fn dtez(&mut self) -> DTEZ_W<GEN_SPEC> {
         DTEZ_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Action on PWM0A triggered by event TEP when timer decreasing"]
     #[inline(always)]
-    #[must_use]
     pub fn dtep(&mut self) -> DTEP_W<GEN_SPEC> {
         DTEP_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - Action on PWM0A triggered by event TEA when timer decreasing"]
     #[inline(always)]
-    #[must_use]
     pub fn dtea(&mut self) -> DTEA_W<GEN_SPEC> {
         DTEA_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - Action on PWM0A triggered by event TEB when timer decreasing"]
     #[inline(always)]
-    #[must_use]
     pub fn dteb(&mut self) -> DTEB_W<GEN_SPEC> {
         DTEB_W::new(self, 18)
     }
     #[doc = "Bits 20:21 - Action on PWM0A triggered by event_t0 when timer decreasing"]
     #[inline(always)]
-    #[must_use]
     pub fn dt0(&mut self) -> DT0_W<GEN_SPEC> {
         DT0_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn dt1(&mut self) -> DT1_W<GEN_SPEC> {
         DT1_W::new(self, 22)
     }
diff --git a/esp32s3/src/mcpwm0/ch/gen_cfg0.rs b/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
index e376f56c5c..e1efa75fde 100644
--- a/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
     #[inline(always)]
-    #[must_use]
     pub fn cfg_upmethod(&mut self) -> CFG_UPMETHOD_W<GEN_CFG0_SPEC> {
         CFG_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 4:6 - Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
     #[inline(always)]
-    #[must_use]
     pub fn t0_sel(&mut self) -> T0_SEL_W<GEN_CFG0_SPEC> {
         T0_SEL_W::new(self, 4)
     }
     #[doc = "Bits 7:9 - Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
     #[inline(always)]
-    #[must_use]
     pub fn t1_sel(&mut self) -> T1_SEL_W<GEN_CFG0_SPEC> {
         T1_SEL_W::new(self, 7)
     }
diff --git a/esp32s3/src/mcpwm0/ch/gen_force.rs b/esp32s3/src/mcpwm0/ch/gen_force.rs
index 752e3fbccb..2e358f06d7 100644
--- a/esp32s3/src/mcpwm0/ch/gen_force.rs
+++ b/esp32s3/src/mcpwm0/ch/gen_force.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
     #[inline(always)]
-    #[must_use]
     pub fn cntuforce_upmethod(&mut self) -> CNTUFORCE_UPMETHOD_W<GEN_FORCE_SPEC> {
         CNTUFORCE_UPMETHOD_W::new(self, 0)
     }
     #[doc = "Bits 6:7 - Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cntuforce_mode(&mut self) -> A_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
         A_CNTUFORCE_MODE_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cntuforce_mode(&mut self) -> B_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
         B_CNTUFORCE_MODE_W::new(self, 8)
     }
     #[doc = "Bit 10 - Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event."]
     #[inline(always)]
-    #[must_use]
     pub fn a_nciforce(&mut self) -> A_NCIFORCE_W<GEN_FORCE_SPEC> {
         A_NCIFORCE_W::new(self, 10)
     }
     #[doc = "Bits 11:12 - non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn a_nciforce_mode(&mut self) -> A_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
         A_NCIFORCE_MODE_W::new(self, 11)
     }
     #[doc = "Bit 13 - Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event."]
     #[inline(always)]
-    #[must_use]
     pub fn b_nciforce(&mut self) -> B_NCIFORCE_W<GEN_FORCE_SPEC> {
         B_NCIFORCE_W::new(self, 13)
     }
     #[doc = "Bits 14:15 - non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn b_nciforce_mode(&mut self) -> B_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
         B_NCIFORCE_MODE_W::new(self, 14)
     }
diff --git a/esp32s3/src/mcpwm0/ch/tz_cfg0.rs b/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
index 1abcc3b2e9..4b553adb4a 100644
--- a/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
+++ b/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_cbc(&mut self) -> SW_CBC_W<TZ_CFG0_SPEC> {
         SW_CBC_W::new(self, 0)
     }
     #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_cbc(&mut self) -> F2_CBC_W<TZ_CFG0_SPEC> {
         F2_CBC_W::new(self, 1)
     }
     #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_cbc(&mut self) -> F1_CBC_W<TZ_CFG0_SPEC> {
         F1_CBC_W::new(self, 2)
     }
     #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_cbc(&mut self) -> F0_CBC_W<TZ_CFG0_SPEC> {
         F0_CBC_W::new(self, 3)
     }
     #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_ost(&mut self) -> SW_OST_W<TZ_CFG0_SPEC> {
         SW_OST_W::new(self, 4)
     }
     #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_ost(&mut self) -> F2_OST_W<TZ_CFG0_SPEC> {
         F2_OST_W::new(self, 5)
     }
     #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_ost(&mut self) -> F1_OST_W<TZ_CFG0_SPEC> {
         F1_OST_W::new(self, 6)
     }
     #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_ost(&mut self) -> F0_OST_W<TZ_CFG0_SPEC> {
         F0_OST_W::new(self, 7)
     }
     #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cbc_d(&mut self) -> A_CBC_D_W<TZ_CFG0_SPEC> {
         A_CBC_D_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn a_cbc_u(&mut self) -> A_CBC_U_W<TZ_CFG0_SPEC> {
         A_CBC_U_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn a_ost_d(&mut self) -> A_OST_D_W<TZ_CFG0_SPEC> {
         A_OST_D_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn a_ost_u(&mut self) -> A_OST_U_W<TZ_CFG0_SPEC> {
         A_OST_U_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cbc_d(&mut self) -> B_CBC_D_W<TZ_CFG0_SPEC> {
         B_CBC_D_W::new(self, 16)
     }
     #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn b_cbc_u(&mut self) -> B_CBC_U_W<TZ_CFG0_SPEC> {
         B_CBC_U_W::new(self, 18)
     }
     #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn b_ost_d(&mut self) -> B_OST_D_W<TZ_CFG0_SPEC> {
         B_OST_D_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
     #[inline(always)]
-    #[must_use]
     pub fn b_ost_u(&mut self) -> B_OST_U_W<TZ_CFG0_SPEC> {
         B_OST_U_W::new(self, 22)
     }
diff --git a/esp32s3/src/mcpwm0/ch/tz_cfg1.rs b/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
index 166b6f95d5..c7a9b8464d 100644
--- a/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
+++ b/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
     #[inline(always)]
-    #[must_use]
     pub fn clr_ost(&mut self) -> CLR_OST_W<TZ_CFG1_SPEC> {
         CLR_OST_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP"]
     #[inline(always)]
-    #[must_use]
     pub fn cbcpulse(&mut self) -> CBCPULSE_W<TZ_CFG1_SPEC> {
         CBCPULSE_W::new(self, 1)
     }
     #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"]
     #[inline(always)]
-    #[must_use]
     pub fn force_cbc(&mut self) -> FORCE_CBC_W<TZ_CFG1_SPEC> {
         FORCE_CBC_W::new(self, 3)
     }
     #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"]
     #[inline(always)]
-    #[must_use]
     pub fn force_ost(&mut self) -> FORCE_OST_W<TZ_CFG1_SPEC> {
         FORCE_OST_W::new(self, 4)
     }
diff --git a/esp32s3/src/mcpwm0/clk.rs b/esp32s3/src/mcpwm0/clk.rs
index c4670f574f..96b434258d 100644
--- a/esp32s3/src/mcpwm0/clk.rs
+++ b/esp32s3/src/mcpwm0/clk.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Force clock on for this register file"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CLK_SPEC> {
         EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/clk_cfg.rs b/esp32s3/src/mcpwm0/clk_cfg.rs
index ed95a9e94d..a28c881f05 100644
--- a/esp32s3/src/mcpwm0/clk_cfg.rs
+++ b/esp32s3/src/mcpwm0/clk_cfg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W<CLK_CFG_SPEC> {
         CLK_PRESCALE_W::new(self, 0)
     }
diff --git a/esp32s3/src/mcpwm0/fault_detect.rs b/esp32s3/src/mcpwm0/fault_detect.rs
index a8284997cc..774c7e5f2f 100644
--- a/esp32s3/src/mcpwm0/fault_detect.rs
+++ b/esp32s3/src/mcpwm0/fault_detect.rs
@@ -98,37 +98,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_en(&mut self) -> F0_EN_W<FAULT_DETECT_SPEC> {
         F0_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - When set, event_f1 generation is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_en(&mut self) -> F1_EN_W<FAULT_DETECT_SPEC> {
         F1_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - When set, event_f2 generation is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_en(&mut self) -> F2_EN_W<FAULT_DETECT_SPEC> {
         F2_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
     #[inline(always)]
-    #[must_use]
     pub fn f0_pole(&mut self) -> F0_POLE_W<FAULT_DETECT_SPEC> {
         F0_POLE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
     #[inline(always)]
-    #[must_use]
     pub fn f1_pole(&mut self) -> F1_POLE_W<FAULT_DETECT_SPEC> {
         F1_POLE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
     #[inline(always)]
-    #[must_use]
     pub fn f2_pole(&mut self) -> F2_POLE_W<FAULT_DETECT_SPEC> {
         F2_POLE_W::new(self, 5)
     }
diff --git a/esp32s3/src/mcpwm0/int_clr.rs b/esp32s3/src/mcpwm0/int_clr.rs
index 183623d7c7..14b6ef10dc 100644
--- a/esp32s3/src/mcpwm0/int_clr.rs
+++ b/esp32s3/src/mcpwm0/int_clr.rs
@@ -69,181 +69,151 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_CLR_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_CLR_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_CLR_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_CLR_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_CLR_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_CLR_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_CLR_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_CLR_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_CLR_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_CLR_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_CLR_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_CLR_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_CLR_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_CLR_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_CLR_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_CLR_SPEC> {
         CMPR0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_CLR_SPEC> {
         CMPR1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_CLR_SPEC> {
         CMPR2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_CLR_SPEC> {
         CMPR0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_CLR_SPEC> {
         CMPR1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_CLR_SPEC> {
         CMPR2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_CLR_SPEC> {
         TZ0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_CLR_SPEC> {
         TZ1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_CLR_SPEC> {
         TZ2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_CLR_SPEC> {
         TZ0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_CLR_SPEC> {
         TZ1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_CLR_SPEC> {
         TZ2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_CLR_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_CLR_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_CLR_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32s3/src/mcpwm0/int_ena.rs b/esp32s3/src/mcpwm0/int_ena.rs
index 7e6edb52ea..4dc8e3cb23 100644
--- a/esp32s3/src/mcpwm0/int_ena.rs
+++ b/esp32s3/src/mcpwm0/int_ena.rs
@@ -314,181 +314,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_ENA_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_ENA_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_ENA_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_ENA_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_ENA_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_ENA_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_ENA_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_ENA_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_ENA_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_ENA_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_ENA_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_ENA_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_ENA_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_ENA_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_ENA_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_ENA_SPEC> {
         CMPR0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_ENA_SPEC> {
         CMPR1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_ENA_SPEC> {
         CMPR2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_ENA_SPEC> {
         CMPR0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_ENA_SPEC> {
         CMPR1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_ENA_SPEC> {
         CMPR2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_ENA_SPEC> {
         TZ0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_ENA_SPEC> {
         TZ1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_ENA_SPEC> {
         TZ2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_ENA_SPEC> {
         TZ0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_ENA_SPEC> {
         TZ1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_ENA_SPEC> {
         TZ2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_ENA_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_ENA_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_ENA_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32s3/src/mcpwm0/int_raw.rs b/esp32s3/src/mcpwm0/int_raw.rs
index 56632ef162..dfb1e4d34b 100644
--- a/esp32s3/src/mcpwm0/int_raw.rs
+++ b/esp32s3/src/mcpwm0/int_raw.rs
@@ -314,181 +314,151 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_RAW_SPEC> {
         TIMER0_STOP_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_RAW_SPEC> {
         TIMER1_STOP_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_RAW_SPEC> {
         TIMER2_STOP_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_RAW_SPEC> {
         TIMER0_TEZ_W::new(self, 3)
     }
     #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_RAW_SPEC> {
         TIMER1_TEZ_W::new(self, 4)
     }
     #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_RAW_SPEC> {
         TIMER2_TEZ_W::new(self, 5)
     }
     #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_RAW_SPEC> {
         TIMER0_TEP_W::new(self, 6)
     }
     #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_RAW_SPEC> {
         TIMER1_TEP_W::new(self, 7)
     }
     #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_RAW_SPEC> {
         TIMER2_TEP_W::new(self, 8)
     }
     #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0(&mut self) -> FAULT0_W<INT_RAW_SPEC> {
         FAULT0_W::new(self, 9)
     }
     #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1(&mut self) -> FAULT1_W<INT_RAW_SPEC> {
         FAULT1_W::new(self, 10)
     }
     #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2(&mut self) -> FAULT2_W<INT_RAW_SPEC> {
         FAULT2_W::new(self, 11)
     }
     #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_RAW_SPEC> {
         FAULT0_CLR_W::new(self, 12)
     }
     #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_RAW_SPEC> {
         FAULT1_CLR_W::new(self, 13)
     }
     #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
     #[inline(always)]
-    #[must_use]
     pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_RAW_SPEC> {
         FAULT2_CLR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_RAW_SPEC> {
         CMPR0_TEA_W::new(self, 15)
     }
     #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_RAW_SPEC> {
         CMPR1_TEA_W::new(self, 16)
     }
     #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_RAW_SPEC> {
         CMPR2_TEA_W::new(self, 17)
     }
     #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_RAW_SPEC> {
         CMPR0_TEB_W::new(self, 18)
     }
     #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_RAW_SPEC> {
         CMPR1_TEB_W::new(self, 19)
     }
     #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
     #[inline(always)]
-    #[must_use]
     pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_RAW_SPEC> {
         CMPR2_TEB_W::new(self, 20)
     }
     #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_RAW_SPEC> {
         TZ0_CBC_W::new(self, 21)
     }
     #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_RAW_SPEC> {
         TZ1_CBC_W::new(self, 22)
     }
     #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_RAW_SPEC> {
         TZ2_CBC_W::new(self, 23)
     }
     #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
     #[inline(always)]
-    #[must_use]
     pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_RAW_SPEC> {
         TZ0_OST_W::new(self, 24)
     }
     #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
     #[inline(always)]
-    #[must_use]
     pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_RAW_SPEC> {
         TZ1_OST_W::new(self, 25)
     }
     #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
     #[inline(always)]
-    #[must_use]
     pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_RAW_SPEC> {
         TZ2_OST_W::new(self, 26)
     }
     #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
     #[inline(always)]
-    #[must_use]
     pub fn cap0(&mut self) -> CAP0_W<INT_RAW_SPEC> {
         CAP0_W::new(self, 27)
     }
     #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cap1(&mut self) -> CAP1_W<INT_RAW_SPEC> {
         CAP1_W::new(self, 28)
     }
     #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
     #[inline(always)]
-    #[must_use]
     pub fn cap2(&mut self) -> CAP2_W<INT_RAW_SPEC> {
         CAP2_W::new(self, 29)
     }
diff --git a/esp32s3/src/mcpwm0/operator_timersel.rs b/esp32s3/src/mcpwm0/operator_timersel.rs
index 7b6e102810..a78f548536 100644
--- a/esp32s3/src/mcpwm0/operator_timersel.rs
+++ b/esp32s3/src/mcpwm0/operator_timersel.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    #[must_use]
     pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR0_TIMERSEL_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    #[must_use]
     pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR1_TIMERSEL_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
-    #[must_use]
     pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
         OPERATOR2_TIMERSEL_W::new(self, 4)
     }
diff --git a/esp32s3/src/mcpwm0/timer/cfg0.rs b/esp32s3/src/mcpwm0/timer/cfg0.rs
index 1a8215a1a5..c9709a150c 100644
--- a/esp32s3/src/mcpwm0/timer/cfg0.rs
+++ b/esp32s3/src/mcpwm0/timer/cfg0.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
     #[inline(always)]
-    #[must_use]
     pub fn prescale(&mut self) -> PRESCALE_W<CFG0_SPEC> {
         PRESCALE_W::new(self, 0)
     }
     #[doc = "Bits 8:23 - period shadow register of PWM timer0"]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<CFG0_SPEC> {
         PERIOD_W::new(self, 8)
     }
     #[doc = "Bits 24:25 - Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event"]
     #[inline(always)]
-    #[must_use]
     pub fn period_upmethod(&mut self) -> PERIOD_UPMETHOD_W<CFG0_SPEC> {
         PERIOD_UPMETHOD_W::new(self, 24)
     }
diff --git a/esp32s3/src/mcpwm0/timer/cfg1.rs b/esp32s3/src/mcpwm0/timer/cfg1.rs
index 6130b98b09..383c708679 100644
--- a/esp32s3/src/mcpwm0/timer/cfg1.rs
+++ b/esp32s3/src/mcpwm0/timer/cfg1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CFG1_SPEC> {
         START_W::new(self, 0)
     }
     #[doc = "Bits 3:4 - PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode"]
     #[inline(always)]
-    #[must_use]
     pub fn mod_(&mut self) -> MOD_W<CFG1_SPEC> {
         MOD_W::new(self, 3)
     }
diff --git a/esp32s3/src/mcpwm0/timer/sync.rs b/esp32s3/src/mcpwm0/timer/sync.rs
index c3a3e5b29d..def67ae500 100644
--- a/esp32s3/src/mcpwm0/timer/sync.rs
+++ b/esp32s3/src/mcpwm0/timer/sync.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn synci_en(&mut self) -> SYNCI_EN_W<SYNC_SPEC> {
         SYNCI_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Toggling this bit will trigger a software sync."]
     #[inline(always)]
-    #[must_use]
     pub fn sw(&mut self) -> SW_W<SYNC_SPEC> {
         SW_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync"]
     #[inline(always)]
-    #[must_use]
     pub fn synco_sel(&mut self) -> SYNCO_SEL_W<SYNC_SPEC> {
         SYNCO_SEL_W::new(self, 2)
     }
     #[doc = "Bits 4:19 - phase for timer reload on sync event"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<SYNC_SPEC> {
         PHASE_W::new(self, 4)
     }
     #[doc = "Bit 20 - Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease."]
     #[inline(always)]
-    #[must_use]
     pub fn phase_direction(&mut self) -> PHASE_DIRECTION_W<SYNC_SPEC> {
         PHASE_DIRECTION_W::new(self, 20)
     }
diff --git a/esp32s3/src/mcpwm0/timer_synci_cfg.rs b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
index 758cd1ba89..407f77e118 100644
--- a/esp32s3/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER0_SYNCISEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER1_SYNCISEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
         TIMER2_SYNCISEL_W::new(self, 6)
     }
     #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
     }
     #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
     }
     #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
     #[inline(always)]
-    #[must_use]
     pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
         EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
     }
diff --git a/esp32s3/src/mcpwm0/update_cfg.rs b/esp32s3/src/mcpwm0/update_cfg.rs
index fd1ba718fb..c972b8a148 100644
--- a/esp32s3/src/mcpwm0/update_cfg.rs
+++ b/esp32s3/src/mcpwm0/update_cfg.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
     #[inline(always)]
-    #[must_use]
     pub fn global_up_en(&mut self) -> GLOBAL_UP_EN_W<UPDATE_CFG_SPEC> {
         GLOBAL_UP_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module"]
     #[inline(always)]
-    #[must_use]
     pub fn global_force_up(&mut self) -> GLOBAL_FORCE_UP_W<UPDATE_CFG_SPEC> {
         GLOBAL_FORCE_UP_W::new(self, 1)
     }
     #[doc = "Bit 2 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_up_en(&mut self) -> OP0_UP_EN_W<UPDATE_CFG_SPEC> {
         OP0_UP_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0"]
     #[inline(always)]
-    #[must_use]
     pub fn op0_force_up(&mut self) -> OP0_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP0_FORCE_UP_W::new(self, 3)
     }
     #[doc = "Bit 4 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_up_en(&mut self) -> OP1_UP_EN_W<UPDATE_CFG_SPEC> {
         OP1_UP_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1"]
     #[inline(always)]
-    #[must_use]
     pub fn op1_force_up(&mut self) -> OP1_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP1_FORCE_UP_W::new(self, 5)
     }
     #[doc = "Bit 6 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_up_en(&mut self) -> OP2_UP_EN_W<UPDATE_CFG_SPEC> {
         OP2_UP_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2"]
     #[inline(always)]
-    #[must_use]
     pub fn op2_force_up(&mut self) -> OP2_FORCE_UP_W<UPDATE_CFG_SPEC> {
         OP2_FORCE_UP_W::new(self, 7)
     }
diff --git a/esp32s3/src/mcpwm0/version.rs b/esp32s3/src/mcpwm0/version.rs
index 3030c6584e..f0f9f0f0d3 100644
--- a/esp32s3/src/mcpwm0/version.rs
+++ b/esp32s3/src/mcpwm0/version.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<VERSION_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/nrx/nrxpd_ctrl.rs b/esp32s3/src/nrx/nrxpd_ctrl.rs
index 4de238a244..c41431ccbe 100644
--- a/esp32s3/src/nrx/nrxpd_ctrl.rs
+++ b/esp32s3/src/nrx/nrxpd_ctrl.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Force Power Down for Demapper"]
     #[inline(always)]
-    #[must_use]
     pub fn demap_force_pd(&mut self) -> DEMAP_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         DEMAP_FORCE_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Force Power Up for Demapper"]
     #[inline(always)]
-    #[must_use]
     pub fn demap_force_pu(&mut self) -> DEMAP_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         DEMAP_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2 - Force Power Down for Viterbi Decoder"]
     #[inline(always)]
-    #[must_use]
     pub fn vit_force_pd(&mut self) -> VIT_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         VIT_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3 - Force Power Up for Viterbi Decoder"]
     #[inline(always)]
-    #[must_use]
     pub fn vit_force_pu(&mut self) -> VIT_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         VIT_FORCE_PU_W::new(self, 3)
     }
     #[doc = "Bit 4 - Force Power Down for RX Rotation"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rot_force_pd(&mut self) -> RX_ROT_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         RX_ROT_FORCE_PD_W::new(self, 4)
     }
     #[doc = "Bit 5 - Force Power Up for RX Rotation"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rot_force_pu(&mut self) -> RX_ROT_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         RX_ROT_FORCE_PU_W::new(self, 5)
     }
     #[doc = "Bit 6 - Force Power Down for Channel Estimation"]
     #[inline(always)]
-    #[must_use]
     pub fn chan_est_force_pd(&mut self) -> CHAN_EST_FORCE_PD_W<NRXPD_CTRL_SPEC> {
         CHAN_EST_FORCE_PD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Force Power Up for Channel Estimation"]
     #[inline(always)]
-    #[must_use]
     pub fn chan_est_force_pu(&mut self) -> CHAN_EST_FORCE_PU_W<NRXPD_CTRL_SPEC> {
         CHAN_EST_FORCE_PU_W::new(self, 7)
     }
diff --git a/esp32s3/src/pcnt/ctrl.rs b/esp32s3/src/pcnt/ctrl.rs
index 9ea11d8451..baec6079be 100644
--- a/esp32s3/src/pcnt/ctrl.rs
+++ b/esp32s3/src/pcnt/ctrl.rs
@@ -112,7 +112,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_RST_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u(&mut self, n: u8) -> CNT_RST_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -120,25 +119,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u0(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 0)
     }
     #[doc = "Bit 2 - Set this bit to clear unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u1(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 2)
     }
     #[doc = "Bit 4 - Set this bit to clear unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u2(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 4)
     }
     #[doc = "Bit 6 - Set this bit to clear unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_rst_u3(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
         CNT_RST_U_W::new(self, 6)
     }
@@ -146,7 +141,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_PAUSE_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u(&mut self, n: u8) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -154,31 +148,26 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to pause unit0's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 1)
     }
     #[doc = "Bit 3 - Set this bit to pause unit1's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to pause unit2's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 5)
     }
     #[doc = "Bit 7 - Set this bit to pause unit3's counter."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
         CNT_PAUSE_U_W::new(self, 7)
     }
     #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
         CLK_EN_W::new(self, 16)
     }
diff --git a/esp32s3/src/pcnt/date.rs b/esp32s3/src/pcnt/date.rs
index 62c52e7519..e946eed689 100644
--- a/esp32s3/src/pcnt/date.rs
+++ b/esp32s3/src/pcnt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the PCNT version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/pcnt/int_clr.rs b/esp32s3/src/pcnt/int_clr.rs
index 60d2b9e5fc..8122a1e7bd 100644
--- a/esp32s3/src/pcnt/int_clr.rs
+++ b/esp32s3/src/pcnt/int_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -21,25 +20,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
diff --git a/esp32s3/src/pcnt/int_ena.rs b/esp32s3/src/pcnt/int_ena.rs
index 97405ab4c3..c96e98eacf 100644
--- a/esp32s3/src/pcnt/int_ena.rs
+++ b/esp32s3/src/pcnt/int_ena.rs
@@ -59,7 +59,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -67,25 +66,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
         CNT_THR_EVENT_U_W::new(self, 3)
     }
diff --git a/esp32s3/src/pcnt/unit/conf0.rs b/esp32s3/src/pcnt/unit/conf0.rs
index 5e715c9173..11efe74c98 100644
--- a/esp32s3/src/pcnt/unit/conf0.rs
+++ b/esp32s3/src/pcnt/unit/conf0.rs
@@ -346,43 +346,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_thres(&mut self) -> FILTER_THRES_W<CONF0_SPEC> {
         FILTER_THRES_W::new(self, 0)
     }
     #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
     #[inline(always)]
-    #[must_use]
     pub fn filter_en(&mut self) -> FILTER_EN_W<CONF0_SPEC> {
         FILTER_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_zero_en(&mut self) -> THR_ZERO_EN_W<CONF0_SPEC> {
         THR_ZERO_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_h_lim_en(&mut self) -> THR_H_LIM_EN_W<CONF0_SPEC> {
         THR_H_LIM_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_l_lim_en(&mut self) -> THR_L_LIM_EN_W<CONF0_SPEC> {
         THR_L_LIM_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres0_en(&mut self) -> THR_THRES0_EN_W<CONF0_SPEC> {
         THR_THRES0_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
     #[inline(always)]
-    #[must_use]
     pub fn thr_thres1_en(&mut self) -> THR_THRES1_EN_W<CONF0_SPEC> {
         THR_THRES1_EN_W::new(self, 15)
     }
@@ -390,7 +383,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_neg_mode(&mut self, n: u8) -> CH_NEG_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -398,13 +390,11 @@ impl W {
     }
     #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 16)
     }
     #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
         CH_NEG_MODE_W::new(self, 24)
     }
@@ -412,7 +402,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_pos_mode(&mut self, n: u8) -> CH_POS_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -420,13 +409,11 @@ impl W {
     }
     #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 18)
     }
     #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
         CH_POS_MODE_W::new(self, 26)
     }
@@ -434,7 +421,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_hctrl_mode(&mut self, n: u8) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -442,13 +428,11 @@ impl W {
     }
     #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 20)
     }
     #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
         CH_HCTRL_MODE_W::new(self, 28)
     }
@@ -456,7 +440,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_lctrl_mode(&mut self, n: u8) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -464,13 +447,11 @@ impl W {
     }
     #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 22)
     }
     #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
         CH_LCTRL_MODE_W::new(self, 30)
     }
diff --git a/esp32s3/src/pcnt/unit/conf1.rs b/esp32s3/src/pcnt/unit/conf1.rs
index 1585465b67..e88cae6aae 100644
--- a/esp32s3/src/pcnt/unit/conf1.rs
+++ b/esp32s3/src/pcnt/unit/conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres0(&mut self) -> CNT_THRES0_W<CONF1_SPEC> {
         CNT_THRES0_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_thres1(&mut self) -> CNT_THRES1_W<CONF1_SPEC> {
         CNT_THRES1_W::new(self, 16)
     }
diff --git a/esp32s3/src/pcnt/unit/conf2.rs b/esp32s3/src/pcnt/unit/conf2.rs
index cfc60509ee..d7b4aaa798 100644
--- a/esp32s3/src/pcnt/unit/conf2.rs
+++ b/esp32s3/src/pcnt/unit/conf2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_h_lim(&mut self) -> CNT_H_LIM_W<CONF2_SPEC> {
         CNT_H_LIM_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s."]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_l_lim(&mut self) -> CNT_L_LIM_W<CONF2_SPEC> {
         CNT_L_LIM_W::new(self, 16)
     }
diff --git a/esp32s3/src/peri_backup/apb_addr.rs b/esp32s3/src/peri_backup/apb_addr.rs
index 66ef22d215..c6ac934f70 100644
--- a/esp32s3/src/peri_backup/apb_addr.rs
+++ b/esp32s3/src/peri_backup/apb_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_start_addr(&mut self) -> APB_START_ADDR_W<APB_ADDR_SPEC> {
         APB_START_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/peri_backup/config.rs b/esp32s3/src/peri_backup/config.rs
index 02d75df7dc..2226eb1b16 100644
--- a/esp32s3/src/peri_backup/config.rs
+++ b/esp32s3/src/peri_backup/config.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn addr_map_mode(&mut self) -> ADDR_MAP_MODE_W<CONFIG_SPEC> {
         ADDR_MAP_MODE_W::new(self, 3)
     }
     #[doc = "Bits 4:8 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn burst_limit(&mut self) -> BURST_LIMIT_W<CONFIG_SPEC> {
         BURST_LIMIT_W::new(self, 4)
     }
     #[doc = "Bits 9:18 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn tout_thres(&mut self) -> TOUT_THRES_W<CONFIG_SPEC> {
         TOUT_THRES_W::new(self, 9)
     }
     #[doc = "Bits 19:28 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<CONFIG_SPEC> {
         SIZE_W::new(self, 19)
     }
     #[doc = "Bit 29 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CONFIG_SPEC> {
         START_W::new(self, 29)
     }
     #[doc = "Bit 30 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn to_mem(&mut self) -> TO_MEM_W<CONFIG_SPEC> {
         TO_MEM_W::new(self, 30)
     }
     #[doc = "Bit 31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn ena(&mut self) -> ENA_W<CONFIG_SPEC> {
         ENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/peri_backup/date.rs b/esp32s3/src/peri_backup/date.rs
index 9c6ef2c2b8..1b7864fcab 100644
--- a/esp32s3/src/peri_backup/date.rs
+++ b/esp32s3/src/peri_backup/date.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
     #[doc = "Bit 31 - register file clk gating"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<DATE_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/peri_backup/int_clr.rs b/esp32s3/src/peri_backup/int_clr.rs
index 732b359b93..490df05e71 100644
--- a/esp32s3/src/peri_backup/int_clr.rs
+++ b/esp32s3/src/peri_backup/int_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn done(&mut self) -> DONE_W<INT_CLR_SPEC> {
         DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn err(&mut self) -> ERR_W<INT_CLR_SPEC> {
         ERR_W::new(self, 1)
     }
diff --git a/esp32s3/src/peri_backup/int_ena.rs b/esp32s3/src/peri_backup/int_ena.rs
index f3268d53dc..530770788f 100644
--- a/esp32s3/src/peri_backup/int_ena.rs
+++ b/esp32s3/src/peri_backup/int_ena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn done(&mut self) -> DONE_W<INT_ENA_SPEC> {
         DONE_W::new(self, 0)
     }
     #[doc = "Bit 1 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn err(&mut self) -> ERR_W<INT_ENA_SPEC> {
         ERR_W::new(self, 1)
     }
diff --git a/esp32s3/src/peri_backup/mem_addr.rs b/esp32s3/src/peri_backup/mem_addr.rs
index 3db09363cb..f8b6cbfda2 100644
--- a/esp32s3/src/peri_backup/mem_addr.rs
+++ b/esp32s3/src/peri_backup/mem_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_start_addr(&mut self) -> MEM_START_ADDR_W<MEM_ADDR_SPEC> {
         MEM_START_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/peri_backup/reg_map0.rs b/esp32s3/src/peri_backup/reg_map0.rs
index 6013396a87..4ab9aed5da 100644
--- a/esp32s3/src/peri_backup/reg_map0.rs
+++ b/esp32s3/src/peri_backup/reg_map0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn map0(&mut self) -> MAP0_W<REG_MAP0_SPEC> {
         MAP0_W::new(self, 0)
     }
diff --git a/esp32s3/src/peri_backup/reg_map1.rs b/esp32s3/src/peri_backup/reg_map1.rs
index f15a13c475..135b85d3bb 100644
--- a/esp32s3/src/peri_backup/reg_map1.rs
+++ b/esp32s3/src/peri_backup/reg_map1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn map1(&mut self) -> MAP1_W<REG_MAP1_SPEC> {
         MAP1_W::new(self, 0)
     }
diff --git a/esp32s3/src/peri_backup/reg_map2.rs b/esp32s3/src/peri_backup/reg_map2.rs
index 5fed7654b4..97172ce58a 100644
--- a/esp32s3/src/peri_backup/reg_map2.rs
+++ b/esp32s3/src/peri_backup/reg_map2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn map2(&mut self) -> MAP2_W<REG_MAP2_SPEC> {
         MAP2_W::new(self, 0)
     }
diff --git a/esp32s3/src/peri_backup/reg_map3.rs b/esp32s3/src/peri_backup/reg_map3.rs
index 062975d31a..3f2de61503 100644
--- a/esp32s3/src/peri_backup/reg_map3.rs
+++ b/esp32s3/src/peri_backup/reg_map3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
-    #[must_use]
     pub fn map3(&mut self) -> MAP3_W<REG_MAP3_SPEC> {
         MAP3_W::new(self, 0)
     }
diff --git a/esp32s3/src/rmt.rs b/esp32s3/src/rmt.rs
index a8fb0a2d9f..22e42578c3 100644
--- a/esp32s3/src/rmt.rs
+++ b/esp32s3/src/rmt.rs
@@ -107,18 +107,31 @@ impl RegisterBlock {
         self.ch_tx_conf0(3)
     }
     #[doc = "0x30..0x40 - Channel %s configure register 0"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `CH4_RX_CONF0` register.</div>"]
     #[inline(always)]
     pub const fn ch_rx_conf0(&self, n: usize) -> &CH_RX_CONF0 {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(48).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(48)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x30..0x40 - Channel %s configure register 0"]
     #[inline(always)]
     pub fn ch_rx_conf0_iter(&self) -> impl Iterator<Item = &CH_RX_CONF0> {
-        (0..4)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(8 * n).cast() })
+        (0..4).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(48)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x30 - Channel 4 configure register 0"]
     #[inline(always)]
@@ -141,18 +154,31 @@ impl RegisterBlock {
         self.ch_rx_conf0(3)
     }
     #[doc = "0x34..0x44 - Channel %s configure register 1"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `CH4_RX_CONF1` register.</div>"]
     #[inline(always)]
     pub const fn ch_rx_conf1(&self, n: usize) -> &CH_RX_CONF1 {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*(self as *const Self).cast::<u8>().add(52).add(8 * n).cast() }
+        unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(52)
+                .add(8 * n)
+                .cast()
+        }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x34..0x44 - Channel %s configure register 1"]
     #[inline(always)]
     pub fn ch_rx_conf1_iter(&self) -> impl Iterator<Item = &CH_RX_CONF1> {
-        (0..4)
-            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(52).add(8 * n).cast() })
+        (0..4).map(move |n| unsafe {
+            &*core::ptr::from_ref(self)
+                .cast::<u8>()
+                .add(52)
+                .add(8 * n)
+                .cast()
+        })
     }
     #[doc = "0x34 - Channel 4 configure register 1"]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_carrier_rm.rs b/esp32s3/src/rmt/ch_rx_carrier_rm.rs
index 44001ff925..0444342463 100644
--- a/esp32s3/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32s3/src/rmt/ch_rx_carrier_rm.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_low_thres(&mut self) -> CARRIER_LOW_THRES_W<CH_RX_CARRIER_RM_SPEC> {
         CARRIER_LOW_THRES_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_high_thres(&mut self) -> CARRIER_HIGH_THRES_W<CH_RX_CARRIER_RM_SPEC> {
         CARRIER_HIGH_THRES_W::new(self, 16)
     }
diff --git a/esp32s3/src/rmt/ch_rx_conf0.rs b/esp32s3/src/rmt/ch_rx_conf0.rs
index 48205dcf69..930c1bd028 100644
--- a/esp32s3/src/rmt/ch_rx_conf0.rs
+++ b/esp32s3/src/rmt/ch_rx_conf0.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn div_cnt(&mut self) -> DIV_CNT_W<CH_RX_CONF0_SPEC> {
         DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_thres(&mut self) -> IDLE_THRES_W<CH_RX_CONF0_SPEC> {
         IDLE_THRES_W::new(self, 8)
     }
     #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_size(&mut self) -> MEM_SIZE_W<CH_RX_CONF0_SPEC> {
         MEM_SIZE_W::new(self, 24)
     }
     #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_en(&mut self) -> CARRIER_EN_W<CH_RX_CONF0_SPEC> {
         CARRIER_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<CH_RX_CONF0_SPEC> {
         CARRIER_OUT_LV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rmt/ch_rx_conf1.rs b/esp32s3/src/rmt/ch_rx_conf1.rs
index befc5121de..a9d38cf260 100644
--- a/esp32s3/src/rmt/ch_rx_conf1.rs
+++ b/esp32s3/src/rmt/ch_rx_conf1.rs
@@ -72,55 +72,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_en(&mut self) -> RX_EN_W<CH_RX_CONF1_SPEC> {
         RX_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_wr_rst(&mut self) -> MEM_WR_RST_W<CH_RX_CONF1_SPEC> {
         MEM_WR_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<CH_RX_CONF1_SPEC> {
         APB_MEM_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_owner(&mut self) -> MEM_OWNER_W<CH_RX_CONF1_SPEC> {
         MEM_OWNER_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the receive filter's enable bit for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_en(&mut self) -> RX_FILTER_EN_W<CH_RX_CONF1_SPEC> {
         RX_FILTER_EN_W::new(self, 4)
     }
     #[doc = "Bits 5:12 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_thres(&mut self) -> RX_FILTER_THRES_W<CH_RX_CONF1_SPEC> {
         RX_FILTER_THRES_W::new(self, 5)
     }
     #[doc = "Bit 13 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_rx_wrap_en(&mut self) -> MEM_RX_WRAP_EN_W<CH_RX_CONF1_SPEC> {
         MEM_RX_WRAP_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn afifo_rst(&mut self) -> AFIFO_RST_W<CH_RX_CONF1_SPEC> {
         AFIFO_RST_W::new(self, 14)
     }
     #[doc = "Bit 15 - synchronization bit for CHANNEL%s"]
     #[inline(always)]
-    #[must_use]
     pub fn conf_update(&mut self) -> CONF_UPDATE_W<CH_RX_CONF1_SPEC> {
         CONF_UPDATE_W::new(self, 15)
     }
diff --git a/esp32s3/src/rmt/ch_rx_lim.rs b/esp32s3/src/rmt/ch_rx_lim.rs
index 94947b4539..ac1d42cdcc 100644
--- a/esp32s3/src/rmt/ch_rx_lim.rs
+++ b/esp32s3/src/rmt/ch_rx_lim.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lim(&mut self) -> RX_LIM_W<CH_RX_LIM_SPEC> {
         RX_LIM_W::new(self, 0)
     }
diff --git a/esp32s3/src/rmt/ch_tx_conf0.rs b/esp32s3/src/rmt/ch_tx_conf0.rs
index efbc8b2072..0b70018287 100644
--- a/esp32s3/src/rmt/ch_tx_conf0.rs
+++ b/esp32s3/src/rmt/ch_tx_conf0.rs
@@ -124,91 +124,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<CH_TX_CONF0_SPEC> {
         TX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_rd_rst(&mut self) -> MEM_RD_RST_W<CH_TX_CONF0_SPEC> {
         MEM_RD_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<CH_TX_CONF0_SPEC> {
         APB_MEM_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_conti_mode(&mut self) -> TX_CONTI_MODE_W<CH_TX_CONF0_SPEC> {
         TX_CONTI_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<CH_TX_CONF0_SPEC> {
         MEM_TX_WRAP_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_lv(&mut self) -> IDLE_OUT_LV_W<CH_TX_CONF0_SPEC> {
         IDLE_OUT_LV_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the output enable-control bit for CHANNEL%s in IDLE state."]
     #[inline(always)]
-    #[must_use]
     pub fn idle_out_en(&mut self) -> IDLE_OUT_EN_W<CH_TX_CONF0_SPEC> {
         IDLE_OUT_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to stop the transmitter of CHANNEL%s sending data out."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_stop(&mut self) -> TX_STOP_W<CH_TX_CONF0_SPEC> {
         TX_STOP_W::new(self, 7)
     }
     #[doc = "Bits 8:15 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn div_cnt(&mut self) -> DIV_CNT_W<CH_TX_CONF0_SPEC> {
         DIV_CNT_W::new(self, 8)
     }
     #[doc = "Bits 16:19 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_size(&mut self) -> MEM_SIZE_W<CH_TX_CONF0_SPEC> {
         MEM_SIZE_W::new(self, 16)
     }
     #[doc = "Bit 20 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_eff_en(&mut self) -> CARRIER_EFF_EN_W<CH_TX_CONF0_SPEC> {
         CARRIER_EFF_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_en(&mut self) -> CARRIER_EN_W<CH_TX_CONF0_SPEC> {
         CARRIER_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<CH_TX_CONF0_SPEC> {
         CARRIER_OUT_LV_W::new(self, 22)
     }
     #[doc = "Bit 23 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn afifo_rst(&mut self) -> AFIFO_RST_W<CH_TX_CONF0_SPEC> {
         AFIFO_RST_W::new(self, 23)
     }
     #[doc = "Bit 24 - synchronization bit for CHANNEL%s"]
     #[inline(always)]
-    #[must_use]
     pub fn conf_update(&mut self) -> CONF_UPDATE_W<CH_TX_CONF0_SPEC> {
         CONF_UPDATE_W::new(self, 24)
     }
diff --git a/esp32s3/src/rmt/ch_tx_lim.rs b/esp32s3/src/rmt/ch_tx_lim.rs
index 34f227c619..39debf5c5b 100644
--- a/esp32s3/src/rmt/ch_tx_lim.rs
+++ b/esp32s3/src/rmt/ch_tx_lim.rs
@@ -56,31 +56,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lim(&mut self) -> TX_LIM_W<CH_TX_LIM_SPEC> {
         TX_LIM_W::new(self, 0)
     }
     #[doc = "Bits 9:18 - This register is used to configure the maximum loop count when tx_conti_mode is valid."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_loop_num(&mut self) -> TX_LOOP_NUM_W<CH_TX_LIM_SPEC> {
         TX_LOOP_NUM_W::new(self, 9)
     }
     #[doc = "Bit 19 - This register is the enabled bit for loop count."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_loop_cnt_en(&mut self) -> TX_LOOP_CNT_EN_W<CH_TX_LIM_SPEC> {
         TX_LOOP_CNT_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - This register is used to reset the loop count when tx_conti_mode is valid."]
     #[inline(always)]
-    #[must_use]
     pub fn loop_count_reset(&mut self) -> LOOP_COUNT_RESET_W<CH_TX_LIM_SPEC> {
         LOOP_COUNT_RESET_W::new(self, 20)
     }
     #[doc = "Bit 21 - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn loop_stop_en(&mut self) -> LOOP_STOP_EN_W<CH_TX_LIM_SPEC> {
         LOOP_STOP_EN_W::new(self, 21)
     }
diff --git a/esp32s3/src/rmt/chcarrier_duty.rs b/esp32s3/src/rmt/chcarrier_duty.rs
index 1aedd08615..a45cf0e6ed 100644
--- a/esp32s3/src/rmt/chcarrier_duty.rs
+++ b/esp32s3/src/rmt/chcarrier_duty.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_low(&mut self) -> CARRIER_LOW_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_LOW_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."]
     #[inline(always)]
-    #[must_use]
     pub fn carrier_high(&mut self) -> CARRIER_HIGH_W<CHCARRIER_DUTY_SPEC> {
         CARRIER_HIGH_W::new(self, 16)
     }
diff --git a/esp32s3/src/rmt/chdata.rs b/esp32s3/src/rmt/chdata.rs
index 7fce764b5e..9cdbe81915 100644
--- a/esp32s3/src/rmt/chdata.rs
+++ b/esp32s3/src/rmt/chdata.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Read and write data for channel %s via APB FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<CHDATA_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/esp32s3/src/rmt/date.rs b/esp32s3/src/rmt/date.rs
index b71004c654..cd57af9245 100644
--- a/esp32s3/src/rmt/date.rs
+++ b/esp32s3/src/rmt/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - This is the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rmt/int_clr.rs b/esp32s3/src/rmt/int_clr.rs
index 2c645ccf6c..eb0a90ffe6 100644
--- a/esp32s3/src/rmt/int_clr.rs
+++ b/esp32s3/src/rmt/int_clr.rs
@@ -29,7 +29,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -37,25 +36,21 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
@@ -63,7 +58,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -71,25 +65,21 @@ impl W {
     }
     #[doc = "Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
         CH_TX_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
         CH_TX_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
         CH_TX_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
         CH_TX_ERR_W::new(self, 7)
     }
@@ -97,7 +87,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -105,25 +94,21 @@ impl W {
     }
     #[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 11)
     }
@@ -131,7 +116,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -139,25 +123,21 @@ impl W {
     }
     #[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
         CH_TX_LOOP_W::new(self, 15)
     }
@@ -165,7 +145,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -173,25 +152,21 @@ impl W {
     }
     #[doc = "Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear theCH4_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear theCH4_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear theCH4_RX_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
         CH_RX_END_W::new(self, 19)
     }
@@ -199,7 +174,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -207,25 +181,21 @@ impl W {
     }
     #[doc = "Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
         CH_RX_ERR_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to clear theCH4_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
         CH_RX_ERR_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to clear theCH4_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
         CH_RX_ERR_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to clear theCH4_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
         CH_RX_ERR_W::new(self, 23)
     }
@@ -233,7 +203,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -241,37 +210,31 @@ impl W {
     }
     #[doc = "Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ch3_dma_access_fail(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
         TX_CH3_DMA_ACCESS_FAIL_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ch7_dma_access_fail(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
         RX_CH7_DMA_ACCESS_FAIL_W::new(self, 29)
     }
diff --git a/esp32s3/src/rmt/int_ena.rs b/esp32s3/src/rmt/int_ena.rs
index 8f10479654..be47d40232 100644
--- a/esp32s3/src/rmt/int_ena.rs
+++ b/esp32s3/src/rmt/int_ena.rs
@@ -337,7 +337,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -345,25 +344,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for CH0_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for CH1_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for CH2_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for CH3_TX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
@@ -371,7 +366,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -379,25 +373,21 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt enable bit for CH0_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
         CH_TX_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for CH1_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
         CH_TX_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for CH2_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
         CH_TX_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for CH3_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_err(&mut self) -> CH_TX_ERR_W<INT_ENA_SPEC> {
         CH_TX_ERR_W::new(self, 7)
     }
@@ -405,7 +395,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -413,25 +402,21 @@ impl W {
     }
     #[doc = "Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for CH2_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for CH3_TX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 11)
     }
@@ -439,7 +424,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -447,25 +431,21 @@ impl W {
     }
     #[doc = "Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt enable bit for CH2_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt enable bit for CH3_TX_LOOP_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_ENA_SPEC> {
         CH_TX_LOOP_W::new(self, 15)
     }
@@ -473,7 +453,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -481,25 +460,21 @@ impl W {
     }
     #[doc = "Bit 16 - The interrupt enable bit for CH4_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt enable bit for CH4_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt enable bit for CH4_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt enable bit for CH4_RX_END_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
         CH_RX_END_W::new(self, 19)
     }
@@ -507,7 +482,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -515,25 +489,21 @@ impl W {
     }
     #[doc = "Bit 20 - The interrupt enable bit for CH4_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
         CH_RX_ERR_W::new(self, 20)
     }
     #[doc = "Bit 21 - The interrupt enable bit for CH4_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
         CH_RX_ERR_W::new(self, 21)
     }
     #[doc = "Bit 22 - The interrupt enable bit for CH4_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
         CH_RX_ERR_W::new(self, 22)
     }
     #[doc = "Bit 23 - The interrupt enable bit for CH4_ERR_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_err(&mut self) -> CH_RX_ERR_W<INT_ENA_SPEC> {
         CH_RX_ERR_W::new(self, 23)
     }
@@ -541,7 +511,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -549,37 +518,31 @@ impl W {
     }
     #[doc = "Bit 24 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 24)
     }
     #[doc = "Bit 25 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 25)
     }
     #[doc = "Bit 26 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 26)
     }
     #[doc = "Bit 27 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_ENA_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 27)
     }
     #[doc = "Bit 28 - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ch3_dma_access_fail(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_W<INT_ENA_SPEC> {
         TX_CH3_DMA_ACCESS_FAIL_W::new(self, 28)
     }
     #[doc = "Bit 29 - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ch7_dma_access_fail(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_W<INT_ENA_SPEC> {
         RX_CH7_DMA_ACCESS_FAIL_W::new(self, 29)
     }
diff --git a/esp32s3/src/rmt/int_raw.rs b/esp32s3/src/rmt/int_raw.rs
index ff111c75fc..e4da0b870b 100644
--- a/esp32s3/src/rmt/int_raw.rs
+++ b/esp32s3/src/rmt/int_raw.rs
@@ -337,7 +337,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -345,25 +344,21 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt raw bit for CHANNEL0. Triggered when transmission done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_RAW_SPEC> {
         CH_TX_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt raw bit for CHANNEL1. Triggered when transmission done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_RAW_SPEC> {
         CH_TX_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt raw bit for CHANNEL2. Triggered when transmission done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_RAW_SPEC> {
         CH_TX_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt raw bit for CHANNEL3. Triggered when transmission done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_RAW_SPEC> {
         CH_TX_END_W::new(self, 3)
     }
@@ -371,7 +366,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -379,25 +373,21 @@ impl W {
     }
     #[doc = "Bit 4 - The interrupt raw bit for CHANNEL0. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_RAW_SPEC> {
         CH_TX_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt raw bit for CHANNEL1. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_RAW_SPEC> {
         CH_TX_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt raw bit for CHANNEL2. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_err(&mut self) -> CH_TX_ERR_W<INT_RAW_SPEC> {
         CH_TX_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt raw bit for CHANNEL3. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_err(&mut self) -> CH_TX_ERR_W<INT_RAW_SPEC> {
         CH_TX_ERR_W::new(self, 7)
     }
@@ -405,7 +395,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -413,25 +402,21 @@ impl W {
     }
     #[doc = "Bit 8 - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_TX_THR_EVENT_W::new(self, 11)
     }
@@ -439,7 +424,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -447,25 +431,21 @@ impl W {
     }
     #[doc = "Bit 12 - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_RAW_SPEC> {
         CH_TX_LOOP_W::new(self, 12)
     }
     #[doc = "Bit 13 - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_RAW_SPEC> {
         CH_TX_LOOP_W::new(self, 13)
     }
     #[doc = "Bit 14 - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_RAW_SPEC> {
         CH_TX_LOOP_W::new(self, 14)
     }
     #[doc = "Bit 15 - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_RAW_SPEC> {
         CH_TX_LOOP_W::new(self, 15)
     }
@@ -473,7 +453,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_END` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -481,25 +460,21 @@ impl W {
     }
     #[doc = "Bit 16 - The interrupt raw bit for CHANNEL4. Triggered when reception done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_RAW_SPEC> {
         CH_RX_END_W::new(self, 16)
     }
     #[doc = "Bit 17 - The interrupt raw bit for CHANNEL4. Triggered when reception done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_RAW_SPEC> {
         CH_RX_END_W::new(self, 17)
     }
     #[doc = "Bit 18 - The interrupt raw bit for CHANNEL4. Triggered when reception done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_RAW_SPEC> {
         CH_RX_END_W::new(self, 18)
     }
     #[doc = "Bit 19 - The interrupt raw bit for CHANNEL4. Triggered when reception done."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_RAW_SPEC> {
         CH_RX_END_W::new(self, 19)
     }
@@ -507,7 +482,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_ERR` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -515,25 +489,21 @@ impl W {
     }
     #[doc = "Bit 20 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_err(&mut self) -> CH_RX_ERR_W<INT_RAW_SPEC> {
         CH_RX_ERR_W::new(self, 20)
     }
     #[doc = "Bit 21 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_err(&mut self) -> CH_RX_ERR_W<INT_RAW_SPEC> {
         CH_RX_ERR_W::new(self, 21)
     }
     #[doc = "Bit 22 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_err(&mut self) -> CH_RX_ERR_W<INT_RAW_SPEC> {
         CH_RX_ERR_W::new(self, 22)
     }
     #[doc = "Bit 23 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_err(&mut self) -> CH_RX_ERR_W<INT_RAW_SPEC> {
         CH_RX_ERR_W::new(self, 23)
     }
@@ -541,7 +511,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH4_RX_THR_EVENT` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 4][n as usize];
@@ -549,37 +518,31 @@ impl W {
     }
     #[doc = "Bit 24 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 24)
     }
     #[doc = "Bit 25 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 25)
     }
     #[doc = "Bit 26 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 26)
     }
     #[doc = "Bit 27 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_RAW_SPEC> {
         CH_RX_THR_EVENT_W::new(self, 27)
     }
     #[doc = "Bit 28 - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ch3_dma_access_fail(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_W<INT_RAW_SPEC> {
         TX_CH3_DMA_ACCESS_FAIL_W::new(self, 28)
     }
     #[doc = "Bit 29 - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_ch7_dma_access_fail(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_W<INT_RAW_SPEC> {
         RX_CH7_DMA_ACCESS_FAIL_W::new(self, 29)
     }
diff --git a/esp32s3/src/rmt/ref_cnt_rst.rs b/esp32s3/src/rmt/ref_cnt_rst.rs
index aaf95b5e49..a602b2abac 100644
--- a/esp32s3/src/rmt/ref_cnt_rst.rs
+++ b/esp32s3/src/rmt/ref_cnt_rst.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn ch(&mut self, n: u8) -> CH_W<REF_CNT_RST_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 8][n as usize];
@@ -21,49 +20,41 @@ impl W {
     }
     #[doc = "Bit 0 - This register is used to reset the clock divider of CHANNEL0."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 0)
     }
     #[doc = "Bit 1 - This register is used to reset the clock divider of CHANNEL1."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 1)
     }
     #[doc = "Bit 2 - This register is used to reset the clock divider of CHANNEL2."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 2)
     }
     #[doc = "Bit 3 - This register is used to reset the clock divider of CHANNEL3."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 3)
     }
     #[doc = "Bit 4 - This register is used to reset the clock divider of CHANNEL4."]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 4)
     }
     #[doc = "Bit 5 - This register is used to reset the clock divider of CHANNEL5."]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 5)
     }
     #[doc = "Bit 6 - This register is used to reset the clock divider of CHANNEL6."]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 6)
     }
     #[doc = "Bit 7 - This register is used to reset the clock divider of CHANNEL7."]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH_W<REF_CNT_RST_SPEC> {
         CH_W::new(self, 7)
     }
diff --git a/esp32s3/src/rmt/sys_conf.rs b/esp32s3/src/rmt/sys_conf.rs
index 9371d428d5..4922aeb4c2 100644
--- a/esp32s3/src/rmt/sys_conf.rs
+++ b/esp32s3/src/rmt/sys_conf.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<SYS_CONF_SPEC> {
         APB_FIFO_MASK_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable the clock for RMT memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<SYS_CONF_SPEC> {
         MEM_CLK_FORCE_ON_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to power down RMT memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<SYS_CONF_SPEC> {
         MEM_FORCE_PD_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<SYS_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 3)
     }
     #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<SYS_CONF_SPEC> {
         SCLK_DIV_NUM_W::new(self, 4)
     }
     #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<SYS_CONF_SPEC> {
         SCLK_DIV_A_W::new(self, 12)
     }
     #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<SYS_CONF_SPEC> {
         SCLK_DIV_B_W::new(self, 18)
     }
     #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_sel(&mut self) -> SCLK_SEL_W<SYS_CONF_SPEC> {
         SCLK_SEL_W::new(self, 24)
     }
     #[doc = "Bit 26 - rmt_sclk switch"]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<SYS_CONF_SPEC> {
         SCLK_ACTIVE_W::new(self, 26)
     }
     #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<SYS_CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rmt/tx_sim.rs b/esp32s3/src/rmt/tx_sim.rs
index edada0cb4d..4d0bb2f875 100644
--- a/esp32s3/src/rmt/tx_sim.rs
+++ b/esp32s3/src/rmt/tx_sim.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<TX_SIM_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<TX_SIM_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<TX_SIM_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<TX_SIM_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4 - This register is used to enable multiple of channels to start sending data synchronously."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<TX_SIM_SPEC> {
         EN_W::new(self, 4)
     }
diff --git a/esp32s3/src/rsa/constant_time.rs b/esp32s3/src/rsa/constant_time.rs
index 01a6e5b6aa..08894c85e6 100644
--- a/esp32s3/src/rsa/constant_time.rs
+++ b/esp32s3/src/rsa/constant_time.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default)."]
     #[inline(always)]
-    #[must_use]
     pub fn constant_time(&mut self) -> CONSTANT_TIME_W<CONSTANT_TIME_SPEC> {
         CONSTANT_TIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/date.rs b/esp32s3/src/rsa/date.rs
index 79e40b7c55..92d5be2b70 100644
--- a/esp32s3/src/rsa/date.rs
+++ b/esp32s3/src/rsa/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - rsa version information"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/int_clr.rs b/esp32s3/src/rsa/int_clr.rs
index 8062163589..2a7e20f1d2 100644
--- a/esp32s3/src/rsa/int_clr.rs
+++ b/esp32s3/src/rsa/int_clr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - set this bit to 1 to clear the RSA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
         INT_CLR_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/int_ena.rs b/esp32s3/src/rsa/int_ena.rs
index f586503c05..dc7de5d0db 100644
--- a/esp32s3/src/rsa/int_ena.rs
+++ b/esp32s3/src/rsa/int_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."]
     #[inline(always)]
-    #[must_use]
     pub fn int_ena(&mut self) -> INT_ENA_W<INT_ENA_SPEC> {
         INT_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/m_prime.rs b/esp32s3/src/rsa/m_prime.rs
index c12354ce00..e6dfa383ab 100644
--- a/esp32s3/src/rsa/m_prime.rs
+++ b/esp32s3/src/rsa/m_prime.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores M'"]
     #[inline(always)]
-    #[must_use]
     pub fn m_prime(&mut self) -> M_PRIME_W<M_PRIME_SPEC> {
         M_PRIME_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/mode.rs b/esp32s3/src/rsa/mode.rs
index 42885adaf4..b84dd88b12 100644
--- a/esp32s3/src/rsa/mode.rs
+++ b/esp32s3/src/rsa/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Stores the RSA length mode"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/modexp_start.rs b/esp32s3/src/rsa/modexp_start.rs
index 44f6cbd7a7..96859ec757 100644
--- a/esp32s3/src/rsa/modexp_start.rs
+++ b/esp32s3/src/rsa/modexp_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MODEXP_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the modular exponentiation."]
     #[inline(always)]
-    #[must_use]
     pub fn modexp_start(&mut self) -> MODEXP_START_W<MODEXP_START_SPEC> {
         MODEXP_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/modmult_start.rs b/esp32s3/src/rsa/modmult_start.rs
index f99704f38e..5ac6f096d6 100644
--- a/esp32s3/src/rsa/modmult_start.rs
+++ b/esp32s3/src/rsa/modmult_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MODMULT_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the modular multiplication"]
     #[inline(always)]
-    #[must_use]
     pub fn modmult_start(&mut self) -> MODMULT_START_W<MODMULT_START_SPEC> {
         MODMULT_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/mult_start.rs b/esp32s3/src/rsa/mult_start.rs
index 67417b768d..59e5b3ea2a 100644
--- a/esp32s3/src/rsa/mult_start.rs
+++ b/esp32s3/src/rsa/mult_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<MULT_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to start the multiplicaiton."]
     #[inline(always)]
-    #[must_use]
     pub fn mult_start(&mut self) -> MULT_START_W<MULT_START_SPEC> {
         MULT_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/search_enable.rs b/esp32s3/src/rsa/search_enable.rs
index 989c78c8a1..9e060b00e4 100644
--- a/esp32s3/src/rsa/search_enable.rs
+++ b/esp32s3/src/rsa/search_enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration."]
     #[inline(always)]
-    #[must_use]
     pub fn search_enable(&mut self) -> SEARCH_ENABLE_W<SEARCH_ENABLE_SPEC> {
         SEARCH_ENABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rsa/search_pos.rs b/esp32s3/src/rsa/search_pos.rs
index 7f042d1f70..1120a068bc 100644
--- a/esp32s3/src/rsa/search_pos.rs
+++ b/esp32s3/src/rsa/search_pos.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - This field is used to configure the starting search position when the acceleration option of SEARCH is used."]
     #[inline(always)]
-    #[must_use]
     pub fn search_pos(&mut self) -> SEARCH_POS_W<SEARCH_POS_SPEC> {
         SEARCH_POS_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/ana_conf.rs b/esp32s3/src/rtc_cntl/ana_conf.rs
index f5a19b437d..2ee9bf549b 100644
--- a/esp32s3/src/rtc_cntl/ana_conf.rs
+++ b/esp32s3/src/rtc_cntl/ana_conf.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 18 - force down I2C_RESET_POR"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_reset_por_force_pd(&mut self) -> I2C_RESET_POR_FORCE_PD_W<ANA_CONF_SPEC> {
         I2C_RESET_POR_FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - force on I2C_RESET_POR"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_reset_por_force_pu(&mut self) -> I2C_RESET_POR_FORCE_PU_W<ANA_CONF_SPEC> {
         I2C_RESET_POR_FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - enable clk glitch"]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_rst_en(&mut self) -> GLITCH_RST_EN_W<ANA_CONF_SPEC> {
         GLITCH_RST_EN_W::new(self, 20)
     }
     #[doc = "Bit 22 - PLLA force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_pu(&mut self) -> SAR_I2C_PU_W<ANA_CONF_SPEC> {
         SAR_I2C_PU_W::new(self, 22)
     }
     #[doc = "Bit 23 - PLLA force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_top_iso_sleep(&mut self) -> ANALOG_TOP_ISO_SLEEP_W<ANA_CONF_SPEC> {
         ANALOG_TOP_ISO_SLEEP_W::new(self, 23)
     }
     #[doc = "Bit 24 - PLLA force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_top_iso_monitor(&mut self) -> ANALOG_TOP_ISO_MONITOR_W<ANA_CONF_SPEC> {
         ANALOG_TOP_ISO_MONITOR_W::new(self, 24)
     }
     #[doc = "Bit 25 - start BBPLL calibration during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<ANA_CONF_SPEC> {
         BBPLL_CAL_SLP_START_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1: PVTMON power up, otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<ANA_CONF_SPEC> {
         PVTMON_PU_W::new(self, 26)
     }
     #[doc = "Bit 27 - 1: TXRF_I2C power up, otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<ANA_CONF_SPEC> {
         TXRF_I2C_PU_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: RFRX_PBUS power up, otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<ANA_CONF_SPEC> {
         RFRX_PBUS_PU_W::new(self, 28)
     }
     #[doc = "Bit 30 - 1: CKGEN_I2C power up, otherwise power down"]
     #[inline(always)]
-    #[must_use]
     pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<ANA_CONF_SPEC> {
         CKGEN_I2C_PU_W::new(self, 30)
     }
     #[doc = "Bit 31 - power on pll i2c"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<ANA_CONF_SPEC> {
         PLL_I2C_PU_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/bias_conf.rs b/esp32s3/src/rtc_cntl/bias_conf.rs
index dd9c0add03..65ed7a2ee3 100644
--- a/esp32s3/src/rtc_cntl/bias_conf.rs
+++ b/esp32s3/src/rtc_cntl/bias_conf.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 10 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_idle(&mut self) -> BIAS_BUF_IDLE_W<BIAS_CONF_SPEC> {
         BIAS_BUF_IDLE_W::new(self, 10)
     }
     #[doc = "Bit 11 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_wake(&mut self) -> BIAS_BUF_WAKE_W<BIAS_CONF_SPEC> {
         BIAS_BUF_WAKE_W::new(self, 11)
     }
     #[doc = "Bit 12 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_deep_slp(&mut self) -> BIAS_BUF_DEEP_SLP_W<BIAS_CONF_SPEC> {
         BIAS_BUF_DEEP_SLP_W::new(self, 12)
     }
     #[doc = "Bit 13 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_buf_monitor(&mut self) -> BIAS_BUF_MONITOR_W<BIAS_CONF_SPEC> {
         BIAS_BUF_MONITOR_W::new(self, 13)
     }
     #[doc = "Bit 14 - xpd cur when rtc in sleep_state"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_cur_deep_slp(&mut self) -> PD_CUR_DEEP_SLP_W<BIAS_CONF_SPEC> {
         PD_CUR_DEEP_SLP_W::new(self, 14)
     }
     #[doc = "Bit 15 - xpd cur when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_cur_monitor(&mut self) -> PD_CUR_MONITOR_W<BIAS_CONF_SPEC> {
         PD_CUR_MONITOR_W::new(self, 15)
     }
     #[doc = "Bit 16 - bias_sleep when rtc in sleep_state"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_sleep_deep_slp(&mut self) -> BIAS_SLEEP_DEEP_SLP_W<BIAS_CONF_SPEC> {
         BIAS_SLEEP_DEEP_SLP_W::new(self, 16)
     }
     #[doc = "Bit 17 - bias_sleep when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn bias_sleep_monitor(&mut self) -> BIAS_SLEEP_MONITOR_W<BIAS_CONF_SPEC> {
         BIAS_SLEEP_MONITOR_W::new(self, 17)
     }
     #[doc = "Bits 18:21 - DBG_ATTEN when rtc in sleep state"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten_deep_slp(&mut self) -> DBG_ATTEN_DEEP_SLP_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_DEEP_SLP_W::new(self, 18)
     }
     #[doc = "Bits 22:25 - DBG_ATTEN when rtc in monitor state"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten_monitor(&mut self) -> DBG_ATTEN_MONITOR_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_MONITOR_W::new(self, 22)
     }
     #[doc = "Bits 26:29 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg_atten_wakeup(&mut self) -> DBG_ATTEN_WAKEUP_W<BIAS_CONF_SPEC> {
         DBG_ATTEN_WAKEUP_W::new(self, 26)
     }
diff --git a/esp32s3/src/rtc_cntl/brown_out.rs b/esp32s3/src/rtc_cntl/brown_out.rs
index 04709677eb..3d21335e58 100644
--- a/esp32s3/src/rtc_cntl/brown_out.rs
+++ b/esp32s3/src/rtc_cntl/brown_out.rs
@@ -107,55 +107,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_int_wait(&mut self) -> BROWN_OUT_INT_WAIT_W<BROWN_OUT_SPEC> {
         BROWN_OUT_INT_WAIT_W::new(self, 4)
     }
     #[doc = "Bit 14 - enable close flash when brown out happens"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_close_flash_ena(&mut self) -> BROWN_OUT_CLOSE_FLASH_ENA_W<BROWN_OUT_SPEC> {
         BROWN_OUT_CLOSE_FLASH_ENA_W::new(self, 14)
     }
     #[doc = "Bit 15 - enable power down RF when brown out happens"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_pd_rf_ena(&mut self) -> BROWN_OUT_PD_RF_ENA_W<BROWN_OUT_SPEC> {
         BROWN_OUT_PD_RF_ENA_W::new(self, 15)
     }
     #[doc = "Bits 16:25 - brown out reset wait cycles"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_rst_wait(&mut self) -> BROWN_OUT_RST_WAIT_W<BROWN_OUT_SPEC> {
         BROWN_OUT_RST_WAIT_W::new(self, 16)
     }
     #[doc = "Bit 26 - enable brown out reset"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_rst_ena(&mut self) -> BROWN_OUT_RST_ENA_W<BROWN_OUT_SPEC> {
         BROWN_OUT_RST_ENA_W::new(self, 26)
     }
     #[doc = "Bit 27 - 1: 4-pos reset, 0: sys_reset"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_rst_sel(&mut self) -> BROWN_OUT_RST_SEL_W<BROWN_OUT_SPEC> {
         BROWN_OUT_RST_SEL_W::new(self, 27)
     }
     #[doc = "Bit 28 - enable brown out reset en"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_ana_rst_en(&mut self) -> BROWN_OUT_ANA_RST_EN_W<BROWN_OUT_SPEC> {
         BROWN_OUT_ANA_RST_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - clear brown out counter"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_cnt_clr(&mut self) -> BROWN_OUT_CNT_CLR_W<BROWN_OUT_SPEC> {
         BROWN_OUT_CNT_CLR_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable brown out"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out_ena(&mut self) -> BROWN_OUT_ENA_W<BROWN_OUT_SPEC> {
         BROWN_OUT_ENA_W::new(self, 30)
     }
diff --git a/esp32s3/src/rtc_cntl/clk_conf.rs b/esp32s3/src/rtc_cntl/clk_conf.rs
index be1c8c21c8..b0f2721694 100644
--- a/esp32s3/src/rtc_cntl/clk_conf.rs
+++ b/esp32s3/src/rtc_cntl/clk_conf.rs
@@ -207,115 +207,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - force efuse clk gating"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_clk_force_gating(&mut self) -> EFUSE_CLK_FORCE_GATING_W<CLK_CONF_SPEC> {
         EFUSE_CLK_FORCE_GATING_W::new(self, 1)
     }
     #[doc = "Bit 2 - force efuse clk nogating"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_clk_force_nogating(&mut self) -> EFUSE_CLK_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         EFUSE_CLK_FORCE_NOGATING_W::new(self, 2)
     }
     #[doc = "Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<CLK_CONF_SPEC> {
         CK8M_DIV_SEL_VLD_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024."]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
         CK8M_DIV_W::new(self, 4)
     }
     #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
         ENB_CK8M_W::new(self, 6)
     }
     #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256"]
     #[inline(always)]
-    #[must_use]
     pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
         ENB_CK8M_DIV_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
         DIG_XTAL32K_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_D256_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
         DIG_CLK8M_EN_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
         CK8M_DIV_SEL_W::new(self, 12)
     }
     #[doc = "Bit 15 - XTAL force no gating during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         XTAL_FORCE_NOGATING_W::new(self, 15)
     }
     #[doc = "Bit 16 - CK8M force no gating during sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         CK8M_FORCE_NOGATING_W::new(self, 16)
     }
     #[doc = "Bits 17:24 - CK8M_DFREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
         CK8M_DFREQ_W::new(self, 17)
     }
     #[doc = "Bit 25 - CK8M force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PD_W::new(self, 25)
     }
     #[doc = "Bit 26 - CK8M force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
         CK8M_FORCE_PU_W::new(self, 26)
     }
     #[doc = "Bit 27 - force global xtal gating"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_global_force_gating(&mut self) -> XTAL_GLOBAL_FORCE_GATING_W<CLK_CONF_SPEC> {
         XTAL_GLOBAL_FORCE_GATING_W::new(self, 27)
     }
     #[doc = "Bit 28 - force global xtal no gating"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal_global_force_nogating(&mut self) -> XTAL_GLOBAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
         XTAL_GLOBAL_FORCE_NOGATING_W::new(self, 28)
     }
     #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M"]
     #[inline(always)]
-    #[must_use]
     pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         FAST_CLK_RTC_SEL_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - select slow clock"]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
         ANA_CLK_RTC_SEL_W::new(self, 30)
     }
diff --git a/esp32s3/src/rtc_cntl/cocpu_ctrl.rs b/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
index 87705dffd3..eb6eff5f92 100644
--- a/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
@@ -116,67 +116,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - cocpu clk force on"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<COCPU_CTRL_SPEC> {
         COCPU_CLK_FO_W::new(self, 0)
     }
     #[doc = "Bits 1:6 - time from start cocpu to pull down reset"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<COCPU_CTRL_SPEC> {
         COCPU_START_2_RESET_DIS_W::new(self, 1)
     }
     #[doc = "Bits 7:12 - time from start cocpu to give start interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<COCPU_CTRL_SPEC> {
         COCPU_START_2_INTR_EN_W::new(self, 7)
     }
     #[doc = "Bit 13 - to shut cocpu"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_W::new(self, 13)
     }
     #[doc = "Bits 14:21 - time from shut cocpu to disable clk"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_2_CLK_DIS_W::new(self, 14)
     }
     #[doc = "Bit 22 - to reset cocpu"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<COCPU_CTRL_SPEC> {
         COCPU_SHUT_RESET_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - 1: old ULP 0: new riscV"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<COCPU_CTRL_SPEC> {
         COCPU_SEL_W::new(self, 23)
     }
     #[doc = "Bit 24 - 1: select riscv done 0: select ulp done"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<COCPU_CTRL_SPEC> {
         COCPU_DONE_FORCE_W::new(self, 24)
     }
     #[doc = "Bit 25 - done signal used by riscv to control timer."]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_done(&mut self) -> COCPU_DONE_W<COCPU_CTRL_SPEC> {
         COCPU_DONE_W::new(self, 25)
     }
     #[doc = "Bit 26 - trigger cocpu register interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<COCPU_CTRL_SPEC> {
         COCPU_SW_INT_TRIGGER_W::new(self, 26)
     }
     #[doc = "Bit 27 - open ulp-riscv clk gate"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_clkgate_en(&mut self) -> COCPU_CLKGATE_EN_W<COCPU_CTRL_SPEC> {
         COCPU_CLKGATE_EN_W::new(self, 27)
     }
diff --git a/esp32s3/src/rtc_cntl/cocpu_disable.rs b/esp32s3/src/rtc_cntl/cocpu_disable.rs
index 115d07693b..56ad6443b9 100644
--- a/esp32s3/src/rtc_cntl/cocpu_disable.rs
+++ b/esp32s3/src/rtc_cntl/cocpu_disable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - configure ulp diable"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_rtc_cpu(&mut self) -> DISABLE_RTC_CPU_W<COCPU_DISABLE_SPEC> {
         DISABLE_RTC_CPU_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/cpu_period_conf.rs b/esp32s3/src/rtc_cntl/cpu_period_conf.rs
index ca2123fb86..9203e1d983 100644
--- a/esp32s3/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32s3/src/rtc_cntl/cpu_period_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
-    #[must_use]
     pub fn cpusel_conf(&mut self) -> CPUSEL_CONF_W<CPU_PERIOD_CONF_SPEC> {
         CPUSEL_CONF_W::new(self, 29)
     }
     #[doc = "Bits 30:31 - conigure cpu freq"]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PERIOD_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 30)
     }
diff --git a/esp32s3/src/rtc_cntl/date.rs b/esp32s3/src/rtc_cntl/date.rs
index cd0b4bb56f..f46fbadefa 100644
--- a/esp32s3/src/rtc_cntl/date.rs
+++ b/esp32s3/src/rtc_cntl/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/dig_iso.rs b/esp32s3/src/rtc_cntl/dig_iso.rs
index 1ab85dca32..4c2fcf088c 100644
--- a/esp32s3/src/rtc_cntl/dig_iso.rs
+++ b/esp32s3/src/rtc_cntl/dig_iso.rs
@@ -194,109 +194,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn force_off(&mut self) -> FORCE_OFF_W<DIG_ISO_SPEC> {
         FORCE_OFF_W::new(self, 7)
     }
     #[doc = "Bit 8 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn force_on(&mut self) -> FORCE_ON_W<DIG_ISO_SPEC> {
         FORCE_ON_W::new(self, 8)
     }
     #[doc = "Bit 10 - wtite only register to clear digital pad auto-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn clr_dg_pad_autohold(&mut self) -> CLR_DG_PAD_AUTOHOLD_W<DIG_ISO_SPEC> {
         CLR_DG_PAD_AUTOHOLD_W::new(self, 10)
     }
     #[doc = "Bit 11 - digital pad enable auto-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_autohold_en(&mut self) -> DG_PAD_AUTOHOLD_EN_W<DIG_ISO_SPEC> {
         DG_PAD_AUTOHOLD_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - digital pad force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_noiso(&mut self) -> DG_PAD_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_NOISO_W::new(self, 12)
     }
     #[doc = "Bit 13 - digital pad force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_iso(&mut self) -> DG_PAD_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_ISO_W::new(self, 13)
     }
     #[doc = "Bit 14 - digital pad force un-hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_unhold(&mut self) -> DG_PAD_FORCE_UNHOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_UNHOLD_W::new(self, 14)
     }
     #[doc = "Bit 15 - digital pad force hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_pad_force_hold(&mut self) -> DG_PAD_FORCE_HOLD_W<DIG_ISO_SPEC> {
         DG_PAD_FORCE_HOLD_W::new(self, 15)
     }
     #[doc = "Bit 22 - internal SRAM 2 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_force_iso(&mut self) -> BT_FORCE_ISO_W<DIG_ISO_SPEC> {
         BT_FORCE_ISO_W::new(self, 22)
     }
     #[doc = "Bit 23 - internal SRAM 2 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_force_noiso(&mut self) -> BT_FORCE_NOISO_W<DIG_ISO_SPEC> {
         BT_FORCE_NOISO_W::new(self, 23)
     }
     #[doc = "Bit 24 - internal SRAM 3 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_force_iso(&mut self) -> DG_PERI_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_PERI_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25 - internal SRAM 3 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_force_noiso(&mut self) -> DG_PERI_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_PERI_FORCE_NOISO_W::new(self, 25)
     }
     #[doc = "Bit 26 - internal SRAM 4 force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_force_iso(&mut self) -> CPU_TOP_FORCE_ISO_W<DIG_ISO_SPEC> {
         CPU_TOP_FORCE_ISO_W::new(self, 26)
     }
     #[doc = "Bit 27 - internal SRAM 4 force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_force_noiso(&mut self) -> CPU_TOP_FORCE_NOISO_W<DIG_ISO_SPEC> {
         CPU_TOP_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28 - wifi force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_iso(&mut self) -> WIFI_FORCE_ISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_ISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - wifi force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_noiso(&mut self) -> WIFI_FORCE_NOISO_W<DIG_ISO_SPEC> {
         WIFI_FORCE_NOISO_W::new(self, 29)
     }
     #[doc = "Bit 30 - digital core force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_iso(&mut self) -> DG_WRAP_FORCE_ISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_ISO_W::new(self, 30)
     }
     #[doc = "Bit 31 - digita core force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_noiso(&mut self) -> DG_WRAP_FORCE_NOISO_W<DIG_ISO_SPEC> {
         DG_WRAP_FORCE_NOISO_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/dig_pad_hold.rs b/esp32s3/src/rtc_cntl/dig_pad_hold.rs
index 2db4f08310..b83412449a 100644
--- a/esp32s3/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32s3/src/rtc_cntl/dig_pad_hold.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - configure digtal pad hold"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_pad_hold(&mut self) -> DIG_PAD_HOLD_W<DIG_PAD_HOLD_SPEC> {
         DIG_PAD_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/dig_pwc.rs b/esp32s3/src/rtc_cntl/dig_pwc.rs
index 9aa6b3079b..0b16cd8584 100644
--- a/esp32s3/src/rtc_cntl/dig_pwc.rs
+++ b/esp32s3/src/rtc_cntl/dig_pwc.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - memories in digital core force PD in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - memories in digital core force no PD in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<DIG_PWC_SPEC> {
         LSLP_MEM_FORCE_PU_W::new(self, 4)
     }
     #[doc = "Bit 11 - internal SRAM 2 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_force_pd(&mut self) -> BT_FORCE_PD_W<DIG_PWC_SPEC> {
         BT_FORCE_PD_W::new(self, 11)
     }
     #[doc = "Bit 12 - internal SRAM 2 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_force_pu(&mut self) -> BT_FORCE_PU_W<DIG_PWC_SPEC> {
         BT_FORCE_PU_W::new(self, 12)
     }
     #[doc = "Bit 13 - internal SRAM 3 force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_force_pd(&mut self) -> DG_PERI_FORCE_PD_W<DIG_PWC_SPEC> {
         DG_PERI_FORCE_PD_W::new(self, 13)
     }
     #[doc = "Bit 14 - internal SRAM 3 force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_force_pu(&mut self) -> DG_PERI_FORCE_PU_W<DIG_PWC_SPEC> {
         DG_PERI_FORCE_PU_W::new(self, 14)
     }
     #[doc = "Bit 17 - wifi force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pd(&mut self) -> WIFI_FORCE_PD_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PD_W::new(self, 17)
     }
     #[doc = "Bit 18 - wifi force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_force_pu(&mut self) -> WIFI_FORCE_PU_W<DIG_PWC_SPEC> {
         WIFI_FORCE_PU_W::new(self, 18)
     }
     #[doc = "Bit 19 - digital core force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PD_W::new(self, 19)
     }
     #[doc = "Bit 20 - digital core force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<DIG_PWC_SPEC> {
         DG_WRAP_FORCE_PU_W::new(self, 20)
     }
     #[doc = "Bit 21 - digital dcdc force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_force_pd(&mut self) -> CPU_TOP_FORCE_PD_W<DIG_PWC_SPEC> {
         CPU_TOP_FORCE_PD_W::new(self, 21)
     }
     #[doc = "Bit 22 - digital dcdc force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_force_pu(&mut self) -> CPU_TOP_FORCE_PU_W<DIG_PWC_SPEC> {
         CPU_TOP_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 27 - enable power down internal SRAM 2 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_pd_en(&mut self) -> BT_PD_EN_W<DIG_PWC_SPEC> {
         BT_PD_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - enable power down internal SRAM 3 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_pd_en(&mut self) -> DG_PERI_PD_EN_W<DIG_PWC_SPEC> {
         DG_PERI_PD_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - enable power down internal SRAM 4 in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_pd_en(&mut self) -> CPU_TOP_PD_EN_W<DIG_PWC_SPEC> {
         CPU_TOP_PD_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable power down wifi in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_pd_en(&mut self) -> WIFI_PD_EN_W<DIG_PWC_SPEC> {
         WIFI_PD_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable power down all digital logic"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<DIG_PWC_SPEC> {
         DG_WRAP_PD_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/ext_wakeup1.rs b/esp32s3/src/rtc_cntl/ext_wakeup1.rs
index 33a6517ce0..4732776ac6 100644
--- a/esp32s3/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32s3/src/rtc_cntl/ext_wakeup1.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Bitmap to select RTC pads for ext wakeup1"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup1_sel(&mut self) -> EXT_WAKEUP1_SEL_W<EXT_WAKEUP1_SPEC> {
         EXT_WAKEUP1_SEL_W::new(self, 0)
     }
     #[doc = "Bit 22 - clear ext wakeup1 status"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup1_status_clr(&mut self) -> EXT_WAKEUP1_STATUS_CLR_W<EXT_WAKEUP1_SPEC> {
         EXT_WAKEUP1_STATUS_CLR_W::new(self, 22)
     }
diff --git a/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs b/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
index 073055ec64..71ea9d2e1f 100644
--- a/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 29 - enable filter for gpio wakeup event"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_wakeup_filter(&mut self) -> GPIO_WAKEUP_FILTER_W<EXT_WAKEUP_CONF_SPEC> {
         GPIO_WAKEUP_FILTER_W::new(self, 29)
     }
     #[doc = "Bit 30 - 0: external wakeup at low level, 1: external wakeup at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup0_lv(&mut self) -> EXT_WAKEUP0_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP0_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - 0: external wakeup at low level, 1: external wakeup at high level"]
     #[inline(always)]
-    #[must_use]
     pub fn ext_wakeup1_lv(&mut self) -> EXT_WAKEUP1_LV_W<EXT_WAKEUP_CONF_SPEC> {
         EXT_WAKEUP1_LV_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/ext_xtl_conf.rs b/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
index d98832c2b3..1164a9e236 100644
--- a/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
@@ -192,103 +192,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - xtal 32k watch dog enable"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_en(&mut self) -> XTAL32K_WDT_EN_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - xtal 32k watch dog clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_clk_fo(&mut self) -> XTAL32K_WDT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_CLK_FO_W::new(self, 1)
     }
     #[doc = "Bit 2 - xtal 32k watch dog sw reset"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_reset(&mut self) -> XTAL32K_WDT_RESET_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_WDT_RESET_W::new(self, 2)
     }
     #[doc = "Bit 3 - xtal 32k external xtal clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_ext_clk_fo(&mut self) -> XTAL32K_EXT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_EXT_CLK_FO_W::new(self, 3)
     }
     #[doc = "Bit 4 - xtal 32k switch to back up clock when xtal is dead"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_backup(&mut self) -> XTAL32K_AUTO_BACKUP_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_BACKUP_W::new(self, 4)
     }
     #[doc = "Bit 5 - xtal 32k restart xtal when xtal is dead"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_restart(&mut self) -> XTAL32K_AUTO_RESTART_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_RESTART_W::new(self, 5)
     }
     #[doc = "Bit 6 - xtal 32k switch back xtal when xtal is restarted"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_auto_return(&mut self) -> XTAL32K_AUTO_RETURN_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_AUTO_RETURN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Xtal 32k xpd control by sw or fsm"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_xpd_force(&mut self) -> XTAL32K_XPD_FORCE_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_XPD_FORCE_W::new(self, 7)
     }
     #[doc = "Bit 8 - apply an internal clock to help xtal 32k to start"]
     #[inline(always)]
-    #[must_use]
     pub fn enckinit_xtal_32k(&mut self) -> ENCKINIT_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         ENCKINIT_XTAL_32K_W::new(self, 8)
     }
     #[doc = "Bit 9 - 0: single-end buffer 1: differential buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn dbuf_xtal_32k(&mut self) -> DBUF_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DBUF_XTAL_32K_W::new(self, 9)
     }
     #[doc = "Bits 10:12 - xtal_32k gm control"]
     #[inline(always)]
-    #[must_use]
     pub fn dgm_xtal_32k(&mut self) -> DGM_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DGM_XTAL_32K_W::new(self, 10)
     }
     #[doc = "Bits 13:15 - DRES_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn dres_xtal_32k(&mut self) -> DRES_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DRES_XTAL_32K_W::new(self, 13)
     }
     #[doc = "Bit 16 - XPD_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_xtal_32k(&mut self) -> XPD_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         XPD_XTAL_32K_W::new(self, 16)
     }
     #[doc = "Bits 17:19 - DAC_XTAL_32K"]
     #[inline(always)]
-    #[must_use]
     pub fn dac_xtal_32k(&mut self) -> DAC_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
         DAC_XTAL_32K_W::new(self, 17)
     }
     #[doc = "Bit 23 - XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_gpio_sel(&mut self) -> XTAL32K_GPIO_SEL_W<EXT_XTL_CONF_SPEC> {
         XTAL32K_GPIO_SEL_W::new(self, 23)
     }
     #[doc = "Bit 30 - 0: power down XTAL at high level, 1: power down XTAL at low level"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_lv(&mut self) -> XTL_EXT_CTR_LV_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_LV_W::new(self, 30)
     }
     #[doc = "Bit 31 - Reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_ext_ctr_en(&mut self) -> XTL_EXT_CTR_EN_W<EXT_XTL_CONF_SPEC> {
         XTL_EXT_CTR_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/fib_sel.rs b/esp32s3/src/rtc_cntl/fib_sel.rs
index 867dda13cd..5c0490282c 100644
--- a/esp32s3/src/rtc_cntl/fib_sel.rs
+++ b/esp32s3/src/rtc_cntl/fib_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn fib_sel(&mut self) -> FIB_SEL_W<FIB_SEL_SPEC> {
         FIB_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/int_clr.rs b/esp32s3/src/rtc_cntl/int_clr.rs
index 815e1ca3a8..b520bc49fa 100644
--- a/esp32s3/src/rtc_cntl/int_clr.rs
+++ b/esp32s3/src/rtc_cntl/int_clr.rs
@@ -51,127 +51,106 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Clear sleep reject interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Clear SDIO idle interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - clear touch scan done interrupt raw"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_CLR_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Clear ULP-coprocessor interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_CLR_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - Clear touch done interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_CLR_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Clear touch active interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_CLR_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Clear touch inactive interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_CLR_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Clear brown out interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Clear RTC main timer interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - Clear saradc1 interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_CLR_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - Clear tsens interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - Clear riscV cocpu interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_CLR_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - Clear saradc2 interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_CLR_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - Clear super watch dog interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - Clear RTC WDT interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_CLR_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - Clear cocpu trap interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_CLR_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - Clear touch timeout interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_CLR_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - Clear glitch det interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
     #[doc = "Bit 20 - cleartouch approach mode loop interrupt state"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_CLR_SPEC> {
         TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
     }
diff --git a/esp32s3/src/rtc_cntl/int_ena.rs b/esp32s3/src/rtc_cntl/int_ena.rs
index d3ef4a30f4..91d7c39e18 100644
--- a/esp32s3/src/rtc_cntl/int_ena.rs
+++ b/esp32s3/src/rtc_cntl/int_ena.rs
@@ -224,127 +224,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - enable sleep reject interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - enable SDIO idle interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable RTC WDT interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - enable touch scan done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable touch done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - enable touch active interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable touch inactive interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable brown out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable RTC main timer interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - enable saradc1 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - enable tsens interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_ENA_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - enable riscV cocpu interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - enable saradc2 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - enable super watch dog interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_ENA_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - enable cocpu trap interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - enable touch timeout interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - enbale gitch det interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
     #[doc = "Bit 20 - touch approach mode loop interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_SPEC> {
         TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
     }
diff --git a/esp32s3/src/rtc_cntl/int_ena_rtc_w1tc.rs b/esp32s3/src/rtc_cntl/int_ena_rtc_w1tc.rs
index 00d1ac9348..9e6b0dc3f3 100644
--- a/esp32s3/src/rtc_cntl/int_ena_rtc_w1tc.rs
+++ b/esp32s3/src/rtc_cntl/int_ena_rtc_w1tc.rs
@@ -51,127 +51,106 @@ impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TC_SPEC> {
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_RTC_W1TC_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - enable sleep reject interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_RTC_W1TC_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - enable SDIO idle interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_RTC_W1TC_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable RTC WDT interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_RTC_W1TC_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - enable touch scan done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_RTC_W1TC_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable touch done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - enable touch active interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_RTC_W1TC_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable touch inactive interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_RTC_W1TC_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable brown out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_RTC_W1TC_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable RTC main timer interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_RTC_W1TC_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - enable saradc1 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_RTC_W1TC_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - enable tsens interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_ENA_RTC_W1TC_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - enable riscV cocpu interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_RTC_W1TC_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - enable saradc2 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_RTC_W1TC_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - enable super watch dog interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_ENA_RTC_W1TC_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_RTC_W1TC_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - enable cocpu trap interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_RTC_W1TC_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - enable touch timeout interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_RTC_W1TC_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - enbale gitch det interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_RTC_W1TC_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
     #[doc = "Bit 20 - enbale touch approach_loop done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_loop_done(
         &mut self,
     ) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
diff --git a/esp32s3/src/rtc_cntl/int_ena_rtc_w1ts.rs b/esp32s3/src/rtc_cntl/int_ena_rtc_w1ts.rs
index c714df58c0..1ac08d82cd 100644
--- a/esp32s3/src/rtc_cntl/int_ena_rtc_w1ts.rs
+++ b/esp32s3/src/rtc_cntl/int_ena_rtc_w1ts.rs
@@ -51,127 +51,106 @@ impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TS_SPEC> {
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_RTC_W1TS_SPEC> {
         SLP_WAKEUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - enable sleep reject interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_RTC_W1TS_SPEC> {
         SLP_REJECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - enable SDIO idle interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_RTC_W1TS_SPEC> {
         SDIO_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable RTC WDT interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_RTC_W1TS_SPEC> {
         WDT_W::new(self, 3)
     }
     #[doc = "Bit 4 - enable touch scan done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
         TOUCH_SCAN_DONE_W::new(self, 4)
     }
     #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_RTC_W1TS_SPEC> {
         ULP_CP_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable touch done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
         TOUCH_DONE_W::new(self, 6)
     }
     #[doc = "Bit 7 - enable touch active interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_RTC_W1TS_SPEC> {
         TOUCH_ACTIVE_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable touch inactive interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_RTC_W1TS_SPEC> {
         TOUCH_INACTIVE_W::new(self, 8)
     }
     #[doc = "Bit 9 - enable brown out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_RTC_W1TS_SPEC> {
         BROWN_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable RTC main timer interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_RTC_W1TS_SPEC> {
         MAIN_TIMER_W::new(self, 10)
     }
     #[doc = "Bit 11 - enable saradc1 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_RTC_W1TS_SPEC> {
         SARADC1_W::new(self, 11)
     }
     #[doc = "Bit 12 - enable tsens interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens(&mut self) -> TSENS_W<INT_ENA_RTC_W1TS_SPEC> {
         TSENS_W::new(self, 12)
     }
     #[doc = "Bit 13 - enable riscV cocpu interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_RTC_W1TS_SPEC> {
         COCPU_W::new(self, 13)
     }
     #[doc = "Bit 14 - enable saradc2 interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_RTC_W1TS_SPEC> {
         SARADC2_W::new(self, 14)
     }
     #[doc = "Bit 15 - enable super watch dog interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn swd(&mut self) -> SWD_W<INT_ENA_RTC_W1TS_SPEC> {
         SWD_W::new(self, 15)
     }
     #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_RTC_W1TS_SPEC> {
         XTAL32K_DEAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - enable cocpu trap interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_RTC_W1TS_SPEC> {
         COCPU_TRAP_W::new(self, 17)
     }
     #[doc = "Bit 18 - enable touch timeout interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_RTC_W1TS_SPEC> {
         TOUCH_TIMEOUT_W::new(self, 18)
     }
     #[doc = "Bit 19 - enbale gitch det interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_RTC_W1TS_SPEC> {
         GLITCH_DET_W::new(self, 19)
     }
     #[doc = "Bit 20 - enbale touch approach_loop done interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_loop_done(
         &mut self,
     ) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
diff --git a/esp32s3/src/rtc_cntl/int_raw.rs b/esp32s3/src/rtc_cntl/int_raw.rs
index d13f99d52c..9d9ec75718 100644
--- a/esp32s3/src/rtc_cntl/int_raw.rs
+++ b/esp32s3/src/rtc_cntl/int_raw.rs
@@ -184,7 +184,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20 - touch approach mode loop interrupt raw"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_RAW_SPEC> {
         TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
     }
diff --git a/esp32s3/src/rtc_cntl/option1.rs b/esp32s3/src/rtc_cntl/option1.rs
index 050f34e5c5..3af032e9b0 100644
--- a/esp32s3/src/rtc_cntl/option1.rs
+++ b/esp32s3/src/rtc_cntl/option1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - force chip entry download boot by sw"]
     #[inline(always)]
-    #[must_use]
     pub fn force_download_boot(&mut self) -> FORCE_DOWNLOAD_BOOT_W<OPTION1_SPEC> {
         FORCE_DOWNLOAD_BOOT_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/options0.rs b/esp32s3/src/rtc_cntl/options0.rs
index c0e801b110..47dd9c8ce1 100644
--- a/esp32s3/src/rtc_cntl/options0.rs
+++ b/esp32s3/src/rtc_cntl/options0.rs
@@ -210,133 +210,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c0(&mut self) -> SW_STALL_APPCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_APPCPU_C0_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c0(&mut self) -> SW_STALL_PROCPU_C0_W<OPTIONS0_SPEC> {
         SW_STALL_PROCPU_C0_W::new(self, 2)
     }
     #[doc = "Bit 4 - APP CPU SW reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_appcpu_rst(&mut self) -> SW_APPCPU_RST_W<OPTIONS0_SPEC> {
         SW_APPCPU_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - PRO CPU SW reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_procpu_rst(&mut self) -> SW_PROCPU_RST_W<OPTIONS0_SPEC> {
         SW_PROCPU_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - BB_I2C force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pd(&mut self) -> BB_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PD_W::new(self, 6)
     }
     #[doc = "Bit 7 - BB_I2C force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bb_i2c_force_pu(&mut self) -> BB_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BB_I2C_FORCE_PU_W::new(self, 7)
     }
     #[doc = "Bit 8 - BB_PLL _I2C force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pd(&mut self) -> BBPLL_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PD_W::new(self, 8)
     }
     #[doc = "Bit 9 - BB_PLL_I2C force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_i2c_force_pu(&mut self) -> BBPLL_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_I2C_FORCE_PU_W::new(self, 9)
     }
     #[doc = "Bit 10 - BB_PLL force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pd(&mut self) -> BBPLL_FORCE_PD_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PD_W::new(self, 10)
     }
     #[doc = "Bit 11 - BB_PLL force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn bbpll_force_pu(&mut self) -> BBPLL_FORCE_PU_W<OPTIONS0_SPEC> {
         BBPLL_FORCE_PU_W::new(self, 11)
     }
     #[doc = "Bit 12 - crystall force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pd(&mut self) -> XTL_FORCE_PD_W<OPTIONS0_SPEC> {
         XTL_FORCE_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - crystall force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_pu(&mut self) -> XTL_FORCE_PU_W<OPTIONS0_SPEC> {
         XTL_FORCE_PU_W::new(self, 13)
     }
     #[doc = "Bits 14:17 - wait bias_sleep and current source wakeup"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_en_wait(&mut self) -> XTL_EN_WAIT_W<OPTIONS0_SPEC> {
         XTL_EN_WAIT_W::new(self, 14)
     }
     #[doc = "Bit 23 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_iso(&mut self) -> XTL_FORCE_ISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_ISO_W::new(self, 23)
     }
     #[doc = "Bit 24 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_iso(&mut self) -> PLL_FORCE_ISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_ISO_W::new(self, 24)
     }
     #[doc = "Bit 25 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_iso(&mut self) -> ANALOG_FORCE_ISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_ISO_W::new(self, 25)
     }
     #[doc = "Bit 26 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_force_noiso(&mut self) -> XTL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         XTL_FORCE_NOISO_W::new(self, 26)
     }
     #[doc = "Bit 27 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_force_noiso(&mut self) -> PLL_FORCE_NOISO_W<OPTIONS0_SPEC> {
         PLL_FORCE_NOISO_W::new(self, 27)
     }
     #[doc = "Bit 28 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn analog_force_noiso(&mut self) -> ANALOG_FORCE_NOISO_W<OPTIONS0_SPEC> {
         ANALOG_FORCE_NOISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - digital wrap force reset in deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_rst(&mut self) -> DG_WRAP_FORCE_RST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - digital core force no reset in deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_force_norst(&mut self) -> DG_WRAP_FORCE_NORST_W<OPTIONS0_SPEC> {
         DG_WRAP_FORCE_NORST_W::new(self, 30)
     }
     #[doc = "Bit 31 - SW system reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_sys_rst(&mut self) -> SW_SYS_RST_W<OPTIONS0_SPEC> {
         SW_SYS_RST_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/pad_hold.rs b/esp32s3/src/rtc_cntl/pad_hold.rs
index 44ea003dcd..86bc8018ca 100644
--- a/esp32s3/src/rtc_cntl/pad_hold.rs
+++ b/esp32s3/src/rtc_cntl/pad_hold.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - hold rtc pad0"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad0_hold(&mut self) -> TOUCH_PAD0_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD0_HOLD_W::new(self, 0)
     }
     #[doc = "Bit 1 - hold rtc pad-1"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad1_hold(&mut self) -> TOUCH_PAD1_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD1_HOLD_W::new(self, 1)
     }
     #[doc = "Bit 2 - hold rtc pad-2"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad2_hold(&mut self) -> TOUCH_PAD2_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD2_HOLD_W::new(self, 2)
     }
     #[doc = "Bit 3 - hold rtc pad-3"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad3_hold(&mut self) -> TOUCH_PAD3_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD3_HOLD_W::new(self, 3)
     }
     #[doc = "Bit 4 - hold rtc pad-4"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad4_hold(&mut self) -> TOUCH_PAD4_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD4_HOLD_W::new(self, 4)
     }
     #[doc = "Bit 5 - hold rtc pad-5"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad5_hold(&mut self) -> TOUCH_PAD5_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD5_HOLD_W::new(self, 5)
     }
     #[doc = "Bit 6 - hold rtc pad-6"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad6_hold(&mut self) -> TOUCH_PAD6_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD6_HOLD_W::new(self, 6)
     }
     #[doc = "Bit 7 - hold rtc pad-7"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad7_hold(&mut self) -> TOUCH_PAD7_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD7_HOLD_W::new(self, 7)
     }
     #[doc = "Bit 8 - hold rtc pad-8"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad8_hold(&mut self) -> TOUCH_PAD8_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD8_HOLD_W::new(self, 8)
     }
     #[doc = "Bit 9 - hold rtc pad-9"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad9_hold(&mut self) -> TOUCH_PAD9_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD9_HOLD_W::new(self, 9)
     }
     #[doc = "Bit 10 - hold rtc pad-10"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad10_hold(&mut self) -> TOUCH_PAD10_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD10_HOLD_W::new(self, 10)
     }
     #[doc = "Bit 11 - hold rtc pad-11"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad11_hold(&mut self) -> TOUCH_PAD11_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD11_HOLD_W::new(self, 11)
     }
     #[doc = "Bit 12 - hold rtc pad-12"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad12_hold(&mut self) -> TOUCH_PAD12_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD12_HOLD_W::new(self, 12)
     }
     #[doc = "Bit 13 - hold rtc pad-13"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad13_hold(&mut self) -> TOUCH_PAD13_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD13_HOLD_W::new(self, 13)
     }
     #[doc = "Bit 14 - hold rtc pad-14"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad14_hold(&mut self) -> TOUCH_PAD14_HOLD_W<PAD_HOLD_SPEC> {
         TOUCH_PAD14_HOLD_W::new(self, 14)
     }
     #[doc = "Bit 15 - hold rtc pad-15"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_hold(&mut self) -> X32P_HOLD_W<PAD_HOLD_SPEC> {
         X32P_HOLD_W::new(self, 15)
     }
     #[doc = "Bit 16 - hold rtc pad-16"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_hold(&mut self) -> X32N_HOLD_W<PAD_HOLD_SPEC> {
         X32N_HOLD_W::new(self, 16)
     }
     #[doc = "Bit 17 - hold rtc pad-17"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_hold(&mut self) -> PDAC1_HOLD_W<PAD_HOLD_SPEC> {
         PDAC1_HOLD_W::new(self, 17)
     }
     #[doc = "Bit 18 - hold rtc pad-18"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_hold(&mut self) -> PDAC2_HOLD_W<PAD_HOLD_SPEC> {
         PDAC2_HOLD_W::new(self, 18)
     }
     #[doc = "Bit 19 - hold rtc pad-19"]
     #[inline(always)]
-    #[must_use]
     pub fn pad19_hold(&mut self) -> PAD19_HOLD_W<PAD_HOLD_SPEC> {
         PAD19_HOLD_W::new(self, 19)
     }
     #[doc = "Bit 20 - hold rtc pad-20"]
     #[inline(always)]
-    #[must_use]
     pub fn pad20_hold(&mut self) -> PAD20_HOLD_W<PAD_HOLD_SPEC> {
         PAD20_HOLD_W::new(self, 20)
     }
     #[doc = "Bit 21 - hold rtc pad-21"]
     #[inline(always)]
-    #[must_use]
     pub fn pad21_hold(&mut self) -> PAD21_HOLD_W<PAD_HOLD_SPEC> {
         PAD21_HOLD_W::new(self, 21)
     }
diff --git a/esp32s3/src/rtc_cntl/pg_ctrl.rs b/esp32s3/src/rtc_cntl/pg_ctrl.rs
index e9f96d40fc..1db7cc1123 100644
--- a/esp32s3/src/rtc_cntl/pg_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/pg_ctrl.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 26:27 - GLITCH_DSENSE"]
     #[inline(always)]
-    #[must_use]
     pub fn power_glitch_dsense(&mut self) -> POWER_GLITCH_DSENSE_W<PG_CTRL_SPEC> {
         POWER_GLITCH_DSENSE_W::new(self, 26)
     }
     #[doc = "Bit 28 - force power glitch disable"]
     #[inline(always)]
-    #[must_use]
     pub fn power_glitch_force_pd(&mut self) -> POWER_GLITCH_FORCE_PD_W<PG_CTRL_SPEC> {
         POWER_GLITCH_FORCE_PD_W::new(self, 28)
     }
     #[doc = "Bit 29 - force power glitch enable"]
     #[inline(always)]
-    #[must_use]
     pub fn power_glitch_force_pu(&mut self) -> POWER_GLITCH_FORCE_PU_W<PG_CTRL_SPEC> {
         POWER_GLITCH_FORCE_PU_W::new(self, 29)
     }
     #[doc = "Bit 30 - select use analog fib signal"]
     #[inline(always)]
-    #[must_use]
     pub fn power_glitch_efuse_sel(&mut self) -> POWER_GLITCH_EFUSE_SEL_W<PG_CTRL_SPEC> {
         POWER_GLITCH_EFUSE_SEL_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable power glitch"]
     #[inline(always)]
-    #[must_use]
     pub fn power_glitch_en(&mut self) -> POWER_GLITCH_EN_W<PG_CTRL_SPEC> {
         POWER_GLITCH_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/pwc.rs b/esp32s3/src/rtc_cntl/pwc.rs
index 02da71a223..9c139e649c 100644
--- a/esp32s3/src/rtc_cntl/pwc.rs
+++ b/esp32s3/src/rtc_cntl/pwc.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Fast RTC memory force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_noiso(&mut self) -> FASTMEM_FORCE_NOISO_W<PWC_SPEC> {
         FASTMEM_FORCE_NOISO_W::new(self, 0)
     }
     #[doc = "Bit 1 - Fast RTC memory force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_iso(&mut self) -> FASTMEM_FORCE_ISO_W<PWC_SPEC> {
         FASTMEM_FORCE_ISO_W::new(self, 1)
     }
     #[doc = "Bit 2 - RTC memory force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_noiso(&mut self) -> SLOWMEM_FORCE_NOISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_NOISO_W::new(self, 2)
     }
     #[doc = "Bit 3 - RTC memory force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_iso(&mut self) -> SLOWMEM_FORCE_ISO_W<PWC_SPEC> {
         SLOWMEM_FORCE_ISO_W::new(self, 3)
     }
     #[doc = "Bit 4 - rtc_peri force ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn force_iso(&mut self) -> FORCE_ISO_W<PWC_SPEC> {
         FORCE_ISO_W::new(self, 4)
     }
     #[doc = "Bit 5 - rtc_peri force no ISO"]
     #[inline(always)]
-    #[must_use]
     pub fn force_noiso(&mut self) -> FORCE_NOISO_W<PWC_SPEC> {
         FORCE_NOISO_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_folw_cpu(&mut self) -> FASTMEM_FOLW_CPU_W<PWC_SPEC> {
         FASTMEM_FOLW_CPU_W::new(self, 6)
     }
     #[doc = "Bit 7 - Fast RTC memory force PD"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpd(&mut self) -> FASTMEM_FORCE_LPD_W<PWC_SPEC> {
         FASTMEM_FORCE_LPD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Fast RTC memory force no PD"]
     #[inline(always)]
-    #[must_use]
     pub fn fastmem_force_lpu(&mut self) -> FASTMEM_FORCE_LPU_W<PWC_SPEC> {
         FASTMEM_FORCE_LPU_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_folw_cpu(&mut self) -> SLOWMEM_FOLW_CPU_W<PWC_SPEC> {
         SLOWMEM_FOLW_CPU_W::new(self, 9)
     }
     #[doc = "Bit 10 - RTC memory force PD"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpd(&mut self) -> SLOWMEM_FORCE_LPD_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPD_W::new(self, 10)
     }
     #[doc = "Bit 11 - RTC memory force no PD"]
     #[inline(always)]
-    #[must_use]
     pub fn slowmem_force_lpu(&mut self) -> SLOWMEM_FORCE_LPU_W<PWC_SPEC> {
         SLOWMEM_FORCE_LPU_W::new(self, 11)
     }
     #[doc = "Bit 18 - rtc_peri force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pd(&mut self) -> FORCE_PD_W<PWC_SPEC> {
         FORCE_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - rtc_peri force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn force_pu(&mut self) -> FORCE_PU_W<PWC_SPEC> {
         FORCE_PU_W::new(self, 19)
     }
     #[doc = "Bit 20 - enable power down rtc_peri in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn pd_en(&mut self) -> PD_EN_W<PWC_SPEC> {
         PD_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - rtc pad force hold"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_force_hold(&mut self) -> PAD_FORCE_HOLD_W<PWC_SPEC> {
         PAD_FORCE_HOLD_W::new(self, 21)
     }
diff --git a/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs b/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
index bc0d95d622..fd666f75fb 100644
--- a/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
@@ -54,7 +54,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_drv_b_monitor(
         &mut self,
     ) -> REGULATOR_DRV_B_MONITOR_W<REGULATOR_DRV_CTRL_SPEC> {
@@ -62,19 +61,16 @@ impl W {
     }
     #[doc = "Bits 6:11 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_drv_b_slp(&mut self) -> REGULATOR_DRV_B_SLP_W<REGULATOR_DRV_CTRL_SPEC> {
         REGULATOR_DRV_B_SLP_W::new(self, 6)
     }
     #[doc = "Bits 12:19 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_vdd_drv_b_slp(&mut self) -> DG_VDD_DRV_B_SLP_W<REGULATOR_DRV_CTRL_SPEC> {
         DG_VDD_DRV_B_SLP_W::new(self, 12)
     }
     #[doc = "Bits 20:27 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_vdd_drv_b_monitor(&mut self) -> DG_VDD_DRV_B_MONITOR_W<REGULATOR_DRV_CTRL_SPEC> {
         DG_VDD_DRV_B_MONITOR_W::new(self, 20)
     }
diff --git a/esp32s3/src/rtc_cntl/reset_state.rs b/esp32s3/src/rtc_cntl/reset_state.rs
index e55d5b4755..b81047fabb 100644
--- a/esp32s3/src/rtc_cntl/reset_state.rs
+++ b/esp32s3/src/rtc_cntl/reset_state.rs
@@ -130,61 +130,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_stat_vector_sel(&mut self) -> APPCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         APPCPU_STAT_VECTOR_SEL_W::new(self, 12)
     }
     #[doc = "Bit 13 - PRO CPU state vector sel"]
     #[inline(always)]
-    #[must_use]
     pub fn procpu_stat_vector_sel(&mut self) -> PROCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
         PROCPU_STAT_VECTOR_SEL_W::new(self, 13)
     }
     #[doc = "Bit 16 - clear PRO CPU reset_flag"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_flag_procpu_clr(&mut self) -> RESET_FLAG_PROCPU_CLR_W<RESET_STATE_SPEC> {
         RESET_FLAG_PROCPU_CLR_W::new(self, 16)
     }
     #[doc = "Bit 17 - clear APP CPU reset flag"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_flag_appcpu_clr(&mut self) -> RESET_FLAG_APPCPU_CLR_W<RESET_STATE_SPEC> {
         RESET_FLAG_APPCPU_CLR_W::new(self, 17)
     }
     #[doc = "Bit 18 - APPCPU OcdHaltOnReset"]
     #[inline(always)]
-    #[must_use]
     pub fn appcpu_ocd_halt_on_reset(&mut self) -> APPCPU_OCD_HALT_ON_RESET_W<RESET_STATE_SPEC> {
         APPCPU_OCD_HALT_ON_RESET_W::new(self, 18)
     }
     #[doc = "Bit 19 - PROCPU OcdHaltOnReset"]
     #[inline(always)]
-    #[must_use]
     pub fn procpu_ocd_halt_on_reset(&mut self) -> PROCPU_OCD_HALT_ON_RESET_W<RESET_STATE_SPEC> {
         PROCPU_OCD_HALT_ON_RESET_W::new(self, 19)
     }
     #[doc = "Bit 22 - clear jtag reset flag"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_flag_jtag_procpu_clr(&mut self) -> RESET_FLAG_JTAG_PROCPU_CLR_W<RESET_STATE_SPEC> {
         RESET_FLAG_JTAG_PROCPU_CLR_W::new(self, 22)
     }
     #[doc = "Bit 23 - clear jtag reset flag"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_flag_jtag_appcpu_clr(&mut self) -> RESET_FLAG_JTAG_APPCPU_CLR_W<RESET_STATE_SPEC> {
         RESET_FLAG_JTAG_APPCPU_CLR_W::new(self, 23)
     }
     #[doc = "Bit 24 - bypass cpu1 dreset"]
     #[inline(always)]
-    #[must_use]
     pub fn app_dreset_mask(&mut self) -> APP_DRESET_MASK_W<RESET_STATE_SPEC> {
         APP_DRESET_MASK_W::new(self, 24)
     }
     #[doc = "Bit 25 - bypass cpu0 dreset"]
     #[inline(always)]
-    #[must_use]
     pub fn pro_dreset_mask(&mut self) -> PRO_DRESET_MASK_W<RESET_STATE_SPEC> {
         PRO_DRESET_MASK_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_cntl/retention_ctrl.rs b/esp32s3/src/rtc_cntl/retention_ctrl.rs
index 5d94be73e9..2c66373f62 100644
--- a/esp32s3/src/rtc_cntl/retention_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/retention_ctrl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:13 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_tag_mode(&mut self) -> RETENTION_TAG_MODE_W<RETENTION_CTRL_SPEC> {
         RETENTION_TAG_MODE_W::new(self, 10)
     }
     #[doc = "Bits 14:15 - congfigure retention target cpu and/or tag"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_target(&mut self) -> RETENTION_TARGET_W<RETENTION_CTRL_SPEC> {
         RETENTION_TARGET_W::new(self, 14)
     }
     #[doc = "Bit 16 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_clk_sel(&mut self) -> RETENTION_CLK_SEL_W<RETENTION_CTRL_SPEC> {
         RETENTION_CLK_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:19 - wait retention done cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_done_wait(&mut self) -> RETENTION_DONE_WAIT_W<RETENTION_CTRL_SPEC> {
         RETENTION_DONE_WAIT_W::new(self, 17)
     }
     #[doc = "Bits 20:23 - wait clk off cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_clkoff_wait(&mut self) -> RETENTION_CLKOFF_WAIT_W<RETENTION_CTRL_SPEC> {
         RETENTION_CLKOFF_WAIT_W::new(self, 20)
     }
     #[doc = "Bit 24 - enable retention"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_en(&mut self) -> RETENTION_EN_W<RETENTION_CTRL_SPEC> {
         RETENTION_EN_W::new(self, 24)
     }
     #[doc = "Bits 25:31 - wait cycles for rention operation"]
     #[inline(always)]
-    #[must_use]
     pub fn retention_wait(&mut self) -> RETENTION_WAIT_W<RETENTION_CTRL_SPEC> {
         RETENTION_WAIT_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_cntl/rtc.rs b/esp32s3/src/rtc_cntl/rtc.rs
index fb1de8c17a..38a22cfbad 100644
--- a/esp32s3/src/rtc_cntl/rtc.rs
+++ b/esp32s3/src/rtc_cntl/rtc.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - enable dig regulator cali"]
     #[inline(always)]
-    #[must_use]
     pub fn dig_reg_cal_en(&mut self) -> DIG_REG_CAL_EN_W<RTC_SPEC> {
         DIG_REG_CAL_EN_W::new(self, 7)
     }
     #[doc = "Bits 14:21 - SCK_DCAP"]
     #[inline(always)]
-    #[must_use]
     pub fn sck_dcap(&mut self) -> SCK_DCAP_W<RTC_SPEC> {
         SCK_DCAP_W::new(self, 14)
     }
     #[doc = "Bit 28 - RTC_DBOOST force power down"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pd(&mut self) -> DBOOST_FORCE_PD_W<RTC_SPEC> {
         DBOOST_FORCE_PD_W::new(self, 28)
     }
     #[doc = "Bit 29 - RTC_DBOOST force power up"]
     #[inline(always)]
-    #[must_use]
     pub fn dboost_force_pu(&mut self) -> DBOOST_FORCE_PU_W<RTC_SPEC> {
         DBOOST_FORCE_PU_W::new(self, 29)
     }
     #[doc = "Bit 30 - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_force_pd(&mut self) -> REGULATOR_FORCE_PD_W<RTC_SPEC> {
         REGULATOR_FORCE_PD_W::new(self, 30)
     }
     #[doc = "Bit 31 - RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
     #[inline(always)]
-    #[must_use]
     pub fn regulator_force_pu(&mut self) -> REGULATOR_FORCE_PU_W<RTC_SPEC> {
         REGULATOR_FORCE_PU_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/sdio_act_conf.rs b/esp32s3/src/rtc_cntl/sdio_act_conf.rs
index a4621c34b1..7a23dace27 100644
--- a/esp32s3/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32s3/src/rtc_cntl/sdio_act_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 22:31 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W<SDIO_ACT_CONF_SPEC> {
         SDIO_ACT_DNUM_W::new(self, 22)
     }
diff --git a/esp32s3/src/rtc_cntl/sdio_conf.rs b/esp32s3/src/rtc_cntl/sdio_conf.rs
index add5b385d4..a94f44bd1b 100644
--- a/esp32s3/src/rtc_cntl/sdio_conf.rs
+++ b/esp32s3/src/rtc_cntl/sdio_conf.rs
@@ -172,91 +172,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_timer_target(&mut self) -> SDIO_TIMER_TARGET_W<SDIO_CONF_SPEC> {
         SDIO_TIMER_TARGET_W::new(self, 0)
     }
     #[doc = "Bits 9:10 - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dthdrv(&mut self) -> SDIO_DTHDRV_W<SDIO_CONF_SPEC> {
         SDIO_DTHDRV_W::new(self, 9)
     }
     #[doc = "Bits 11:12 - ability to prevent LDO from overshoot"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dcap(&mut self) -> SDIO_DCAP_W<SDIO_CONF_SPEC> {
         SDIO_DCAP_W::new(self, 11)
     }
     #[doc = "Bits 13:14 - add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_initi(&mut self) -> SDIO_INITI_W<SDIO_CONF_SPEC> {
         SDIO_INITI_W::new(self, 13)
     }
     #[doc = "Bit 15 - 0 to set init\\[1:0\\]=0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_en_initi(&mut self) -> SDIO_EN_INITI_W<SDIO_CONF_SPEC> {
         SDIO_EN_INITI_W::new(self, 15)
     }
     #[doc = "Bits 16:18 - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_dcurlim(&mut self) -> SDIO_DCURLIM_W<SDIO_CONF_SPEC> {
         SDIO_DCURLIM_W::new(self, 16)
     }
     #[doc = "Bit 19 - select current limit mode"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_modecurlim(&mut self) -> SDIO_MODECURLIM_W<SDIO_CONF_SPEC> {
         SDIO_MODECURLIM_W::new(self, 19)
     }
     #[doc = "Bit 20 - enable current limit"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_encurlim(&mut self) -> SDIO_ENCURLIM_W<SDIO_CONF_SPEC> {
         SDIO_ENCURLIM_W::new(self, 20)
     }
     #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_reg_pd_en(&mut self) -> SDIO_REG_PD_EN_W<SDIO_CONF_SPEC> {
         SDIO_REG_PD_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - 1: use SW option to control SDIO_REG, 0: use state machine"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_force(&mut self) -> SDIO_FORCE_W<SDIO_CONF_SPEC> {
         SDIO_FORCE_W::new(self, 22)
     }
     #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<SDIO_CONF_SPEC> {
         SDIO_TIEH_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<SDIO_CONF_SPEC> {
         DREFL_SDIO_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<SDIO_CONF_SPEC> {
         DREFM_SDIO_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<SDIO_CONF_SPEC> {
         DREFH_SDIO_W::new(self, 29)
     }
     #[doc = "Bit 31 - power on flash regulator"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sdio(&mut self) -> XPD_SDIO_W<SDIO_CONF_SPEC> {
         XPD_SDIO_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/slow_clk_conf.rs b/esp32s3/src/rtc_cntl/slow_clk_conf.rs
index 6588aa4666..dcd3b53a88 100644
--- a/esp32s3/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32s3/src/rtc_cntl/slow_clk_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<SLOW_CLK_CONF_SPEC> {
         ANA_CLK_DIV_VLD_W::new(self, 22)
     }
     #[doc = "Bits 23:30 - rtc clk div"]
     #[inline(always)]
-    #[must_use]
     pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<SLOW_CLK_CONF_SPEC> {
         ANA_CLK_DIV_W::new(self, 23)
     }
     #[doc = "Bit 31 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<SLOW_CLK_CONF_SPEC> {
         SLOW_CLK_NEXT_EDGE_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/slp_reject_conf.rs b/esp32s3/src/rtc_cntl/slp_reject_conf.rs
index cc51ec6daf..f68024e2d0 100644
--- a/esp32s3/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32s3/src/rtc_cntl/slp_reject_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 12:29 - sleep reject enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_reject_ena(&mut self) -> SLEEP_REJECT_ENA_W<SLP_REJECT_CONF_SPEC> {
         SLEEP_REJECT_ENA_W::new(self, 12)
     }
     #[doc = "Bit 30 - enable reject for light sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn light_slp_reject_en(&mut self) -> LIGHT_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         LIGHT_SLP_REJECT_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable reject for deep sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn deep_slp_reject_en(&mut self) -> DEEP_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
         DEEP_SLP_REJECT_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/slp_timer0.rs b/esp32s3/src/rtc_cntl/slp_timer0.rs
index f65dbb1829..1c5a821cd5 100644
--- a/esp32s3/src/rtc_cntl/slp_timer0.rs
+++ b/esp32s3/src/rtc_cntl/slp_timer0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_lo(&mut self) -> SLP_VAL_LO_W<SLP_TIMER0_SPEC> {
         SLP_VAL_LO_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/slp_timer1.rs b/esp32s3/src/rtc_cntl/slp_timer1.rs
index bae8df9de7..cd675e829a 100644
--- a/esp32s3/src/rtc_cntl/slp_timer1.rs
+++ b/esp32s3/src/rtc_cntl/slp_timer1.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<SLP_TIMER1_SPEC> {
         SLP_VAL_HI_W::new(self, 0)
     }
     #[doc = "Bit 16 - timer alarm enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<SLP_TIMER1_SPEC> {
         MAIN_TIMER_ALARM_EN_W::new(self, 16)
     }
diff --git a/esp32s3/src/rtc_cntl/state0.rs b/esp32s3/src/rtc_cntl/state0.rs
index a6ed6c6a47..085f9a86c3 100644
--- a/esp32s3/src/rtc_cntl/state0.rs
+++ b/esp32s3/src/rtc_cntl/state0.rs
@@ -66,37 +66,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - rtc software interrupt to main cpu"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_cpu_int(&mut self) -> SW_CPU_INT_W<STATE0_SPEC> {
         SW_CPU_INT_W::new(self, 0)
     }
     #[doc = "Bit 1 - clear rtc sleep reject cause"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject_cause_clr(&mut self) -> SLP_REJECT_CAUSE_CLR_W<STATE0_SPEC> {
         SLP_REJECT_CAUSE_CLR_W::new(self, 1)
     }
     #[doc = "Bit 22 - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
     #[inline(always)]
-    #[must_use]
     pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<STATE0_SPEC> {
         APB2RTC_BRIDGE_SEL_W::new(self, 22)
     }
     #[doc = "Bit 29 - leep wakeup bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<STATE0_SPEC> {
         SLP_WAKEUP_W::new(self, 29)
     }
     #[doc = "Bit 30 - leep reject bit"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_reject(&mut self) -> SLP_REJECT_W<STATE0_SPEC> {
         SLP_REJECT_W::new(self, 30)
     }
     #[doc = "Bit 31 - sleep enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn sleep_en(&mut self) -> SLEEP_EN_W<STATE0_SPEC> {
         SLEEP_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/store0.rs b/esp32s3/src/rtc_cntl/store0.rs
index b0d717b8bd..b2da923499 100644
--- a/esp32s3/src/rtc_cntl/store0.rs
+++ b/esp32s3/src/rtc_cntl/store0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch0(&mut self) -> SCRATCH0_W<STORE0_SPEC> {
         SCRATCH0_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store1.rs b/esp32s3/src/rtc_cntl/store1.rs
index 0638e53630..7a8c3f811b 100644
--- a/esp32s3/src/rtc_cntl/store1.rs
+++ b/esp32s3/src/rtc_cntl/store1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch1(&mut self) -> SCRATCH1_W<STORE1_SPEC> {
         SCRATCH1_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store2.rs b/esp32s3/src/rtc_cntl/store2.rs
index 9eed854931..850b2d00a6 100644
--- a/esp32s3/src/rtc_cntl/store2.rs
+++ b/esp32s3/src/rtc_cntl/store2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch2(&mut self) -> SCRATCH2_W<STORE2_SPEC> {
         SCRATCH2_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store3.rs b/esp32s3/src/rtc_cntl/store3.rs
index 0752e41386..dae47119b4 100644
--- a/esp32s3/src/rtc_cntl/store3.rs
+++ b/esp32s3/src/rtc_cntl/store3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch3(&mut self) -> SCRATCH3_W<STORE3_SPEC> {
         SCRATCH3_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store4.rs b/esp32s3/src/rtc_cntl/store4.rs
index 7fefa7880d..0f43ae912a 100644
--- a/esp32s3/src/rtc_cntl/store4.rs
+++ b/esp32s3/src/rtc_cntl/store4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch4(&mut self) -> SCRATCH4_W<STORE4_SPEC> {
         SCRATCH4_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store5.rs b/esp32s3/src/rtc_cntl/store5.rs
index a753f76918..d1feb9ab84 100644
--- a/esp32s3/src/rtc_cntl/store5.rs
+++ b/esp32s3/src/rtc_cntl/store5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch5(&mut self) -> SCRATCH5_W<STORE5_SPEC> {
         SCRATCH5_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store6.rs b/esp32s3/src/rtc_cntl/store6.rs
index 7654b9c792..6070a2f378 100644
--- a/esp32s3/src/rtc_cntl/store6.rs
+++ b/esp32s3/src/rtc_cntl/store6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch6(&mut self) -> SCRATCH6_W<STORE6_SPEC> {
         SCRATCH6_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/store7.rs b/esp32s3/src/rtc_cntl/store7.rs
index f053ac90d2..f33b081cf0 100644
--- a/esp32s3/src/rtc_cntl/store7.rs
+++ b/esp32s3/src/rtc_cntl/store7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch7(&mut self) -> SCRATCH7_W<STORE7_SPEC> {
         SCRATCH7_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/sw_cpu_stall.rs b/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
index bc9ad000df..b82c58e9ff 100644
--- a/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_appcpu_c1(&mut self) -> SW_STALL_APPCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_APPCPU_C1_W::new(self, 20)
     }
     #[doc = "Bits 26:31 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_stall_procpu_c1(&mut self) -> SW_STALL_PROCPU_C1_W<SW_CPU_STALL_SPEC> {
         SW_STALL_PROCPU_C1_W::new(self, 26)
     }
diff --git a/esp32s3/src/rtc_cntl/swd_conf.rs b/esp32s3/src/rtc_cntl/swd_conf.rs
index 3646c7d0c0..9253cac530 100644
--- a/esp32s3/src/rtc_cntl/swd_conf.rs
+++ b/esp32s3/src/rtc_cntl/swd_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - bypass super watch dog reset"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_bypass_rst(&mut self) -> SWD_BYPASS_RST_W<SWD_CONF_SPEC> {
         SWD_BYPASS_RST_W::new(self, 17)
     }
     #[doc = "Bits 18:27 - adjust signal width send to swd"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_signal_width(&mut self) -> SWD_SIGNAL_WIDTH_W<SWD_CONF_SPEC> {
         SWD_SIGNAL_WIDTH_W::new(self, 18)
     }
     #[doc = "Bit 28 - reset swd reset flag"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_rst_flag_clr(&mut self) -> SWD_RST_FLAG_CLR_W<SWD_CONF_SPEC> {
         SWD_RST_FLAG_CLR_W::new(self, 28)
     }
     #[doc = "Bit 29 - Sw feed swd"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_feed(&mut self) -> SWD_FEED_W<SWD_CONF_SPEC> {
         SWD_FEED_W::new(self, 29)
     }
     #[doc = "Bit 30 - disabel SWD"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_disable(&mut self) -> SWD_DISABLE_W<SWD_CONF_SPEC> {
         SWD_DISABLE_W::new(self, 30)
     }
     #[doc = "Bit 31 - automatically feed swd when int comes"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_auto_feed_en(&mut self) -> SWD_AUTO_FEED_EN_W<SWD_CONF_SPEC> {
         SWD_AUTO_FEED_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/swd_wprotect.rs b/esp32s3/src/rtc_cntl/swd_wprotect.rs
index 2e3f80eb4b..f94ca2cb1c 100644
--- a/esp32s3/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32s3/src/rtc_cntl/swd_wprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - super watch dog key"]
     #[inline(always)]
-    #[must_use]
     pub fn swd_wkey(&mut self) -> SWD_WKEY_W<SWD_WPROTECT_SPEC> {
         SWD_WKEY_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/time_update.rs b/esp32s3/src/rtc_cntl/time_update.rs
index 79a1dfddf1..99de4e5b2b 100644
--- a/esp32s3/src/rtc_cntl/time_update.rs
+++ b/esp32s3/src/rtc_cntl/time_update.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 27 - Enable to record system stall time"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sys_stall(&mut self) -> TIMER_SYS_STALL_W<TIME_UPDATE_SPEC> {
         TIMER_SYS_STALL_W::new(self, 27)
     }
     #[doc = "Bit 28 - Enable to record 40M XTAL OFF time"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_xtl_off(&mut self) -> TIMER_XTL_OFF_W<TIME_UPDATE_SPEC> {
         TIMER_XTL_OFF_W::new(self, 28)
     }
     #[doc = "Bit 29 - enable to record system reset time"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_sys_rst(&mut self) -> TIMER_SYS_RST_W<TIME_UPDATE_SPEC> {
         TIMER_SYS_RST_W::new(self, 29)
     }
     #[doc = "Bit 31 - Set 1: to update register with RTC timer"]
     #[inline(always)]
-    #[must_use]
     pub fn time_update(&mut self) -> TIME_UPDATE_W<TIME_UPDATE_SPEC> {
         TIME_UPDATE_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/timer1.rs b/esp32s3/src/rtc_cntl/timer1.rs
index b3bc897ac9..7cc48f52e4 100644
--- a/esp32s3/src/rtc_cntl/timer1.rs
+++ b/esp32s3/src/rtc_cntl/timer1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<TIMER1_SPEC> {
         CPU_STALL_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<TIMER1_SPEC> {
         CPU_STALL_WAIT_W::new(self, 1)
     }
     #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<TIMER1_SPEC> {
         CK8M_WAIT_W::new(self, 6)
     }
     #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<TIMER1_SPEC> {
         XTL_BUF_WAIT_W::new(self, 14)
     }
     #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<TIMER1_SPEC> {
         PLL_BUF_WAIT_W::new(self, 24)
     }
diff --git a/esp32s3/src/rtc_cntl/timer2.rs b/esp32s3/src/rtc_cntl/timer2.rs
index 0474cec49c..65158bf83e 100644
--- a/esp32s3/src/rtc_cntl/timer2.rs
+++ b/esp32s3/src/rtc_cntl/timer2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
     #[inline(always)]
-    #[must_use]
     pub fn ulpcp_touch_start_wait(&mut self) -> ULPCP_TOUCH_START_WAIT_W<TIMER2_SPEC> {
         ULPCP_TOUCH_START_WAIT_W::new(self, 15)
     }
     #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
     #[inline(always)]
-    #[must_use]
     pub fn min_time_ck8m_off(&mut self) -> MIN_TIME_CK8M_OFF_W<TIMER2_SPEC> {
         MIN_TIME_CK8M_OFF_W::new(self, 24)
     }
diff --git a/esp32s3/src/rtc_cntl/timer3.rs b/esp32s3/src/rtc_cntl/timer3.rs
index 97b98a756d..5345e4030a 100644
--- a/esp32s3/src/rtc_cntl/timer3.rs
+++ b/esp32s3/src/rtc_cntl/timer3.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_wait_timer(&mut self) -> WIFI_WAIT_TIMER_W<TIMER3_SPEC> {
         WIFI_WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn wifi_powerup_timer(&mut self) -> WIFI_POWERUP_TIMER_W<TIMER3_SPEC> {
         WIFI_POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_wait_timer(&mut self) -> BT_WAIT_TIMER_W<TIMER3_SPEC> {
         BT_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_powerup_timer(&mut self) -> BT_POWERUP_TIMER_W<TIMER3_SPEC> {
         BT_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_cntl/timer4.rs b/esp32s3/src/rtc_cntl/timer4.rs
index 942fb4727c..a9e3eda5a1 100644
--- a/esp32s3/src/rtc_cntl/timer4.rs
+++ b/esp32s3/src/rtc_cntl/timer4.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn wait_timer(&mut self) -> WAIT_TIMER_W<TIMER4_SPEC> {
         WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn powerup_timer(&mut self) -> POWERUP_TIMER_W<TIMER4_SPEC> {
         POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_wait_timer(&mut self) -> DG_WRAP_WAIT_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_wrap_powerup_timer(&mut self) -> DG_WRAP_POWERUP_TIMER_W<TIMER4_SPEC> {
         DG_WRAP_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_cntl/timer5.rs b/esp32s3/src/rtc_cntl/timer5.rs
index f845b52ac2..02cc578e3a 100644
--- a/esp32s3/src/rtc_cntl/timer5.rs
+++ b/esp32s3/src/rtc_cntl/timer5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
     #[inline(always)]
-    #[must_use]
     pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<TIMER5_SPEC> {
         MIN_SLP_VAL_W::new(self, 8)
     }
diff --git a/esp32s3/src/rtc_cntl/timer6.rs b/esp32s3/src/rtc_cntl/timer6.rs
index a413617021..2e36ef6857 100644
--- a/esp32s3/src/rtc_cntl/timer6.rs
+++ b/esp32s3/src/rtc_cntl/timer6.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_wait_timer(&mut self) -> CPU_TOP_WAIT_TIMER_W<TIMER6_SPEC> {
         CPU_TOP_WAIT_TIMER_W::new(self, 0)
     }
     #[doc = "Bits 9:15 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_top_powerup_timer(&mut self) -> CPU_TOP_POWERUP_TIMER_W<TIMER6_SPEC> {
         CPU_TOP_POWERUP_TIMER_W::new(self, 9)
     }
     #[doc = "Bits 16:24 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_wait_timer(&mut self) -> DG_PERI_WAIT_TIMER_W<TIMER6_SPEC> {
         DG_PERI_WAIT_TIMER_W::new(self, 16)
     }
     #[doc = "Bits 25:31 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn dg_peri_powerup_timer(&mut self) -> DG_PERI_POWERUP_TIMER_W<TIMER6_SPEC> {
         DG_PERI_POWERUP_TIMER_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_approach.rs b/esp32s3/src/rtc_cntl/touch_approach.rs
index 6e7230fc4b..3be008fb95 100644
--- a/esp32s3/src/rtc_cntl/touch_approach.rs
+++ b/esp32s3/src/rtc_cntl/touch_approach.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 23 - clear touch slp channel"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_channel_clr(&mut self) -> TOUCH_SLP_CHANNEL_CLR_W<TOUCH_APPROACH_SPEC> {
         TOUCH_SLP_CHANNEL_CLR_W::new(self, 23)
     }
     #[doc = "Bits 24:31 - approach pads total meas times"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_approach_meas_time(&mut self) -> TOUCH_APPROACH_MEAS_TIME_W<TOUCH_APPROACH_SPEC> {
         TOUCH_APPROACH_MEAS_TIME_W::new(self, 24)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_ctrl1.rs b/esp32s3/src/rtc_cntl/touch_ctrl1.rs
index b8d45d3f42..5a2c4f86fd 100644
--- a/esp32s3/src/rtc_cntl/touch_ctrl1.rs
+++ b/esp32s3/src/rtc_cntl/touch_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - sleep cycles for timer"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W<TOUCH_CTRL1_SPEC> {
         TOUCH_SLEEP_CYCLES_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - the meas length (in 8MHz)"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_meas_num(&mut self) -> TOUCH_MEAS_NUM_W<TOUCH_CTRL1_SPEC> {
         TOUCH_MEAS_NUM_W::new(self, 16)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_ctrl2.rs b/esp32s3/src/rtc_cntl/touch_ctrl2.rs
index 8477053011..a8aab7b7aa 100644
--- a/esp32s3/src/rtc_cntl/touch_ctrl2.rs
+++ b/esp32s3/src/rtc_cntl/touch_ctrl2.rs
@@ -30,9 +30,9 @@ pub type TOUCH_DBIAS_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type TOUCH_SLP_TIMER_EN_R = crate::BitReader;
 #[doc = "Field `TOUCH_SLP_TIMER_EN` writer - touch timer enable bit"]
 pub type TOUCH_SLP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `TOUCH_START_FSM_EN` reader - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm"]
+#[doc = "Field `TOUCH_START_FSM_EN` reader - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
 pub type TOUCH_START_FSM_EN_R = crate::BitReader;
-#[doc = "Field `TOUCH_START_FSM_EN` writer - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm"]
+#[doc = "Field `TOUCH_START_FSM_EN` writer - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
 pub type TOUCH_START_FSM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `TOUCH_START_EN` reader - 1: start touch fsm"]
 pub type TOUCH_START_EN_R = crate::BitReader;
@@ -102,7 +102,7 @@ impl R {
     pub fn touch_slp_timer_en(&self) -> TOUCH_SLP_TIMER_EN_R {
         TOUCH_SLP_TIMER_EN_R::new(((self.bits >> 13) & 1) != 0)
     }
-    #[doc = "Bit 14 - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm"]
+    #[doc = "Bit 14 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
     #[inline(always)]
     pub fn touch_start_fsm_en(&self) -> TOUCH_START_FSM_EN_R {
         TOUCH_START_FSM_EN_R::new(((self.bits >> 14) & 1) != 0)
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 2:3 - TOUCH_DRANGE"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drange(&mut self) -> TOUCH_DRANGE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DRANGE_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - TOUCH_DREFL"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefl(&mut self) -> TOUCH_DREFL_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DREFL_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - TOUCH_DREFH"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_drefh(&mut self) -> TOUCH_DREFH_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DREFH_W::new(self, 6)
     }
     #[doc = "Bit 8 - TOUCH_XPD_BIAS"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_bias(&mut self) -> TOUCH_XPD_BIAS_W<TOUCH_CTRL2_SPEC> {
         TOUCH_XPD_BIAS_W::new(self, 8)
     }
     #[doc = "Bits 9:11 - TOUCH pad0 reference cap"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_refc(&mut self) -> TOUCH_REFC_W<TOUCH_CTRL2_SPEC> {
         TOUCH_REFC_W::new(self, 9)
     }
     #[doc = "Bit 12 - 1:use self bias 0:use bandgap bias"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_dbias(&mut self) -> TOUCH_DBIAS_W<TOUCH_CTRL2_SPEC> {
         TOUCH_DBIAS_W::new(self, 12)
     }
     #[doc = "Bit 13 - touch timer enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_timer_en(&mut self) -> TOUCH_SLP_TIMER_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_SLP_TIMER_EN_W::new(self, 13)
     }
-    #[doc = "Bit 14 - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm"]
+    #[doc = "Bit 14 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_fsm_en(&mut self) -> TOUCH_START_FSM_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_FSM_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: start touch fsm"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_en(&mut self) -> TOUCH_START_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: to start touch fsm by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_start_force(&mut self) -> TOUCH_START_FORCE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_START_FORCE_W::new(self, 16)
     }
     #[doc = "Bits 17:24 - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_xpd_wait(&mut self) -> TOUCH_XPD_WAIT_W<TOUCH_CTRL2_SPEC> {
         TOUCH_XPD_WAIT_W::new(self, 17)
     }
     #[doc = "Bits 25:26 - when a touch pad is active sleep cycle could be divided by this number"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_cyc_div(&mut self) -> TOUCH_SLP_CYC_DIV_W<TOUCH_CTRL2_SPEC> {
         TOUCH_SLP_CYC_DIV_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - force touch timer done"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timer_force_done(&mut self) -> TOUCH_TIMER_FORCE_DONE_W<TOUCH_CTRL2_SPEC> {
         TOUCH_TIMER_FORCE_DONE_W::new(self, 27)
     }
     #[doc = "Bit 29 - reset upgrade touch"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_reset(&mut self) -> TOUCH_RESET_W<TOUCH_CTRL2_SPEC> {
         TOUCH_RESET_W::new(self, 29)
     }
     #[doc = "Bit 30 - touch clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_clk_fo(&mut self) -> TOUCH_CLK_FO_W<TOUCH_CTRL2_SPEC> {
         TOUCH_CLK_FO_W::new(self, 30)
     }
     #[doc = "Bit 31 - touch clock enable"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_clkgate_en(&mut self) -> TOUCH_CLKGATE_EN_W<TOUCH_CTRL2_SPEC> {
         TOUCH_CLKGATE_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_dac.rs b/esp32s3/src/rtc_cntl/touch_dac.rs
index 3f62bd19b4..72ee5fd923 100644
--- a/esp32s3/src/rtc_cntl/touch_dac.rs
+++ b/esp32s3/src/rtc_cntl/touch_dac.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 2:4 - configure touch pad dac9"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad9_dac(&mut self) -> TOUCH_PAD9_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD9_DAC_W::new(self, 2)
     }
     #[doc = "Bits 5:7 - configure touch pad dac8"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad8_dac(&mut self) -> TOUCH_PAD8_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD8_DAC_W::new(self, 5)
     }
     #[doc = "Bits 8:10 - configure touch pad dac7"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad7_dac(&mut self) -> TOUCH_PAD7_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD7_DAC_W::new(self, 8)
     }
     #[doc = "Bits 11:13 - configure touch pad dac6"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad6_dac(&mut self) -> TOUCH_PAD6_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD6_DAC_W::new(self, 11)
     }
     #[doc = "Bits 14:16 - configure touch pad dac5"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad5_dac(&mut self) -> TOUCH_PAD5_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD5_DAC_W::new(self, 14)
     }
     #[doc = "Bits 17:19 - configure touch pad dac4"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad4_dac(&mut self) -> TOUCH_PAD4_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD4_DAC_W::new(self, 17)
     }
     #[doc = "Bits 20:22 - configure touch pad dac3"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad3_dac(&mut self) -> TOUCH_PAD3_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD3_DAC_W::new(self, 20)
     }
     #[doc = "Bits 23:25 - configure touch pad dac2"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad2_dac(&mut self) -> TOUCH_PAD2_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD2_DAC_W::new(self, 23)
     }
     #[doc = "Bits 26:28 - configure touch pad dac1"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad1_dac(&mut self) -> TOUCH_PAD1_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD1_DAC_W::new(self, 26)
     }
     #[doc = "Bits 29:31 - configure touch pad dac0"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad0_dac(&mut self) -> TOUCH_PAD0_DAC_W<TOUCH_DAC_SPEC> {
         TOUCH_PAD0_DAC_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_dac1.rs b/esp32s3/src/rtc_cntl/touch_dac1.rs
index d95eec820f..7201396366 100644
--- a/esp32s3/src/rtc_cntl/touch_dac1.rs
+++ b/esp32s3/src/rtc_cntl/touch_dac1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 17:19 - configure touch pad dac14"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad14_dac(&mut self) -> TOUCH_PAD14_DAC_W<TOUCH_DAC1_SPEC> {
         TOUCH_PAD14_DAC_W::new(self, 17)
     }
     #[doc = "Bits 20:22 - configure touch pad dac13"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad13_dac(&mut self) -> TOUCH_PAD13_DAC_W<TOUCH_DAC1_SPEC> {
         TOUCH_PAD13_DAC_W::new(self, 20)
     }
     #[doc = "Bits 23:25 - configure touch pad dac12"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad12_dac(&mut self) -> TOUCH_PAD12_DAC_W<TOUCH_DAC1_SPEC> {
         TOUCH_PAD12_DAC_W::new(self, 23)
     }
     #[doc = "Bits 26:28 - configure touch pad dac11"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad11_dac(&mut self) -> TOUCH_PAD11_DAC_W<TOUCH_DAC1_SPEC> {
         TOUCH_PAD11_DAC_W::new(self, 26)
     }
     #[doc = "Bits 29:31 - configure touch pad dac10"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_pad10_dac(&mut self) -> TOUCH_PAD10_DAC_W<TOUCH_DAC1_SPEC> {
         TOUCH_PAD10_DAC_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs b/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
index ab366c7be3..e4bd4e8276 100644
--- a/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
@@ -127,7 +127,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 7 - bypass neg noise thres"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_bypass_neg_noise_thres(
         &mut self,
     ) -> TOUCH_BYPASS_NEG_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
@@ -135,7 +134,6 @@ impl W {
     }
     #[doc = "Bit 8 - bypaas noise thres"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_bypass_noise_thres(
         &mut self,
     ) -> TOUCH_BYPASS_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
@@ -143,55 +141,46 @@ impl W {
     }
     #[doc = "Bits 9:10 - smooth filter factor"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_smooth_lvl(&mut self) -> TOUCH_SMOOTH_LVL_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_SMOOTH_LVL_W::new(self, 9)
     }
     #[doc = "Bits 11:14 - touch jitter step"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_jitter_step(&mut self) -> TOUCH_JITTER_STEP_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_JITTER_STEP_W::new(self, 11)
     }
     #[doc = "Bits 15:18 - negative threshold counter limit"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_neg_noise_limit(&mut self) -> TOUCH_NEG_NOISE_LIMIT_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NEG_NOISE_LIMIT_W::new(self, 15)
     }
     #[doc = "Bits 19:20 - neg noise thres"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_neg_noise_thres(&mut self) -> TOUCH_NEG_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NEG_NOISE_THRES_W::new(self, 19)
     }
     #[doc = "Bits 21:22 - noise thres"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_noise_thres(&mut self) -> TOUCH_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_NOISE_THRES_W::new(self, 21)
     }
     #[doc = "Bits 23:24 - hysteresis"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_hysteresis(&mut self) -> TOUCH_HYSTERESIS_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_HYSTERESIS_W::new(self, 23)
     }
     #[doc = "Bits 25:27 - debounce counter"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_debounce(&mut self) -> TOUCH_DEBOUNCE_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_DEBOUNCE_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_filter_mode(&mut self) -> TOUCH_FILTER_MODE_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_FILTER_MODE_W::new(self, 28)
     }
     #[doc = "Bit 31 - touch filter enable"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_filter_en(&mut self) -> TOUCH_FILTER_EN_W<TOUCH_FILTER_CTRL_SPEC> {
         TOUCH_FILTER_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs b/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
index a646e5465a..5a10cf32de 100644
--- a/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
@@ -87,19 +87,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - De-noise resolution: 12/10/8/4 bit"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_denoise_res(&mut self) -> TOUCH_DENOISE_RES_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_DENOISE_RES_W::new(self, 0)
     }
     #[doc = "Bit 2 - touch pad0 will be used to de-noise"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_denoise_en(&mut self) -> TOUCH_DENOISE_EN_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_DENOISE_EN_W::new(self, 2)
     }
     #[doc = "Bit 8 - inactive touch pads connect to 1: gnd 0: HighZ"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_inactive_connection(
         &mut self,
     ) -> TOUCH_INACTIVE_CONNECTION_W<TOUCH_SCAN_CTRL_SPEC> {
@@ -107,25 +104,21 @@ impl W {
     }
     #[doc = "Bit 9 - touch pad14 will be used as shield"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_shield_pad_en(&mut self) -> TOUCH_SHIELD_PAD_EN_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_SHIELD_PAD_EN_W::new(self, 9)
     }
     #[doc = "Bits 10:24 - touch scan mode pad enable map"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_scan_pad_map(&mut self) -> TOUCH_SCAN_PAD_MAP_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_SCAN_PAD_MAP_W::new(self, 10)
     }
     #[doc = "Bits 25:27 - touch7 buffer driver strength"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_bufdrv(&mut self) -> TOUCH_BUFDRV_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_BUFDRV_W::new(self, 25)
     }
     #[doc = "Bits 28:31 - select out ring pad"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_out_ring(&mut self) -> TOUCH_OUT_RING_W<TOUCH_SCAN_CTRL_SPEC> {
         TOUCH_OUT_RING_W::new(self, 28)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_slp_thres.rs b/esp32s3/src/rtc_cntl/touch_slp_thres.rs
index 6e5e0a35f2..1acd1672a5 100644
--- a/esp32s3/src/rtc_cntl/touch_slp_thres.rs
+++ b/esp32s3/src/rtc_cntl/touch_slp_thres.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - the threshold for sleep touch pad"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_th(&mut self) -> TOUCH_SLP_TH_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_TH_W::new(self, 0)
     }
     #[doc = "Bit 26 - sleep pad approach function enable"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_approach_en(&mut self) -> TOUCH_SLP_APPROACH_EN_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_APPROACH_EN_W::new(self, 26)
     }
     #[doc = "Bits 27:31 - configure which pad as slp pad"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_slp_pad(&mut self) -> TOUCH_SLP_PAD_W<TOUCH_SLP_THRES_SPEC> {
         TOUCH_SLP_PAD_W::new(self, 27)
     }
diff --git a/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs b/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
index 3197b0f41e..d0e232a88a 100644
--- a/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - configure touch timerout time"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout_num(&mut self) -> TOUCH_TIMEOUT_NUM_W<TOUCH_TIMEOUT_CTRL_SPEC> {
         TOUCH_TIMEOUT_NUM_W::new(self, 0)
     }
     #[doc = "Bit 22 - enable touch timerout"]
     #[inline(always)]
-    #[must_use]
     pub fn touch_timeout_en(&mut self) -> TOUCH_TIMEOUT_EN_W<TOUCH_TIMEOUT_CTRL_SPEC> {
         TOUCH_TIMEOUT_EN_W::new(self, 22)
     }
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs b/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
index 5122431f03..4e0acef98f 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
@@ -76,43 +76,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_addr_init(&mut self) -> ULP_CP_MEM_ADDR_INIT_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_ADDR_INIT_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_addr_size(&mut self) -> ULP_CP_MEM_ADDR_SIZE_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_ADDR_SIZE_W::new(self, 11)
     }
     #[doc = "Bit 22 - No public"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_mem_offst_clr(&mut self) -> ULP_CP_MEM_OFFST_CLR_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_MEM_OFFST_CLR_W::new(self, 22)
     }
     #[doc = "Bit 28 - ulp coprocessor clk force on"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_clk_fo(&mut self) -> ULP_CP_CLK_FO_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_CLK_FO_W::new(self, 28)
     }
     #[doc = "Bit 29 - ulp coprocessor clk software reset"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_reset(&mut self) -> ULP_CP_RESET_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_RESET_W::new(self, 29)
     }
     #[doc = "Bit 30 - 1: ULP-coprocessor is started by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_force_start_top(&mut self) -> ULP_CP_FORCE_START_TOP_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_FORCE_START_TOP_W::new(self, 30)
     }
     #[doc = "Bit 31 - Write 1 to start ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_start_top(&mut self) -> ULP_CP_START_TOP_W<ULP_CP_CTRL_SPEC> {
         ULP_CP_START_TOP_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_timer.rs b/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
index 412d49721c..c2d6ae8aa2 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
@@ -46,25 +46,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_pc_init(&mut self) -> ULP_CP_PC_INIT_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_PC_INIT_W::new(self, 0)
     }
     #[doc = "Bit 29 - ULP-coprocessor wakeup by GPIO enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_gpio_wakeup_ena(&mut self) -> ULP_CP_GPIO_WAKEUP_ENA_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_GPIO_WAKEUP_ENA_W::new(self, 29)
     }
     #[doc = "Bit 30 - ULP-coprocessor wakeup by GPIO state clear"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_gpio_wakeup_clr(&mut self) -> ULP_CP_GPIO_WAKEUP_CLR_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_GPIO_WAKEUP_CLR_W::new(self, 30)
     }
     #[doc = "Bit 31 - ULP-coprocessor timer enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<ULP_CP_TIMER_SPEC> {
         ULP_CP_SLP_TIMER_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
index 088f7bd86f..bf26beac51 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
-    #[must_use]
     pub fn ulp_cp_timer_slp_cycle(&mut self) -> ULP_CP_TIMER_SLP_CYCLE_W<ULP_CP_TIMER_1_SPEC> {
         ULP_CP_TIMER_SLP_CYCLE_W::new(self, 8)
     }
diff --git a/esp32s3/src/rtc_cntl/usb_conf.rs b/esp32s3/src/rtc_cntl/usb_conf.rs
index 539a5533c9..fb7e1a45cb 100644
--- a/esp32s3/src/rtc_cntl/usb_conf.rs
+++ b/esp32s3/src/rtc_cntl/usb_conf.rs
@@ -204,115 +204,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - reg_usb_vrefh"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vrefh(&mut self) -> USB_VREFH_W<USB_CONF_SPEC> {
         USB_VREFH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - reg_usb_vrefl"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vrefl(&mut self) -> USB_VREFL_W<USB_CONF_SPEC> {
         USB_VREFL_W::new(self, 2)
     }
     #[doc = "Bit 4 - reg_usb_vref_override"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_vref_override(&mut self) -> USB_VREF_OVERRIDE_W<USB_CONF_SPEC> {
         USB_VREF_OVERRIDE_W::new(self, 4)
     }
     #[doc = "Bit 5 - reg_usb_pad_pull_override"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_pull_override(&mut self) -> USB_PAD_PULL_OVERRIDE_W<USB_CONF_SPEC> {
         USB_PAD_PULL_OVERRIDE_W::new(self, 5)
     }
     #[doc = "Bit 6 - reg_usb_dp_pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp_pullup(&mut self) -> USB_DP_PULLUP_W<USB_CONF_SPEC> {
         USB_DP_PULLUP_W::new(self, 6)
     }
     #[doc = "Bit 7 - reg_usb_dp_pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp_pulldown(&mut self) -> USB_DP_PULLDOWN_W<USB_CONF_SPEC> {
         USB_DP_PULLDOWN_W::new(self, 7)
     }
     #[doc = "Bit 8 - reg_usb_dm_pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm_pullup(&mut self) -> USB_DM_PULLUP_W<USB_CONF_SPEC> {
         USB_DM_PULLUP_W::new(self, 8)
     }
     #[doc = "Bit 9 - reg_usb_dm_pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm_pulldown(&mut self) -> USB_DM_PULLDOWN_W<USB_CONF_SPEC> {
         USB_DM_PULLDOWN_W::new(self, 9)
     }
     #[doc = "Bit 10 - reg_usb_pullup_value"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pullup_value(&mut self) -> USB_PULLUP_VALUE_W<USB_CONF_SPEC> {
         USB_PULLUP_VALUE_W::new(self, 10)
     }
     #[doc = "Bit 11 - reg_usb_pad_enable_override"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable_override(&mut self) -> USB_PAD_ENABLE_OVERRIDE_W<USB_CONF_SPEC> {
         USB_PAD_ENABLE_OVERRIDE_W::new(self, 11)
     }
     #[doc = "Bit 12 - reg_usb_pad_enable"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<USB_CONF_SPEC> {
         USB_PAD_ENABLE_W::new(self, 12)
     }
     #[doc = "Bit 13 - reg_usb_txm"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_txm(&mut self) -> USB_TXM_W<USB_CONF_SPEC> {
         USB_TXM_W::new(self, 13)
     }
     #[doc = "Bit 14 - reg_usb_txp"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_txp(&mut self) -> USB_TXP_W<USB_CONF_SPEC> {
         USB_TXP_W::new(self, 14)
     }
     #[doc = "Bit 15 - reg_usb_tx_en"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_tx_en(&mut self) -> USB_TX_EN_W<USB_CONF_SPEC> {
         USB_TX_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - reg_usb_tx_en_override"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_tx_en_override(&mut self) -> USB_TX_EN_OVERRIDE_W<USB_CONF_SPEC> {
         USB_TX_EN_OVERRIDE_W::new(self, 16)
     }
     #[doc = "Bit 17 - reg_usb_reset_disable"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_reset_disable(&mut self) -> USB_RESET_DISABLE_W<USB_CONF_SPEC> {
         USB_RESET_DISABLE_W::new(self, 17)
     }
     #[doc = "Bit 18 - reg_io_mux_reset_disable"]
     #[inline(always)]
-    #[must_use]
     pub fn io_mux_reset_disable(&mut self) -> IO_MUX_RESET_DISABLE_W<USB_CONF_SPEC> {
         IO_MUX_RESET_DISABLE_W::new(self, 18)
     }
     #[doc = "Bit 19 - reg_sw_usb_phy_sel"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_usb_phy_sel(&mut self) -> SW_USB_PHY_SEL_W<USB_CONF_SPEC> {
         SW_USB_PHY_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - reg_sw_hw_usb_phy_sel"]
     #[inline(always)]
-    #[must_use]
     pub fn sw_hw_usb_phy_sel(&mut self) -> SW_HW_USB_PHY_SEL_W<USB_CONF_SPEC> {
         SW_HW_USB_PHY_SEL_W::new(self, 20)
     }
diff --git a/esp32s3/src/rtc_cntl/wakeup_state.rs b/esp32s3/src/rtc_cntl/wakeup_state.rs
index cbe0ffb63f..76925fd758 100644
--- a/esp32s3/src/rtc_cntl/wakeup_state.rs
+++ b/esp32s3/src/rtc_cntl/wakeup_state.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:31 - wakeup enable bitmap"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W<WAKEUP_STATE_SPEC> {
         WAKEUP_ENA_W::new(self, 15)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtconfig0.rs b/esp32s3/src/rtc_cntl/wdtconfig0.rs
index c8f3bca143..19d899f1dd 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig0.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_chip_reset_width(&mut self) -> WDT_CHIP_RESET_WIDTH_W<WDTCONFIG0_SPEC> {
         WDT_CHIP_RESET_WIDTH_W::new(self, 0)
     }
     #[doc = "Bit 8 - wdt reset whole chip enable"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_chip_reset_en(&mut self) -> WDT_CHIP_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_CHIP_RESET_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - pause WDT in sleep"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<WDTCONFIG0_SPEC> {
         WDT_PAUSE_IN_SLP_W::new(self, 9)
     }
     #[doc = "Bit 10 - enable WDT reset APP CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_APPCPU_RESET_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - enable WDT reset PRO CPU"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_PROCPU_RESET_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - enable WDT in flash boot"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 12)
     }
     #[doc = "Bits 13:15 - system reset counter length"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 13)
     }
     #[doc = "Bits 16:18 - CPU reset counter length"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 16)
     }
     #[doc = "Bits 19:21 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 19)
     }
     #[doc = "Bits 22:24 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 22)
     }
     #[doc = "Bits 25:27 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 25)
     }
     #[doc = "Bits 28:30 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 28)
     }
     #[doc = "Bit 31 - enable rtc watch dog"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtconfig1.rs b/esp32s3/src/rtc_cntl/wdtconfig1.rs
index 0bc081636c..4d83ea2e1d 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stage0 hold time"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG1_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtconfig2.rs b/esp32s3/src/rtc_cntl/wdtconfig2.rs
index 47bf95908b..88f40347e3 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stage1 hold time"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtconfig3.rs b/esp32s3/src/rtc_cntl/wdtconfig3.rs
index 1a780b5a7d..1cf0bfd550 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stage2 hold time"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtconfig4.rs b/esp32s3/src/rtc_cntl/wdtconfig4.rs
index 3cb37561d5..9e3d7a79e9 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - stage3 hold time"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtfeed.rs b/esp32s3/src/rtc_cntl/wdtfeed.rs
index 46d3cedb66..31055e13de 100644
--- a/esp32s3/src/rtc_cntl/wdtfeed.rs
+++ b/esp32s3/src/rtc_cntl/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bit 31 - rtc wdt feed"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_cntl/wdtwprotect.rs b/esp32s3/src/rtc_cntl/wdtwprotect.rs
index fab68cfe38..3e86386a83 100644
--- a/esp32s3/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32s3/src/rtc_cntl/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - rtc watch dog key"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs b/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
index a4526789ab..120984b624 100644
--- a/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
+++ b/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - xtal 32k watch dog backup clock factor"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_clk_factor(&mut self) -> XTAL32K_CLK_FACTOR_W<XTAL32K_CLK_FACTOR_SPEC> {
         XTAL32K_CLK_FACTOR_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_cntl/xtal32k_conf.rs b/esp32s3/src/rtc_cntl/xtal32k_conf.rs
index e43cad3be3..dac1059d19 100644
--- a/esp32s3/src/rtc_cntl/xtal32k_conf.rs
+++ b/esp32s3/src/rtc_cntl/xtal32k_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - cycles to wait to return noral xtal 32k"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_return_wait(&mut self) -> XTAL32K_RETURN_WAIT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_RETURN_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 4:19 - cycles to wait to repower on xtal 32k"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_restart_wait(&mut self) -> XTAL32K_RESTART_WAIT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_RESTART_WAIT_W::new(self, 4)
     }
     #[doc = "Bits 20:27 - If no clock detected for this amount of time 32k is regarded as dead"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_wdt_timeout(&mut self) -> XTAL32K_WDT_TIMEOUT_W<XTAL32K_CONF_SPEC> {
         XTAL32K_WDT_TIMEOUT_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - if restarted xtal32k period is smaller than this, it is regarded as stable"]
     #[inline(always)]
-    #[must_use]
     pub fn xtal32k_stable_thres(&mut self) -> XTAL32K_STABLE_THRES_W<XTAL32K_CONF_SPEC> {
         XTAL32K_STABLE_THRES_W::new(self, 28)
     }
diff --git a/esp32s3/src/rtc_i2c/cmd.rs b/esp32s3/src/rtc_i2c/cmd.rs
index 9431bd59c5..8e4b53048f 100644
--- a/esp32s3/src/rtc_i2c/cmd.rs
+++ b/esp32s3/src/rtc_i2c/cmd.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - command0"]
     #[inline(always)]
-    #[must_use]
     pub fn command(&mut self) -> COMMAND_W<CMD_SPEC> {
         COMMAND_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/ctrl.rs b/esp32s3/src/rtc_i2c/ctrl.rs
index d189e964e6..fe27d3741d 100644
--- a/esp32s3/src/rtc_i2c/ctrl.rs
+++ b/esp32s3/src/rtc_i2c/ctrl.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1=push pull,0=open drain"]
     #[inline(always)]
-    #[must_use]
     pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
         SDA_FORCE_OUT_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1=push pull,0=open drain"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
         SCL_FORCE_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1=master,0=slave"]
     #[inline(always)]
-    #[must_use]
     pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
         MS_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - force start"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
         TRANS_START_W::new(self, 3)
     }
     #[doc = "Bit 4 - transit lsb first"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
         TX_LSB_FIRST_W::new(self, 4)
     }
     #[doc = "Bit 5 - receive lsb first"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
         RX_LSB_FIRST_W::new(self, 5)
     }
     #[doc = "Bit 29 - configure i2c ctrl clk enable"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ctrl_clk_gate_en(&mut self) -> I2C_CTRL_CLK_GATE_EN_W<CTRL_SPEC> {
         I2C_CTRL_CLK_GATE_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - rtc i2c sw reset"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_reset(&mut self) -> I2C_RESET_W<CTRL_SPEC> {
         I2C_RESET_W::new(self, 30)
     }
     #[doc = "Bit 31 - rtc i2c reg clk gating"]
     #[inline(always)]
-    #[must_use]
     pub fn i2cclk_en(&mut self) -> I2CCLK_EN_W<CTRL_SPEC> {
         I2CCLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_i2c/data.rs b/esp32s3/src/rtc_i2c/data.rs
index 81fb9243a1..2997fa2359 100644
--- a/esp32s3/src/rtc_i2c/data.rs
+++ b/esp32s3/src/rtc_i2c/data.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 8:15 - data sent by slave"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tx_data(&mut self) -> SLAVE_TX_DATA_W<DATA_SPEC> {
         SLAVE_TX_DATA_W::new(self, 8)
     }
diff --git a/esp32s3/src/rtc_i2c/date.rs b/esp32s3/src/rtc_i2c/date.rs
index 9c8f5d7643..fa2e03a3dc 100644
--- a/esp32s3/src/rtc_i2c/date.rs
+++ b/esp32s3/src/rtc_i2c/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_date(&mut self) -> I2C_DATE_W<DATE_SPEC> {
         I2C_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/int_clr.rs b/esp32s3/src/rtc_i2c/int_clr.rs
index 14ed438a97..b97b2cc5b2 100644
--- a/esp32s3/src/rtc_i2c/int_clr.rs
+++ b/esp32s3/src/rtc_i2c/int_clr.rs
@@ -27,55 +27,46 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - clear slave transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_CLR_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 0)
     }
     #[doc = "Bit 1 - clear arbitration lost interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
         ARBITRATION_LOST_W::new(self, 1)
     }
     #[doc = "Bit 2 - clear master transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_CLR_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 2)
     }
     #[doc = "Bit 3 - clear transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - clear time out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
         TIME_OUT_W::new(self, 4)
     }
     #[doc = "Bit 5 - clear ack error interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ack_err(&mut self) -> ACK_ERR_W<INT_CLR_SPEC> {
         ACK_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - clear receive data interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data(&mut self) -> RX_DATA_W<INT_CLR_SPEC> {
         RX_DATA_W::new(self, 6)
     }
     #[doc = "Bit 7 - clear transit load data complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data(&mut self) -> TX_DATA_W<INT_CLR_SPEC> {
         TX_DATA_W::new(self, 7)
     }
     #[doc = "Bit 8 - clear detect start interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn detect_start(&mut self) -> DETECT_START_W<INT_CLR_SPEC> {
         DETECT_START_W::new(self, 8)
     }
diff --git a/esp32s3/src/rtc_i2c/int_ena.rs b/esp32s3/src/rtc_i2c/int_ena.rs
index 535e2cf991..c93688d765 100644
--- a/esp32s3/src/rtc_i2c/int_ena.rs
+++ b/esp32s3/src/rtc_i2c/int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - enable slave transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
         SLAVE_TRAN_COMP_W::new(self, 0)
     }
     #[doc = "Bit 1 - enable arbitration lost interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
         ARBITRATION_LOST_W::new(self, 1)
     }
     #[doc = "Bit 2 - enable master transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
         MASTER_TRAN_COMP_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable transit complete interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - enable time out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
         TIME_OUT_W::new(self, 4)
     }
     #[doc = "Bit 5 - enable eack error interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn ack_err(&mut self) -> ACK_ERR_W<INT_ENA_SPEC> {
         ACK_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - enable receive data interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_data(&mut self) -> RX_DATA_W<INT_ENA_SPEC> {
         RX_DATA_W::new(self, 6)
     }
     #[doc = "Bit 7 - enable transit data interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_data(&mut self) -> TX_DATA_W<INT_ENA_SPEC> {
         TX_DATA_W::new(self, 7)
     }
     #[doc = "Bit 8 - enable detect start interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn detect_start(&mut self) -> DETECT_START_W<INT_ENA_SPEC> {
         DETECT_START_W::new(self, 8)
     }
diff --git a/esp32s3/src/rtc_i2c/scl_high.rs b/esp32s3/src/rtc_i2c/scl_high.rs
index a89201e7f8..d09f79550c 100644
--- a/esp32s3/src/rtc_i2c/scl_high.rs
+++ b/esp32s3/src/rtc_i2c/scl_high.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time period that scl = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<SCL_HIGH_SPEC> {
         PERIOD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/scl_low.rs b/esp32s3/src/rtc_i2c/scl_low.rs
index 53dcc14829..0f909ec964 100644
--- a/esp32s3/src/rtc_i2c/scl_low.rs
+++ b/esp32s3/src/rtc_i2c/scl_low.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time period that scl =0"]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<SCL_LOW_SPEC> {
         PERIOD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/scl_start_period.rs b/esp32s3/src/rtc_i2c/scl_start_period.rs
index 5614db9ae1..a640576abf 100644
--- a/esp32s3/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s3/src/rtc_i2c/scl_start_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to toggle after I2C start is triggered"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_start_period(&mut self) -> SCL_START_PERIOD_W<SCL_START_PERIOD_SPEC> {
         SCL_START_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/scl_stop_period.rs b/esp32s3/src/rtc_i2c/scl_stop_period.rs
index 12b069956d..d4fb2dad2d 100644
--- a/esp32s3/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s3/src/rtc_i2c/scl_stop_period.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to stop after I2C end is triggered"]
     #[inline(always)]
-    #[must_use]
     pub fn scl_stop_period(&mut self) -> SCL_STOP_PERIOD_W<SCL_STOP_PERIOD_SPEC> {
         SCL_STOP_PERIOD_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/sda_duty.rs b/esp32s3/src/rtc_i2c/sda_duty.rs
index c0dfb7d3c5..80a68ffb7e 100644
--- a/esp32s3/src/rtc_i2c/sda_duty.rs
+++ b/esp32s3/src/rtc_i2c/sda_duty.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time period for SDA to toggle after SCL goes low"]
     #[inline(always)]
-    #[must_use]
     pub fn num(&mut self) -> NUM_W<SDA_DUTY_SPEC> {
         NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_i2c/slave_addr.rs b/esp32s3/src/rtc_i2c/slave_addr.rs
index c01aadc237..9b9fcc9b2f 100644
--- a/esp32s3/src/rtc_i2c/slave_addr.rs
+++ b/esp32s3/src/rtc_i2c/slave_addr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
-    #[must_use]
     pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
         SLAVE_ADDR_W::new(self, 0)
     }
     #[doc = "Bit 31 - i2c 10bit mode enable"]
     #[inline(always)]
-    #[must_use]
     pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
         ADDR_10BIT_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/rtc_i2c/to.rs b/esp32s3/src/rtc_i2c/to.rs
index 7e2b22bd38..f3f8f33a4b 100644
--- a/esp32s3/src/rtc_i2c/to.rs
+++ b/esp32s3/src/rtc_i2c/to.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - time out threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn time_out(&mut self) -> TIME_OUT_W<TO_SPEC> {
         TIME_OUT_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_io/date.rs b/esp32s3/src/rtc_io/date.rs
index 9d15c525a5..ad2e7f0d1b 100644
--- a/esp32s3/src/rtc_io/date.rs
+++ b/esp32s3/src/rtc_io/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/rtc_io/enable_w1tc.rs b/esp32s3/src/rtc_io/enable_w1tc.rs
index ebd83b6d83..7946d89436 100644
--- a/esp32s3/src/rtc_io/enable_w1tc.rs
+++ b/esp32s3/src/rtc_io/enable_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         ENABLE_W1TC_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/ext_wakeup0.rs b/esp32s3/src/rtc_io/ext_wakeup0.rs
index 99df4fe521..7e4eb2b0f2 100644
--- a/esp32s3/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s3/src/rtc_io/ext_wakeup0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - ******* Description configure***"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP0_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32s3/src/rtc_io/pad_dac1.rs b/esp32s3/src/rtc_io/pad_dac1.rs
index bb729eb64b..c475d09203 100644
--- a/esp32s3/src/rtc_io/pad_dac1.rs
+++ b/esp32s3/src/rtc_io/pad_dac1.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 3:10 - PDAC1_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_dac(&mut self) -> PDAC1_DAC_W<PAD_DAC1_SPEC> {
         PDAC1_DAC_W::new(self, 3)
     }
     #[doc = "Bit 11 - PDAC1_XPD_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_xpd_dac(&mut self) -> PDAC1_XPD_DAC_W<PAD_DAC1_SPEC> {
         PDAC1_XPD_DAC_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_dac_xpd_force(&mut self) -> PDAC1_DAC_XPD_FORCE_W<PAD_DAC1_SPEC> {
         PDAC1_DAC_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_fun_ie(&mut self) -> PDAC1_FUN_IE_W<PAD_DAC1_SPEC> {
         PDAC1_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_slp_oe(&mut self) -> PDAC1_SLP_OE_W<PAD_DAC1_SPEC> {
         PDAC1_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_slp_ie(&mut self) -> PDAC1_SLP_IE_W<PAD_DAC1_SPEC> {
         PDAC1_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_slp_sel(&mut self) -> PDAC1_SLP_SEL_W<PAD_DAC1_SPEC> {
         PDAC1_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - PDAC1 function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_fun_sel(&mut self) -> PDAC1_FUN_SEL_W<PAD_DAC1_SPEC> {
         PDAC1_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_mux_sel(&mut self) -> PDAC1_MUX_SEL_W<PAD_DAC1_SPEC> {
         PDAC1_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - PDAC1_RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_rue(&mut self) -> PDAC1_RUE_W<PAD_DAC1_SPEC> {
         PDAC1_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - PDAC1_RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_rde(&mut self) -> PDAC1_RDE_W<PAD_DAC1_SPEC> {
         PDAC1_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - PDAC1_DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac1_drv(&mut self) -> PDAC1_DRV_W<PAD_DAC1_SPEC> {
         PDAC1_DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/pad_dac2.rs b/esp32s3/src/rtc_io/pad_dac2.rs
index 9ca09cc882..14756aea6e 100644
--- a/esp32s3/src/rtc_io/pad_dac2.rs
+++ b/esp32s3/src/rtc_io/pad_dac2.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 3:10 - PDAC2_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_dac(&mut self) -> PDAC2_DAC_W<PAD_DAC2_SPEC> {
         PDAC2_DAC_W::new(self, 3)
     }
     #[doc = "Bit 11 - PDAC2_XPD_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_xpd_dac(&mut self) -> PDAC2_XPD_DAC_W<PAD_DAC2_SPEC> {
         PDAC2_XPD_DAC_W::new(self, 11)
     }
     #[doc = "Bit 12 - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_dac_xpd_force(&mut self) -> PDAC2_DAC_XPD_FORCE_W<PAD_DAC2_SPEC> {
         PDAC2_DAC_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_fun_ie(&mut self) -> PDAC2_FUN_IE_W<PAD_DAC2_SPEC> {
         PDAC2_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_slp_oe(&mut self) -> PDAC2_SLP_OE_W<PAD_DAC2_SPEC> {
         PDAC2_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_slp_ie(&mut self) -> PDAC2_SLP_IE_W<PAD_DAC2_SPEC> {
         PDAC2_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_slp_sel(&mut self) -> PDAC2_SLP_SEL_W<PAD_DAC2_SPEC> {
         PDAC2_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - PDAC1 function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_fun_sel(&mut self) -> PDAC2_FUN_SEL_W<PAD_DAC2_SPEC> {
         PDAC2_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_mux_sel(&mut self) -> PDAC2_MUX_SEL_W<PAD_DAC2_SPEC> {
         PDAC2_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - PDAC2_RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_rue(&mut self) -> PDAC2_RUE_W<PAD_DAC2_SPEC> {
         PDAC2_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - PDAC2_RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_rde(&mut self) -> PDAC2_RDE_W<PAD_DAC2_SPEC> {
         PDAC2_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - PDAC2_DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn pdac2_drv(&mut self) -> PDAC2_DRV_W<PAD_DAC2_SPEC> {
         PDAC2_DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/pin.rs b/esp32s3/src/rtc_io/pin.rs
index 4e20c3d52a..e89a1cf64f 100644
--- a/esp32s3/src/rtc_io/pin.rs
+++ b/esp32s3/src/rtc_io/pin.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
         PAD_DRIVER_W::new(self, 2)
     }
     #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
         INT_TYPE_W::new(self, 7)
     }
     #[doc = "Bit 10 - RTC GPIO wakeup enable bit"]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
         WAKEUP_ENABLE_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_debug_sel.rs b/esp32s3/src/rtc_io/rtc_debug_sel.rs
index d75c7b95df..43e8871200 100644
--- a/esp32s3/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s3/src/rtc_io/rtc_debug_sel.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel0(&mut self) -> RTC_DEBUG_SEL0_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL0_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel1(&mut self) -> RTC_DEBUG_SEL1_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL1_W::new(self, 5)
     }
     #[doc = "Bits 10:14 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel2(&mut self) -> RTC_DEBUG_SEL2_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL2_W::new(self, 10)
     }
     #[doc = "Bits 15:19 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel3(&mut self) -> RTC_DEBUG_SEL3_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL3_W::new(self, 15)
     }
     #[doc = "Bits 20:24 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_sel4(&mut self) -> RTC_DEBUG_SEL4_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_SEL4_W::new(self, 20)
     }
     #[doc = "Bit 25 - configure rtc debug"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_debug_12m_no_gating(&mut self) -> RTC_DEBUG_12M_NO_GATING_W<RTC_DEBUG_SEL_SPEC> {
         RTC_DEBUG_12M_NO_GATING_W::new(self, 25)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_enable.rs b/esp32s3/src/rtc_io/rtc_gpio_enable.rs
index 18662ddac1..d85e5d21a5 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_enable.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_enable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_enable(&mut self) -> RTC_GPIO_ENABLE_W<RTC_GPIO_ENABLE_SPEC> {
         RTC_GPIO_ENABLE_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_enable_w1ts.rs b/esp32s3/src/rtc_io/rtc_gpio_enable_w1ts.rs
index 355f056237..069ed939a8 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_enable_w1ts.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_enable_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_enable_w1ts(&mut self) -> RTC_GPIO_ENABLE_W1TS_W<RTC_GPIO_ENABLE_W1TS_SPEC> {
         RTC_GPIO_ENABLE_W1TS_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_out.rs b/esp32s3/src/rtc_io/rtc_gpio_out.rs
index 27b902a790..b0a5770509 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_out.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_out.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data"]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<RTC_GPIO_OUT_SPEC> {
         DATA_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_out_w1tc.rs b/esp32s3/src/rtc_io/rtc_gpio_out_w1tc.rs
index d505d2d474..6b6eb3de5f 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_out_w1tc.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_out_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_out_data_w1tc(&mut self) -> RTC_GPIO_OUT_DATA_W1TC_W<RTC_GPIO_OUT_W1TC_SPEC> {
         RTC_GPIO_OUT_DATA_W1TC_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_out_w1ts.rs b/esp32s3/src/rtc_io/rtc_gpio_out_w1ts.rs
index acaa48f0ca..c1e75e0c0d 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_out_w1ts.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_out_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_out_data_w1ts(&mut self) -> RTC_GPIO_OUT_DATA_W1TS_W<RTC_GPIO_OUT_W1TS_SPEC> {
         RTC_GPIO_OUT_DATA_W1TS_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_status.rs b/esp32s3/src/rtc_io/rtc_gpio_status.rs
index c52c41f25e..0f3f65fe6a 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_status.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<RTC_GPIO_STATUS_SPEC> {
         INT_W::new(self, 10)
     }
diff --git a/esp32s3/src/rtc_io/rtc_gpio_status_w1tc.rs b/esp32s3/src/rtc_io/rtc_gpio_status_w1tc.rs
index 29329521b8..83571af0ec 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_status_w1tc.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_status_w1tc.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TC_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status write 1 to clear"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_status_int_w1tc(
         &mut self,
     ) -> RTC_GPIO_STATUS_INT_W1TC_W<RTC_GPIO_STATUS_W1TC_SPEC> {
diff --git a/esp32s3/src/rtc_io/rtc_gpio_status_w1ts.rs b/esp32s3/src/rtc_io/rtc_gpio_status_w1ts.rs
index ec83aa8e2c..1ccc4f5c07 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_status_w1ts.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_status_w1ts.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TS_SPEC> {
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status write 1 to set"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_gpio_status_int_w1ts(
         &mut self,
     ) -> RTC_GPIO_STATUS_INT_W1TS_W<RTC_GPIO_STATUS_W1TS_SPEC> {
diff --git a/esp32s3/src/rtc_io/rtc_pad19.rs b/esp32s3/src/rtc_io/rtc_pad19.rs
index df3b94eb50..ab0116229a 100644
--- a/esp32s3/src/rtc_io/rtc_pad19.rs
+++ b/esp32s3/src/rtc_io/rtc_pad19.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD19_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD19_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD19_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD19_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD19_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD19_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD19_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD19_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD19_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/rtc_pad20.rs b/esp32s3/src/rtc_io/rtc_pad20.rs
index dfd3f9859a..0c202c9690 100644
--- a/esp32s3/src/rtc_io/rtc_pad20.rs
+++ b/esp32s3/src/rtc_io/rtc_pad20.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD20_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD20_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD20_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD20_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD20_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD20_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD20_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD20_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD20_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/rtc_pad21.rs b/esp32s3/src/rtc_io/rtc_pad21.rs
index 9c6e5a5229..16fad2fc2b 100644
--- a/esp32s3/src/rtc_io/rtc_pad21.rs
+++ b/esp32s3/src/rtc_io/rtc_pad21.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD21_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD21_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD21_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD21_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD21_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD21_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<RTC_PAD21_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<RTC_PAD21_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<RTC_PAD21_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/sar_i2c_io.rs b/esp32s3/src/rtc_io/sar_i2c_io.rs
index 3f9c87d3a2..4873a03506 100644
--- a/esp32s3/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s3/src/rtc_io/sar_i2c_io.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 23:27 - ******* Description configure***"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_DEBUG_BIT_SEL_W::new(self, 23)
     }
     #[doc = "Bits 28:29 - ******* Description configure***"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SCL_SEL_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - ******* Description configure***"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<SAR_I2C_IO_SPEC> {
         SAR_I2C_SDA_SEL_W::new(self, 30)
     }
diff --git a/esp32s3/src/rtc_io/touch_ctrl.rs b/esp32s3/src/rtc_io/touch_ctrl.rs
index e95c4223d6..4533fbff14 100644
--- a/esp32s3/src/rtc_io/touch_ctrl.rs
+++ b/esp32s3/src/rtc_io/touch_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - BUF_SEL when touch work without fsm"]
     #[inline(always)]
-    #[must_use]
     pub fn io_touch_bufsel(&mut self) -> IO_TOUCH_BUFSEL_W<TOUCH_CTRL_SPEC> {
         IO_TOUCH_BUFSEL_W::new(self, 0)
     }
     #[doc = "Bit 4 - BUF_MODE when touch work without fsm"]
     #[inline(always)]
-    #[must_use]
     pub fn io_touch_bufmode(&mut self) -> IO_TOUCH_BUFMODE_W<TOUCH_CTRL_SPEC> {
         IO_TOUCH_BUFMODE_W::new(self, 4)
     }
diff --git a/esp32s3/src/rtc_io/touch_pad.rs b/esp32s3/src/rtc_io/touch_pad.rs
index 15f0604e10..2a67dd9df1 100644
--- a/esp32s3/src/rtc_io/touch_pad.rs
+++ b/esp32s3/src/rtc_io/touch_pad.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD_SPEC> {
         FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD_SPEC> {
         SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD_SPEC> {
         SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD_SPEC> {
         SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD_SPEC> {
         FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD_SPEC> {
         MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 20 - TOUCH_XPD"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD_SPEC> {
         XPD_W::new(self, 20)
     }
     #[doc = "Bit 21 - TOUCH_TIE_OPT"]
     #[inline(always)]
-    #[must_use]
     pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD_SPEC> {
         TIE_OPT_W::new(self, 21)
     }
     #[doc = "Bit 22 - TOUCH_START"]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<TOUCH_PAD_SPEC> {
         START_W::new(self, 22)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn rue(&mut self) -> RUE_W<TOUCH_PAD_SPEC> {
         RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn rde(&mut self) -> RDE_W<TOUCH_PAD_SPEC> {
         RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn drv(&mut self) -> DRV_W<TOUCH_PAD_SPEC> {
         DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/xtal_32n_pad.rs b/esp32s3/src/rtc_io/xtal_32n_pad.rs
index cb1288f696..76569de7ab 100644
--- a/esp32s3/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s3/src/rtc_io/xtal_32n_pad.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_ie(&mut self) -> X32N_FUN_IE_W<XTAL_32N_PAD_SPEC> {
         X32N_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_oe(&mut self) -> X32N_SLP_OE_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_ie(&mut self) -> X32N_SLP_IE_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_slp_sel(&mut self) -> X32N_SLP_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_fun_sel(&mut self) -> X32N_FUN_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_mux_sel(&mut self) -> X32N_MUX_SEL_W<XTAL_32N_PAD_SPEC> {
         X32N_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rue(&mut self) -> X32N_RUE_W<XTAL_32N_PAD_SPEC> {
         X32N_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_rde(&mut self) -> X32N_RDE_W<XTAL_32N_PAD_SPEC> {
         X32N_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn x32n_drv(&mut self) -> X32N_DRV_W<XTAL_32N_PAD_SPEC> {
         X32N_DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/xtal_32p_pad.rs b/esp32s3/src/rtc_io/xtal_32p_pad.rs
index dda44697bc..ffdc77c02a 100644
--- a/esp32s3/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s3/src/rtc_io/xtal_32p_pad.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_ie(&mut self) -> X32P_FUN_IE_W<XTAL_32P_PAD_SPEC> {
         X32P_FUN_IE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_oe(&mut self) -> X32P_SLP_OE_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_OE_W::new(self, 14)
     }
     #[doc = "Bit 15 - input enable in sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_ie(&mut self) -> X32P_SLP_IE_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_IE_W::new(self, 15)
     }
     #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_slp_sel(&mut self) -> X32P_SLP_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_SLP_SEL_W::new(self, 16)
     }
     #[doc = "Bits 17:18 - function sel"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_fun_sel(&mut self) -> X32P_FUN_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_FUN_SEL_W::new(self, 17)
     }
     #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_mux_sel(&mut self) -> X32P_MUX_SEL_W<XTAL_32P_PAD_SPEC> {
         X32P_MUX_SEL_W::new(self, 19)
     }
     #[doc = "Bit 27 - RUE"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rue(&mut self) -> X32P_RUE_W<XTAL_32P_PAD_SPEC> {
         X32P_RUE_W::new(self, 27)
     }
     #[doc = "Bit 28 - RDE"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_rde(&mut self) -> X32P_RDE_W<XTAL_32P_PAD_SPEC> {
         X32P_RDE_W::new(self, 28)
     }
     #[doc = "Bits 29:30 - DRV"]
     #[inline(always)]
-    #[must_use]
     pub fn x32p_drv(&mut self) -> X32P_DRV_W<XTAL_32P_PAD_SPEC> {
         X32P_DRV_W::new(self, 29)
     }
diff --git a/esp32s3/src/rtc_io/xtl_ext_ctr.rs b/esp32s3/src/rtc_io/xtl_ext_ctr.rs
index acfc3b25b3..b8dfc88494 100644
--- a/esp32s3/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s3/src/rtc_io/xtl_ext_ctr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 27:31 - select RTC GPIO 0 ~ 17 to control XTAL"]
     #[inline(always)]
-    #[must_use]
     pub fn sel(&mut self) -> SEL_W<XTL_EXT_CTR_SPEC> {
         SEL_W::new(self, 27)
     }
diff --git a/esp32s3/src/sdhost/blksiz.rs b/esp32s3/src/sdhost/blksiz.rs
index 7ac50857b9..97a552eab9 100644
--- a/esp32s3/src/sdhost/blksiz.rs
+++ b/esp32s3/src/sdhost/blksiz.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Block size."]
     #[inline(always)]
-    #[must_use]
     pub fn block_size(&mut self) -> BLOCK_SIZE_W<BLKSIZ_SPEC> {
         BLOCK_SIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/bmod.rs b/esp32s3/src/sdhost/bmod.rs
index e2aff690f5..75568d4b2e 100644
--- a/esp32s3/src/sdhost/bmod.rs
+++ b/esp32s3/src/sdhost/bmod.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn swr(&mut self) -> SWR_W<BMOD_SPEC> {
         SWR_W::new(self, 0)
     }
     #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
     #[inline(always)]
-    #[must_use]
     pub fn fb(&mut self) -> FB_W<BMOD_SPEC> {
         FB_W::new(self, 1)
     }
     #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn de(&mut self) -> DE_W<BMOD_SPEC> {
         DE_W::new(self, 7)
     }
     #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
     #[inline(always)]
-    #[must_use]
     pub fn pbl(&mut self) -> PBL_W<BMOD_SPEC> {
         PBL_W::new(self, 8)
     }
diff --git a/esp32s3/src/sdhost/buffifo.rs b/esp32s3/src/sdhost/buffifo.rs
index 5886f135ca..6ff254e646 100644
--- a/esp32s3/src/sdhost/buffifo.rs
+++ b/esp32s3/src/sdhost/buffifo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
     #[inline(always)]
-    #[must_use]
     pub fn buffifo(&mut self) -> BUFFIFO_W<BUFFIFO_SPEC> {
         BUFFIFO_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/bytcnt.rs b/esp32s3/src/sdhost/bytcnt.rs
index 95bbb226ce..52246a239f 100644
--- a/esp32s3/src/sdhost/bytcnt.rs
+++ b/esp32s3/src/sdhost/bytcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn byte_count(&mut self) -> BYTE_COUNT_W<BYTCNT_SPEC> {
         BYTE_COUNT_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/cardthrctl.rs b/esp32s3/src/sdhost/cardthrctl.rs
index a3a12f56ea..29187b55f5 100644
--- a/esp32s3/src/sdhost/cardthrctl.rs
+++ b/esp32s3/src/sdhost/cardthrctl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardrdthren(&mut self) -> CARDRDTHREN_W<CARDTHRCTL_SPEC> {
         CARDRDTHREN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardclrinten(&mut self) -> CARDCLRINTEN_W<CARDTHRCTL_SPEC> {
         CARDCLRINTEN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cardwrthren(&mut self) -> CARDWRTHREN_W<CARDTHRCTL_SPEC> {
         CARDWRTHREN_W::new(self, 2)
     }
     #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn cardthreshold(&mut self) -> CARDTHRESHOLD_W<CARDTHRCTL_SPEC> {
         CARDTHRESHOLD_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/clk_edge_sel.rs b/esp32s3/src/sdhost/clk_edge_sel.rs
index 1fa3b67b25..14f1cad1f1 100644
--- a/esp32s3/src/sdhost/clk_edge_sel.rs
+++ b/esp32s3/src/sdhost/clk_edge_sel.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_DRV_SEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_SAM_SEL_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
-    #[must_use]
     pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<CLK_EDGE_SEL_SPEC> {
         CCLKIN_EDGE_SLF_SEL_W::new(self, 6)
     }
     #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_H_W::new(self, 9)
     }
     #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_L_W::new(self, 13)
     }
     #[doc = "Bits 17:20 - The clock division of cclk_in."]
     #[inline(always)]
-    #[must_use]
     pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<CLK_EDGE_SEL_SPEC> {
         CCLLKIN_EDGE_N_W::new(self, 17)
     }
     #[doc = "Bit 21 - Enable esdio mode."]
     #[inline(always)]
-    #[must_use]
     pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<CLK_EDGE_SEL_SPEC> {
         ESDIO_MODE_W::new(self, 21)
     }
     #[doc = "Bit 22 - Enable esd mode."]
     #[inline(always)]
-    #[must_use]
     pub fn esd_mode(&mut self) -> ESD_MODE_W<CLK_EDGE_SEL_SPEC> {
         ESD_MODE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Sdio clock enable."]
     #[inline(always)]
-    #[must_use]
     pub fn cclk_en(&mut self) -> CCLK_EN_W<CLK_EDGE_SEL_SPEC> {
         CCLK_EN_W::new(self, 23)
     }
diff --git a/esp32s3/src/sdhost/clkdiv.rs b/esp32s3/src/sdhost/clkdiv.rs
index 6d43304da9..4e556096c2 100644
--- a/esp32s3/src/sdhost/clkdiv.rs
+++ b/esp32s3/src/sdhost/clkdiv.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W<CLKDIV_SPEC> {
         CLK_DIVIDER0_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider1(&mut self) -> CLK_DIVIDER1_W<CLKDIV_SPEC> {
         CLK_DIVIDER1_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider2(&mut self) -> CLK_DIVIDER2_W<CLKDIV_SPEC> {
         CLK_DIVIDER2_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_divider3(&mut self) -> CLK_DIVIDER3_W<CLKDIV_SPEC> {
         CLK_DIVIDER3_W::new(self, 24)
     }
diff --git a/esp32s3/src/sdhost/clkena.rs b/esp32s3/src/sdhost/clkena.rs
index 8ea549e305..38637db020 100644
--- a/esp32s3/src/sdhost/clkena.rs
+++ b/esp32s3/src/sdhost/clkena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn cclk_enable(&mut self) -> CCLK_ENABLE_W<CLKENA_SPEC> {
         CCLK_ENABLE_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn lp_enable(&mut self) -> LP_ENABLE_W<CLKENA_SPEC> {
         LP_ENABLE_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/clksrc.rs b/esp32s3/src/sdhost/clksrc.rs
index 291b8b4cce..6065175aa7 100644
--- a/esp32s3/src/sdhost/clksrc.rs
+++ b/esp32s3/src/sdhost/clksrc.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
     #[inline(always)]
-    #[must_use]
     pub fn clksrc(&mut self) -> CLKSRC_W<CLKSRC_SPEC> {
         CLKSRC_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/cmd.rs b/esp32s3/src/sdhost/cmd.rs
index 29b5cdd46b..f5187e2015 100644
--- a/esp32s3/src/sdhost/cmd.rs
+++ b/esp32s3/src/sdhost/cmd.rs
@@ -34,9 +34,9 @@ pub type TRANSFER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type SEND_AUTO_STOP_R = crate::BitReader;
 #[doc = "Field `SEND_AUTO_STOP` writer - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
 pub type SEND_AUTO_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
 pub type WAIT_PRVDATA_COMPLETE_R = crate::BitReader;
-#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
 pub type WAIT_PRVDATA_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `STOP_ABORT_CMD` reader - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
 pub type STOP_ABORT_CMD_R = crate::BitReader;
@@ -111,7 +111,7 @@ impl R {
     pub fn send_auto_stop(&self) -> SEND_AUTO_STOP_R {
         SEND_AUTO_STOP_R::new(((self.bits >> 12) & 1) != 0)
     }
-    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
     #[inline(always)]
     pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETE_R {
         WAIT_PRVDATA_COMPLETE_R::new(((self.bits >> 13) & 1) != 0)
@@ -187,103 +187,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - Command index."]
     #[inline(always)]
-    #[must_use]
     pub fn index(&mut self) -> INDEX_W<CMD_SPEC> {
         INDEX_W::new(self, 0)
     }
     #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W<CMD_SPEC> {
         RESPONSE_EXPECT_W::new(self, 6)
     }
     #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn response_length(&mut self) -> RESPONSE_LENGTH_W<CMD_SPEC> {
         RESPONSE_LENGTH_W::new(self, 7)
     }
     #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
     #[inline(always)]
-    #[must_use]
     pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W<CMD_SPEC> {
         CHECK_RESPONSE_CRC_W::new(self, 8)
     }
     #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
     #[inline(always)]
-    #[must_use]
     pub fn data_expected(&mut self) -> DATA_EXPECTED_W<CMD_SPEC> {
         DATA_EXPECTED_W::new(self, 9)
     }
     #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
     #[inline(always)]
-    #[must_use]
     pub fn read_write(&mut self) -> READ_WRITE_W<CMD_SPEC> {
         READ_WRITE_W::new(self, 10)
     }
     #[doc = "Bit 11 - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
     #[inline(always)]
-    #[must_use]
     pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W<CMD_SPEC> {
         TRANSFER_MODE_W::new(self, 11)
     }
     #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W<CMD_SPEC> {
         SEND_AUTO_STOP_W::new(self, 12)
     }
-    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W<CMD_SPEC> {
         WAIT_PRVDATA_COMPLETE_W::new(self, 13)
     }
     #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W<CMD_SPEC> {
         STOP_ABORT_CMD_W::new(self, 14)
     }
     #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
     #[inline(always)]
-    #[must_use]
     pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W<CMD_SPEC> {
         SEND_INITIALIZATION_W::new(self, 15)
     }
     #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn card_number(&mut self) -> CARD_NUMBER_W<CMD_SPEC> {
         CARD_NUMBER_W::new(self, 16)
     }
     #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
     #[inline(always)]
-    #[must_use]
     pub fn update_clock_registers_only(&mut self) -> UPDATE_CLOCK_REGISTERS_ONLY_W<CMD_SPEC> {
         UPDATE_CLOCK_REGISTERS_ONLY_W::new(self, 21)
     }
     #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
     #[inline(always)]
-    #[must_use]
     pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W<CMD_SPEC> {
         READ_CEATA_DEVICE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W<CMD_SPEC> {
         CCS_EXPECTED_W::new(self, 23)
     }
     #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
     #[inline(always)]
-    #[must_use]
     pub fn use_hole(&mut self) -> USE_HOLE_W<CMD_SPEC> {
         USE_HOLE_W::new(self, 29)
     }
     #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
     #[inline(always)]
-    #[must_use]
     pub fn start_cmd(&mut self) -> START_CMD_W<CMD_SPEC> {
         START_CMD_W::new(self, 31)
     }
diff --git a/esp32s3/src/sdhost/cmdarg.rs b/esp32s3/src/sdhost/cmdarg.rs
index 9b54253c45..16efa0eb23 100644
--- a/esp32s3/src/sdhost/cmdarg.rs
+++ b/esp32s3/src/sdhost/cmdarg.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
     #[inline(always)]
-    #[must_use]
     pub fn cmdarg(&mut self) -> CMDARG_W<CMDARG_SPEC> {
         CMDARG_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/ctrl.rs b/esp32s3/src/sdhost/ctrl.rs
index 188695044f..bdeba0dd0d 100644
--- a/esp32s3/src/sdhost/ctrl.rs
+++ b/esp32s3/src/sdhost/ctrl.rs
@@ -117,61 +117,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W<CTRL_SPEC> {
         CONTROLLER_RESET_W::new(self, 0)
     }
     #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_reset(&mut self) -> FIFO_RESET_W<CTRL_SPEC> {
         FIFO_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_reset(&mut self) -> DMA_RESET_W<CTRL_SPEC> {
         DMA_RESET_W::new(self, 2)
     }
     #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
     #[inline(always)]
-    #[must_use]
     pub fn int_enable(&mut self) -> INT_ENABLE_W<CTRL_SPEC> {
         INT_ENABLE_W::new(self, 4)
     }
     #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
     #[inline(always)]
-    #[must_use]
     pub fn read_wait(&mut self) -> READ_WAIT_W<CTRL_SPEC> {
         READ_WAIT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W<CTRL_SPEC> {
         SEND_IRQ_RESPONSE_W::new(self, 7)
     }
     #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W<CTRL_SPEC> {
         ABORT_READ_DATA_W::new(self, 8)
     }
     #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
     #[inline(always)]
-    #[must_use]
     pub fn send_ccsd(&mut self) -> SEND_CCSD_W<CTRL_SPEC> {
         SEND_CCSD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
     #[inline(always)]
-    #[must_use]
     pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W<CTRL_SPEC> {
         SEND_AUTO_STOP_CCSD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ceata_device_interrupt_status(&mut self) -> CEATA_DEVICE_INTERRUPT_STATUS_W<CTRL_SPEC> {
         CEATA_DEVICE_INTERRUPT_STATUS_W::new(self, 11)
     }
diff --git a/esp32s3/src/sdhost/ctype.rs b/esp32s3/src/sdhost/ctype.rs
index 87fd7264c1..626c966262 100644
--- a/esp32s3/src/sdhost/ctype.rs
+++ b/esp32s3/src/sdhost/ctype.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn card_width4(&mut self) -> CARD_WIDTH4_W<CTYPE_SPEC> {
         CARD_WIDTH4_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
-    #[must_use]
     pub fn card_width8(&mut self) -> CARD_WIDTH8_W<CTYPE_SPEC> {
         CARD_WIDTH8_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/dbaddr.rs b/esp32s3/src/sdhost/dbaddr.rs
index aaf52a61c5..d3c712d63a 100644
--- a/esp32s3/src/sdhost/dbaddr.rs
+++ b/esp32s3/src/sdhost/dbaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
     #[inline(always)]
-    #[must_use]
     pub fn dbaddr(&mut self) -> DBADDR_W<DBADDR_SPEC> {
         DBADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/debnce.rs b/esp32s3/src/sdhost/debnce.rs
index f5664a5673..06e70e3dcd 100644
--- a/esp32s3/src/sdhost/debnce.rs
+++ b/esp32s3/src/sdhost/debnce.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
     #[inline(always)]
-    #[must_use]
     pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W<DEBNCE_SPEC> {
         DEBOUNCE_COUNT_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/emmcddr.rs b/esp32s3/src/sdhost/emmcddr.rs
index 405b5d2739..31ada02122 100644
--- a/esp32s3/src/sdhost/emmcddr.rs
+++ b/esp32s3/src/sdhost/emmcddr.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
     #[inline(always)]
-    #[must_use]
     pub fn halfstartbit(&mut self) -> HALFSTARTBIT_W<EMMCDDR_SPEC> {
         HALFSTARTBIT_W::new(self, 0)
     }
     #[doc = "Bit 31 - Set 1 to enable HS400 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn hs400_mode(&mut self) -> HS400_MODE_W<EMMCDDR_SPEC> {
         HS400_MODE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sdhost/enshift.rs b/esp32s3/src/sdhost/enshift.rs
index bd77802532..3d441e55f7 100644
--- a/esp32s3/src/sdhost/enshift.rs
+++ b/esp32s3/src/sdhost/enshift.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_shift(&mut self) -> ENABLE_SHIFT_W<ENSHIFT_SPEC> {
         ENABLE_SHIFT_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/fifoth.rs b/esp32s3/src/sdhost/fifoth.rs
index 841b6ce6d7..557b69a335 100644
--- a/esp32s3/src/sdhost/fifoth.rs
+++ b/esp32s3/src/sdhost/fifoth.rs
@@ -47,19 +47,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_wmark(&mut self) -> TX_WMARK_W<FIFOTH_SPEC> {
         TX_WMARK_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_wmark(&mut self) -> RX_WMARK_W<FIFOTH_SPEC> {
         RX_WMARK_W::new(self, 16)
     }
     #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_multiple_transaction_size(
         &mut self,
     ) -> DMA_MULTIPLE_TRANSACTION_SIZE_W<FIFOTH_SPEC> {
diff --git a/esp32s3/src/sdhost/idinten.rs b/esp32s3/src/sdhost/idinten.rs
index 730c7c8bd1..5c9d873d90 100644
--- a/esp32s3/src/sdhost/idinten.rs
+++ b/esp32s3/src/sdhost/idinten.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn ti(&mut self) -> TI_W<IDINTEN_SPEC> {
         TI_W::new(self, 0)
     }
     #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn ri(&mut self) -> RI_W<IDINTEN_SPEC> {
         RI_W::new(self, 1)
     }
     #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe(&mut self) -> FBE_W<IDINTEN_SPEC> {
         FBE_W::new(self, 2)
     }
     #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn du(&mut self) -> DU_W<IDINTEN_SPEC> {
         DU_W::new(self, 4)
     }
     #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
     #[inline(always)]
-    #[must_use]
     pub fn ces(&mut self) -> CES_W<IDINTEN_SPEC> {
         CES_W::new(self, 5)
     }
     #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ni(&mut self) -> NI_W<IDINTEN_SPEC> {
         NI_W::new(self, 8)
     }
     #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ai(&mut self) -> AI_W<IDINTEN_SPEC> {
         AI_W::new(self, 9)
     }
diff --git a/esp32s3/src/sdhost/idsts.rs b/esp32s3/src/sdhost/idsts.rs
index fbf3d95fb4..b9ded110b9 100644
--- a/esp32s3/src/sdhost/idsts.rs
+++ b/esp32s3/src/sdhost/idsts.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ti(&mut self) -> TI_W<IDSTS_SPEC> {
         TI_W::new(self, 0)
     }
     #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ri(&mut self) -> RI_W<IDSTS_SPEC> {
         RI_W::new(self, 1)
     }
     #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe(&mut self) -> FBE_W<IDSTS_SPEC> {
         FBE_W::new(self, 2)
     }
     #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn du(&mut self) -> DU_W<IDSTS_SPEC> {
         DU_W::new(self, 4)
     }
     #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
     #[inline(always)]
-    #[must_use]
     pub fn ces(&mut self) -> CES_W<IDSTS_SPEC> {
         CES_W::new(self, 5)
     }
     #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn nis(&mut self) -> NIS_W<IDSTS_SPEC> {
         NIS_W::new(self, 8)
     }
     #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ais(&mut self) -> AIS_W<IDSTS_SPEC> {
         AIS_W::new(self, 9)
     }
     #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn fbe_code(&mut self) -> FBE_CODE_W<IDSTS_SPEC> {
         FBE_CODE_W::new(self, 10)
     }
     #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
     #[inline(always)]
-    #[must_use]
     pub fn fsm(&mut self) -> FSM_W<IDSTS_SPEC> {
         FSM_W::new(self, 13)
     }
diff --git a/esp32s3/src/sdhost/intmask.rs b/esp32s3/src/sdhost/intmask.rs
index d8f06f1b7b..04af2f6725 100644
--- a/esp32s3/src/sdhost/intmask.rs
+++ b/esp32s3/src/sdhost/intmask.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
-    #[must_use]
     pub fn int_mask(&mut self) -> INT_MASK_W<INTMASK_SPEC> {
         INT_MASK_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<INTMASK_SPEC> {
         SDIO_INT_MASK_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/pldmnd.rs b/esp32s3/src/sdhost/pldmnd.rs
index feb2236b6a..593156e368 100644
--- a/esp32s3/src/sdhost/pldmnd.rs
+++ b/esp32s3/src/sdhost/pldmnd.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<PLDMND_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."]
     #[inline(always)]
-    #[must_use]
     pub fn pd(&mut self) -> PD_W<PLDMND_SPEC> {
         PD_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/rintsts.rs b/esp32s3/src/sdhost/rintsts.rs
index 9bc56751d6..5d6e6f419f 100644
--- a/esp32s3/src/sdhost/rintsts.rs
+++ b/esp32s3/src/sdhost/rintsts.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
-    #[must_use]
     pub fn int_status_raw(&mut self) -> INT_STATUS_RAW_W<RINTSTS_SPEC> {
         INT_STATUS_RAW_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_interrupt_raw(&mut self) -> SDIO_INTERRUPT_RAW_W<RINTSTS_SPEC> {
         SDIO_INTERRUPT_RAW_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/rst_n.rs b/esp32s3/src/sdhost/rst_n.rs
index c9aee83112..b7bcd3f632 100644
--- a/esp32s3/src/sdhost/rst_n.rs
+++ b/esp32s3/src/sdhost/rst_n.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
     #[inline(always)]
-    #[must_use]
     pub fn card_reset(&mut self) -> CARD_RESET_W<RST_N_SPEC> {
         CARD_RESET_W::new(self, 0)
     }
diff --git a/esp32s3/src/sdhost/tmout.rs b/esp32s3/src/sdhost/tmout.rs
index e8c4de9106..8c443976e0 100644
--- a/esp32s3/src/sdhost/tmout.rs
+++ b/esp32s3/src/sdhost/tmout.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
     #[inline(always)]
-    #[must_use]
     pub fn response_timeout(&mut self) -> RESPONSE_TIMEOUT_W<TMOUT_SPEC> {
         RESPONSE_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn data_timeout(&mut self) -> DATA_TIMEOUT_W<TMOUT_SPEC> {
         DATA_TIMEOUT_W::new(self, 8)
     }
diff --git a/esp32s3/src/sdhost/uhs.rs b/esp32s3/src/sdhost/uhs.rs
index 7ab87510f3..92f0b1c227 100644
--- a/esp32s3/src/sdhost/uhs.rs
+++ b/esp32s3/src/sdhost/uhs.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
     #[inline(always)]
-    #[must_use]
     pub fn ddr(&mut self) -> DDR_W<UHS_SPEC> {
         DDR_W::new(self, 16)
     }
diff --git a/esp32s3/src/sdhost/usrid.rs b/esp32s3/src/sdhost/usrid.rs
index 7a0013604a..ca2811794d 100644
--- a/esp32s3/src/sdhost/usrid.rs
+++ b/esp32s3/src/sdhost/usrid.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
     #[inline(always)]
-    #[must_use]
     pub fn usrid(&mut self) -> USRID_W<USRID_SPEC> {
         USRID_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_amp_ctrl1.rs b/esp32s3/src/sens/sar_amp_ctrl1.rs
index 5a82270150..64e360d88f 100644
--- a/esp32s3/src/sens/sar_amp_ctrl1.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W<SAR_AMP_CTRL1_SPEC> {
         SAR_AMP_WAIT1_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W<SAR_AMP_CTRL1_SPEC> {
         SAR_AMP_WAIT2_W::new(self, 16)
     }
diff --git a/esp32s3/src/sens/sar_amp_ctrl2.rs b/esp32s3/src/sens/sar_amp_ctrl2.rs
index 52a0790af5..d760b0d411 100644
--- a/esp32s3/src/sens/sar_amp_ctrl2.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl2.rs
@@ -103,25 +103,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_dac_xpd_fsm_idle(&mut self) -> SAR_SAR1_DAC_XPD_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_SAR1_DAC_XPD_FSM_IDLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_xpd_sar_amp_fsm_idle(&mut self) -> SAR_XPD_SAR_AMP_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_XPD_SAR_AMP_FSM_IDLE_W::new(self, 1)
     }
     #[doc = "Bit 2 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_rst_fb_fsm_idle(&mut self) -> SAR_AMP_RST_FB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_AMP_RST_FB_FSM_IDLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_short_ref_fsm_idle(
         &mut self,
     ) -> SAR_AMP_SHORT_REF_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
@@ -129,7 +125,6 @@ impl W {
     }
     #[doc = "Bit 4 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_short_ref_gnd_fsm_idle(
         &mut self,
     ) -> SAR_AMP_SHORT_REF_GND_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
@@ -137,19 +132,16 @@ impl W {
     }
     #[doc = "Bit 5 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_xpd_sar_fsm_idle(&mut self) -> SAR_XPD_SAR_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_XPD_SAR_FSM_IDLE_W::new(self, 5)
     }
     #[doc = "Bit 6 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
         SAR_RSTB_FSM_IDLE_W::new(self, 6)
     }
     #[doc = "Bits 16:31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W<SAR_AMP_CTRL2_SPEC> {
         SAR_AMP_WAIT3_W::new(self, 16)
     }
diff --git a/esp32s3/src/sens/sar_amp_ctrl3.rs b/esp32s3/src/sens/sar_amp_ctrl3.rs
index 3bd058fe34..a86ac7147d 100644
--- a/esp32s3/src/sens/sar_amp_ctrl3.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl3.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W<SAR_AMP_CTRL3_SPEC> {
         SAR1_DAC_XPD_FSM_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W<SAR_AMP_CTRL3_SPEC> {
         XPD_SAR_AMP_FSM_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_RST_FB_FSM_W::new(self, 8)
     }
     #[doc = "Bits 12:15 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_SHORT_REF_FSM_W::new(self, 12)
     }
     #[doc = "Bits 16:19 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W<SAR_AMP_CTRL3_SPEC> {
         AMP_SHORT_REF_GND_FSM_W::new(self, 16)
     }
     #[doc = "Bits 20:23 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W<SAR_AMP_CTRL3_SPEC> {
         XPD_SAR_FSM_W::new(self, 20)
     }
     #[doc = "Bits 24:27 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn rstb_fsm(&mut self) -> RSTB_FSM_W<SAR_AMP_CTRL3_SPEC> {
         RSTB_FSM_W::new(self, 24)
     }
diff --git a/esp32s3/src/sens/sar_atten1.rs b/esp32s3/src/sens/sar_atten1.rs
index 587228e8fa..3f558b1d93 100644
--- a/esp32s3/src/sens/sar_atten1.rs
+++ b/esp32s3/src/sens/sar_atten1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W<SAR_ATTEN1_SPEC> {
         SAR1_ATTEN_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_atten2.rs b/esp32s3/src/sens/sar_atten2.rs
index 1ede7d1d39..d3d2826570 100644
--- a/esp32s3/src/sens/sar_atten2.rs
+++ b/esp32s3/src/sens/sar_atten2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W<SAR_ATTEN2_SPEC> {
         SAR2_ATTEN_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_cocpu_int_clr.rs b/esp32s3/src/sens/sar_cocpu_int_clr.rs
index 13aa3b2545..5e49bad6ed 100644
--- a/esp32s3/src/sens/sar_cocpu_int_clr.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_clr.rs
@@ -33,7 +33,6 @@ impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - int clear of touch done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_done_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -41,7 +40,6 @@ impl W {
     }
     #[doc = "Bit 1 - int clear of from touch inactive"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_inactive_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_INACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -49,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 2 - int clear of touch active"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_active_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_ACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -57,7 +54,6 @@ impl W {
     }
     #[doc = "Bit 3 - int clear of from saradc1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc1_int_clr(
         &mut self,
     ) -> SAR_COCPU_SARADC1_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -65,7 +61,6 @@ impl W {
     }
     #[doc = "Bit 4 - int clear of from saradc2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc2_int_clr(
         &mut self,
     ) -> SAR_COCPU_SARADC2_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -73,31 +68,26 @@ impl W {
     }
     #[doc = "Bit 5 - int clear of tsens"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_tsens_int_clr(&mut self) -> SAR_COCPU_TSENS_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         SAR_COCPU_TSENS_INT_CLR_W::new(self, 5)
     }
     #[doc = "Bit 6 - int clear of start"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_start_int_clr(&mut self) -> SAR_COCPU_START_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         SAR_COCPU_START_INT_CLR_W::new(self, 6)
     }
     #[doc = "Bit 7 - int clear of software"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_sw_int_clr(&mut self) -> SAR_COCPU_SW_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         SAR_COCPU_SW_INT_CLR_W::new(self, 7)
     }
     #[doc = "Bit 8 - int clear of super watch dog"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_swd_int_clr(&mut self) -> SAR_COCPU_SWD_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
         SAR_COCPU_SWD_INT_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9 - int clear of timeout done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_timeout_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -105,7 +95,6 @@ impl W {
     }
     #[doc = "Bit 10 - int clear of approach loop done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_approach_loop_done_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
@@ -113,7 +102,6 @@ impl W {
     }
     #[doc = "Bit 11 - int clear of touch scan done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_scan_done_int_clr(
         &mut self,
     ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
diff --git a/esp32s3/src/sens/sar_cocpu_int_ena.rs b/esp32s3/src/sens/sar_cocpu_int_ena.rs
index 78dedbca4e..89b45f655c 100644
--- a/esp32s3/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_ena.rs
@@ -160,7 +160,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - int enable of touch done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_done_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -168,7 +167,6 @@ impl W {
     }
     #[doc = "Bit 1 - int enable of from touch inactive"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_inactive_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -176,7 +174,6 @@ impl W {
     }
     #[doc = "Bit 2 - int enable of touch active"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_active_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -184,7 +181,6 @@ impl W {
     }
     #[doc = "Bit 3 - int enable of from saradc1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc1_int_ena(
         &mut self,
     ) -> SAR_COCPU_SARADC1_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -192,7 +188,6 @@ impl W {
     }
     #[doc = "Bit 4 - int enable of from saradc2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc2_int_ena(
         &mut self,
     ) -> SAR_COCPU_SARADC2_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -200,31 +195,26 @@ impl W {
     }
     #[doc = "Bit 5 - int enable of tsens"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_tsens_int_ena(&mut self) -> SAR_COCPU_TSENS_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         SAR_COCPU_TSENS_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6 - int enable of start"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_start_int_ena(&mut self) -> SAR_COCPU_START_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         SAR_COCPU_START_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - int enable of software"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_sw_int_ena(&mut self) -> SAR_COCPU_SW_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         SAR_COCPU_SW_INT_ENA_W::new(self, 7)
     }
     #[doc = "Bit 8 - int enable of super watch dog"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_swd_int_ena(&mut self) -> SAR_COCPU_SWD_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
         SAR_COCPU_SWD_INT_ENA_W::new(self, 8)
     }
     #[doc = "Bit 9 - int enable of timeout done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_timeout_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -232,7 +222,6 @@ impl W {
     }
     #[doc = "Bit 10 - int enable of approach loop done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_approach_loop_done_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
@@ -240,7 +229,6 @@ impl W {
     }
     #[doc = "Bit 11 - int enable of touch scan done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_scan_done_int_ena(
         &mut self,
     ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
diff --git a/esp32s3/src/sens/sar_cocpu_int_ena_w1tc.rs b/esp32s3/src/sens/sar_cocpu_int_ena_w1tc.rs
index 39c9630079..25cef35016 100644
--- a/esp32s3/src/sens/sar_cocpu_int_ena_w1tc.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_ena_w1tc.rs
@@ -33,7 +33,6 @@ impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_W1TC_SPEC> {
 impl W {
     #[doc = "Bit 0 - Clear int enable of touch done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_done_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -41,7 +40,6 @@ impl W {
     }
     #[doc = "Bit 1 - Clear int enable of from touch inactive"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_inactive_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -49,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 2 - Clear int enable of touch active"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_active_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -57,7 +54,6 @@ impl W {
     }
     #[doc = "Bit 3 - Clear int enable of from saradc1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc1_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_SARADC1_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -65,7 +61,6 @@ impl W {
     }
     #[doc = "Bit 4 - Clear int enable of from saradc2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc2_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_SARADC2_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -73,7 +68,6 @@ impl W {
     }
     #[doc = "Bit 5 - Clear int enable of tsens"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_tsens_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TSENS_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -81,7 +75,6 @@ impl W {
     }
     #[doc = "Bit 6 - Clear int enable of start"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_start_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_START_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -89,7 +82,6 @@ impl W {
     }
     #[doc = "Bit 7 - Clear int enable of software"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_sw_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_SW_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -97,7 +89,6 @@ impl W {
     }
     #[doc = "Bit 8 - Clear int enable of super watch dog"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_swd_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_SWD_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -105,7 +96,6 @@ impl W {
     }
     #[doc = "Bit 9 - Clear int enable of timeout done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_timeout_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -113,7 +103,6 @@ impl W {
     }
     #[doc = "Bit 10 - Clear int enable of approach loop done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_approach_loop_done_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
@@ -121,7 +110,6 @@ impl W {
     }
     #[doc = "Bit 11 - Clear int enable of touch scan done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_scan_done_int_ena_w1tc(
         &mut self,
     ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
diff --git a/esp32s3/src/sens/sar_cocpu_int_ena_w1ts.rs b/esp32s3/src/sens/sar_cocpu_int_ena_w1ts.rs
index 6ebabe92d3..f825ef88a2 100644
--- a/esp32s3/src/sens/sar_cocpu_int_ena_w1ts.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_ena_w1ts.rs
@@ -33,7 +33,6 @@ impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_W1TS_SPEC> {
 impl W {
     #[doc = "Bit 0 - int enable of touch done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_done_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -41,7 +40,6 @@ impl W {
     }
     #[doc = "Bit 1 - int enable of from touch inactive"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_inactive_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -49,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 2 - int enable of touch active"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_active_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -57,7 +54,6 @@ impl W {
     }
     #[doc = "Bit 3 - int enable of from saradc1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc1_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_SARADC1_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -65,7 +61,6 @@ impl W {
     }
     #[doc = "Bit 4 - int enable of from saradc2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_saradc2_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_SARADC2_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -73,7 +68,6 @@ impl W {
     }
     #[doc = "Bit 5 - int enable of tsens"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_tsens_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TSENS_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -81,7 +75,6 @@ impl W {
     }
     #[doc = "Bit 6 - int enable of start"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_start_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_START_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -89,7 +82,6 @@ impl W {
     }
     #[doc = "Bit 7 - int enable of software"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_sw_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_SW_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -97,7 +89,6 @@ impl W {
     }
     #[doc = "Bit 8 - int enable of super watch dog"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_swd_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_SWD_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -105,7 +96,6 @@ impl W {
     }
     #[doc = "Bit 9 - int enable of timeout done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_timeout_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -113,7 +103,6 @@ impl W {
     }
     #[doc = "Bit 10 - int enable of approach loop done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_approach_loop_done_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
@@ -121,7 +110,6 @@ impl W {
     }
     #[doc = "Bit 11 - int enable of touch scan done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_touch_scan_done_int_ena_w1ts(
         &mut self,
     ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
diff --git a/esp32s3/src/sens/sar_cocpu_state.rs b/esp32s3/src/sens/sar_cocpu_state.rs
index 8ba9d7d43b..2de6a61070 100644
--- a/esp32s3/src/sens/sar_cocpu_state.rs
+++ b/esp32s3/src/sens/sar_cocpu_state.rs
@@ -56,7 +56,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 25 - trigger cocpu debug registers"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_dbg_trigger(&mut self) -> SAR_COCPU_DBG_TRIGGER_W<SAR_COCPU_STATE_SPEC> {
         SAR_COCPU_DBG_TRIGGER_W::new(self, 25)
     }
diff --git a/esp32s3/src/sens/sar_debug_conf.rs b/esp32s3/src/sens/sar_debug_conf.rs
index b0e54d623f..722a3fede5 100644
--- a/esp32s3/src/sens/sar_debug_conf.rs
+++ b/esp32s3/src/sens/sar_debug_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_DEBUG_CONF_SPEC> {
         SAR_DEBUG_BIT_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_hall_ctrl.rs b/esp32s3/src/sens/sar_hall_ctrl.rs
index 0bdbeb3fbb..814166d27e 100644
--- a/esp32s3/src/sens/sar_hall_ctrl.rs
+++ b/esp32s3/src/sens/sar_hall_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall(&mut self) -> XPD_HALL_W<SAR_HALL_CTRL_SPEC> {
         XPD_HALL_W::new(self, 28)
     }
     #[doc = "Bit 29 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn xpd_hall_force(&mut self) -> XPD_HALL_FORCE_W<SAR_HALL_CTRL_SPEC> {
         XPD_HALL_FORCE_W::new(self, 29)
     }
     #[doc = "Bit 30 - Reverse phase of hall sensor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase(&mut self) -> HALL_PHASE_W<SAR_HALL_CTRL_SPEC> {
         HALL_PHASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn hall_phase_force(&mut self) -> HALL_PHASE_FORCE_W<SAR_HALL_CTRL_SPEC> {
         HALL_PHASE_FORCE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_i2c_ctrl.rs b/esp32s3/src/sens/sar_i2c_ctrl.rs
index 5d1b0c41c1..26c5277a54 100644
--- a/esp32s3/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s3/src/sens/sar_i2c_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_CTRL_W::new(self, 0)
     }
     #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_W::new(self, 28)
     }
     #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<SAR_I2C_CTRL_SPEC> {
         SAR_I2C_START_FORCE_W::new(self, 29)
     }
diff --git a/esp32s3/src/sens/sar_meas1_ctrl1.rs b/esp32s3/src/sens/sar_meas1_ctrl1.rs
index 994073d4d1..506a94d702 100644
--- a/esp32s3/src/sens/sar_meas1_ctrl1.rs
+++ b/esp32s3/src/sens/sar_meas1_ctrl1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 24:25 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W<SAR_MEAS1_CTRL1_SPEC> {
         FORCE_XPD_AMP_W::new(self, 24)
     }
     #[doc = "Bits 26:27 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_RST_FB_FORCE_W::new(self, 26)
     }
     #[doc = "Bits 28:29 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_SHORT_REF_FORCE_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
         AMP_SHORT_REF_GND_FORCE_W::new(self, 30)
     }
diff --git a/esp32s3/src/sens/sar_meas1_ctrl2.rs b/esp32s3/src/sens/sar_meas1_ctrl2.rs
index 8ffb43a6db..01338847b6 100644
--- a/esp32s3/src/sens/sar_meas1_ctrl2.rs
+++ b/esp32s3/src/sens/sar_meas1_ctrl2.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion"]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W<SAR_MEAS1_CTRL2_SPEC> {
         MEAS1_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
         MEAS1_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W<SAR_MEAS1_CTRL2_SPEC> {
         SAR1_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
         SAR1_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_meas1_mux.rs b/esp32s3/src/sens/sar_meas1_mux.rs
index d97f65e6d6..bf934e2c22 100644
--- a/esp32s3/src/sens/sar_meas1_mux.rs
+++ b/esp32s3/src/sens/sar_meas1_mux.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
     #[inline(always)]
-    #[must_use]
     pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W<SAR_MEAS1_MUX_SPEC> {
         SAR1_DIG_FORCE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_meas2_ctrl1.rs b/esp32s3/src/sens/sar_meas2_ctrl1.rs
index 4550528888..59d23a2ec5 100644
--- a/esp32s3/src/sens/sar_meas2_ctrl1.rs
+++ b/esp32s3/src/sens/sar_meas2_ctrl1.rs
@@ -92,43 +92,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - rtc control pwdet enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_pwdet_cal_en(&mut self) -> SAR_SAR2_PWDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_PWDET_CAL_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - rtc control pkdet enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_pkdet_cal_en(&mut self) -> SAR_SAR2_PKDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_PKDET_CAL_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - SAR2_EN_TEST"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_en_test(&mut self) -> SAR_SAR2_EN_TEST_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_EN_TEST_W::new(self, 5)
     }
     #[doc = "Bits 6:7 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_rstb_force(&mut self) -> SAR_SAR2_RSTB_FORCE_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_RSTB_FORCE_W::new(self, 6)
     }
     #[doc = "Bits 8:15 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_standby_wait(&mut self) -> SAR_SAR2_STANDBY_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_STANDBY_WAIT_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_rstb_wait(&mut self) -> SAR_SAR2_RSTB_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_RSTB_WAIT_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_xpd_wait(&mut self) -> SAR_SAR2_XPD_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
         SAR_SAR2_XPD_WAIT_W::new(self, 24)
     }
diff --git a/esp32s3/src/sens/sar_meas2_ctrl2.rs b/esp32s3/src/sens/sar_meas2_ctrl2.rs
index 6041977a04..7d17c051f2 100644
--- a/esp32s3/src/sens/sar_meas2_ctrl2.rs
+++ b/esp32s3/src/sens/sar_meas2_ctrl2.rs
@@ -70,25 +70,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion"]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W<SAR_MEAS2_CTRL2_SPEC> {
         MEAS2_START_SAR_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
         MEAS2_START_FORCE_W::new(self, 18)
     }
     #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W<SAR_MEAS2_CTRL2_SPEC> {
         SAR2_EN_PAD_W::new(self, 19)
     }
     #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
         SAR2_EN_PAD_FORCE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_meas2_mux.rs b/esp32s3/src/sens/sar_meas2_mux.rs
index 6dc3624190..2b77991769 100644
--- a/esp32s3/src/sens/sar_meas2_mux.rs
+++ b/esp32s3/src/sens/sar_meas2_mux.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<SAR_MEAS2_MUX_SPEC> {
         SAR2_PWDET_CCT_W::new(self, 28)
     }
     #[doc = "Bit 31 - in sleep, force to use rtc to control ADC"]
     #[inline(always)]
-    #[must_use]
     pub fn sar2_rtc_force(&mut self) -> SAR2_RTC_FORCE_W<SAR_MEAS2_MUX_SPEC> {
         SAR2_RTC_FORCE_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_nouse.rs b/esp32s3/src/sens/sar_nouse.rs
index 541df17732..e5e072782a 100644
--- a/esp32s3/src/sens/sar_nouse.rs
+++ b/esp32s3/src/sens/sar_nouse.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_nouse(&mut self) -> SAR_NOUSE_W<SAR_NOUSE_SPEC> {
         SAR_NOUSE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_peri_clk_gate_conf.rs b/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
index 4a2aa1fe7c..748cbdff8a 100644
--- a/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
+++ b/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 27 - enable rtc i2c clock"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_i2c_clk_en(&mut self) -> RTC_I2C_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
         RTC_I2C_CLK_EN_W::new(self, 27)
     }
     #[doc = "Bit 29 - enable tsens clock"]
     #[inline(always)]
-    #[must_use]
     pub fn tsens_clk_en(&mut self) -> TSENS_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
         TSENS_CLK_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - enbale saradc clock"]
     #[inline(always)]
-    #[must_use]
     pub fn saradc_clk_en(&mut self) -> SARADC_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
         SARADC_CLK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - enable io_mux clock"]
     #[inline(always)]
-    #[must_use]
     pub fn iomux_clk_en(&mut self) -> IOMUX_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
         IOMUX_CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_peri_reset_conf.rs b/esp32s3/src/sens/sar_peri_reset_conf.rs
index 420be3f160..d81ffa385f 100644
--- a/esp32s3/src/sens/sar_peri_reset_conf.rs
+++ b/esp32s3/src/sens/sar_peri_reset_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 25 - enable ulp-riscv reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_cocpu_reset(&mut self) -> SAR_COCPU_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
         SAR_COCPU_RESET_W::new(self, 25)
     }
     #[doc = "Bit 27 - Reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn sar_rtc_i2c_reset(&mut self) -> SAR_RTC_I2C_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
         SAR_RTC_I2C_RESET_W::new(self, 27)
     }
     #[doc = "Bit 29 - enbale saradc reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_reset(&mut self) -> SAR_TSENS_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
         SAR_TSENS_RESET_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable io_mux reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_saradc_reset(&mut self) -> SAR_SARADC_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
         SAR_SARADC_RESET_W::new(self, 30)
     }
diff --git a/esp32s3/src/sens/sar_power_xpd_sar.rs b/esp32s3/src/sens/sar_power_xpd_sar.rs
index 135d0f842c..87c70c94b2 100644
--- a/esp32s3/src/sens/sar_power_xpd_sar.rs
+++ b/esp32s3/src/sens/sar_power_xpd_sar.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 29:30 - force power on/off saradc"]
     #[inline(always)]
-    #[must_use]
     pub fn force_xpd_sar(&mut self) -> FORCE_XPD_SAR_W<SAR_POWER_XPD_SAR_SPEC> {
         FORCE_XPD_SAR_W::new(self, 29)
     }
     #[doc = "Bit 31 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sarclk_en(&mut self) -> SARCLK_EN_W<SAR_POWER_XPD_SAR_SPEC> {
         SARCLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/sens/sar_reader1_ctrl.rs b/esp32s3/src/sens/sar_reader1_ctrl.rs
index b8590371aa..17578583f4 100644
--- a/esp32s3/src/sens/sar_reader1_ctrl.rs
+++ b/esp32s3/src/sens/sar_reader1_ctrl.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_clk_div(&mut self) -> SAR_SAR1_CLK_DIV_W<SAR_READER1_CTRL_SPEC> {
         SAR_SAR1_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bit 18 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_clk_gated(&mut self) -> SAR_SAR1_CLK_GATED_W<SAR_READER1_CTRL_SPEC> {
         SAR_SAR1_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_sample_num(&mut self) -> SAR_SAR1_SAMPLE_NUM_W<SAR_READER1_CTRL_SPEC> {
         SAR_SAR1_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 28 - Invert SAR ADC1 data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_data_inv(&mut self) -> SAR_SAR1_DATA_INV_W<SAR_READER1_CTRL_SPEC> {
         SAR_SAR1_DATA_INV_W::new(self, 28)
     }
     #[doc = "Bit 29 - enable saradc1 to send out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar1_int_en(&mut self) -> SAR_SAR1_INT_EN_W<SAR_READER1_CTRL_SPEC> {
         SAR_SAR1_INT_EN_W::new(self, 29)
     }
diff --git a/esp32s3/src/sens/sar_reader2_ctrl.rs b/esp32s3/src/sens/sar_reader2_ctrl.rs
index 9947adabc6..eaa20e055b 100644
--- a/esp32s3/src/sens/sar_reader2_ctrl.rs
+++ b/esp32s3/src/sens/sar_reader2_ctrl.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_clk_div(&mut self) -> SAR_SAR2_CLK_DIV_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_CLK_DIV_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_wait_arb_cycle(&mut self) -> SAR_SAR2_WAIT_ARB_CYCLE_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_WAIT_ARB_CYCLE_W::new(self, 16)
     }
     #[doc = "Bit 18 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_clk_gated(&mut self) -> SAR_SAR2_CLK_GATED_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_CLK_GATED_W::new(self, 18)
     }
     #[doc = "Bits 19:26 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_sample_num(&mut self) -> SAR_SAR2_SAMPLE_NUM_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_SAMPLE_NUM_W::new(self, 19)
     }
     #[doc = "Bit 29 - Invert SAR ADC2 data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_data_inv(&mut self) -> SAR_SAR2_DATA_INV_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_DATA_INV_W::new(self, 29)
     }
     #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_sar2_int_en(&mut self) -> SAR_SAR2_INT_EN_W<SAR_READER2_CTRL_SPEC> {
         SAR_SAR2_INT_EN_W::new(self, 30)
     }
diff --git a/esp32s3/src/sens/sar_sardate.rs b/esp32s3/src/sens/sar_sardate.rs
index 5a66c04f8e..25a80520de 100644
--- a/esp32s3/src/sens/sar_sardate.rs
+++ b/esp32s3/src/sens/sar_sardate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_date(&mut self) -> SAR_DATE_W<SAR_SARDATE_SPEC> {
         SAR_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_slave_addr1.rs b/esp32s3/src/sens/sar_slave_addr1.rs
index 2c41c0e27c..340182ae9d 100644
--- a/esp32s3/src/sens/sar_slave_addr1.rs
+++ b/esp32s3/src/sens/sar_slave_addr1.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr1(&mut self) -> SAR_I2C_SLAVE_ADDR1_W<SAR_SLAVE_ADDR1_SPEC> {
         SAR_I2C_SLAVE_ADDR1_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - configure i2c slave address0"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr0(&mut self) -> SAR_I2C_SLAVE_ADDR0_W<SAR_SLAVE_ADDR1_SPEC> {
         SAR_I2C_SLAVE_ADDR0_W::new(self, 11)
     }
diff --git a/esp32s3/src/sens/sar_slave_addr2.rs b/esp32s3/src/sens/sar_slave_addr2.rs
index 23064f2b03..826eefdc0c 100644
--- a/esp32s3/src/sens/sar_slave_addr2.rs
+++ b/esp32s3/src/sens/sar_slave_addr2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address3"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr3(&mut self) -> SAR_I2C_SLAVE_ADDR3_W<SAR_SLAVE_ADDR2_SPEC> {
         SAR_I2C_SLAVE_ADDR3_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - configure i2c slave address2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr2(&mut self) -> SAR_I2C_SLAVE_ADDR2_W<SAR_SLAVE_ADDR2_SPEC> {
         SAR_I2C_SLAVE_ADDR2_W::new(self, 11)
     }
diff --git a/esp32s3/src/sens/sar_slave_addr3.rs b/esp32s3/src/sens/sar_slave_addr3.rs
index 7c9d636f59..8931ebd411 100644
--- a/esp32s3/src/sens/sar_slave_addr3.rs
+++ b/esp32s3/src/sens/sar_slave_addr3.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address5"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr5(&mut self) -> SAR_I2C_SLAVE_ADDR5_W<SAR_SLAVE_ADDR3_SPEC> {
         SAR_I2C_SLAVE_ADDR5_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - configure i2c slave address4"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr4(&mut self) -> SAR_I2C_SLAVE_ADDR4_W<SAR_SLAVE_ADDR3_SPEC> {
         SAR_I2C_SLAVE_ADDR4_W::new(self, 11)
     }
diff --git a/esp32s3/src/sens/sar_slave_addr4.rs b/esp32s3/src/sens/sar_slave_addr4.rs
index d5c776a657..600cda2068 100644
--- a/esp32s3/src/sens/sar_slave_addr4.rs
+++ b/esp32s3/src/sens/sar_slave_addr4.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address7"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr7(&mut self) -> SAR_I2C_SLAVE_ADDR7_W<SAR_SLAVE_ADDR4_SPEC> {
         SAR_I2C_SLAVE_ADDR7_W::new(self, 0)
     }
     #[doc = "Bits 11:21 - configure i2c slave address6"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_i2c_slave_addr6(&mut self) -> SAR_I2C_SLAVE_ADDR6_W<SAR_SLAVE_ADDR4_SPEC> {
         SAR_I2C_SLAVE_ADDR6_W::new(self, 11)
     }
diff --git a/esp32s3/src/sens/sar_touch_chn_st.rs b/esp32s3/src/sens/sar_touch_chn_st.rs
index 7eba168afa..7feb715004 100644
--- a/esp32s3/src/sens/sar_touch_chn_st.rs
+++ b/esp32s3/src/sens/sar_touch_chn_st.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 15:29 - Clear touch channel"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_channel_clr(&mut self) -> SAR_TOUCH_CHANNEL_CLR_W<SAR_TOUCH_CHN_ST_SPEC> {
         SAR_TOUCH_CHANNEL_CLR_W::new(self, 15)
     }
diff --git a/esp32s3/src/sens/sar_touch_conf.rs b/esp32s3/src/sens/sar_touch_conf.rs
index 69d6408e62..df8197c3dd 100644
--- a/esp32s3/src/sens/sar_touch_conf.rs
+++ b/esp32s3/src/sens/sar_touch_conf.rs
@@ -82,37 +82,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:14 - touch controller output enable"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_outen(&mut self) -> SAR_TOUCH_OUTEN_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_OUTEN_W::new(self, 0)
     }
     #[doc = "Bit 15 - clear all touch active status"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_status_clr(&mut self) -> SAR_TOUCH_STATUS_CLR_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_STATUS_CLR_W::new(self, 15)
     }
     #[doc = "Bits 16:17 - 3: smooth data 2: baseline 1,0: raw_data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_data_sel(&mut self) -> SAR_TOUCH_DATA_SEL_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_DATA_SEL_W::new(self, 16)
     }
     #[doc = "Bits 20:23 - indicate which pad is approach pad2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_approach_pad2(&mut self) -> SAR_TOUCH_APPROACH_PAD2_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_APPROACH_PAD2_W::new(self, 20)
     }
     #[doc = "Bits 24:27 - indicate which pad is approach pad1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_approach_pad1(&mut self) -> SAR_TOUCH_APPROACH_PAD1_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_APPROACH_PAD1_W::new(self, 24)
     }
     #[doc = "Bits 28:31 - indicate which pad is approach pad0"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_approach_pad0(&mut self) -> SAR_TOUCH_APPROACH_PAD0_W<SAR_TOUCH_CONF_SPEC> {
         SAR_TOUCH_APPROACH_PAD0_W::new(self, 28)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres1.rs b/esp32s3/src/sens/sar_touch_thres1.rs
index 5c26448023..66bd0310d9 100644
--- a/esp32s3/src/sens/sar_touch_thres1.rs
+++ b/esp32s3/src/sens/sar_touch_thres1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th1(&mut self) -> SAR_TOUCH_OUT_TH1_W<SAR_TOUCH_THRES1_SPEC> {
         SAR_TOUCH_OUT_TH1_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres10.rs b/esp32s3/src/sens/sar_touch_thres10.rs
index 30ac1df630..64cd14ceba 100644
--- a/esp32s3/src/sens/sar_touch_thres10.rs
+++ b/esp32s3/src/sens/sar_touch_thres10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th10(&mut self) -> SAR_TOUCH_OUT_TH10_W<SAR_TOUCH_THRES10_SPEC> {
         SAR_TOUCH_OUT_TH10_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres11.rs b/esp32s3/src/sens/sar_touch_thres11.rs
index d3f69aac90..a13a4eb7f0 100644
--- a/esp32s3/src/sens/sar_touch_thres11.rs
+++ b/esp32s3/src/sens/sar_touch_thres11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th11(&mut self) -> SAR_TOUCH_OUT_TH11_W<SAR_TOUCH_THRES11_SPEC> {
         SAR_TOUCH_OUT_TH11_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres12.rs b/esp32s3/src/sens/sar_touch_thres12.rs
index 0b6a0831d0..c063d8fbd0 100644
--- a/esp32s3/src/sens/sar_touch_thres12.rs
+++ b/esp32s3/src/sens/sar_touch_thres12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th12(&mut self) -> SAR_TOUCH_OUT_TH12_W<SAR_TOUCH_THRES12_SPEC> {
         SAR_TOUCH_OUT_TH12_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres13.rs b/esp32s3/src/sens/sar_touch_thres13.rs
index 928daf0a67..05b33033a7 100644
--- a/esp32s3/src/sens/sar_touch_thres13.rs
+++ b/esp32s3/src/sens/sar_touch_thres13.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th13(&mut self) -> SAR_TOUCH_OUT_TH13_W<SAR_TOUCH_THRES13_SPEC> {
         SAR_TOUCH_OUT_TH13_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres14.rs b/esp32s3/src/sens/sar_touch_thres14.rs
index 6c79dd92f3..62bd7205f2 100644
--- a/esp32s3/src/sens/sar_touch_thres14.rs
+++ b/esp32s3/src/sens/sar_touch_thres14.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th14(&mut self) -> SAR_TOUCH_OUT_TH14_W<SAR_TOUCH_THRES14_SPEC> {
         SAR_TOUCH_OUT_TH14_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres2.rs b/esp32s3/src/sens/sar_touch_thres2.rs
index 6ebdc10d44..8657a12b6f 100644
--- a/esp32s3/src/sens/sar_touch_thres2.rs
+++ b/esp32s3/src/sens/sar_touch_thres2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th2(&mut self) -> SAR_TOUCH_OUT_TH2_W<SAR_TOUCH_THRES2_SPEC> {
         SAR_TOUCH_OUT_TH2_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres3.rs b/esp32s3/src/sens/sar_touch_thres3.rs
index 6aa732cf4f..b2f17bf08c 100644
--- a/esp32s3/src/sens/sar_touch_thres3.rs
+++ b/esp32s3/src/sens/sar_touch_thres3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th3(&mut self) -> SAR_TOUCH_OUT_TH3_W<SAR_TOUCH_THRES3_SPEC> {
         SAR_TOUCH_OUT_TH3_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres4.rs b/esp32s3/src/sens/sar_touch_thres4.rs
index f9184d6608..6a7d7f2ee5 100644
--- a/esp32s3/src/sens/sar_touch_thres4.rs
+++ b/esp32s3/src/sens/sar_touch_thres4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th4(&mut self) -> SAR_TOUCH_OUT_TH4_W<SAR_TOUCH_THRES4_SPEC> {
         SAR_TOUCH_OUT_TH4_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres5.rs b/esp32s3/src/sens/sar_touch_thres5.rs
index 40dc624f95..580bf220e1 100644
--- a/esp32s3/src/sens/sar_touch_thres5.rs
+++ b/esp32s3/src/sens/sar_touch_thres5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th5(&mut self) -> SAR_TOUCH_OUT_TH5_W<SAR_TOUCH_THRES5_SPEC> {
         SAR_TOUCH_OUT_TH5_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres6.rs b/esp32s3/src/sens/sar_touch_thres6.rs
index 718536c5f5..04c3893367 100644
--- a/esp32s3/src/sens/sar_touch_thres6.rs
+++ b/esp32s3/src/sens/sar_touch_thres6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th6(&mut self) -> SAR_TOUCH_OUT_TH6_W<SAR_TOUCH_THRES6_SPEC> {
         SAR_TOUCH_OUT_TH6_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres7.rs b/esp32s3/src/sens/sar_touch_thres7.rs
index f216510a1a..a947cb3199 100644
--- a/esp32s3/src/sens/sar_touch_thres7.rs
+++ b/esp32s3/src/sens/sar_touch_thres7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th7(&mut self) -> SAR_TOUCH_OUT_TH7_W<SAR_TOUCH_THRES7_SPEC> {
         SAR_TOUCH_OUT_TH7_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres8.rs b/esp32s3/src/sens/sar_touch_thres8.rs
index 31e8e84f40..5ecc8683c2 100644
--- a/esp32s3/src/sens/sar_touch_thres8.rs
+++ b/esp32s3/src/sens/sar_touch_thres8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th8(&mut self) -> SAR_TOUCH_OUT_TH8_W<SAR_TOUCH_THRES8_SPEC> {
         SAR_TOUCH_OUT_TH8_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_touch_thres9.rs b/esp32s3/src/sens/sar_touch_thres9.rs
index 072d7c5a84..d560270ef7 100644
--- a/esp32s3/src/sens/sar_touch_thres9.rs
+++ b/esp32s3/src/sens/sar_touch_thres9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_touch_out_th9(&mut self) -> SAR_TOUCH_OUT_TH9_W<SAR_TOUCH_THRES9_SPEC> {
         SAR_TOUCH_OUT_TH9_W::new(self, 0)
     }
diff --git a/esp32s3/src/sens/sar_tsens_ctrl.rs b/esp32s3/src/sens/sar_tsens_ctrl.rs
index 944bec3034..54fc44f8ae 100644
--- a/esp32s3/src/sens/sar_tsens_ctrl.rs
+++ b/esp32s3/src/sens/sar_tsens_ctrl.rs
@@ -22,9 +22,9 @@ pub type SAR_TSENS_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 pub type SAR_TSENS_POWER_UP_R = crate::BitReader;
 #[doc = "Field `SAR_TSENS_POWER_UP` writer - temperature sensor power up"]
 pub type SAR_TSENS_POWER_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` reader - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` reader - 1: dump out & power up controlled by SW 0: by FSM"]
 pub type SAR_TSENS_POWER_UP_FORCE_R = crate::BitReader;
-#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` writer - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` writer - 1: dump out & power up controlled by SW 0: by FSM"]
 pub type SAR_TSENS_POWER_UP_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SAR_TSENS_DUMP_OUT` reader - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
 pub type SAR_TSENS_DUMP_OUT_R = crate::BitReader;
@@ -61,7 +61,7 @@ impl R {
     pub fn sar_tsens_power_up(&self) -> SAR_TSENS_POWER_UP_R {
         SAR_TSENS_POWER_UP_R::new(((self.bits >> 22) & 1) != 0)
     }
-    #[doc = "Bit 23 - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+    #[doc = "Bit 23 - 1: dump out & power up controlled by SW 0: by FSM"]
     #[inline(always)]
     pub fn sar_tsens_power_up_force(&self) -> SAR_TSENS_POWER_UP_FORCE_R {
         SAR_TSENS_POWER_UP_FORCE_R::new(((self.bits >> 23) & 1) != 0)
@@ -90,37 +90,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - enable temperature sensor to send out interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_int_en(&mut self) -> SAR_TSENS_INT_EN_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_INT_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - invert temperature sensor data"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_in_inv(&mut self) -> SAR_TSENS_IN_INV_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_IN_INV_W::new(self, 13)
     }
     #[doc = "Bits 14:21 - temperature sensor clock divider"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_clk_div(&mut self) -> SAR_TSENS_CLK_DIV_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_CLK_DIV_W::new(self, 14)
     }
     #[doc = "Bit 22 - temperature sensor power up"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_power_up(&mut self) -> SAR_TSENS_POWER_UP_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_POWER_UP_W::new(self, 22)
     }
-    #[doc = "Bit 23 - 1: dump out &amp; power up controlled by SW 0: by FSM"]
+    #[doc = "Bit 23 - 1: dump out & power up controlled by SW 0: by FSM"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_power_up_force(&mut self) -> SAR_TSENS_POWER_UP_FORCE_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_POWER_UP_FORCE_W::new(self, 23)
     }
     #[doc = "Bit 24 - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_dump_out(&mut self) -> SAR_TSENS_DUMP_OUT_W<SAR_TSENS_CTRL_SPEC> {
         SAR_TSENS_DUMP_OUT_W::new(self, 24)
     }
diff --git a/esp32s3/src/sens/sar_tsens_ctrl2.rs b/esp32s3/src/sens/sar_tsens_ctrl2.rs
index 6a04917766..8eaa336a2a 100644
--- a/esp32s3/src/sens/sar_tsens_ctrl2.rs
+++ b/esp32s3/src/sens/sar_tsens_ctrl2.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_xpd_wait(&mut self) -> SAR_TSENS_XPD_WAIT_W<SAR_TSENS_CTRL2_SPEC> {
         SAR_TSENS_XPD_WAIT_W::new(self, 0)
     }
     #[doc = "Bits 12:13 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_xpd_force(&mut self) -> SAR_TSENS_XPD_FORCE_W<SAR_TSENS_CTRL2_SPEC> {
         SAR_TSENS_XPD_FORCE_W::new(self, 12)
     }
     #[doc = "Bit 14 - no public"]
     #[inline(always)]
-    #[must_use]
     pub fn sar_tsens_clk_inv(&mut self) -> SAR_TSENS_CLK_INV_W<SAR_TSENS_CTRL2_SPEC> {
         SAR_TSENS_CLK_INV_W::new(self, 14)
     }
diff --git a/esp32s3/src/sensitive/apb_peripheral_access_0.rs b/esp32s3/src/sensitive/apb_peripheral_access_0.rs
index 8c0e7f6378..bf18831054 100644
--- a/esp32s3/src/sensitive/apb_peripheral_access_0.rs
+++ b/esp32s3/src/sensitive/apb_peripheral_access_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock APB peripheral Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peripheral_access_lock(
         &mut self,
     ) -> APB_PERIPHERAL_ACCESS_LOCK_W<APB_PERIPHERAL_ACCESS_0_SPEC> {
diff --git a/esp32s3/src/sensitive/apb_peripheral_access_1.rs b/esp32s3/src/sensitive/apb_peripheral_access_1.rs
index c0f0668115..167704e5bb 100644
--- a/esp32s3/src/sensitive/apb_peripheral_access_1.rs
+++ b/esp32s3/src/sensitive/apb_peripheral_access_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to support split function for AHB access to APB peripherals."]
     #[inline(always)]
-    #[must_use]
     pub fn apb_peripheral_access_split_burst(
         &mut self,
     ) -> APB_PERIPHERAL_ACCESS_SPLIT_BURST_W<APB_PERIPHERAL_ACCESS_1_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
index da6cfe7ee0..94fa9b08c3 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock BackUp permission configuration registers."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_lock(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_LOCK_W<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
index 60c31eaa7b..c8d1734755 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
@@ -183,7 +183,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - BackUp access uart permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_uart(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_UART_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -191,7 +190,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - BackUp access g0spi_1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_g0spi_1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -199,7 +197,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - BackUp access g0spi_0 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_g0spi_0(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -207,7 +204,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - BackUp access gpio permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_gpio(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_GPIO_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -215,7 +211,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - BackUp access fe2 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_fe2(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_FE2_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -223,7 +218,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - BackUp access fe permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_fe(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_FE_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -231,7 +225,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - BackUp access rtc permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rtc(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RTC_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -239,7 +232,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - BackUp access io_mux permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_io_mux(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -247,7 +239,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - BackUp access hinf permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_hinf(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_HINF_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -255,7 +246,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - BackUp access misc permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_misc(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_MISC_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -263,7 +253,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - BackUp access i2c permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_i2c(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -271,7 +260,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - BackUp access i2s0 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_i2s0(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_I2S0_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
@@ -279,7 +267,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - BackUp access uart1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_uart1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_UART1_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
index 430481dc85..749e96f648 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
@@ -196,7 +196,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - BackUp access bt permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_bt(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_BT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -204,7 +203,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - BackUp access i2c_ext0 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_i2c_ext0(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -212,7 +210,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - BackUp access uhci0 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_uhci0(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_UHCI0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -220,7 +217,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - BackUp access slchost permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_slchost(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -228,7 +224,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - BackUp access rmt permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rmt(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RMT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -236,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - BackUp access pcnt permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_pcnt(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_PCNT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -244,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - BackUp access slc permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_slc(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SLC_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -252,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - BackUp access ledc permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_ledc(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_LEDC_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -260,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - BackUp access backup permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_backup(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_BACKUP_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -268,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - BackUp access bb permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_bb(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_BB_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -276,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - BackUp access pwm0 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_pwm0(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_PWM0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -284,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - BackUp access timergroup permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_timergroup(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -292,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - BackUp access timergroup1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_timergroup1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
@@ -300,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - BackUp access systimer permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_systimer(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
index bf7233ca93..62019e179e 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
@@ -170,7 +170,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - BackUp access spi_2 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_spi_2(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_2_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -178,7 +177,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - BackUp access spi_3 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_spi_3(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_3_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -186,7 +184,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - BackUp access apb_ctrl permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_apb_ctrl(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -194,7 +191,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - BackUp access i2c_ext1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_i2c_ext1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -202,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - BackUp access sdio_host permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_sdio_host(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -210,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - BackUp access can permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_can(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_CAN_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -218,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - BackUp access pwm1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_pwm1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_PWM1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -226,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - BackUp access i2s1 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_i2s1(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_I2S1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -234,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - BackUp access uart2 permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_uart2(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_UART2_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -242,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - BackUp access rwbt permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rwbt(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RWBT_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -250,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - BackUp access wifimac permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_wifimac(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
@@ -258,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - BackUp access pwr permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_pwr(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_PWR_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
index ae3fa57833..ec4f627565 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
@@ -224,7 +224,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - BackUp access usb_device permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_usb_device(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -232,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - BackUp access usb_wrap permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_usb_wrap(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -240,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - BackUp access crypto_peri permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_crypto_peri(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -248,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - BackUp access crypto_dma permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_crypto_dma(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -256,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - BackUp access apb_adc permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_apb_adc(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -264,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - BackUp access lcd_cam permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_lcd_cam(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -272,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - BackUp access bt_pwr permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_bt_pwr(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -280,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - BackUp access usb permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_usb(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_USB_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -288,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - BackUp access system permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_system(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -296,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - BackUp access sensitive permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_sensitive(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -304,7 +294,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - BackUp access interrupt permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_interrupt(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -312,7 +301,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - BackUp access dma_copy permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_dma_copy(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -320,7 +308,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - BackUp access cache_config permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_cache_config(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -328,7 +315,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - BackUp access ad permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_ad(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_AD_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -336,7 +322,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - BackUp access dio permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_dio(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_DIO_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
@@ -344,7 +329,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - BackUp access world_controller permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_world_controller(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
index 0e911ff96d..c915780260 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
@@ -30,7 +30,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - BackUp access rtcfast_spltaddr permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rtcfast_spltaddr(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_W<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
index c83491b5a3..9503704f52 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - BackUp access rtcfast_l permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rtcfast_l(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_W<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - BackUp access rtcfast_h permission."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_constrain_rtcfast_h(
         &mut self,
     ) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_W<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
index 56e0ebcc79..d4a134899e 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock BackUp permission report registers."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_monitor_lock(
         &mut self,
     ) -> BACKUP_BUS_PMS_MONITOR_LOCK_W<BACKUP_BUS_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
index 86b206502c..f13e45dd1f 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that BackUp initiate illegal access."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_monitor_violate_clr(
         &mut self,
     ) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_W<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable interrupt that BackUp initiate illegal access."]
     #[inline(always)]
-    #[must_use]
     pub fn backup_bus_pms_monitor_violate_en(
         &mut self,
     ) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_W<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/cache_dataarray_connect_0.rs b/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
index 8c5ecc3435..c88be93372 100644
--- a/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
+++ b/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache data array registers."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_dataarray_connect_lock(
         &mut self,
     ) -> CACHE_DATAARRAY_CONNECT_LOCK_W<CACHE_DATAARRAY_CONNECT_0_SPEC> {
diff --git a/esp32s3/src/sensitive/cache_dataarray_connect_1.rs b/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
index e4a7b47427..613541f816 100644
--- a/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
+++ b/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Cache data array connection configuration."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_dataarray_connect_flatten(
         &mut self,
     ) -> CACHE_DATAARRAY_CONNECT_FLATTEN_W<CACHE_DATAARRAY_CONNECT_1_SPEC> {
diff --git a/esp32s3/src/sensitive/cache_mmu_access_0.rs b/esp32s3/src/sensitive/cache_mmu_access_0.rs
index ea1ac314d5..035cae60ad 100644
--- a/esp32s3/src/sensitive/cache_mmu_access_0.rs
+++ b/esp32s3/src/sensitive/cache_mmu_access_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache MMU registers."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_mmu_access_lock(&mut self) -> CACHE_MMU_ACCESS_LOCK_W<CACHE_MMU_ACCESS_0_SPEC> {
         CACHE_MMU_ACCESS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/cache_mmu_access_1.rs b/esp32s3/src/sensitive/cache_mmu_access_1.rs
index b0f174e307..4b1145f0b6 100644
--- a/esp32s3/src/sensitive/cache_mmu_access_1.rs
+++ b/esp32s3/src/sensitive/cache_mmu_access_1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable read access MMU memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mmu_rd_acs(&mut self) -> PRO_MMU_RD_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
         PRO_MMU_RD_ACS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to enable write access MMU memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_mmu_wr_acs(&mut self) -> PRO_MMU_WR_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
         PRO_MMU_WR_ACS_W::new(self, 1)
     }
diff --git a/esp32s3/src/sensitive/cache_tag_access_0.rs b/esp32s3/src/sensitive/cache_tag_access_0.rs
index 5e57791048..c0113518cf 100644
--- a/esp32s3/src/sensitive/cache_tag_access_0.rs
+++ b/esp32s3/src/sensitive/cache_tag_access_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache tag Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_tag_access_lock(&mut self) -> CACHE_TAG_ACCESS_LOCK_W<CACHE_TAG_ACCESS_0_SPEC> {
         CACHE_TAG_ACCESS_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/cache_tag_access_1.rs b/esp32s3/src/sensitive/cache_tag_access_1.rs
index cefc79cd23..683eec61a4 100644
--- a/esp32s3/src/sensitive/cache_tag_access_1.rs
+++ b/esp32s3/src/sensitive/cache_tag_access_1.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable Icache read access tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i_tag_rd_acs(&mut self) -> PRO_I_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_I_TAG_RD_ACS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to enable Icache wrtie access tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_i_tag_wr_acs(&mut self) -> PRO_I_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_I_TAG_WR_ACS_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to enable Dcache read access tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_d_tag_rd_acs(&mut self) -> PRO_D_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_D_TAG_RD_ACS_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to enable Dcache wrtie access tag memory."]
     #[inline(always)]
-    #[must_use]
     pub fn pro_d_tag_wr_acs(&mut self) -> PRO_D_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
         PRO_D_TAG_WR_ACS_W::new(self, 3)
     }
diff --git a/esp32s3/src/sensitive/clock_gate.rs b/esp32s3/src/sensitive/clock_gate.rs
index daa253321a..8b01d1ef22 100644
--- a/esp32s3/src/sensitive/clock_gate.rs
+++ b/esp32s3/src/sensitive/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable clock gate function."]
     #[inline(always)]
-    #[must_use]
     pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W<CLOCK_GATE_SPEC> {
         REG_CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
index 9c3aa7bcdc..3abb2e8346 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 dram0 permission monitor configuration register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_pms_monitor_lock(
         &mut self,
     ) -> CORE_0_DRAM0_PMS_MONITOR_LOCK_W<CORE_0_DRAM0_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
index a54a00a526..ce62a0a895 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core0 dram0 permission monior interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable core0 dram0 permission monitor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_dram0_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
index db7cdb6165..e058f621c7 100644
--- a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 iram0 permission monitor register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_pms_monitor_lock(
         &mut self,
     ) -> CORE_0_IRAM0_PMS_MONITOR_LOCK_W<CORE_0_IRAM0_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
index ee76fafdc1..ba2ca86e36 100644
--- a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core0 iram0 permission violated interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_iram0_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
index faccc3ce26..901833b40b 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 access peripherals permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_lock(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_LOCK_W<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
index fde0f3adbd..a756367aaf 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
@@ -191,7 +191,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access uart permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_uart(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -199,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -207,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -215,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access gpio permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_gpio(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -223,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access fe2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_fe2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -231,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access fe permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_fe(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -239,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access rtc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_rtc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -247,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access io_mux permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_io_mux(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -255,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core0 access hinf permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_hinf(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -263,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access misc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_misc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -271,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access i2c permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_i2c(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -279,7 +268,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access i2s0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_i2s0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -287,7 +275,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access uart1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_uart1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
index d72bc533f7..9cc2779450 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_world_0_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_world_0_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_world_1_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_world_1_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
index 6db041d8d4..0cc7edb314 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>
@@ -57,7 +56,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
index 359f45004f..099efdb46c 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
index ab9b47070d..9c2bd7958c 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>
@@ -57,7 +56,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
index 8cb06174bc..0e6ea92daa 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_l(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_h(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
index 260c3716f8..60f2691481 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
@@ -210,7 +210,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access bt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_bt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -218,7 +217,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_i2c_ext0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -226,7 +224,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access uhci0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_uhci0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -234,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access slchost permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_slchost(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -242,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access rmt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_rmt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -250,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access pcnt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_pcnt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -258,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access slc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_slc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -266,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access ledc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_ledc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -274,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core0 access backup permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_backup(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -282,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access bb permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_bb(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -290,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access pwm0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_pwm0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -298,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access timergroup permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_timergroup(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -306,7 +294,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access timergroup1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_timergroup1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -314,7 +301,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access systimer permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_systimer(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
index 28145c0743..3b4dec85e9 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
@@ -184,7 +184,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access spi_2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_spi_2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -192,7 +191,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access spi_3 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_spi_3(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -200,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_apb_ctrl(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -208,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_i2c_ext1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -216,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access sdio_host permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_sdio_host(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -224,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access can permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_can(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -232,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access pwm1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_pwm1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -240,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access i2s1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_i2s1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -248,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access uart2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_uart2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -256,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access rwbt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_rwbt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -264,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access wifimac permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_wifimac(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -272,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access pwr permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_pwr(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
index f34fb1763a..a184f8a3db 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
@@ -249,7 +249,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access usb_device permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_usb_device(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -257,7 +256,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access usb_wrap permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_usb_wrap(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -265,7 +263,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access crypto_peri permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_crypto_peri(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -273,7 +270,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access crypto_dma permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_crypto_dma(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -281,7 +277,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access apb_adc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_apb_adc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -289,7 +284,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access lcd_cam permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_lcd_cam(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -297,7 +291,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access bt_pwr permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_bt_pwr(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -305,7 +298,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access usb permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_usb(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -313,7 +305,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access system permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_system(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -321,7 +312,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core0 access sensitive permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_sensitive(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -329,7 +319,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core0 access interrupt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_interrupt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -337,7 +326,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access dma_copy permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_dma_copy(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -345,7 +333,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access cache_config permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_cache_config(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -353,7 +340,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access ad permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_ad(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -361,7 +347,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access dio permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_dio(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -369,7 +354,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access world_controller permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_0_world_controller(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
index ec7e7e13bb..c10e32cc41 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
@@ -191,7 +191,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access uart permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_uart(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -199,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_g0spi_1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -207,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_g0spi_0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -215,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access gpio permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_gpio(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -223,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access fe2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_fe2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -231,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access fe permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_fe(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -239,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access rtc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_rtc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -247,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access io_mux permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_io_mux(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -255,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core0 access hinf permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_hinf(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -263,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access misc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_misc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -271,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access i2c permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_i2c(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -279,7 +268,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access i2s0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_i2s0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -287,7 +275,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access uart1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_uart1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
index fb4af29a9f..58422e31f0 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
@@ -210,7 +210,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access bt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_bt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -218,7 +217,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_i2c_ext0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -226,7 +224,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access uhci0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_uhci0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -234,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access slchost permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_slchost(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -242,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access rmt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_rmt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -250,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access pcnt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_pcnt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -258,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access slc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_slc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -266,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access ledc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_ledc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -274,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core0 access backup permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_backup(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -282,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access bb permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_bb(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -290,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access pwm0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_pwm0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -298,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access timergroup permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_timergroup(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -306,7 +294,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access timergroup1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_timergroup1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -314,7 +301,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access systimer permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_systimer(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
index 7eece30486..7f37db940b 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
@@ -184,7 +184,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_spi_2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -192,7 +191,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access spi_3 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_spi_3(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -200,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_apb_ctrl(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -208,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_i2c_ext1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -216,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access sdio_host permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_sdio_host(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -224,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access can permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_can(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -232,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access pwm1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_pwm1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -240,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access i2s1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_i2s1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -248,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access uart2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_uart2(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -256,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access rwbt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_rwbt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -264,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access wifimac permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_wifimac(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -272,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access pwr permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_pwr(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
index 60cd00d3db..fb258c063c 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
@@ -249,7 +249,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core0 access usb_device permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_usb_device(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -257,7 +256,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core0 access usb_wrap permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_usb_wrap(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -265,7 +263,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core0 access crypto_peri permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_crypto_peri(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -273,7 +270,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core0 access crypto_dma permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_crypto_dma(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -281,7 +277,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core0 access apb_adc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_apb_adc(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -289,7 +284,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core0 access lcd_cam permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_lcd_cam(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -297,7 +291,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core0 access bt_pwr permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_bt_pwr(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -305,7 +298,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core0 access usb permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_usb(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -313,7 +305,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core0 access system permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_system(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -321,7 +312,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core0 access sensitive permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_sensitive(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -329,7 +319,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core0 access interrupt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_interrupt(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -337,7 +326,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core0 access dma_copy permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_dma_copy(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -345,7 +333,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core0 access cache_config permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_cache_config(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -353,7 +340,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core0 access ad permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_ad(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -361,7 +347,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core0 access dio permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_dio(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -369,7 +354,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core0 access world_controller permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_world_1_world_controller(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
index 3ab4c61dce..8cc38be534 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
@@ -56,7 +55,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(
         &mut self,
     ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
index 28af291737..ed8497ccca 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 permission report registers."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_lock(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_LOCK_W<CORE_0_PIF_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
index 815d541984..f0bc418f2a 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate illegal PIF bus access."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_W<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
index c66ce3ebf5..944ab4a143 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
@@ -44,7 +44,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate unsupported access type."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_nonword_violate_clr(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
@@ -52,7 +51,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate unsupported access type."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_pif_pms_monitor_nonword_violate_en(
         &mut self,
     ) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
index 6fc37c01d0..f3e4eaab2f 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 region permission registers."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_lock(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_LOCK_W<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
index a2e8e83785..0005f3a4ec 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
@@ -179,7 +179,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_0(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -187,7 +186,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Region 1 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_1(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -195,7 +193,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Region 2 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_2(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -203,7 +200,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Region 3 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_3(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -211,7 +207,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Region 4 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_4(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -219,7 +214,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Region 5 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_5(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -227,7 +221,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Region 6 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_6(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -235,7 +228,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Region 7 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_7(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -243,7 +235,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Region 8 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_8(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -251,7 +242,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Region 9 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_9(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -259,7 +249,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Region 10 permission in world 0 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_0_area_10(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
index a13712d7e6..9d2589a91c 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_7(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_W<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
index e3a2f9ead3..c06a8bae02 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_8(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_W<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
index 45efd90e6c..384e01d9ac 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_9(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_W<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
index ec3b20923b..3db34115c4 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_10(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_W<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
index f0d8434fbf..fad0cdbce8 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 10 end address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_11(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_W<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
index 3c6dfdd863..06e03db3be 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
@@ -179,7 +179,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_0(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -187,7 +186,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Region 1 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_1(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -195,7 +193,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Region 2 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_2(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -203,7 +200,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Region 3 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_3(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -211,7 +207,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Region 4 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_4(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -219,7 +214,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Region 5 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_5(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -227,7 +221,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Region 6 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_6(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -235,7 +228,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Region 7 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_7(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -243,7 +235,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Region 8 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_8(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -251,7 +242,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Region 9 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_9(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -259,7 +249,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Region 10 permission in world 1 for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_world_1_area_10(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
index f68df7f0ce..0e56405735 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 0 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_0(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_W<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
index bede420e6c..c8743c4f97 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_1(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_W<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
index f17beb79e2..0995413ec4 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_2(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_W<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
index 12c1edc3d3..279b335978 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_3(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_W<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
index cc15f15273..b722d3a4c5 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_4(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_W<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
index c5540e4e4b..3875d106c2 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_5(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_W<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
index cb568c5560..70516b3d0c 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_region_pms_constrain_addr_6(
         &mut self,
     ) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_W<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
index 060219f5c9..6fd8021936 100644
--- a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
+++ b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 toomanyexception override configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_toomanyexceptions_m_override_lock(
         &mut self,
     ) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>
diff --git a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
index cd831c4b11..4d19f86145 100644
--- a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
+++ b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to mask toomanyexception."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_toomanyexceptions_m_override(
         &mut self,
     ) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_0.rs b/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
index 68cd11b7db..45dde320be 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_vecbase_world_mask(
         &mut self,
     ) -> CORE_0_VECBASE_WORLD_MASK_W<CORE_0_VECBASE_OVERRIDE_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_1.rs b/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
index bf846f3a65..013be2abf4 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_vecbase_override_world0_value(
         &mut self,
     ) -> CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_W<CORE_0_VECBASE_OVERRIDE_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Set 0x3 to sel vecbase_override to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_vecbase_override_sel(
         &mut self,
     ) -> CORE_0_VECBASE_OVERRIDE_SEL_W<CORE_0_VECBASE_OVERRIDE_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_2.rs b/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
index 76ac991405..d419d8e27d 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_vecbase_override_world1_value(
         &mut self,
     ) -> CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_W<CORE_0_VECBASE_OVERRIDE_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs b/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
index a1d7daa43f..d32d93ad58 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 vecbase configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_vecbase_override_lock(
         &mut self,
     ) -> CORE_0_VECBASE_OVERRIDE_LOCK_W<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
index 0318ad5806..75f6305860 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 dram0 permission monitor configuration register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_pms_monitor_lock(
         &mut self,
     ) -> CORE_1_DRAM0_PMS_MONITOR_LOCK_W<CORE_1_DRAM0_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
index 3621b4a349..23d7b455c1 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable core1 dram0 permission monitor interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_dram0_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
index a09c3c082a..2502d0f13a 100644
--- a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 iram0 permission monitor register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_pms_monitor_lock(
         &mut self,
     ) -> CORE_1_IRAM0_PMS_MONITOR_LOCK_W<CORE_1_IRAM0_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
index 9c90178ee8..5e06f338ff 100644
--- a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core1 iram0 permission violated interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_IRAM0_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_iram0_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_1_IRAM0_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
index 7b2f985b4c..0698e9d4e2 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 pif permission configuration register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_lock(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_LOCK_W<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
index 612bc65663..63f240d6ae 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
@@ -191,7 +191,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access uart permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_uart(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -199,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_g0spi_1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -207,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_g0spi_0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -215,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access gpio permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_gpio(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -223,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access fe2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_fe2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -231,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access fe permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_fe(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -239,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access rtc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_rtc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -247,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access io_mux permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_io_mux(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -255,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core1 access hinf permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_hinf(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -263,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access misc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_misc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -271,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access i2c permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_i2c(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -279,7 +268,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access i2s0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_i2s0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
@@ -287,7 +275,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access uart1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_uart1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
index 83e62da609..70c209738c 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_world_0_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_world_0_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_world_1_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_world_1_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
index c2c7ad67d1..17bd71389d 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>
@@ -57,7 +56,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
index 83962299f0..a08cc26f2d 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
index 3b7294c778..5033be1b95 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>
@@ -57,7 +56,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
index 400d22a76b..c4495db563 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
@@ -74,7 +74,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -82,7 +81,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -90,7 +88,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_l(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
@@ -98,7 +95,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_h(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
index 2c4215860a..e1e9851114 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
@@ -210,7 +210,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access bt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_bt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -218,7 +217,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_i2c_ext0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -226,7 +224,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access uhci0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_uhci0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -234,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access slchost permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_slchost(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -242,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access rmt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_rmt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -250,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access pcnt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_pcnt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -258,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access slc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_slc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -266,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access ledc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_ledc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -274,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core1 access backup permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_backup(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -282,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access bb permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_bb(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -290,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access pwm0 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_pwm0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -298,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access timergroup permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_timergroup(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -306,7 +294,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access timergroup1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_timergroup1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
@@ -314,7 +301,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access systimer permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_systimer(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
index f4aa7afe64..7c2a99c273 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
@@ -184,7 +184,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access spi_2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_spi_2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -192,7 +191,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access spi_3 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_spi_3(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -200,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_apb_ctrl(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -208,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_i2c_ext1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -216,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access sdio_host permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_sdio_host(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -224,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access can permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_can(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -232,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access pwm1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_pwm1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -240,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access i2s1 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_i2s1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -248,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access uart2 permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_uart2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -256,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access rwbt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_rwbt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -264,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access wifimac permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_wifimac(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
@@ -272,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access pwr permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_pwr(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
index f74f976115..4a94655db2 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
@@ -249,7 +249,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access usb_device permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_usb_device(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -257,7 +256,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access usb_wrap permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_usb_wrap(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -265,7 +263,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access crypto_peri permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_crypto_peri(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -273,7 +270,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access crypto_dma permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_crypto_dma(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -281,7 +277,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access apb_adc permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_apb_adc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -289,7 +284,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access lcd_cam permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_lcd_cam(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -297,7 +291,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access bt_pwr permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_bt_pwr(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -305,7 +298,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access usb permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_usb(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -313,7 +305,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access system permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_system(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -321,7 +312,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core1 access sensitive permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_sensitive(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -329,7 +319,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core1 access interrupt permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_interrupt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -337,7 +326,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access dma_copy permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_dma_copy(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -345,7 +333,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access cache_config permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_cache_config(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -353,7 +340,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access ad permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_ad(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -361,7 +347,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access dio permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_dio(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
@@ -369,7 +354,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access world_controller permission in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_0_world_controller(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
index 6f2dfef043..2d78bb921e 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
@@ -191,7 +191,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access uart permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_uart(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -199,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_g0spi_1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -207,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_g0spi_0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -215,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access gpio permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_gpio(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -223,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access fe2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_fe2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -231,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access fe permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_fe(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -239,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access rtc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_rtc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -247,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access io_mux permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_io_mux(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -255,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core1 access hinf permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_hinf(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -263,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access misc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_misc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -271,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access i2c permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_i2c(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -279,7 +268,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access i2s0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_i2s0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
@@ -287,7 +275,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access uart1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_uart1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
index e2e7cf6efc..e36984bb6e 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
@@ -210,7 +210,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access bt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_bt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -218,7 +217,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_i2c_ext0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -226,7 +224,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access uhci0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_uhci0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -234,7 +231,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access slchost permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_slchost(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -242,7 +238,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access rmt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_rmt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -250,7 +245,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access pcnt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_pcnt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -258,7 +252,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access slc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_slc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -266,7 +259,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access ledc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_ledc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -274,7 +266,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core1 access backup permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_backup(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -282,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access bb permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_bb(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -290,7 +280,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access pwm0 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_pwm0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -298,7 +287,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access timergroup permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_timergroup(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -306,7 +294,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access timergroup1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_timergroup1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
@@ -314,7 +301,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access systimer permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_systimer(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
index 43b068fcb1..89e450a1b0 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
@@ -184,7 +184,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access spi_2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_spi_2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -192,7 +191,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access spi_3 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_spi_3(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -200,7 +198,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_apb_ctrl(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -208,7 +205,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_i2c_ext1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -216,7 +212,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access sdio_host permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_sdio_host(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -224,7 +219,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access can permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_can(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -232,7 +226,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access pwm1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_pwm1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -240,7 +233,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access i2s1 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_i2s1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -248,7 +240,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access uart2 permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_uart2(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -256,7 +247,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access rwbt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_rwbt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -264,7 +254,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access wifimac permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_wifimac(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
@@ -272,7 +261,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access pwr permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_pwr(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
index 253729eb0f..135ff6d136 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
@@ -249,7 +249,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Core1 access usb_device permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_usb_device(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -257,7 +256,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Core1 access usb_wrap permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_usb_wrap(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -265,7 +263,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Core1 access crypto_peri permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_crypto_peri(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -273,7 +270,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Core1 access crypto_dma permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_crypto_dma(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -281,7 +277,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Core1 access apb_adc permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_apb_adc(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -289,7 +284,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Core1 access lcd_cam permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_lcd_cam(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -297,7 +291,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Core1 access bt_pwr permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_bt_pwr(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -305,7 +298,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Core1 access usb permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_usb(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -313,7 +305,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Core1 access system permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_system(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -321,7 +312,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Core1 access sensitive permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_sensitive(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -329,7 +319,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Core1 access interrupt permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_interrupt(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -337,7 +326,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Core1 access dma_copy permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_dma_copy(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -345,7 +333,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - Core1 access cache_config permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_cache_config(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -353,7 +340,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - Core1 access ad permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_ad(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -361,7 +347,6 @@ impl W {
     }
     #[doc = "Bits 28:29 - Core1 access dio permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_dio(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
@@ -369,7 +354,6 @@ impl W {
     }
     #[doc = "Bits 30:31 - Core1 access world_controller permission in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_world_1_world_controller(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
index 471ecd0de0..8c43b67a4d 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
@@ -48,7 +48,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_0(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC> {
@@ -56,7 +55,6 @@ impl W {
     }
     #[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_1(
         &mut self,
     ) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
index 9b0c0d5e41..94e797653f 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 permission report registers."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_lock(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_LOCK_W<CORE_1_PIF_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
index de902f5378..ecc0df814b 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_clr(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_PIF_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate illegal PIF bus access."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_violate_en(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_W<CORE_1_PIF_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
index 3ddd88d623..9e5f66efc5 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
@@ -44,7 +44,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate unsupported access type."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_nonword_violate_clr(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<CORE_1_PIF_PMS_MONITOR_4_SPEC> {
@@ -52,7 +51,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate unsupported access type."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_pif_pms_monitor_nonword_violate_en(
         &mut self,
     ) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<CORE_1_PIF_PMS_MONITOR_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
index e91a2d18f5..5bc4366812 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 region permission registers."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_lock(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_LOCK_W<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
index bd3fd579da..dc0933908f 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
@@ -179,7 +179,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_0(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -187,7 +186,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Region 1 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_1(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -195,7 +193,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Region 2 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_2(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -203,7 +200,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Region 3 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_3(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -211,7 +207,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Region 4 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_4(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -219,7 +214,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Region 5 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_5(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -227,7 +221,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Region 6 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_6(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -235,7 +228,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Region 7 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_7(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -243,7 +235,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Region 8 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_8(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -251,7 +242,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Region 9 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_9(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
@@ -259,7 +249,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Region 10 permission in world 0 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_0_area_10(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_W<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
index 297467df8f..7059bc350c 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_7(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_W<CORE_1_REGION_PMS_CONSTRAIN_10_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
index 3653d3a32e..2c3bbb0c7a 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_8(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_W<CORE_1_REGION_PMS_CONSTRAIN_11_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
index 8cca7db979..f8ce493bf2 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_9(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_W<CORE_1_REGION_PMS_CONSTRAIN_12_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
index 3556f74e66..6f83ca0fba 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_10(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_W<CORE_1_REGION_PMS_CONSTRAIN_13_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
index f028101836..478664477f 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 10 end address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_11(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_W<CORE_1_REGION_PMS_CONSTRAIN_14_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
index 233207f50f..e73e6d4ac3 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
@@ -179,7 +179,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_0(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -187,7 +186,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Region 1 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_1(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -195,7 +193,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - Region 2 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_2(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -203,7 +200,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - Region 3 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_3(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -211,7 +207,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - Region 4 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_4(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -219,7 +214,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - Region 5 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_5(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -227,7 +221,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - Region 6 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_6(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -235,7 +228,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Region 7 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_7(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -243,7 +235,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Region 8 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_8(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -251,7 +242,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - Region 9 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_9(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
@@ -259,7 +249,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - Region 10 permission in world 1 for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_world_1_area_10(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_W<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
index a6cd728344..8c8a42af6d 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 0 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_0(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_W<CORE_1_REGION_PMS_CONSTRAIN_3_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
index 62b95fd715..7e0fcf9e03 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_1(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_W<CORE_1_REGION_PMS_CONSTRAIN_4_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
index f5f50f16a8..3760d7af4d 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_2(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_W<CORE_1_REGION_PMS_CONSTRAIN_5_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
index e3d94ac146..6808c033b8 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_3(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_W<CORE_1_REGION_PMS_CONSTRAIN_6_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
index 2661e892b1..8873c10dfb 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_4(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_W<CORE_1_REGION_PMS_CONSTRAIN_7_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
index 91bd7bc949..44db8322f4 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_5(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_W<CORE_1_REGION_PMS_CONSTRAIN_8_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
index 392b06cdb9..61953fd1a2 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_region_pms_constrain_addr_6(
         &mut self,
     ) -> CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_W<CORE_1_REGION_PMS_CONSTRAIN_9_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
index f1a3bf9cf8..1a3712058e 100644
--- a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
+++ b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 toomanyexception override configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_toomanyexceptions_m_override_lock(
         &mut self,
     ) -> CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_W<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>
diff --git a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
index 8a6d6056b9..1a25e6d44a 100644
--- a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
+++ b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to mask toomanyexception."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_toomanyexceptions_m_override(
         &mut self,
     ) -> CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_W<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_0.rs b/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
index ae99575dc0..3e9c55250d 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_vecbase_world_mask(
         &mut self,
     ) -> CORE_1_VECBASE_WORLD_MASK_W<CORE_1_VECBASE_OVERRIDE_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_1.rs b/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
index 037b5b2a81..c0b98f8b46 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - world0 vecbase_override register, when core1 in world0 use this register to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_vecbase_override_world0_value(
         &mut self,
     ) -> CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_W<CORE_1_VECBASE_OVERRIDE_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - Set 0x3 to sel vecbase_override to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_vecbase_override_sel(
         &mut self,
     ) -> CORE_1_VECBASE_OVERRIDE_SEL_W<CORE_1_VECBASE_OVERRIDE_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_2.rs b/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
index f585a559cd..84a00cad83 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - world1 vecbase_override register, when core1 in world1 use this register to override vecbase register."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_vecbase_override_world1_value(
         &mut self,
     ) -> CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_W<CORE_1_VECBASE_OVERRIDE_2_SPEC> {
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs b/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
index e7d976227d..43d3e73f39 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 vecbase configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_vecbase_override_lock(
         &mut self,
     ) -> CORE_1_VECBASE_OVERRIDE_LOCK_W<CORE_1_VECBASE_OVERRIDE_LOCK_SPEC> {
diff --git a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
index bb557ed046..5aaa1bed00 100644
--- a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock corex dram0 permission configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_lock(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_W<CORE_X_DRAM0_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
index cbad0aa9c2..0e1779380f 100644
--- a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
@@ -236,7 +236,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - core0/core1's permission of data region0 of SRAM in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_pms_0(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -244,7 +243,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - core0/core1's permission of data region1 of SRAM in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_pms_1(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -252,7 +250,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - core0/core1's permission of data region2 of SRAM in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_pms_2(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -260,7 +257,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - core0/core1's permission of data region3 of SRAM in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_pms_3(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -268,7 +264,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - core0/core1's permission of dcache data sram block0 in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_W<
@@ -278,7 +273,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - core0/core1's permission of dcache data sram block1 in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_W<
@@ -288,7 +282,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - core0/core1's permission of data region0 of SRAM in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_pms_0(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -296,7 +289,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - core0/core1's permission of data region1 of SRAM in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_pms_1(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -304,7 +296,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - core0/core1's permission of data region2 of SRAM in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_pms_2(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -312,7 +303,6 @@ impl W {
     }
     #[doc = "Bits 18:19 - core0/core1's permission of data region3 of SRAM in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_pms_3(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -320,7 +310,6 @@ impl W {
     }
     #[doc = "Bits 20:21 - core0/core1's permission of dcache data sram block0 in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_W<
@@ -330,7 +319,6 @@ impl W {
     }
     #[doc = "Bits 22:23 - core0/core1's permission of dcache data sram block1 in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_W<
@@ -340,7 +328,6 @@ impl W {
     }
     #[doc = "Bits 24:25 - core0/core1's permission(sotre,load) of rom in world0."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_rom_world_0_pms(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -348,7 +335,6 @@ impl W {
     }
     #[doc = "Bits 26:27 - core0/core1's permission(sotre,load) of rom in world1."]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_pms_constrain_rom_world_1_pms(
         &mut self,
     ) -> CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_W<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
index 5b90efe4a6..59e1f85bf7 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sram split configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_split_line_constrain_lock(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_W<
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
index 934eda94ec..de575769ca 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
@@ -132,7 +132,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_0(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -141,7 +140,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_1(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -150,7 +148,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_2(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -159,7 +156,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_3(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -168,7 +164,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_4(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -177,7 +172,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_5(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -186,7 +180,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_category_6(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
@@ -195,7 +188,6 @@ impl W {
     }
     #[doc = "Bits 14:21 - splitaddr of core_x_iram0_dram_dma_line, configured as \\[15:8\\]bit of actual address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_dram0_dma_sram_splitaddr(
         &mut self,
     ) -> CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
index 8257f89d0b..bb5b3cdaff 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
@@ -118,7 +118,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_0(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -127,7 +126,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_1(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -136,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_2(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -145,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_3(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -154,7 +150,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_4(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -163,7 +158,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_5(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -172,7 +166,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_category_6(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
@@ -181,7 +174,6 @@ impl W {
     }
     #[doc = "Bits 14:21 - splitaddr of core_x_iram0_dram_dma_line, configured as \\[15:8\\]bit of actual address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_0_splitaddr(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
index d4de65f449..dfc7b56b17 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
@@ -118,7 +118,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_0(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -127,7 +126,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_1(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -136,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_2(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -145,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_3(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -154,7 +150,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_4(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -163,7 +158,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_5(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -172,7 +166,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_category_6(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
@@ -181,7 +174,6 @@ impl W {
     }
     #[doc = "Bits 14:21 - splitaddr of core_x_iram0_dram_dma_line, configured as \\[15:8\\]bit of actual address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_sram_line_1_splitaddr(
         &mut self,
     ) -> CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
index 60290657ac..43417c7c39 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
@@ -134,7 +134,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_0(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -143,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_1(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -152,7 +150,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_2(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -161,7 +158,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_3(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -170,7 +166,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_4(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -179,7 +174,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_5(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -188,7 +182,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_category_6(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
@@ -197,7 +190,6 @@ impl W {
     }
     #[doc = "Bits 14:21 - splitaddr of core_x_iram0_dram_dma_line, configured as \\[15:8\\]bit of actual address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_0_splitaddr(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
index dd2405d24b..ab1e5265ff 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
@@ -134,7 +134,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_0(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -143,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_1(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -152,7 +150,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_2(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -161,7 +158,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_3(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -170,7 +166,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_4(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -179,7 +174,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_5(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -188,7 +182,6 @@ impl W {
     }
     #[doc = "Bits 12:13 - category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_category_6(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
@@ -197,7 +190,6 @@ impl W {
     }
     #[doc = "Bits 14:21 - splitaddr of core_x_iram0_dram_dma_line, configured as \\[15:8\\]bit of actual address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_dram0_dma_sram_line_1_splitaddr(
         &mut self,
     ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
index b40a360964..ffb97e918d 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock corex iram0 permission configuration register"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_lock(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_W<CORE_X_IRAM0_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
index a94f3710b8..f3573b1745 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
@@ -125,7 +125,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - core0/core1's permission of instruction region0 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_pms_0(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_W<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -133,7 +132,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - core0/core1's permission of instruction region1 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_pms_1(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_W<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -141,7 +139,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - core0/core1's permission of instruction region2 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_pms_2(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_W<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -149,7 +146,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - core0/core1's permission of instruction region3 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_pms_3(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_W<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
@@ -157,7 +153,6 @@ impl W {
     }
     #[doc = "Bits 12:14 - core0/core1's permission of icache data sram block0 in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_W<
@@ -167,7 +162,6 @@ impl W {
     }
     #[doc = "Bits 15:17 - core0/core1's permission of icache data sram block1 in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_W<
@@ -177,7 +171,6 @@ impl W {
     }
     #[doc = "Bits 18:20 - core0/core1's permission of rom in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_rom_world_1_pms(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_W<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
index 6294f67eed..c57c7040e5 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
@@ -125,7 +125,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - core0/core1's permission of instruction region0 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_pms_0(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_W<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
@@ -133,7 +132,6 @@ impl W {
     }
     #[doc = "Bits 3:5 - core0/core1's permission of instruction region1 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_pms_1(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_W<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
@@ -141,7 +139,6 @@ impl W {
     }
     #[doc = "Bits 6:8 - core0/core1's permission of instruction region2 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_pms_2(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_W<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
@@ -149,7 +146,6 @@ impl W {
     }
     #[doc = "Bits 9:11 - core0/core1's permission of instruction region3 of SRAM in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_pms_3(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_W<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
@@ -157,7 +153,6 @@ impl W {
     }
     #[doc = "Bits 12:14 - core0/core1's permission of icache data sram block0 in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_W<
@@ -167,7 +162,6 @@ impl W {
     }
     #[doc = "Bits 15:17 - core0/core1's permission of icache data sram block1 in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_W<
@@ -177,7 +171,6 @@ impl W {
     }
     #[doc = "Bits 18:20 - core0/core1's permission of rom in world1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_x_iram0_pms_constrain_rom_world_0_pms(
         &mut self,
     ) -> CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_W<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
diff --git a/esp32s3/src/sensitive/date.rs b/esp32s3/src/sensitive/date.rs
index 06ddb5249b..619dd2c3b3 100644
--- a/esp32s3/src/sensitive/date.rs
+++ b/esp32s3/src/sensitive/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Sensitive Date register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
index 1ce41c1609..f0ba8cad4e 100644
--- a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock adc_dac dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
index 935b618e44..7a88d712e1 100644
--- a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - adc_dac's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>
@@ -119,7 +118,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - adc_dac's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>
@@ -128,7 +126,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - adc_dac's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>
@@ -137,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - adc_dac's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>
@@ -146,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - adc_dac's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -156,7 +151,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - adc_dac's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
index 068e4860c7..33d00213af 100644
--- a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock aes dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_AES_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
index 24acf3aeb8..4ad1fe35f4 100644
--- a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
@@ -108,7 +108,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - aes's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
@@ -116,7 +115,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - aes's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
@@ -124,7 +122,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - aes's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
@@ -132,7 +129,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - aes's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
@@ -140,7 +136,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - aes's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -150,7 +145,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - aes's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
index 2caf7bfa8b..929a453079 100644
--- a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock backup dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
index 34b3999c5b..949e4c4a11 100644
--- a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - backup's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>
@@ -119,7 +118,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - backup's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>
@@ -128,7 +126,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - backup's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>
@@ -137,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - backup's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>
@@ -146,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - backup's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -156,7 +151,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - backup's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
index 39912d17ec..e6e1135170 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock i2s0 dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
index 352f4ae239..324fa611d7 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - i2s0's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - i2s0's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - i2s0's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - i2s0's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - i2s0's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - i2s0's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
index d46d7a55e4..b33fa810d5 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock i2s1 dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
index c2a5a705ed..7f5f2e8d45 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - i2s1's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - i2s1's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - i2s1's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - i2s1's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - i2s1's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - i2s1's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
index ba51d13051..20a5a9707a 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock lc dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_LC_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
index a723187c58..3999755287 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
@@ -106,7 +106,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - lc's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
@@ -114,7 +113,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - lc's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
@@ -122,7 +120,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - lc's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
@@ -130,7 +127,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - lc's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
@@ -138,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - lc's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC>
@@ -147,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - lc's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC>
diff --git a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
index 756de9acd4..e885ed3f10 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
@@ -29,7 +29,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock lcd_cam dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
index a05e4ff72f..3406d1b684 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - lcd_cam's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>
@@ -119,7 +118,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - lcd_cam's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>
@@ -128,7 +126,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - lcd_cam's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>
@@ -137,7 +134,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - lcd_cam's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>
@@ -146,7 +142,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - lcd_cam's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -156,7 +151,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - lcd_cam's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
index 5d5182bbeb..e731819699 100644
--- a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock mac dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_MAC_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
index 1731a7c06b..47830bd872 100644
--- a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
@@ -108,7 +108,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - mac's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
@@ -116,7 +115,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - mac's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
@@ -124,7 +122,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - mac's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
@@ -132,7 +129,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - mac's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
@@ -140,7 +136,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - mac's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -150,7 +145,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - mac's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
index 2295fbdacb..0b258e72df 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock dma permission monitor Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_pms_monitor_lock(
         &mut self,
     ) -> DMA_APBPERI_PMS_MONITOR_LOCK_W<DMA_APBPERI_PMS_MONITOR_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
index 3af13500b3..5dc0a8ec69 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to clear dma_pms_monitor_violate interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_pms_monitor_violate_clr(
         &mut self,
     ) -> DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_W<DMA_APBPERI_PMS_MONITOR_1_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_pms_monitor_violate_en(
         &mut self,
     ) -> DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_W<DMA_APBPERI_PMS_MONITOR_1_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
index a8ea416ae3..25bbf77fd1 100644
--- a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock rmt dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_RMT_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
index c4dd482834..a88201d3ee 100644
--- a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
@@ -108,7 +108,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - rmt's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC> {
@@ -116,7 +115,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - rmt's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC> {
@@ -124,7 +122,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - rmt's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC> {
@@ -132,7 +129,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - rmt's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC> {
@@ -140,7 +136,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - rmt's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -150,7 +145,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - rmt's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
index 7a430164cc..518bbec608 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sdio dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
index 0c5ed45665..5634e0dcc2 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - sdio's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - sdio's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - sdio's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - sdio's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - sdio's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - sdio's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
index 54282566ee..2c5553dc7d 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sha dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_SHA_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
index ab2ad229c2..79bd1fe233 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
@@ -108,7 +108,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - sha's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
@@ -116,7 +115,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - sha's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
@@ -124,7 +122,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - sha's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
@@ -132,7 +129,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - sha's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
@@ -140,7 +136,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - sha's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -150,7 +145,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - sha's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
index d77099713b..388b5acaac 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock spi2 dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
index 63dc99c934..0beb66c804 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - spi2's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - spi2's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - spi2's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - spi2's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - spi2's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - spi2's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
index 2ec94074db..1151a542cd 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock spi3 dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
index 5948da9825..3bc703165b 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - spi3's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - spi3's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - spi3's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - spi3's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - spi3's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - spi3's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
index be14923020..303e8e771f 100644
--- a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock uhci0 dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
index 40c3f33b62..9769033979 100644
--- a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
@@ -110,7 +110,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - uhci0's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC> {
@@ -118,7 +117,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - uhci0's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC> {
@@ -126,7 +124,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - uhci0's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC> {
@@ -134,7 +131,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - uhci0's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC> {
@@ -142,7 +138,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - uhci0's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -152,7 +147,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - uhci0's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
index ce69ec9820..6e72f96fbb 100644
--- a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock usb dma permission Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_lock(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_W<DMA_APBPERI_USB_PMS_CONSTRAIN_0_SPEC> {
diff --git a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
index aec5287a8d..55f0665485 100644
--- a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
@@ -108,7 +108,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - usb's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_pms_0(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_W<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC> {
@@ -116,7 +115,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - usb's permission(store,load) in data region1 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_pms_1(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_W<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC> {
@@ -124,7 +122,6 @@ impl W {
     }
     #[doc = "Bits 4:5 - usb's permission(store,load) in data region2 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_pms_2(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_W<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC> {
@@ -132,7 +129,6 @@ impl W {
     }
     #[doc = "Bits 6:7 - usb's permission(store,load) in data region3 of SRAM"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_pms_3(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_W<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC> {
@@ -140,7 +136,6 @@ impl W {
     }
     #[doc = "Bits 8:9 - usb's permission(store,load) in dcache data sram block0"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<
@@ -150,7 +145,6 @@ impl W {
     }
     #[doc = "Bits 10:11 - usb's permission(store,load) in dcache data sram block1"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1(
         &mut self,
     ) -> DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<
diff --git a/esp32s3/src/sensitive/edma_boundary_0.rs b/esp32s3/src/sensitive/edma_boundary_0.rs
index b7e2eb7513..3676d8501d 100644
--- a/esp32s3/src/sensitive/edma_boundary_0.rs
+++ b/esp32s3/src/sensitive/edma_boundary_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_boundary_0(&mut self) -> EDMA_BOUNDARY_0_W<EDMA_BOUNDARY_0_SPEC> {
         EDMA_BOUNDARY_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_boundary_1.rs b/esp32s3/src/sensitive/edma_boundary_1.rs
index a47a89b772..e6b6667dd0 100644
--- a/esp32s3/src/sensitive/edma_boundary_1.rs
+++ b/esp32s3/src/sensitive/edma_boundary_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_boundary_1(&mut self) -> EDMA_BOUNDARY_1_W<EDMA_BOUNDARY_1_SPEC> {
         EDMA_BOUNDARY_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_boundary_2.rs b/esp32s3/src/sensitive/edma_boundary_2.rs
index e833e635f5..8db316a6fa 100644
--- a/esp32s3/src/sensitive/edma_boundary_2.rs
+++ b/esp32s3/src/sensitive/edma_boundary_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_boundary_2(&mut self) -> EDMA_BOUNDARY_2_W<EDMA_BOUNDARY_2_SPEC> {
         EDMA_BOUNDARY_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_boundary_lock.rs b/esp32s3/src/sensitive/edma_boundary_lock.rs
index e34654b8f4..988d6623a3 100644
--- a/esp32s3/src/sensitive/edma_boundary_lock.rs
+++ b/esp32s3/src/sensitive/edma_boundary_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA boundary registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_boundary_lock(&mut self) -> EDMA_BOUNDARY_LOCK_W<EDMA_BOUNDARY_LOCK_SPEC> {
         EDMA_BOUNDARY_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_adc_dac.rs b/esp32s3/src/sensitive/edma_pms_adc_dac.rs
index 0438b04d17..a1b9a7986f 100644
--- a/esp32s3/src/sensitive/edma_pms_adc_dac.rs
+++ b/esp32s3/src/sensitive/edma_pms_adc_dac.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_ADC_DAC_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_ADC_DAC_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs b/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
index 7c5aa436f5..c27fc9bfd8 100644
--- a/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-ADC/DAC permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_adc_dac_lock(&mut self) -> EDMA_PMS_ADC_DAC_LOCK_W<EDMA_PMS_ADC_DAC_LOCK_SPEC> {
         EDMA_PMS_ADC_DAC_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_aes.rs b/esp32s3/src/sensitive/edma_pms_aes.rs
index 0ccd8ec783..83f7a8fb44 100644
--- a/esp32s3/src/sensitive/edma_pms_aes.rs
+++ b/esp32s3/src/sensitive/edma_pms_aes.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_AES_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_AES_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_aes_lock.rs b/esp32s3/src/sensitive/edma_pms_aes_lock.rs
index d5fbe57208..f3eed72098 100644
--- a/esp32s3/src/sensitive/edma_pms_aes_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_aes_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-AES permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_aes_lock(&mut self) -> EDMA_PMS_AES_LOCK_W<EDMA_PMS_AES_LOCK_SPEC> {
         EDMA_PMS_AES_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_i2s0.rs b/esp32s3/src/sensitive/edma_pms_i2s0.rs
index 17fcf7d91f..6b87c30247 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s0.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_I2S0_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_I2S0_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs b/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
index 667972e4f7..731bbbc31b 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-I2S0 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_i2s0_lock(&mut self) -> EDMA_PMS_I2S0_LOCK_W<EDMA_PMS_I2S0_LOCK_SPEC> {
         EDMA_PMS_I2S0_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_i2s1.rs b/esp32s3/src/sensitive/edma_pms_i2s1.rs
index e03b7a7bf2..4bbc348a2b 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s1.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_I2S1_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_I2S1_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs b/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
index 123972cc85..24b8289709 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-I2S1 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_i2s1_lock(&mut self) -> EDMA_PMS_I2S1_LOCK_W<EDMA_PMS_I2S1_LOCK_SPEC> {
         EDMA_PMS_I2S1_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_lcd_cam.rs b/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
index 0ee572717b..7b90f3c384 100644
--- a/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
+++ b/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_LCD_CAM_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_LCD_CAM_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs b/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
index bfe76e38e5..e4e3bd1deb 100644
--- a/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-LCD/CAM permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_lcd_cam_lock(&mut self) -> EDMA_PMS_LCD_CAM_LOCK_W<EDMA_PMS_LCD_CAM_LOCK_SPEC> {
         EDMA_PMS_LCD_CAM_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_rmt.rs b/esp32s3/src/sensitive/edma_pms_rmt.rs
index 3bc2457c62..8f578509e0 100644
--- a/esp32s3/src/sensitive/edma_pms_rmt.rs
+++ b/esp32s3/src/sensitive/edma_pms_rmt.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_RMT_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_RMT_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_rmt_lock.rs b/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
index 677d2f9e8e..9aaa611348 100644
--- a/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-RMT permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_rmt_lock(&mut self) -> EDMA_PMS_RMT_LOCK_W<EDMA_PMS_RMT_LOCK_SPEC> {
         EDMA_PMS_RMT_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_sha.rs b/esp32s3/src/sensitive/edma_pms_sha.rs
index 3f548f8c77..64d038a827 100644
--- a/esp32s3/src/sensitive/edma_pms_sha.rs
+++ b/esp32s3/src/sensitive/edma_pms_sha.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_SHA_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_SHA_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_sha_lock.rs b/esp32s3/src/sensitive/edma_pms_sha_lock.rs
index 6a973cbb13..a102f0e976 100644
--- a/esp32s3/src/sensitive/edma_pms_sha_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_sha_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SHA permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_sha_lock(&mut self) -> EDMA_PMS_SHA_LOCK_W<EDMA_PMS_SHA_LOCK_SPEC> {
         EDMA_PMS_SHA_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_spi2.rs b/esp32s3/src/sensitive/edma_pms_spi2.rs
index 2ac86e53e0..82c555c3f7 100644
--- a/esp32s3/src/sensitive/edma_pms_spi2.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_SPI2_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_SPI2_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_spi2_lock.rs b/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
index 28516bc818..d33e191bc4 100644
--- a/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SPI2 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_spi2_lock(&mut self) -> EDMA_PMS_SPI2_LOCK_W<EDMA_PMS_SPI2_LOCK_SPEC> {
         EDMA_PMS_SPI2_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_spi3.rs b/esp32s3/src/sensitive/edma_pms_spi3.rs
index 98a9a80b99..9a679c96d9 100644
--- a/esp32s3/src/sensitive/edma_pms_spi3.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi3.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_SPI3_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_SPI3_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_spi3_lock.rs b/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
index 446bf9cc14..a0bcafca94 100644
--- a/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SPI3 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_spi3_lock(&mut self) -> EDMA_PMS_SPI3_LOCK_W<EDMA_PMS_SPI3_LOCK_SPEC> {
         EDMA_PMS_SPI3_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_uhci0.rs b/esp32s3/src/sensitive/edma_pms_uhci0.rs
index d01ff1e206..79c5d47314 100644
--- a/esp32s3/src/sensitive/edma_pms_uhci0.rs
+++ b/esp32s3/src/sensitive/edma_pms_uhci0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<EDMA_PMS_UHCI0_SPEC> {
         ATTR1_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<EDMA_PMS_UHCI0_SPEC> {
         ATTR2_W::new(self, 2)
     }
diff --git a/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs b/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
index 65abaf5877..6801e43bb0 100644
--- a/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-UHCI0 permission control registers."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_pms_uhci0_lock(&mut self) -> EDMA_PMS_UHCI0_LOCK_W<EDMA_PMS_UHCI0_LOCK_SPEC> {
         EDMA_PMS_UHCI0_LOCK_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/internal_sram_usage_0.rs b/esp32s3/src/sensitive/internal_sram_usage_0.rs
index 86a630ba15..0663bf2bd1 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_0.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to lock internal SRAM Configuration Register."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_usage_lock(
         &mut self,
     ) -> INTERNAL_SRAM_USAGE_LOCK_W<INTERNAL_SRAM_USAGE_0_SPEC> {
diff --git a/esp32s3/src/sensitive/internal_sram_usage_1.rs b/esp32s3/src/sensitive/internal_sram_usage_1.rs
index b61060fae3..c6b1987e58 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_1.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_1.rs
@@ -50,7 +50,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_icache_usage(
         &mut self,
     ) -> INTERNAL_SRAM_ICACHE_USAGE_W<INTERNAL_SRAM_USAGE_1_SPEC> {
@@ -58,7 +57,6 @@ impl W {
     }
     #[doc = "Bits 2:3 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_dcache_usage(
         &mut self,
     ) -> INTERNAL_SRAM_DCACHE_USAGE_W<INTERNAL_SRAM_USAGE_1_SPEC> {
@@ -66,7 +64,6 @@ impl W {
     }
     #[doc = "Bits 4:10 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_cpu_usage(
         &mut self,
     ) -> INTERNAL_SRAM_CPU_USAGE_W<INTERNAL_SRAM_USAGE_1_SPEC> {
diff --git a/esp32s3/src/sensitive/internal_sram_usage_2.rs b/esp32s3/src/sensitive/internal_sram_usage_2.rs
index 77054ac3e4..96817fac00 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_2.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_2.rs
@@ -66,7 +66,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_core0_trace_usage(
         &mut self,
     ) -> INTERNAL_SRAM_CORE0_TRACE_USAGE_W<INTERNAL_SRAM_USAGE_2_SPEC> {
@@ -74,7 +73,6 @@ impl W {
     }
     #[doc = "Bits 7:13 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_core1_trace_usage(
         &mut self,
     ) -> INTERNAL_SRAM_CORE1_TRACE_USAGE_W<INTERNAL_SRAM_USAGE_2_SPEC> {
@@ -82,7 +80,6 @@ impl W {
     }
     #[doc = "Bits 14:15 - Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_core0_trace_alloc(
         &mut self,
     ) -> INTERNAL_SRAM_CORE0_TRACE_ALLOC_W<INTERNAL_SRAM_USAGE_2_SPEC> {
@@ -90,7 +87,6 @@ impl W {
     }
     #[doc = "Bits 16:17 - Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_core1_trace_alloc(
         &mut self,
     ) -> INTERNAL_SRAM_CORE1_TRACE_ALLOC_W<INTERNAL_SRAM_USAGE_2_SPEC> {
diff --git a/esp32s3/src/sensitive/internal_sram_usage_3.rs b/esp32s3/src/sensitive/internal_sram_usage_3.rs
index 436752ec3b..ba21671a52 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_3.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_3.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_mac_dump_usage(
         &mut self,
     ) -> INTERNAL_SRAM_MAC_DUMP_USAGE_W<INTERNAL_SRAM_USAGE_3_SPEC> {
diff --git a/esp32s3/src/sensitive/internal_sram_usage_4.rs b/esp32s3/src/sensitive/internal_sram_usage_4.rs
index a8ec6b8330..20713bbde4 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_4.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus."]
     #[inline(always)]
-    #[must_use]
     pub fn internal_sram_log_usage(
         &mut self,
     ) -> INTERNAL_SRAM_LOG_USAGE_W<INTERNAL_SRAM_USAGE_4_SPEC> {
diff --git a/esp32s3/src/sensitive/retention_disable.rs b/esp32s3/src/sensitive/retention_disable.rs
index e9d6aa15e1..71c81d0742 100644
--- a/esp32s3/src/sensitive/retention_disable.rs
+++ b/esp32s3/src/sensitive/retention_disable.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to disable retention function and lock disable state."]
     #[inline(always)]
-    #[must_use]
     pub fn retention_disable(&mut self) -> RETENTION_DISABLE_W<RETENTION_DISABLE_SPEC> {
         RETENTION_DISABLE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sensitive/rtc_pms.rs b/esp32s3/src/sensitive/rtc_pms.rs
index 438c99ae88..cabb23e4f6 100644
--- a/esp32s3/src/sensitive/rtc_pms.rs
+++ b/esp32s3/src/sensitive/rtc_pms.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to disable rtc coprocessor."]
     #[inline(always)]
-    #[must_use]
     pub fn dis_rtc_cpu(&mut self) -> DIS_RTC_CPU_W<RTC_PMS_SPEC> {
         DIS_RTC_CPU_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/clear_irq.rs b/esp32s3/src/sha/clear_irq.rs
index 7842974c40..a9a3d79fa3 100644
--- a/esp32s3/src/sha/clear_irq.rs
+++ b/esp32s3/src/sha/clear_irq.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CLEAR_IRQ_SPEC> {
 impl W {
     #[doc = "Bit 0 - clear sha interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<CLEAR_IRQ_SPEC> {
         CLEAR_INTERRUPT_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/continue_.rs b/esp32s3/src/sha/continue_.rs
index 801c595166..b8daec4e22 100644
--- a/esp32s3/src/sha/continue_.rs
+++ b/esp32s3/src/sha/continue_.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
 impl W {
     #[doc = "Bits 1:31 - reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
         CONTINUE_W::new(self, 1)
     }
diff --git a/esp32s3/src/sha/date.rs b/esp32s3/src/sha/date.rs
index d53b46309f..e2e94043bb 100644
--- a/esp32s3/src/sha/date.rs
+++ b/esp32s3/src/sha/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - sha date information/ sha version information"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/dma_block_num.rs b/esp32s3/src/sha/dma_block_num.rs
index 9cb4dfb076..f90d9ca9a2 100644
--- a/esp32s3/src/sha/dma_block_num.rs
+++ b/esp32s3/src/sha/dma_block_num.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - dma-sha block number"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_block_num(&mut self) -> DMA_BLOCK_NUM_W<DMA_BLOCK_NUM_SPEC> {
         DMA_BLOCK_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/dma_continue.rs b/esp32s3/src/sha/dma_continue.rs
index 671d87c1d5..8773c4e290 100644
--- a/esp32s3/src/sha/dma_continue.rs
+++ b/esp32s3/src/sha/dma_continue.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_CONTINUE_SPEC> {
 impl W {
     #[doc = "Bit 0 - continue dma-sha"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<DMA_CONTINUE_SPEC> {
         DMA_CONTINUE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/dma_start.rs b/esp32s3/src/sha/dma_start.rs
index 48488385ab..01d5cacf80 100644
--- a/esp32s3/src/sha/dma_start.rs
+++ b/esp32s3/src/sha/dma_start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_START_SPEC> {
 impl W {
     #[doc = "Bit 0 - start dma-sha"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_start(&mut self) -> DMA_START_W<DMA_START_SPEC> {
         DMA_START_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/irq_ena.rs b/esp32s3/src/sha/irq_ena.rs
index 96599bcbf5..73429bffe1 100644
--- a/esp32s3/src/sha/irq_ena.rs
+++ b/esp32s3/src/sha/irq_ena.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W<IRQ_ENA_SPEC> {
         INTERRUPT_ENA_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/mode.rs b/esp32s3/src/sha/mode.rs
index 2fbd7e2043..2d59d19535 100644
--- a/esp32s3/src/sha/mode.rs
+++ b/esp32s3/src/sha/mode.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - sha mode"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
         MODE_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/start.rs b/esp32s3/src/sha/start.rs
index e8af336fc1..7b69601477 100644
--- a/esp32s3/src/sha/start.rs
+++ b/esp32s3/src/sha/start.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
 impl W {
     #[doc = "Bits 1:31 - reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<START_SPEC> {
         START_W::new(self, 1)
     }
diff --git a/esp32s3/src/sha/t_length.rs b/esp32s3/src/sha/t_length.rs
index 9b6f6f52af..7cfddb1ae2 100644
--- a/esp32s3/src/sha/t_length.rs
+++ b/esp32s3/src/sha/t_length.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - sha t_length(used if and only if mode == sha_256/t)"]
     #[inline(always)]
-    #[must_use]
     pub fn t_length(&mut self) -> T_LENGTH_W<T_LENGTH_SPEC> {
         T_LENGTH_W::new(self, 0)
     }
diff --git a/esp32s3/src/sha/t_string.rs b/esp32s3/src/sha/t_string.rs
index 2b91489645..d6f0e01935 100644
--- a/esp32s3/src/sha/t_string.rs
+++ b/esp32s3/src/sha/t_string.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - sha t_string(used if and only if mode == sha_256/t)"]
     #[inline(always)]
-    #[must_use]
     pub fn t_string(&mut self) -> T_STRING_W<T_STRING_SPEC> {
         T_STRING_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi0/cache_fctrl.rs b/esp32s3/src/spi0/cache_fctrl.rs
index aad88d1ce8..961acdec35 100644
--- a/esp32s3/src/spi0/cache_fctrl.rs
+++ b/esp32s3/src/spi0/cache_fctrl.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable Cache's access and SPI0's transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<CACHE_FCTRL_SPEC> {
         CACHE_REQ_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<CACHE_FCTRL_SPEC> {
         CACHE_USR_CMD_4BYTE_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<CACHE_FCTRL_SPEC> {
         CACHE_FLASH_USR_CMD_W::new(self, 2)
     }
     #[doc = "Bit 3 - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<CACHE_FCTRL_SPEC> {
         FDIN_DUAL_W::new(self, 3)
     }
     #[doc = "Bit 4 - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<CACHE_FCTRL_SPEC> {
         FDOUT_DUAL_W::new(self, 4)
     }
     #[doc = "Bit 5 - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CACHE_FCTRL_SPEC> {
         FADDR_DUAL_W::new(self, 5)
     }
     #[doc = "Bit 6 - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<CACHE_FCTRL_SPEC> {
         FDIN_QUAD_W::new(self, 6)
     }
     #[doc = "Bit 7 - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<CACHE_FCTRL_SPEC> {
         FDOUT_QUAD_W::new(self, 7)
     }
     #[doc = "Bit 8 - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CACHE_FCTRL_SPEC> {
         FADDR_QUAD_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi0/cache_sctrl.rs b/esp32s3/src/spi0/cache_sctrl.rs
index 54ed61b385..aebe5e2937 100644
--- a/esp32s3/src/spi0/cache_sctrl.rs
+++ b/esp32s3/src/spi0/cache_sctrl.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_usr_scmd_4byte(&mut self) -> CACHE_USR_SCMD_4BYTE_W<CACHE_SCTRL_SPEC> {
         CACHE_USR_SCMD_4BYTE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_DIO_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<CACHE_SCTRL_SPEC> {
         USR_SRAM_QIO_W::new(self, 2)
     }
     #[doc = "Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_WR_SRAM_DUMMY_W::new(self, 3)
     }
     #[doc = "Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<CACHE_SCTRL_SPEC> {
         USR_RD_SRAM_DUMMY_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_RCMD_W::new(self, 5)
     }
     #[doc = "Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_rdummy_cyclelen(&mut self) -> SRAM_RDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
         SRAM_RDUMMY_CYCLELEN_W::new(self, 6)
     }
     #[doc = "Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<CACHE_SCTRL_SPEC> {
         SRAM_ADDR_BITLEN_W::new(self, 14)
     }
     #[doc = "Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<CACHE_SCTRL_SPEC> {
         CACHE_SRAM_USR_WCMD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_oct(&mut self) -> SRAM_OCT_W<CACHE_SCTRL_SPEC> {
         SRAM_OCT_W::new(self, 21)
     }
     #[doc = "Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn sram_wdummy_cyclelen(&mut self) -> SRAM_WDUMMY_CYCLELEN_W<CACHE_SCTRL_SPEC> {
         SRAM_WDUMMY_CYCLELEN_W::new(self, 22)
     }
diff --git a/esp32s3/src/spi0/clock.rs b/esp32s3/src/spi0/clock.rs
index 8b3aa1f9a7..3d0ba8efd3 100644
--- a/esp32s3/src/spi0/clock.rs
+++ b/esp32s3/src/spi0/clock.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_CLKCNT_N."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
         CLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
         CLKCNT_H_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)"]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
         CLKCNT_N_W::new(self, 16)
     }
     #[doc = "Bit 31 - When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
         CLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi0/clock_gate.rs b/esp32s3/src/spi0/clock_gate.rs
index 86a5536d5c..d2c393bb91 100644
--- a/esp32s3/src/spi0/clock_gate.rs
+++ b/esp32s3/src/spi0/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi0/core_clk_sel.rs b/esp32s3/src/spi0/core_clk_sel.rs
index c697b6f52a..49feb60213 100644
--- a/esp32s3/src/spi0/core_clk_sel.rs
+++ b/esp32s3/src/spi0/core_clk_sel.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used."]
     #[inline(always)]
-    #[must_use]
     pub fn core_clk_sel(&mut self) -> CORE_CLK_SEL_W<CORE_CLK_SEL_SPEC> {
         CORE_CLK_SEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi0/ctrl.rs b/esp32s3/src/spi0/ctrl.rs
index 5ccba2d1e6..e6269a3b9d 100644
--- a/esp32s3/src/spi0/ctrl.rs
+++ b/esp32s3/src/spi0/ctrl.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
     #[inline(always)]
-    #[must_use]
     pub fn fdummy_out(&mut self) -> FDUMMY_OUT_W<CTRL_SPEC> {
         FDUMMY_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_oct(&mut self) -> FDOUT_OCT_W<CTRL_SPEC> {
         FDOUT_OCT_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_oct(&mut self) -> FDIN_OCT_W<CTRL_SPEC> {
         FDIN_OCT_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
         FADDR_OCT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
         FCMD_DUAL_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
         FCMD_QUAD_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
         FCMD_OCT_W::new(self, 9)
     }
     #[doc = "Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
     #[inline(always)]
-    #[must_use]
     pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
         FASTRD_MODE_W::new(self, 13)
     }
     #[doc = "Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
         FREAD_DUAL_W::new(self, 14)
     }
     #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
     #[inline(always)]
-    #[must_use]
     pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
         Q_POL_W::new(self, 18)
     }
     #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
     #[inline(always)]
-    #[must_use]
     pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
         D_POL_W::new(self, 19)
     }
     #[doc = "Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
         FREAD_QUAD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
     #[inline(always)]
-    #[must_use]
     pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
         WP_W::new(self, 21)
     }
     #[doc = "Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
         FREAD_DIO_W::new(self, 23)
     }
     #[doc = "Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
         FREAD_QIO_W::new(self, 24)
     }
diff --git a/esp32s3/src/spi0/ctrl1.rs b/esp32s3/src/spi0/ctrl1.rs
index 9068309ac9..180f79c708 100644
--- a/esp32s3/src/spi0/ctrl1.rs
+++ b/esp32s3/src/spi0/ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode(&mut self) -> CLK_MODE_W<CTRL1_SPEC> {
         CLK_MODE_W::new(self, 0)
     }
     #[doc = "Bit 30 - SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CTRL1_SPEC> {
         RXFIFO_RST_W::new(self, 30)
     }
diff --git a/esp32s3/src/spi0/ctrl2.rs b/esp32s3/src/spi0/ctrl2.rs
index bc02d4afeb..a81f8d3705 100644
--- a/esp32s3/src/spi0/ctrl2.rs
+++ b/esp32s3/src/spi0/ctrl2.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<CTRL2_SPEC> {
         CS_SETUP_TIME_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<CTRL2_SPEC> {
         CS_HOLD_TIME_W::new(self, 5)
     }
     #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_cs_hold_time(&mut self) -> ECC_CS_HOLD_TIME_W<CTRL2_SPEC> {
         ECC_CS_HOLD_TIME_W::new(self, 10)
     }
     #[doc = "Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_skip_page_corner(&mut self) -> ECC_SKIP_PAGE_CORNER_W<CTRL2_SPEC> {
         ECC_SKIP_PAGE_CORNER_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_16to18_byte_en(&mut self) -> ECC_16TO18_BYTE_EN_W<CTRL2_SPEC> {
         ECC_16TO18_BYTE_EN_W::new(self, 14)
     }
     #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<CTRL2_SPEC> {
         CS_HOLD_DELAY_W::new(self, 25)
     }
     #[doc = "Bit 31 - The FSM will be reset."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_reset(&mut self) -> SYNC_RESET_W<CTRL2_SPEC> {
         SYNC_RESET_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi0/date.rs b/esp32s3/src/spi0/date.rs
index a9d337537b..f719c8e16c 100644
--- a/esp32s3/src/spi0/date.rs
+++ b/esp32s3/src/spi0/date.rs
@@ -57,25 +57,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_spiclk_fun_drv(&mut self) -> SPI_SMEM_SPICLK_FUN_DRV_W<DATE_SPEC> {
         SPI_SMEM_SPICLK_FUN_DRV_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_spiclk_fun_drv(&mut self) -> SPI_FMEM_SPICLK_FUN_DRV_W<DATE_SPEC> {
         SPI_FMEM_SPICLK_FUN_DRV_W::new(self, 2)
     }
     #[doc = "Bit 4 - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] and SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV\\[1:0\\] of SPICLK PAD."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_spiclk_pad_drv_ctl_en(&mut self) -> SPI_SPICLK_PAD_DRV_CTL_EN_W<DATE_SPEC> {
         SPI_SPICLK_PAD_DRV_CTL_EN_W::new(self, 4)
     }
     #[doc = "Bits 5:27 - SPI register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 5)
     }
diff --git a/esp32s3/src/spi0/ddr.rs b/esp32s3/src/spi0/ddr.rs
index fbe8a466f1..23b795aa08 100644
--- a/esp32s3/src/spi0/ddr.rs
+++ b/esp32s3/src/spi0/ddr.rs
@@ -200,109 +200,91 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W<DDR_SPEC> {
         SPI_FMEM_DDR_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W<DDR_SPEC> {
         SPI_FMEM_VAR_DUMMY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W<DDR_SPEC> {
         SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to swap TX data of a word in DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W<DDR_SPEC> {
         SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3)
     }
     #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W<DDR_SPEC> {
         SPI_FMEM_DDR_CMD_DIS_W::new(self, 4)
     }
     #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W<DDR_SPEC> {
         SPI_FMEM_OUTMINBYTELEN_W::new(self, 5)
     }
     #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_tx_ddr_msk_en(&mut self) -> SPI_FMEM_TX_DDR_MSK_EN_W<DDR_SPEC> {
         SPI_FMEM_TX_DDR_MSK_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_rx_ddr_msk_en(&mut self) -> SPI_FMEM_RX_DDR_MSK_EN_W<DDR_SPEC> {
         SPI_FMEM_RX_DDR_MSK_EN_W::new(self, 13)
     }
     #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W<DDR_SPEC> {
         SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14)
     }
     #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W<DDR_SPEC> {
         SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21)
     }
     #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_dqs_loop_mode(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_W<DDR_SPEC> {
         SPI_FMEM_DDR_DQS_LOOP_MODE_W::new(self, 22)
     }
     #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W<DDR_SPEC> {
         SPI_FMEM_CLK_DIFF_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_mode(&mut self) -> SPI_FMEM_HYPERBUS_MODE_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_MODE_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W<DDR_SPEC> {
         SPI_FMEM_DQS_CA_IN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W<DDR_SPEC> {
         SPI_FMEM_CLK_DIFF_INV_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W<DDR_SPEC> {
         SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_CA_W::new(self, 30)
     }
diff --git a/esp32s3/src/spi0/din_mode.rs b/esp32s3/src/spi0/din_mode.rs
index 4264a35a23..a77f9db2c7 100644
--- a/esp32s3/src/spi0/din_mode.rs
+++ b/esp32s3/src/spi0/din_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
         DIN0_MODE_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
         DIN1_MODE_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
         DIN2_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
         DIN3_MODE_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_mode(&mut self) -> DIN4_MODE_W<DIN_MODE_SPEC> {
         DIN4_MODE_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_mode(&mut self) -> DIN5_MODE_W<DIN_MODE_SPEC> {
         DIN5_MODE_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_mode(&mut self) -> DIN6_MODE_W<DIN_MODE_SPEC> {
         DIN6_MODE_W::new(self, 18)
     }
     #[doc = "Bits 21:23 - SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_mode(&mut self) -> DIN7_MODE_W<DIN_MODE_SPEC> {
         DIN7_MODE_W::new(self, 21)
     }
     #[doc = "Bits 24:26 - SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dins_mode(&mut self) -> DINS_MODE_W<DIN_MODE_SPEC> {
         DINS_MODE_W::new(self, 24)
     }
diff --git a/esp32s3/src/spi0/din_num.rs b/esp32s3/src/spi0/din_num.rs
index 7a6d8b7a0b..226aac8d14 100644
--- a/esp32s3/src/spi0/din_num.rs
+++ b/esp32s3/src/spi0/din_num.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI_D input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
         DIN0_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - SPI_Q input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
         DIN1_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - SPI_WP input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
         DIN2_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - SPI_HD input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
         DIN3_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - SPI_IO4 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
         DIN4_NUM_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - SPI_IO5 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
         DIN5_NUM_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - SPI_IO6 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
         DIN6_NUM_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - SPI_IO7 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
         DIN7_NUM_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - SPI_DQS input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn dins_num(&mut self) -> DINS_NUM_W<DIN_NUM_SPEC> {
         DINS_NUM_W::new(self, 16)
     }
diff --git a/esp32s3/src/spi0/dout_mode.rs b/esp32s3/src/spi0/dout_mode.rs
index bb4bf1ea71..cfd4f7a07f 100644
--- a/esp32s3/src/spi0/dout_mode.rs
+++ b/esp32s3/src/spi0/dout_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
         DOUT0_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
         DOUT1_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
         DOUT2_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
         DOUT3_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<DOUT_MODE_SPEC> {
         DOUT4_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<DOUT_MODE_SPEC> {
         DOUT5_MODE_W::new(self, 5)
     }
     #[doc = "Bit 6 - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<DOUT_MODE_SPEC> {
         DOUT6_MODE_W::new(self, 6)
     }
     #[doc = "Bit 7 - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<DOUT_MODE_SPEC> {
         DOUT7_MODE_W::new(self, 7)
     }
     #[doc = "Bit 8 - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn douts_mode(&mut self) -> DOUTS_MODE_W<DOUT_MODE_SPEC> {
         DOUTS_MODE_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi0/ecc_ctrl.rs b/esp32s3/src/spi0/ecc_ctrl.rs
index b1ed93e5fe..bb02584c44 100644
--- a/esp32s3/src/spi0/ecc_ctrl.rs
+++ b/esp32s3/src/spi0/ecc_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_err_int_num(&mut self) -> ECC_ERR_INT_NUM_W<ECC_CTRL_SPEC> {
         ECC_ERR_INT_NUM_W::new(self, 0)
     }
     #[doc = "Bit 8 - Set this bit to calculate the error times of MSPI ECC read when accesses to flash."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ecc_err_int_en(&mut self) -> SPI_FMEM_ECC_ERR_INT_EN_W<ECC_CTRL_SPEC> {
         SPI_FMEM_ECC_ERR_INT_EN_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi0/ext_addr.rs b/esp32s3/src/spi0/ext_addr.rs
index 6ca2b72ec8..2e88b57779 100644
--- a/esp32s3/src/spi0/ext_addr.rs
+++ b/esp32s3/src/spi0/ext_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The register are the higher 32bits in the 64 bits address mode."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_addr(&mut self) -> EXT_ADDR_W<EXT_ADDR_SPEC> {
         EXT_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi0/int_clr.rs b/esp32s3/src/spi0/int_clr.rs
index a29a323e4d..57b81e8da4 100644
--- a/esp32s3/src/spi0/int_clr.rs
+++ b/esp32s3/src/spi0/int_clr.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 2 - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_CLR_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 4 - The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_CLR_SPEC> {
         ECC_ERR_W::new(self, 4)
     }
diff --git a/esp32s3/src/spi0/int_ena.rs b/esp32s3/src/spi0/int_ena.rs
index 2c89808e4c..fa8f1050fd 100644
--- a/esp32s3/src/spi0/int_ena.rs
+++ b/esp32s3/src/spi0/int_ena.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_ENA_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 4 - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_ENA_SPEC> {
         ECC_ERR_W::new(self, 4)
     }
diff --git a/esp32s3/src/spi0/int_raw.rs b/esp32s3/src/spi0/int_raw.rs
index 79d62a7d86..d26135dd50 100644
--- a/esp32s3/src/spi0/int_raw.rs
+++ b/esp32s3/src/spi0/int_raw.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2 - The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_RAW_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 4 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered."]
     #[inline(always)]
-    #[must_use]
     pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_RAW_SPEC> {
         ECC_ERR_W::new(self, 4)
     }
diff --git a/esp32s3/src/spi0/misc.rs b/esp32s3/src/spi0/misc.rs
index 114d6e1e7c..cbebaee92e 100644
--- a/esp32s3/src/spi0/misc.rs
+++ b/esp32s3/src/spi0/misc.rs
@@ -87,7 +87,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -95,37 +94,31 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 1)
     }
     #[doc = "Bit 7 - Flash is connected to SPI SUBPIN bus."]
     #[inline(always)]
-    #[must_use]
     pub fn fsub_pin(&mut self) -> FSUB_PIN_W<MISC_SPEC> {
         FSUB_PIN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Ext_RAM is connected to SPI SUBPIN bus."]
     #[inline(always)]
-    #[must_use]
     pub fn ssub_pin(&mut self) -> SSUB_PIN_W<MISC_SPEC> {
         SSUB_PIN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle"]
     #[inline(always)]
-    #[must_use]
     pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
         CK_IDLE_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
         CS_KEEP_ACTIVE_W::new(self, 10)
     }
diff --git a/esp32s3/src/spi0/rd_status.rs b/esp32s3/src/spi0/rd_status.rs
index dd327a637b..495e69e8aa 100644
--- a/esp32s3/src/spi0/rd_status.rs
+++ b/esp32s3/src/spi0/rd_status.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit."]
     #[inline(always)]
-    #[must_use]
     pub fn wb_mode(&mut self) -> WB_MODE_W<RD_STATUS_SPEC> {
         WB_MODE_W::new(self, 16)
     }
diff --git a/esp32s3/src/spi0/spi_smem_ac.rs b/esp32s3/src/spi0/spi_smem_ac.rs
index bd329d16fa..a51fbf28bc 100644
--- a/esp32s3/src/spi0/spi_smem_ac.rs
+++ b/esp32s3/src/spi0/spi_smem_ac.rs
@@ -113,37 +113,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_cs_setup(&mut self) -> SPI_SMEM_CS_SETUP_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_CS_SETUP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_cs_hold(&mut self) -> SPI_SMEM_CS_HOLD_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_CS_HOLD_W::new(self, 1)
     }
     #[doc = "Bits 2:6 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_cs_setup_time(&mut self) -> SPI_SMEM_CS_SETUP_TIME_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_CS_SETUP_TIME_W::new(self, 2)
     }
     #[doc = "Bits 7:11 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_cs_hold_time(&mut self) -> SPI_SMEM_CS_HOLD_TIME_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_CS_HOLD_TIME_W::new(self, 7)
     }
     #[doc = "Bits 12:14 - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_ecc_cs_hold_time(&mut self) -> SPI_SMEM_ECC_CS_HOLD_TIME_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_ECC_CS_HOLD_TIME_W::new(self, 12)
     }
     #[doc = "Bit 15 - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_ecc_skip_page_corner(
         &mut self,
     ) -> SPI_SMEM_ECC_SKIP_PAGE_CORNER_W<SPI_SMEM_AC_SPEC> {
@@ -151,7 +145,6 @@ impl W {
     }
     #[doc = "Bit 16 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_ecc_16to18_byte_en(
         &mut self,
     ) -> SPI_SMEM_ECC_16TO18_BYTE_EN_W<SPI_SMEM_AC_SPEC> {
@@ -159,13 +152,11 @@ impl W {
     }
     #[doc = "Bit 24 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_ecc_err_int_en(&mut self) -> SPI_SMEM_ECC_ERR_INT_EN_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_ECC_ERR_INT_EN_W::new(self, 24)
     }
     #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_cs_hold_delay(&mut self) -> SPI_SMEM_CS_HOLD_DELAY_W<SPI_SMEM_AC_SPEC> {
         SPI_SMEM_CS_HOLD_DELAY_W::new(self, 25)
     }
diff --git a/esp32s3/src/spi0/spi_smem_ddr.rs b/esp32s3/src/spi0/spi_smem_ddr.rs
index 48bbde7769..ef0353db6a 100644
--- a/esp32s3/src/spi0/spi_smem_ddr.rs
+++ b/esp32s3/src/spi0/spi_smem_ddr.rs
@@ -197,91 +197,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<SPI_SMEM_DDR_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_var_dummy(&mut self) -> SPI_SMEM_VAR_DUMMY_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_VAR_DUMMY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rdat_swp(&mut self) -> RDAT_SWP_W<SPI_SMEM_DDR_SPEC> {
         RDAT_SWP_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode."]
     #[inline(always)]
-    #[must_use]
     pub fn wdat_swp(&mut self) -> WDAT_SWP_W<SPI_SMEM_DDR_SPEC> {
         WDAT_SWP_W::new(self, 3)
     }
     #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dis(&mut self) -> CMD_DIS_W<SPI_SMEM_DDR_SPEC> {
         CMD_DIS_W::new(self, 4)
     }
     #[doc = "Bits 5:11 - It is the minimum output data length in the ddr psram."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_outminbytelen(&mut self) -> SPI_SMEM_OUTMINBYTELEN_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_OUTMINBYTELEN_W::new(self, 5)
     }
     #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_tx_ddr_msk_en(&mut self) -> SPI_SMEM_TX_DDR_MSK_EN_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_TX_DDR_MSK_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_rx_ddr_msk_en(&mut self) -> SPI_SMEM_RX_DDR_MSK_EN_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_RX_DDR_MSK_EN_W::new(self, 13)
     }
     #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_usr_ddr_dqs_thd(&mut self) -> SPI_SMEM_USR_DDR_DQS_THD_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_USR_DDR_DQS_THD_W::new(self, 14)
     }
     #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
     #[inline(always)]
-    #[must_use]
     pub fn dqs_loop(&mut self) -> DQS_LOOP_W<SPI_SMEM_DDR_SPEC> {
         DQS_LOOP_W::new(self, 21)
     }
     #[doc = "Bit 22 - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
     #[inline(always)]
-    #[must_use]
     pub fn dqs_loop_mode(&mut self) -> DQS_LOOP_MODE_W<SPI_SMEM_DDR_SPEC> {
         DQS_LOOP_MODE_W::new(self, 22)
     }
     #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_clk_diff_en(&mut self) -> SPI_SMEM_CLK_DIFF_EN_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_CLK_DIFF_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_hyperbus_mode(&mut self) -> SPI_SMEM_HYPERBUS_MODE_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_HYPERBUS_MODE_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dqs_ca_in(&mut self) -> SPI_SMEM_DQS_CA_IN_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_DQS_CA_IN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_hyperbus_dummy_2x(
         &mut self,
     ) -> SPI_SMEM_HYPERBUS_DUMMY_2X_W<SPI_SMEM_DDR_SPEC> {
@@ -289,19 +274,16 @@ impl W {
     }
     #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. ."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_clk_diff_inv(&mut self) -> SPI_SMEM_CLK_DIFF_INV_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_CLK_DIFF_INV_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_octa_ram_addr(&mut self) -> SPI_SMEM_OCTA_RAM_ADDR_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_OCTA_RAM_ADDR_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_hyperbus_ca(&mut self) -> SPI_SMEM_HYPERBUS_CA_W<SPI_SMEM_DDR_SPEC> {
         SPI_SMEM_HYPERBUS_CA_W::new(self, 30)
     }
diff --git a/esp32s3/src/spi0/spi_smem_din_mode.rs b/esp32s3/src/spi0/spi_smem_din_mode.rs
index e2915b8c2e..b71929ec49 100644
--- a/esp32s3/src/spi0/spi_smem_din_mode.rs
+++ b/esp32s3/src/spi0/spi_smem_din_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din0_mode(&mut self) -> SPI_SMEM_DIN0_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN0_MODE_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din1_mode(&mut self) -> SPI_SMEM_DIN1_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN1_MODE_W::new(self, 3)
     }
     #[doc = "Bits 6:8 - SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din2_mode(&mut self) -> SPI_SMEM_DIN2_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN2_MODE_W::new(self, 6)
     }
     #[doc = "Bits 9:11 - SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din3_mode(&mut self) -> SPI_SMEM_DIN3_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN3_MODE_W::new(self, 9)
     }
     #[doc = "Bits 12:14 - SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din4_mode(&mut self) -> SPI_SMEM_DIN4_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN4_MODE_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din5_mode(&mut self) -> SPI_SMEM_DIN5_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN5_MODE_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din6_mode(&mut self) -> SPI_SMEM_DIN6_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN6_MODE_W::new(self, 18)
     }
     #[doc = "Bits 21:23 - SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din7_mode(&mut self) -> SPI_SMEM_DIN7_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DIN7_MODE_W::new(self, 21)
     }
     #[doc = "Bits 24:26 - SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dins_mode(&mut self) -> SPI_SMEM_DINS_MODE_W<SPI_SMEM_DIN_MODE_SPEC> {
         SPI_SMEM_DINS_MODE_W::new(self, 24)
     }
diff --git a/esp32s3/src/spi0/spi_smem_din_num.rs b/esp32s3/src/spi0/spi_smem_din_num.rs
index 9f5bbe2f58..3c5e311350 100644
--- a/esp32s3/src/spi0/spi_smem_din_num.rs
+++ b/esp32s3/src/spi0/spi_smem_din_num.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI_D input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din0_num(&mut self) -> SPI_SMEM_DIN0_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN0_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - SPI_Q input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din1_num(&mut self) -> SPI_SMEM_DIN1_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN1_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - SPI_WP input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din2_num(&mut self) -> SPI_SMEM_DIN2_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN2_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - SPI_HD input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din3_num(&mut self) -> SPI_SMEM_DIN3_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN3_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - SPI_IO4 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din4_num(&mut self) -> SPI_SMEM_DIN4_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN4_NUM_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - SPI_IO5 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din5_num(&mut self) -> SPI_SMEM_DIN5_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN5_NUM_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - SPI_IO6 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din6_num(&mut self) -> SPI_SMEM_DIN6_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN6_NUM_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - SPI_IO7 input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_din7_num(&mut self) -> SPI_SMEM_DIN7_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DIN7_NUM_W::new(self, 14)
     }
     #[doc = "Bits 16:17 - SPI_DQS input delay number."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dins_num(&mut self) -> SPI_SMEM_DINS_NUM_W<SPI_SMEM_DIN_NUM_SPEC> {
         SPI_SMEM_DINS_NUM_W::new(self, 16)
     }
diff --git a/esp32s3/src/spi0/spi_smem_dout_mode.rs b/esp32s3/src/spi0/spi_smem_dout_mode.rs
index db2e9e9d67..392b9ac72b 100644
--- a/esp32s3/src/spi0/spi_smem_dout_mode.rs
+++ b/esp32s3/src/spi0/spi_smem_dout_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout0_mode(&mut self) -> SPI_SMEM_DOUT0_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT0_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout1_mode(&mut self) -> SPI_SMEM_DOUT1_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT1_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout2_mode(&mut self) -> SPI_SMEM_DOUT2_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT2_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout3_mode(&mut self) -> SPI_SMEM_DOUT3_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT3_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout4_mode(&mut self) -> SPI_SMEM_DOUT4_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT4_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout5_mode(&mut self) -> SPI_SMEM_DOUT5_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT5_MODE_W::new(self, 5)
     }
     #[doc = "Bit 6 - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout6_mode(&mut self) -> SPI_SMEM_DOUT6_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT6_MODE_W::new(self, 6)
     }
     #[doc = "Bit 7 - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_dout7_mode(&mut self) -> SPI_SMEM_DOUT7_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUT7_MODE_W::new(self, 7)
     }
     #[doc = "Bit 8 - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_douts_mode(&mut self) -> SPI_SMEM_DOUTS_MODE_W<SPI_SMEM_DOUT_MODE_SPEC> {
         SPI_SMEM_DOUTS_MODE_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi0/spi_smem_timing_cali.rs b/esp32s3/src/spi0/spi_smem_timing_cali.rs
index 2aa02c67e8..65579d4f4e 100644
--- a/esp32s3/src/spi0/spi_smem_timing_cali.rs
+++ b/esp32s3/src/spi0/spi_smem_timing_cali.rs
@@ -47,7 +47,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_timing_clk_ena(
         &mut self,
     ) -> SPI_SMEM_TIMING_CLK_ENA_W<SPI_SMEM_TIMING_CALI_SPEC> {
@@ -55,13 +54,11 @@ impl W {
     }
     #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_timing_cali(&mut self) -> SPI_SMEM_TIMING_CALI_W<SPI_SMEM_TIMING_CALI_SPEC> {
         SPI_SMEM_TIMING_CALI_W::new(self, 1)
     }
     #[doc = "Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_smem_extra_dummy_cyclelen(
         &mut self,
     ) -> SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W<SPI_SMEM_TIMING_CALI_SPEC> {
diff --git a/esp32s3/src/spi0/sram_clk.rs b/esp32s3/src/spi0/sram_clk.rs
index 84b254850c..62646fe6f1 100644
--- a/esp32s3/src/spi0/sram_clk.rs
+++ b/esp32s3/src/spi0/sram_clk.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_SCLKCNT_N."]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_l(&mut self) -> SCLKCNT_L_W<SRAM_CLK_SPEC> {
         SCLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_h(&mut self) -> SCLKCNT_H_W<SRAM_CLK_SPEC> {
         SCLKCNT_H_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)"]
     #[inline(always)]
-    #[must_use]
     pub fn sclkcnt_n(&mut self) -> SCLKCNT_N_W<SRAM_CLK_SPEC> {
         SCLKCNT_N_W::new(self, 16)
     }
     #[doc = "Bit 31 - When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_equ_sysclk(&mut self) -> SCLK_EQU_SYSCLK_W<SRAM_CLK_SPEC> {
         SCLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi0/sram_cmd.rs b/esp32s3/src/spi0/sram_cmd.rs
index 0c768d1282..617e18721a 100644
--- a/esp32s3/src/spi0/sram_cmd.rs
+++ b/esp32s3/src/spi0/sram_cmd.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_mode(&mut self) -> SCLK_MODE_W<SRAM_CMD_SPEC> {
         SCLK_MODE_W::new(self, 0)
     }
     #[doc = "Bits 2:9 - Mode bits when SPI0 accesses to Ext_RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn swb_mode(&mut self) -> SWB_MODE_W<SRAM_CMD_SPEC> {
         SWB_MODE_W::new(self, 2)
     }
     #[doc = "Bit 10 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdin_dual(&mut self) -> SDIN_DUAL_W<SRAM_CMD_SPEC> {
         SDIN_DUAL_W::new(self, 10)
     }
     #[doc = "Bit 11 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdout_dual(&mut self) -> SDOUT_DUAL_W<SRAM_CMD_SPEC> {
         SDOUT_DUAL_W::new(self, 11)
     }
     #[doc = "Bit 12 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn saddr_dual(&mut self) -> SADDR_DUAL_W<SRAM_CMD_SPEC> {
         SADDR_DUAL_W::new(self, 12)
     }
     #[doc = "Bit 13 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn scmd_dual(&mut self) -> SCMD_DUAL_W<SRAM_CMD_SPEC> {
         SCMD_DUAL_W::new(self, 13)
     }
     #[doc = "Bit 14 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdin_quad(&mut self) -> SDIN_QUAD_W<SRAM_CMD_SPEC> {
         SDIN_QUAD_W::new(self, 14)
     }
     #[doc = "Bit 15 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdout_quad(&mut self) -> SDOUT_QUAD_W<SRAM_CMD_SPEC> {
         SDOUT_QUAD_W::new(self, 15)
     }
     #[doc = "Bit 16 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn saddr_quad(&mut self) -> SADDR_QUAD_W<SRAM_CMD_SPEC> {
         SADDR_QUAD_W::new(self, 16)
     }
     #[doc = "Bit 17 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn scmd_quad(&mut self) -> SCMD_QUAD_W<SRAM_CMD_SPEC> {
         SCMD_QUAD_W::new(self, 17)
     }
     #[doc = "Bit 18 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdin_oct(&mut self) -> SDIN_OCT_W<SRAM_CMD_SPEC> {
         SDIN_OCT_W::new(self, 18)
     }
     #[doc = "Bit 19 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn sdout_oct(&mut self) -> SDOUT_OCT_W<SRAM_CMD_SPEC> {
         SDOUT_OCT_W::new(self, 19)
     }
     #[doc = "Bit 20 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn saddr_oct(&mut self) -> SADDR_OCT_W<SRAM_CMD_SPEC> {
         SADDR_OCT_W::new(self, 20)
     }
     #[doc = "Bit 21 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn scmd_oct(&mut self) -> SCMD_OCT_W<SRAM_CMD_SPEC> {
         SCMD_OCT_W::new(self, 21)
     }
     #[doc = "Bit 22 - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
     #[inline(always)]
-    #[must_use]
     pub fn sdummy_out(&mut self) -> SDUMMY_OUT_W<SRAM_CMD_SPEC> {
         SDUMMY_OUT_W::new(self, 22)
     }
diff --git a/esp32s3/src/spi0/sram_drd_cmd.rs b/esp32s3/src/spi0/sram_drd_cmd.rs
index 6b2797b5c9..e71dcb5ea2 100644
--- a/esp32s3/src/spi0/sram_drd_cmd.rs
+++ b/esp32s3/src/spi0/sram_drd_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - When SPI0 reads Ext_RAM, it is the command value of CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_VALUE_W<SRAM_DRD_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_rd_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_RD_CMD_BITLEN_W<SRAM_DRD_CMD_SPEC> {
diff --git a/esp32s3/src/spi0/sram_dwr_cmd.rs b/esp32s3/src/spi0/sram_dwr_cmd.rs
index 91025bf6e1..529ed7fc7e 100644
--- a/esp32s3/src/spi0/sram_dwr_cmd.rs
+++ b/esp32s3/src/spi0/sram_dwr_cmd.rs
@@ -40,7 +40,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - When SPI0 writes Ext_RAM, it is the command value of CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_value(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_VALUE_W<SRAM_DWR_CMD_SPEC> {
@@ -48,7 +47,6 @@ impl W {
     }
     #[doc = "Bits 28:31 - When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_sram_usr_wr_cmd_bitlen(
         &mut self,
     ) -> CACHE_SRAM_USR_WR_CMD_BITLEN_W<SRAM_DWR_CMD_SPEC> {
diff --git a/esp32s3/src/spi0/timing_cali.rs b/esp32s3/src/spi0/timing_cali.rs
index 3da4e45a2a..7bacca9e23 100644
--- a/esp32s3/src/spi0/timing_cali.rs
+++ b/esp32s3/src/spi0/timing_cali.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
     #[inline(always)]
-    #[must_use]
     pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<TIMING_CALI_SPEC> {
         TIMING_CLK_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
     #[inline(always)]
-    #[must_use]
     pub fn timing_cali(&mut self) -> TIMING_CALI_W<TIMING_CALI_SPEC> {
         TIMING_CALI_W::new(self, 1)
     }
     #[doc = "Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<TIMING_CALI_SPEC> {
         EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
     }
diff --git a/esp32s3/src/spi0/user.rs b/esp32s3/src/spi0/user.rs
index 3c81d977a3..aa12a6d8c8 100644
--- a/esp32s3/src/spi0/user.rs
+++ b/esp32s3/src/spi0/user.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 6 - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
         CS_HOLD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
         CS_SETUP_W::new(self, 7)
     }
     #[doc = "Bit 9 - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
         CK_OUT_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 26 - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
         USR_DUMMY_IDLE_W::new(self, 26)
     }
     #[doc = "Bit 29 - This bit enable the DUMMY phase of an SPI transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
         USR_DUMMY_W::new(self, 29)
     }
diff --git a/esp32s3/src/spi0/user1.rs b/esp32s3/src/spi0/user1.rs
index 70f8bf331e..ab6427a70f 100644
--- a/esp32s3/src/spi0/user1.rs
+++ b/esp32s3/src/spi0/user1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - The SPI_CLK cycle length minus 1 of DUMMY phase."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bits 26:31 - The length in bits of ADDR phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
         USR_ADDR_BITLEN_W::new(self, 26)
     }
diff --git a/esp32s3/src/spi0/user2.rs b/esp32s3/src/spi0/user2.rs
index c59595a288..a5e23437e6 100644
--- a/esp32s3/src/spi0/user2.rs
+++ b/esp32s3/src/spi0/user2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value of user defined(USR) command."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<USER2_SPEC> {
         USR_COMMAND_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 28:31 - The length in bits of CMD phase. The register value shall be (bit_num-1)"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<USER2_SPEC> {
         USR_COMMAND_BITLEN_W::new(self, 28)
     }
diff --git a/esp32s3/src/spi1/addr.rs b/esp32s3/src/spi1/addr.rs
index a0213e15b9..0d0a1be434 100644
--- a/esp32s3/src/spi1/addr.rs
+++ b/esp32s3/src/spi1/addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_value(&mut self) -> USR_ADDR_VALUE_W<ADDR_SPEC> {
         USR_ADDR_VALUE_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/cache_fctrl.rs b/esp32s3/src/spi1/cache_fctrl.rs
index e3c1a05c45..d2eff4f91b 100644
--- a/esp32s3/src/spi1/cache_fctrl.rs
+++ b/esp32s3/src/spi1/cache_fctrl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31."]
     #[inline(always)]
-    #[must_use]
     pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<CACHE_FCTRL_SPEC> {
         CACHE_USR_CMD_4BYTE_W::new(self, 1)
     }
     #[doc = "Bit 3 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<CACHE_FCTRL_SPEC> {
         FDIN_DUAL_W::new(self, 3)
     }
     #[doc = "Bit 4 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<CACHE_FCTRL_SPEC> {
         FDOUT_DUAL_W::new(self, 4)
     }
     #[doc = "Bit 5 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CACHE_FCTRL_SPEC> {
         FADDR_DUAL_W::new(self, 5)
     }
     #[doc = "Bit 6 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<CACHE_FCTRL_SPEC> {
         FDIN_QUAD_W::new(self, 6)
     }
     #[doc = "Bit 7 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<CACHE_FCTRL_SPEC> {
         FDOUT_QUAD_W::new(self, 7)
     }
     #[doc = "Bit 8 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CACHE_FCTRL_SPEC> {
         FADDR_QUAD_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi1/clock.rs b/esp32s3/src/spi1/clock.rs
index e62dad8e82..ea5b8f5196 100644
--- a/esp32s3/src/spi1/clock.rs
+++ b/esp32s3/src/spi1/clock.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_CLKCNT_N."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
         CLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
         CLKCNT_H_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)"]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
         CLKCNT_N_W::new(self, 16)
     }
     #[doc = "Bit 31 - When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
         CLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi1/clock_gate.rs b/esp32s3/src/spi1/clock_gate.rs
index 5c0eb9d0d7..5e04c4947e 100644
--- a/esp32s3/src/spi1/clock_gate.rs
+++ b/esp32s3/src/spi1/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/cmd.rs b/esp32s3/src/spi1/cmd.rs
index 8e7ba343f5..0b013a372b 100644
--- a/esp32s3/src/spi1/cmd.rs
+++ b/esp32s3/src/spi1/cmd.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pe(&mut self) -> FLASH_PE_W<CMD_SPEC> {
         FLASH_PE_W::new(self, 17)
     }
     #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
         USR_W::new(self, 18)
     }
     #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_hpm(&mut self) -> FLASH_HPM_W<CMD_SPEC> {
         FLASH_HPM_W::new(self, 19)
     }
     #[doc = "Bit 20 - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_res(&mut self) -> FLASH_RES_W<CMD_SPEC> {
         FLASH_RES_W::new(self, 20)
     }
     #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_dp(&mut self) -> FLASH_DP_W<CMD_SPEC> {
         FLASH_DP_W::new(self, 21)
     }
     #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_ce(&mut self) -> FLASH_CE_W<CMD_SPEC> {
         FLASH_CE_W::new(self, 22)
     }
     #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_be(&mut self) -> FLASH_BE_W<CMD_SPEC> {
         FLASH_BE_W::new(self, 23)
     }
     #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_se(&mut self) -> FLASH_SE_W<CMD_SPEC> {
         FLASH_SE_W::new(self, 24)
     }
     #[doc = "Bit 25 - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pp(&mut self) -> FLASH_PP_W<CMD_SPEC> {
         FLASH_PP_W::new(self, 25)
     }
     #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wrsr(&mut self) -> FLASH_WRSR_W<CMD_SPEC> {
         FLASH_WRSR_W::new(self, 26)
     }
     #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_rdsr(&mut self) -> FLASH_RDSR_W<CMD_SPEC> {
         FLASH_RDSR_W::new(self, 27)
     }
     #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_rdid(&mut self) -> FLASH_RDID_W<CMD_SPEC> {
         FLASH_RDID_W::new(self, 28)
     }
     #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wrdi(&mut self) -> FLASH_WRDI_W<CMD_SPEC> {
         FLASH_WRDI_W::new(self, 29)
     }
     #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_wren(&mut self) -> FLASH_WREN_W<CMD_SPEC> {
         FLASH_WREN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_read(&mut self) -> FLASH_READ_W<CMD_SPEC> {
         FLASH_READ_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi1/ctrl.rs b/esp32s3/src/spi1/ctrl.rs
index 9f55902525..9df400d3da 100644
--- a/esp32s3/src/spi1/ctrl.rs
+++ b/esp32s3/src/spi1/ctrl.rs
@@ -204,115 +204,96 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
     #[inline(always)]
-    #[must_use]
     pub fn fdummy_out(&mut self) -> FDUMMY_OUT_W<CTRL_SPEC> {
         FDUMMY_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdout_oct(&mut self) -> FDOUT_OCT_W<CTRL_SPEC> {
         FDOUT_OCT_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fdin_oct(&mut self) -> FDIN_OCT_W<CTRL_SPEC> {
         FDIN_OCT_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
         FADDR_OCT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
         FCMD_DUAL_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
         FCMD_QUAD_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
         FCMD_OCT_W::new(self, 9)
     }
     #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
     #[inline(always)]
-    #[must_use]
     pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
         FCS_CRC_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
         TX_CRC_EN_W::new(self, 11)
     }
     #[doc = "Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set."]
     #[inline(always)]
-    #[must_use]
     pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
         FASTRD_MODE_W::new(self, 13)
     }
     #[doc = "Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
         FREAD_DUAL_W::new(self, 14)
     }
     #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
         RESANDRES_W::new(self, 15)
     }
     #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
     #[inline(always)]
-    #[must_use]
     pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
         Q_POL_W::new(self, 18)
     }
     #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
     #[inline(always)]
-    #[must_use]
     pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
         D_POL_W::new(self, 19)
     }
     #[doc = "Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
         FREAD_QUAD_W::new(self, 20)
     }
     #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
     #[inline(always)]
-    #[must_use]
     pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
         WP_W::new(self, 21)
     }
     #[doc = "Bit 22 - Two bytes data will be written to status register when it is set. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
         WRSR_2B_W::new(self, 22)
     }
     #[doc = "Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
         FREAD_DIO_W::new(self, 23)
     }
     #[doc = "Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
         FREAD_QIO_W::new(self, 24)
     }
diff --git a/esp32s3/src/spi1/ctrl1.rs b/esp32s3/src/spi1/ctrl1.rs
index 3a3f526608..3abd95216b 100644
--- a/esp32s3/src/spi1/ctrl1.rs
+++ b/esp32s3/src/spi1/ctrl1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode(&mut self) -> CLK_MODE_W<CTRL1_SPEC> {
         CLK_MODE_W::new(self, 0)
     }
     #[doc = "Bits 2:11 - After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or * 256) SPI_CLK cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_dly_res(&mut self) -> CS_HOLD_DLY_RES_W<CTRL1_SPEC> {
         CS_HOLD_DLY_RES_W::new(self, 2)
     }
diff --git a/esp32s3/src/spi1/ctrl2.rs b/esp32s3/src/spi1/ctrl2.rs
index 98ca548bc9..38a0c1c4dc 100644
--- a/esp32s3/src/spi1/ctrl2.rs
+++ b/esp32s3/src/spi1/ctrl2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - The FSM will be reset."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_reset(&mut self) -> SYNC_RESET_W<CTRL2_SPEC> {
         SYNC_RESET_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi1/date.rs b/esp32s3/src/spi1/date.rs
index c6ae018e98..474fa780f4 100644
--- a/esp32s3/src/spi1/date.rs
+++ b/esp32s3/src/spi1/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - SPI register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/ddr.rs b/esp32s3/src/spi1/ddr.rs
index 316a7fffcb..5cb8b9498f 100644
--- a/esp32s3/src/spi1/ddr.rs
+++ b/esp32s3/src/spi1/ddr.rs
@@ -180,97 +180,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: in DDR mode, 0: in SDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W<DDR_SPEC> {
         SPI_FMEM_DDR_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDRmode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W<DDR_SPEC> {
         SPI_FMEM_VAR_DUMMY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W<DDR_SPEC> {
         SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to reorder TX data of the word in DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W<DDR_SPEC> {
         SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3)
     }
     #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W<DDR_SPEC> {
         SPI_FMEM_DDR_CMD_DIS_W::new(self, 4)
     }
     #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W<DDR_SPEC> {
         SPI_FMEM_OUTMINBYTELEN_W::new(self, 5)
     }
     #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W<DDR_SPEC> {
         SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14)
     }
     #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W<DDR_SPEC> {
         SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21)
     }
     #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_ddr_dqs_loop_mode(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_W<DDR_SPEC> {
         SPI_FMEM_DDR_DQS_LOOP_MODE_W::new(self, 22)
     }
     #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W<DDR_SPEC> {
         SPI_FMEM_CLK_DIFF_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_mode(&mut self) -> SPI_FMEM_HYPERBUS_MODE_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_MODE_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W<DDR_SPEC> {
         SPI_FMEM_DQS_CA_IN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W<DDR_SPEC> {
         SPI_FMEM_CLK_DIFF_INV_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W<DDR_SPEC> {
         SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
     #[inline(always)]
-    #[must_use]
     pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W<DDR_SPEC> {
         SPI_FMEM_HYPERBUS_CA_W::new(self, 30)
     }
diff --git a/esp32s3/src/spi1/ext_addr.rs b/esp32s3/src/spi1/ext_addr.rs
index 25f0b50424..b84e2c7f78 100644
--- a/esp32s3/src/spi1/ext_addr.rs
+++ b/esp32s3/src/spi1/ext_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - The register are the higher 32bits in the 64 bits address mode."]
     #[inline(always)]
-    #[must_use]
     pub fn ext_addr(&mut self) -> EXT_ADDR_W<EXT_ADDR_SPEC> {
         EXT_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/flash_sus_cmd.rs b/esp32s3/src/spi1/flash_sus_cmd.rs
index 52cb49fb4e..ef5a440cee 100644
--- a/esp32s3/src/spi1/flash_sus_cmd.rs
+++ b/esp32s3/src/spi1/flash_sus_cmd.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_per(&mut self) -> FLASH_PER_W<FLASH_SUS_CMD_SPEC> {
         FLASH_PER_W::new(self, 0)
     }
     #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes(&mut self) -> FLASH_PES_W<FLASH_SUS_CMD_SPEC> {
         FLASH_PES_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to add delay time after program erase resume(PER) is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_per_wait_en(&mut self) -> FLASH_PER_WAIT_EN_W<FLASH_SUS_CMD_SPEC> {
         FLASH_PER_WAIT_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to add delay time after program erase suspend(PES) command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes_wait_en(&mut self) -> FLASH_PES_WAIT_EN_W<FLASH_SUS_CMD_SPEC> {
         FLASH_PES_WAIT_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable PES transfer trigger PES transfer option."]
     #[inline(always)]
-    #[must_use]
     pub fn pes_per_en(&mut self) -> PES_PER_EN_W<FLASH_SUS_CMD_SPEC> {
         PES_PER_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate."]
     #[inline(always)]
-    #[must_use]
     pub fn pesr_idle_en(&mut self) -> PESR_IDLE_EN_W<FLASH_SUS_CMD_SPEC> {
         PESR_IDLE_EN_W::new(self, 5)
     }
diff --git a/esp32s3/src/spi1/flash_sus_ctrl.rs b/esp32s3/src/spi1/flash_sus_ctrl.rs
index c88ba8383d..da8886ca11 100644
--- a/esp32s3/src/spi1/flash_sus_ctrl.rs
+++ b/esp32s3/src/spi1/flash_sus_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable auto-suspend function."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes_en(&mut self) -> FLASH_PES_EN_W<FLASH_SUS_CTRL_SPEC> {
         FLASH_PES_EN_W::new(self, 0)
     }
     #[doc = "Bits 1:8 - Program/Erase resume command value."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_per_command(&mut self) -> FLASH_PER_COMMAND_W<FLASH_SUS_CTRL_SPEC> {
         FLASH_PER_COMMAND_W::new(self, 1)
     }
     #[doc = "Bits 9:16 - Program/Erase suspend command value."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes_command(&mut self) -> FLASH_PES_COMMAND_W<FLASH_SUS_CTRL_SPEC> {
         FLASH_PES_COMMAND_W::new(self, 9)
     }
diff --git a/esp32s3/src/spi1/flash_waiti_ctrl.rs b/esp32s3/src/spi1/flash_waiti_ctrl.rs
index a676dda23d..794fe3d64c 100644
--- a/esp32s3/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32s3/src/spi1/flash_waiti_ctrl.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn waiti_en(&mut self) -> WAITI_EN_W<FLASH_WAITI_CTRL_SPEC> {
         WAITI_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR)."]
     #[inline(always)]
-    #[must_use]
     pub fn waiti_dummy(&mut self) -> WAITI_DUMMY_W<FLASH_WAITI_CTRL_SPEC> {
         WAITI_DUMMY_W::new(self, 1)
     }
     #[doc = "Bits 2:9 - The command value of auto wait flash idle transfer(RDSR)."]
     #[inline(always)]
-    #[must_use]
     pub fn waiti_cmd(&mut self) -> WAITI_CMD_W<FLASH_WAITI_CTRL_SPEC> {
         WAITI_CMD_W::new(self, 2)
     }
     #[doc = "Bits 10:15 - The dummy cycle length when wait flash idle(RDSR)."]
     #[inline(always)]
-    #[must_use]
     pub fn waiti_dummy_cyclelen(&mut self) -> WAITI_DUMMY_CYCLELEN_W<FLASH_WAITI_CTRL_SPEC> {
         WAITI_DUMMY_CYCLELEN_W::new(self, 10)
     }
diff --git a/esp32s3/src/spi1/int_clr.rs b/esp32s3/src/spi1/int_clr.rs
index c241a01ffc..a82cd080bf 100644
--- a/esp32s3/src/spi1/int_clr.rs
+++ b/esp32s3/src/spi1/int_clr.rs
@@ -17,25 +17,21 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The clear bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn per_end(&mut self) -> PER_END_W<INT_CLR_SPEC> {
         PER_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear bit for SPI_MEM_PES_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pes_end(&mut self) -> PES_END_W<INT_CLR_SPEC> {
         PES_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_CLR_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
         BROWN_OUT_W::new(self, 3)
     }
diff --git a/esp32s3/src/spi1/int_ena.rs b/esp32s3/src/spi1/int_ena.rs
index 69a10741d5..53b4c2efda 100644
--- a/esp32s3/src/spi1/int_ena.rs
+++ b/esp32s3/src/spi1/int_ena.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn per_end(&mut self) -> PER_END_W<INT_ENA_SPEC> {
         PER_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pes_end(&mut self) -> PES_END_W<INT_ENA_SPEC> {
         PES_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_ENA_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
         BROWN_OUT_W::new(self, 3)
     }
diff --git a/esp32s3/src/spi1/int_raw.rs b/esp32s3/src/spi1/int_raw.rs
index 8197ee4c17..c14cfede93 100644
--- a/esp32s3/src/spi1/int_raw.rs
+++ b/esp32s3/src/spi1/int_raw.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn per_end(&mut self) -> PER_END_W<INT_RAW_SPEC> {
         PER_END_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn pes_end(&mut self) -> PES_END_W<INT_RAW_SPEC> {
         PES_END_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_RAW_SPEC> {
         TOTAL_TRANS_END_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_RAW_SPEC> {
         BROWN_OUT_W::new(self, 3)
     }
diff --git a/esp32s3/src/spi1/misc.rs b/esp32s3/src/spi1/misc.rs
index 810be3e5be..5c9f68a6bc 100644
--- a/esp32s3/src/spi1/misc.rs
+++ b/esp32s3/src/spi1/misc.rs
@@ -77,7 +77,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -85,31 +84,26 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
     #[inline(always)]
-    #[must_use]
     pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
         CS_DIS_W::new(self, 1)
     }
     #[doc = "Bit 9 - 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
         CK_IDLE_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
         CS_KEEP_ACTIVE_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn auto_per(&mut self) -> AUTO_PER_W<MISC_SPEC> {
         AUTO_PER_W::new(self, 11)
     }
diff --git a/esp32s3/src/spi1/miso_dlen.rs b/esp32s3/src/spi1/miso_dlen.rs
index 9c24a24987..969bb3d617 100644
--- a/esp32s3/src/spi1/miso_dlen.rs
+++ b/esp32s3/src/spi1/miso_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The length in bits of DIN phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_dbitlen(&mut self) -> USR_MISO_DBITLEN_W<MISO_DLEN_SPEC> {
         USR_MISO_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/mosi_dlen.rs b/esp32s3/src/spi1/mosi_dlen.rs
index c29866eee9..028efe8939 100644
--- a/esp32s3/src/spi1/mosi_dlen.rs
+++ b/esp32s3/src/spi1/mosi_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The length in bits of DOUT phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_dbitlen(&mut self) -> USR_MOSI_DBITLEN_W<MOSI_DLEN_SPEC> {
         USR_MOSI_DBITLEN_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi1/rd_status.rs b/esp32s3/src/spi1/rd_status.rs
index 5058bfc9cd..5bb1e33071 100644
--- a/esp32s3/src/spi1/rd_status.rs
+++ b/esp32s3/src/spi1/rd_status.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<RD_STATUS_SPEC> {
         STATUS_W::new(self, 0)
     }
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit."]
     #[inline(always)]
-    #[must_use]
     pub fn wb_mode(&mut self) -> WB_MODE_W<RD_STATUS_SPEC> {
         WB_MODE_W::new(self, 16)
     }
diff --git a/esp32s3/src/spi1/sus_status.rs b/esp32s3/src/spi1/sus_status.rs
index 2ac9642ba2..df801c7ad2 100644
--- a/esp32s3/src/spi1/sus_status.rs
+++ b/esp32s3/src/spi1/sus_status.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_sus(&mut self) -> FLASH_SUS_W<SUS_STATUS_SPEC> {
         FLASH_SUS_W::new(self, 0)
     }
     #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_hpm_dly_256(&mut self) -> FLASH_HPM_DLY_256_W<SUS_STATUS_SPEC> {
         FLASH_HPM_DLY_256_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_res_dly_256(&mut self) -> FLASH_RES_DLY_256_W<SUS_STATUS_SPEC> {
         FLASH_RES_DLY_256_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_dp_dly_256(&mut self) -> FLASH_DP_DLY_256_W<SUS_STATUS_SPEC> {
         FLASH_DP_DLY_256_W::new(self, 4)
     }
     #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_per_dly_256(&mut self) -> FLASH_PER_DLY_256_W<SUS_STATUS_SPEC> {
         FLASH_PER_DLY_256_W::new(self, 5)
     }
     #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."]
     #[inline(always)]
-    #[must_use]
     pub fn flash_pes_dly_256(&mut self) -> FLASH_PES_DLY_256_W<SUS_STATUS_SPEC> {
         FLASH_PES_DLY_256_W::new(self, 6)
     }
diff --git a/esp32s3/src/spi1/timing_cali.rs b/esp32s3/src/spi1/timing_cali.rs
index 1e86227fab..5c8caae97d 100644
--- a/esp32s3/src/spi1/timing_cali.rs
+++ b/esp32s3/src/spi1/timing_cali.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
     #[inline(always)]
-    #[must_use]
     pub fn timing_cali(&mut self) -> TIMING_CALI_W<TIMING_CALI_SPEC> {
         TIMING_CALI_W::new(self, 1)
     }
     #[doc = "Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<TIMING_CALI_SPEC> {
         EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
     }
diff --git a/esp32s3/src/spi1/user.rs b/esp32s3/src/spi1/user.rs
index bfca198ff9..706fba8ce1 100644
--- a/esp32s3/src/spi1/user.rs
+++ b/esp32s3/src/spi1/user.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9 - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
         CK_OUT_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 12 - Set this bit to enable 2-bm in DOUT phase in SPI1 write operation."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
         FWRITE_DUAL_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to enable 4-bm in DOUT phase in SPI1 write operation."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
         FWRITE_QUAD_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<USER_SPEC> {
         FWRITE_DIO_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<USER_SPEC> {
         FWRITE_QIO_W::new(self, 15)
     }
     #[doc = "Bit 24 - DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
         USR_MISO_HIGHPART_W::new(self, 24)
     }
     #[doc = "Bit 25 - DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
         USR_MOSI_HIGHPART_W::new(self, 25)
     }
     #[doc = "Bit 26 - SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
         USR_DUMMY_IDLE_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set this bit to enable the DOUT phase of an write-data operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
         USR_MOSI_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to enable enable the DIN phase of a read-data operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
         USR_MISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to enable enable the DUMMY phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
         USR_DUMMY_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to enable enable the ADDR phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
         USR_ADDR_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to enable enable the CMD phase of an operation."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
         USR_COMMAND_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi1/user1.rs b/esp32s3/src/spi1/user1.rs
index 8b31c6e753..7c07e84747 100644
--- a/esp32s3/src/spi1/user1.rs
+++ b/esp32s3/src/spi1/user1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - The SPI_CLK cycle length minus 1 of DUMMY phase."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bits 26:31 - The length in bits of ADDR phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
         USR_ADDR_BITLEN_W::new(self, 26)
     }
diff --git a/esp32s3/src/spi1/user2.rs b/esp32s3/src/spi1/user2.rs
index 5f8be662c4..268479bda5 100644
--- a/esp32s3/src/spi1/user2.rs
+++ b/esp32s3/src/spi1/user2.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value of user defined(USR) command."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<USER2_SPEC> {
         USR_COMMAND_VALUE_W::new(self, 0)
     }
     #[doc = "Bits 28:31 - The length in bits of CMD phase. The register value shall be (bit_num-1)"]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<USER2_SPEC> {
         USR_COMMAND_BITLEN_W::new(self, 28)
     }
diff --git a/esp32s3/src/spi1/w.rs b/esp32s3/src/spi1/w.rs
index 5b54f2c664..a1537b342a 100644
--- a/esp32s3/src/spi1/w.rs
+++ b/esp32s3/src/spi1/w.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - data buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn buf(&mut self) -> BUF_W<W_SPEC> {
         BUF_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi2/addr.rs b/esp32s3/src/spi2/addr.rs
index 03ea07541d..acb1a7dfa7 100644
--- a/esp32s3/src/spi2/addr.rs
+++ b/esp32s3/src/spi2/addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_value(&mut self) -> USR_ADDR_VALUE_W<ADDR_SPEC> {
         USR_ADDR_VALUE_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi2/clk_gate.rs b/esp32s3/src/spi2/clk_gate.rs
index 20f0adfc48..a8142d4385 100644
--- a/esp32s3/src/spi2/clk_gate.rs
+++ b/esp32s3/src/spi2/clk_gate.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to power on the SPI module clock."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_clk_active(&mut self) -> MST_CLK_ACTIVE_W<CLK_GATE_SPEC> {
         MST_CLK_ACTIVE_W::new(self, 1)
     }
     #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_clk_sel(&mut self) -> MST_CLK_SEL_W<CLK_GATE_SPEC> {
         MST_CLK_SEL_W::new(self, 2)
     }
diff --git a/esp32s3/src/spi2/clock.rs b/esp32s3/src/spi2/clock.rs
index 8b450b70fc..78e6f168df 100644
--- a/esp32s3/src/spi2/clock.rs
+++ b/esp32s3/src/spi2/clock.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
         CLKCNT_L_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
         CLKCNT_H_W::new(self, 6)
     }
     #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
         CLKCNT_N_W::new(self, 12)
     }
     #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<CLOCK_SPEC> {
         CLKDIV_PRE_W::new(self, 18)
     }
     #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
         CLK_EQU_SYSCLK_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi2/cmd.rs b/esp32s3/src/spi2/cmd.rs
index 1ada226097..6946c7b016 100644
--- a/esp32s3/src/spi2/cmd.rs
+++ b/esp32s3/src/spi2/cmd.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn conf_bitlen(&mut self) -> CONF_BITLEN_W<CMD_SPEC> {
         CONF_BITLEN_W::new(self, 0)
     }
     #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<CMD_SPEC> {
         UPDATE_W::new(self, 23)
     }
     #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
     #[inline(always)]
-    #[must_use]
     pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
         USR_W::new(self, 24)
     }
diff --git a/esp32s3/src/spi2/ctrl.rs b/esp32s3/src/spi2/ctrl.rs
index f6b5c0d97d..9b3b654b3d 100644
--- a/esp32s3/src/spi2/ctrl.rs
+++ b/esp32s3/src/spi2/ctrl.rs
@@ -174,97 +174,81 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_out(&mut self) -> DUMMY_OUT_W<CTRL_SPEC> {
         DUMMY_OUT_W::new(self, 3)
     }
     #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CTRL_SPEC> {
         FADDR_DUAL_W::new(self, 5)
     }
     #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CTRL_SPEC> {
         FADDR_QUAD_W::new(self, 6)
     }
     #[doc = "Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
         FADDR_OCT_W::new(self, 7)
     }
     #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
         FCMD_DUAL_W::new(self, 8)
     }
     #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
         FCMD_QUAD_W::new(self, 9)
     }
     #[doc = "Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
         FCMD_OCT_W::new(self, 10)
     }
     #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
         FREAD_DUAL_W::new(self, 14)
     }
     #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
         FREAD_QUAD_W::new(self, 15)
     }
     #[doc = "Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fread_oct(&mut self) -> FREAD_OCT_W<CTRL_SPEC> {
         FREAD_OCT_W::new(self, 16)
     }
     #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
         Q_POL_W::new(self, 18)
     }
     #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
         D_POL_W::new(self, 19)
     }
     #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn hold_pol(&mut self) -> HOLD_POL_W<CTRL_SPEC> {
         HOLD_POL_W::new(self, 20)
     }
     #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn wp_pol(&mut self) -> WP_POL_W<CTRL_SPEC> {
         WP_POL_W::new(self, 21)
     }
     #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
         RD_BIT_ORDER_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
         WR_BIT_ORDER_W::new(self, 25)
     }
diff --git a/esp32s3/src/spi2/date.rs b/esp32s3/src/spi2/date.rs
index a31f077a34..d19c97f359 100644
--- a/esp32s3/src/spi2/date.rs
+++ b/esp32s3/src/spi2/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - SPI register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi2/din_mode.rs b/esp32s3/src/spi2/din_mode.rs
index ad01eb127a..3a72f4fc2f 100644
--- a/esp32s3/src/spi2/din_mode.rs
+++ b/esp32s3/src/spi2/din_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
         DIN0_MODE_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
         DIN1_MODE_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
         DIN2_MODE_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
         DIN3_MODE_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_mode(&mut self) -> DIN4_MODE_W<DIN_MODE_SPEC> {
         DIN4_MODE_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_mode(&mut self) -> DIN5_MODE_W<DIN_MODE_SPEC> {
         DIN5_MODE_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_mode(&mut self) -> DIN6_MODE_W<DIN_MODE_SPEC> {
         DIN6_MODE_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_mode(&mut self) -> DIN7_MODE_W<DIN_MODE_SPEC> {
         DIN7_MODE_W::new(self, 14)
     }
     #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<DIN_MODE_SPEC> {
         TIMING_HCLK_ACTIVE_W::new(self, 16)
     }
diff --git a/esp32s3/src/spi2/din_num.rs b/esp32s3/src/spi2/din_num.rs
index a7a17a7335..838b6215ff 100644
--- a/esp32s3/src/spi2/din_num.rs
+++ b/esp32s3/src/spi2/din_num.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
         DIN0_NUM_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
         DIN1_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
         DIN2_NUM_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
         DIN3_NUM_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
         DIN4_NUM_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
         DIN5_NUM_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
         DIN6_NUM_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
         DIN7_NUM_W::new(self, 14)
     }
diff --git a/esp32s3/src/spi2/dma_conf.rs b/esp32s3/src/spi2/dma_conf.rs
index 83e8fa3de1..29de1d9bb0 100644
--- a/esp32s3/src/spi2/dma_conf.rs
+++ b/esp32s3/src/spi2/dma_conf.rs
@@ -96,55 +96,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_slv_seg_trans_en(&mut self) -> DMA_SLV_SEG_TRANS_EN_W<DMA_CONF_SPEC> {
         DMA_SLV_SEG_TRANS_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rx_seg_trans_clr_en(&mut self) -> SLV_RX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
         SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_tx_seg_trans_clr_en(&mut self) -> SLV_TX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
         SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_eof_en(&mut self) -> RX_EOF_EN_W<DMA_CONF_SPEC> {
         RX_EOF_EN_W::new(self, 21)
     }
     #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rx_ena(&mut self) -> DMA_RX_ENA_W<DMA_CONF_SPEC> {
         DMA_RX_ENA_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_tx_ena(&mut self) -> DMA_TX_ENA_W<DMA_CONF_SPEC> {
         DMA_TX_ENA_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_afifo_rst(&mut self) -> RX_AFIFO_RST_W<DMA_CONF_SPEC> {
         RX_AFIFO_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn buf_afifo_rst(&mut self) -> BUF_AFIFO_RST_W<DMA_CONF_SPEC> {
         BUF_AFIFO_RST_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_afifo_rst(&mut self) -> DMA_AFIFO_RST_W<DMA_CONF_SPEC> {
         DMA_AFIFO_RST_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi2/dma_int_clr.rs b/esp32s3/src/spi2/dma_int_clr.rs
index f313dfe4f1..5de2402ddc 100644
--- a/esp32s3/src/spi2/dma_int_clr.rs
+++ b/esp32s3/src/spi2/dma_int_clr.rs
@@ -51,127 +51,106 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_CLR_SPEC> {
         DMA_INFIFO_FULL_ERR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_CLR_SPEC> {
         DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The clear bit for SPI slave Ex_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_CLR_SPEC> {
         SLV_EX_QPI_W::new(self, 2)
     }
     #[doc = "Bit 3 - The clear bit for SPI slave En_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_CLR_SPEC> {
         SLV_EN_QPI_W::new(self, 3)
     }
     #[doc = "Bit 4 - The clear bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_CLR_SPEC> {
         SLV_CMD7_W::new(self, 4)
     }
     #[doc = "Bit 5 - The clear bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_CLR_SPEC> {
         SLV_CMD8_W::new(self, 5)
     }
     #[doc = "Bit 6 - The clear bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_CLR_SPEC> {
         SLV_CMD9_W::new(self, 6)
     }
     #[doc = "Bit 7 - The clear bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_CLR_SPEC> {
         SLV_CMDA_W::new(self, 7)
     }
     #[doc = "Bit 8 - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_CLR_SPEC> {
         SLV_RD_DMA_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9 - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_CLR_SPEC> {
         SLV_WR_DMA_DONE_W::new(self, 9)
     }
     #[doc = "Bit 10 - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_CLR_SPEC> {
         SLV_RD_BUF_DONE_W::new(self, 10)
     }
     #[doc = "Bit 11 - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_CLR_SPEC> {
         SLV_WR_BUF_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12 - The clear bit for SPI_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_CLR_SPEC> {
         TRANS_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_CLR_SPEC> {
         DMA_SEG_TRANS_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_CLR_SPEC> {
         SEG_MAGIC_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_CLR_SPEC> {
         SLV_BUF_ADDR_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_CLR_SPEC> {
         SLV_CMD_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_CLR_SPEC> {
         MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
     }
     #[doc = "Bit 18 - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_CLR_SPEC> {
         MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
     }
     #[doc = "Bit 19 - The clear bit for SPI_APP2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app2(&mut self) -> APP2_W<DMA_INT_CLR_SPEC> {
         APP2_W::new(self, 19)
     }
     #[doc = "Bit 20 - The clear bit for SPI_APP1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app1(&mut self) -> APP1_W<DMA_INT_CLR_SPEC> {
         APP1_W::new(self, 20)
     }
diff --git a/esp32s3/src/spi2/dma_int_ena.rs b/esp32s3/src/spi2/dma_int_ena.rs
index 05ed98c335..f90d704190 100644
--- a/esp32s3/src/spi2/dma_int_ena.rs
+++ b/esp32s3/src/spi2/dma_int_ena.rs
@@ -224,127 +224,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_ENA_SPEC> {
         DMA_INFIFO_FULL_ERR_W::new(self, 0)
     }
     #[doc = "Bit 1 - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_ENA_SPEC> {
         DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The enable bit for SPI slave Ex_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_ENA_SPEC> {
         SLV_EX_QPI_W::new(self, 2)
     }
     #[doc = "Bit 3 - The enable bit for SPI slave En_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_ENA_SPEC> {
         SLV_EN_QPI_W::new(self, 3)
     }
     #[doc = "Bit 4 - The enable bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_ENA_SPEC> {
         SLV_CMD7_W::new(self, 4)
     }
     #[doc = "Bit 5 - The enable bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_ENA_SPEC> {
         SLV_CMD8_W::new(self, 5)
     }
     #[doc = "Bit 6 - The enable bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_ENA_SPEC> {
         SLV_CMD9_W::new(self, 6)
     }
     #[doc = "Bit 7 - The enable bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_ENA_SPEC> {
         SLV_CMDA_W::new(self, 7)
     }
     #[doc = "Bit 8 - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_ENA_SPEC> {
         SLV_RD_DMA_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9 - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_ENA_SPEC> {
         SLV_WR_DMA_DONE_W::new(self, 9)
     }
     #[doc = "Bit 10 - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_ENA_SPEC> {
         SLV_RD_BUF_DONE_W::new(self, 10)
     }
     #[doc = "Bit 11 - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_ENA_SPEC> {
         SLV_WR_BUF_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12 - The enable bit for SPI_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_ENA_SPEC> {
         TRANS_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_ENA_SPEC> {
         DMA_SEG_TRANS_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_ENA_SPEC> {
         SEG_MAGIC_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_ENA_SPEC> {
         SLV_BUF_ADDR_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_ENA_SPEC> {
         SLV_CMD_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_ENA_SPEC> {
         MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
     }
     #[doc = "Bit 18 - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_ENA_SPEC> {
         MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
     }
     #[doc = "Bit 19 - The enable bit for SPI_APP2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app2(&mut self) -> APP2_W<DMA_INT_ENA_SPEC> {
         APP2_W::new(self, 19)
     }
     #[doc = "Bit 20 - The enable bit for SPI_APP1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app1(&mut self) -> APP1_W<DMA_INT_ENA_SPEC> {
         APP1_W::new(self, 20)
     }
diff --git a/esp32s3/src/spi2/dma_int_raw.rs b/esp32s3/src/spi2/dma_int_raw.rs
index 36e00d4a8f..5ad114f0ce 100644
--- a/esp32s3/src/spi2/dma_int_raw.rs
+++ b/esp32s3/src/spi2/dma_int_raw.rs
@@ -224,127 +224,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_RAW_SPEC> {
         DMA_INFIFO_FULL_ERR_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_RAW_SPEC> {
         DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_RAW_SPEC> {
         SLV_EX_QPI_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_RAW_SPEC> {
         SLV_EN_QPI_W::new(self, 3)
     }
     #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_RAW_SPEC> {
         SLV_CMD7_W::new(self, 4)
     }
     #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_RAW_SPEC> {
         SLV_CMD8_W::new(self, 5)
     }
     #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_RAW_SPEC> {
         SLV_CMD9_W::new(self, 6)
     }
     #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_RAW_SPEC> {
         SLV_CMDA_W::new(self, 7)
     }
     #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_RAW_SPEC> {
         SLV_RD_DMA_DONE_W::new(self, 8)
     }
     #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_RAW_SPEC> {
         SLV_WR_DMA_DONE_W::new(self, 9)
     }
     #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_RAW_SPEC> {
         SLV_RD_BUF_DONE_W::new(self, 10)
     }
     #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_RAW_SPEC> {
         SLV_WR_BUF_DONE_W::new(self, 11)
     }
     #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_RAW_SPEC> {
         TRANS_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_RAW_SPEC> {
         DMA_SEG_TRANS_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_RAW_SPEC> {
         SEG_MAGIC_ERR_W::new(self, 14)
     }
     #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_RAW_SPEC> {
         SLV_BUF_ADDR_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_RAW_SPEC> {
         SLV_CMD_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_RAW_SPEC> {
         MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
     }
     #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_RAW_SPEC> {
         MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
     }
     #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."]
     #[inline(always)]
-    #[must_use]
     pub fn app2(&mut self) -> APP2_W<DMA_INT_RAW_SPEC> {
         APP2_W::new(self, 19)
     }
     #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."]
     #[inline(always)]
-    #[must_use]
     pub fn app1(&mut self) -> APP1_W<DMA_INT_RAW_SPEC> {
         APP1_W::new(self, 20)
     }
diff --git a/esp32s3/src/spi2/dma_int_set.rs b/esp32s3/src/spi2/dma_int_set.rs
index 3da095f20a..aa2d02d1e4 100644
--- a/esp32s3/src/spi2/dma_int_set.rs
+++ b/esp32s3/src/spi2/dma_int_set.rs
@@ -51,7 +51,6 @@ impl core::fmt::Debug for crate::generic::Reg<DMA_INT_SET_SPEC> {
 impl W {
     #[doc = "Bit 0 - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_infifo_full_err_int_set(
         &mut self,
     ) -> DMA_INFIFO_FULL_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
@@ -59,7 +58,6 @@ impl W {
     }
     #[doc = "Bit 1 - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_outfifo_empty_err_int_set(
         &mut self,
     ) -> DMA_OUTFIFO_EMPTY_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
@@ -67,97 +65,81 @@ impl W {
     }
     #[doc = "Bit 2 - The software set bit for SPI slave Ex_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_ex_qpi_int_set(&mut self) -> SLV_EX_QPI_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_EX_QPI_INT_SET_W::new(self, 2)
     }
     #[doc = "Bit 3 - The software set bit for SPI slave En_QPI interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_en_qpi_int_set(&mut self) -> SLV_EN_QPI_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_EN_QPI_INT_SET_W::new(self, 3)
     }
     #[doc = "Bit 4 - The software set bit for SPI slave CMD7 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd7_int_set(&mut self) -> SLV_CMD7_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_CMD7_INT_SET_W::new(self, 4)
     }
     #[doc = "Bit 5 - The software set bit for SPI slave CMD8 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd8_int_set(&mut self) -> SLV_CMD8_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_CMD8_INT_SET_W::new(self, 5)
     }
     #[doc = "Bit 6 - The software set bit for SPI slave CMD9 interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd9_int_set(&mut self) -> SLV_CMD9_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_CMD9_INT_SET_W::new(self, 6)
     }
     #[doc = "Bit 7 - The software set bit for SPI slave CMDA interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmda_int_set(&mut self) -> SLV_CMDA_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_CMDA_INT_SET_W::new(self, 7)
     }
     #[doc = "Bit 8 - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_dma_done_int_set(&mut self) -> SLV_RD_DMA_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_RD_DMA_DONE_INT_SET_W::new(self, 8)
     }
     #[doc = "Bit 9 - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_dma_done_int_set(&mut self) -> SLV_WR_DMA_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_WR_DMA_DONE_INT_SET_W::new(self, 9)
     }
     #[doc = "Bit 10 - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rd_buf_done_int_set(&mut self) -> SLV_RD_BUF_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_RD_BUF_DONE_INT_SET_W::new(self, 10)
     }
     #[doc = "Bit 11 - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wr_buf_done_int_set(&mut self) -> SLV_WR_BUF_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_WR_BUF_DONE_INT_SET_W::new(self, 11)
     }
     #[doc = "Bit 12 - The software set bit for SPI_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_done_int_set(&mut self) -> TRANS_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         TRANS_DONE_INT_SET_W::new(self, 12)
     }
     #[doc = "Bit 13 - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_trans_done_int_set(&mut self) -> DMA_SEG_TRANS_DONE_INT_SET_W<DMA_INT_SET_SPEC> {
         DMA_SEG_TRANS_DONE_INT_SET_W::new(self, 13)
     }
     #[doc = "Bit 14 - The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn seg_magic_err_int_set(&mut self) -> SEG_MAGIC_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
         SEG_MAGIC_ERR_INT_SET_W::new(self, 14)
     }
     #[doc = "Bit 15 - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_buf_addr_err_int_set(&mut self) -> SLV_BUF_ADDR_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_BUF_ADDR_ERR_INT_SET_W::new(self, 15)
     }
     #[doc = "Bit 16 - The software set bit for SPI_SLV_CMD_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_cmd_err_int_set(&mut self) -> SLV_CMD_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
         SLV_CMD_ERR_INT_SET_W::new(self, 16)
     }
     #[doc = "Bit 17 - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_rx_afifo_wfull_err_int_set(
         &mut self,
     ) -> MST_RX_AFIFO_WFULL_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
@@ -165,7 +147,6 @@ impl W {
     }
     #[doc = "Bit 18 - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_tx_afifo_rempty_err_int_set(
         &mut self,
     ) -> MST_TX_AFIFO_REMPTY_ERR_INT_SET_W<DMA_INT_SET_SPEC> {
@@ -173,13 +154,11 @@ impl W {
     }
     #[doc = "Bit 19 - The software set bit for SPI_APP2_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app2_int_set(&mut self) -> APP2_INT_SET_W<DMA_INT_SET_SPEC> {
         APP2_INT_SET_W::new(self, 19)
     }
     #[doc = "Bit 20 - The software set bit for SPI_APP1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app1_int_set(&mut self) -> APP1_INT_SET_W<DMA_INT_SET_SPEC> {
         APP1_INT_SET_W::new(self, 20)
     }
diff --git a/esp32s3/src/spi2/dout_mode.rs b/esp32s3/src/spi2/dout_mode.rs
index 86cbf0d32b..b2a344a9b5 100644
--- a/esp32s3/src/spi2/dout_mode.rs
+++ b/esp32s3/src/spi2/dout_mode.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
         DOUT0_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
         DOUT1_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
         DOUT2_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
         DOUT3_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<DOUT_MODE_SPEC> {
         DOUT4_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<DOUT_MODE_SPEC> {
         DOUT5_MODE_W::new(self, 5)
     }
     #[doc = "Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<DOUT_MODE_SPEC> {
         DOUT6_MODE_W::new(self, 6)
     }
     #[doc = "Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<DOUT_MODE_SPEC> {
         DOUT7_MODE_W::new(self, 7)
     }
     #[doc = "Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn d_dqs_mode(&mut self) -> D_DQS_MODE_W<DOUT_MODE_SPEC> {
         D_DQS_MODE_W::new(self, 8)
     }
diff --git a/esp32s3/src/spi2/misc.rs b/esp32s3/src/spi2/misc.rs
index 34adcca723..1e26e6b99d 100644
--- a/esp32s3/src/spi2/misc.rs
+++ b/esp32s3/src/spi2/misc.rs
@@ -184,103 +184,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs0_dis(&mut self) -> CS0_DIS_W<MISC_SPEC> {
         CS0_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs1_dis(&mut self) -> CS1_DIS_W<MISC_SPEC> {
         CS1_DIS_W::new(self, 1)
     }
     #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs2_dis(&mut self) -> CS2_DIS_W<MISC_SPEC> {
         CS2_DIS_W::new(self, 2)
     }
     #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs3_dis(&mut self) -> CS3_DIS_W<MISC_SPEC> {
         CS3_DIS_W::new(self, 3)
     }
     #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs4_dis(&mut self) -> CS4_DIS_W<MISC_SPEC> {
         CS4_DIS_W::new(self, 4)
     }
     #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs5_dis(&mut self) -> CS5_DIS_W<MISC_SPEC> {
         CS5_DIS_W::new(self, 5)
     }
     #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
         CK_DIS_W::new(self, 6)
     }
     #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
         MASTER_CS_POL_W::new(self, 7)
     }
     #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<MISC_SPEC> {
         CLK_DATA_DTR_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<MISC_SPEC> {
         DATA_DTR_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<MISC_SPEC> {
         ADDR_DTR_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<MISC_SPEC> {
         CMD_DTR_EN_W::new(self, 19)
     }
     #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
         SLAVE_CS_POL_W::new(self, 23)
     }
     #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<MISC_SPEC> {
         DQS_IDLE_EDGE_W::new(self, 24)
     }
     #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
         CK_IDLE_EDGE_W::new(self, 29)
     }
     #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
         CS_KEEP_ACTIVE_W::new(self, 30)
     }
     #[doc = "Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
         QUAD_DIN_PIN_SWAP_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi2/ms_dlen.rs b/esp32s3/src/spi2/ms_dlen.rs
index 14a0b1bf7f..fab214224a 100644
--- a/esp32s3/src/spi2/ms_dlen.rs
+++ b/esp32s3/src/spi2/ms_dlen.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ms_data_bitlen(&mut self) -> MS_DATA_BITLEN_W<MS_DLEN_SPEC> {
         MS_DATA_BITLEN_W::new(self, 0)
     }
diff --git a/esp32s3/src/spi2/slave.rs b/esp32s3/src/spi2/slave.rs
index 790884a738..ae7b3d4f66 100644
--- a/esp32s3/src/spi2/slave.rs
+++ b/esp32s3/src/spi2/slave.rs
@@ -116,67 +116,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode(&mut self) -> CLK_MODE_W<SLAVE_SPEC> {
         CLK_MODE_W::new(self, 0)
     }
     #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<SLAVE_SPEC> {
         CLK_MODE_13_W::new(self, 2)
     }
     #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
     #[inline(always)]
-    #[must_use]
     pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<SLAVE_SPEC> {
         RSCK_DATA_OUT_W::new(self, 3)
     }
     #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rddma_bitlen_en(&mut self) -> SLV_RDDMA_BITLEN_EN_W<SLAVE_SPEC> {
         SLV_RDDMA_BITLEN_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrdma_bitlen_en(&mut self) -> SLV_WRDMA_BITLEN_EN_W<SLAVE_SPEC> {
         SLV_WRDMA_BITLEN_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_rdbuf_bitlen_en(&mut self) -> SLV_RDBUF_BITLEN_EN_W<SLAVE_SPEC> {
         SLV_RDBUF_BITLEN_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
     #[inline(always)]
-    #[must_use]
     pub fn slv_wrbuf_bitlen_en(&mut self) -> SLV_WRBUF_BITLEN_EN_W<SLAVE_SPEC> {
         SLV_WRBUF_BITLEN_EN_W::new(self, 11)
     }
     #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<SLAVE_SPEC> {
         DMA_SEG_MAGIC_VALUE_W::new(self, 22)
     }
     #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
         MODE_W::new(self, 26)
     }
     #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
         SOFT_RESET_W::new(self, 27)
     }
     #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_conf(&mut self) -> USR_CONF_W<SLAVE_SPEC> {
         USR_CONF_W::new(self, 28)
     }
diff --git a/esp32s3/src/spi2/slave1.rs b/esp32s3/src/spi2/slave1.rs
index 4e464a31b4..2408ff65a5 100644
--- a/esp32s3/src/spi2/slave1.rs
+++ b/esp32s3/src/spi2/slave1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_data_bitlen(&mut self) -> SLV_DATA_BITLEN_W<SLAVE1_SPEC> {
         SLV_DATA_BITLEN_W::new(self, 0)
     }
     #[doc = "Bits 18:25 - In the slave mode it is the value of command."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_last_command(&mut self) -> SLV_LAST_COMMAND_W<SLAVE1_SPEC> {
         SLV_LAST_COMMAND_W::new(self, 18)
     }
     #[doc = "Bits 26:31 - In the slave mode it is the value of address."]
     #[inline(always)]
-    #[must_use]
     pub fn slv_last_addr(&mut self) -> SLV_LAST_ADDR_W<SLAVE1_SPEC> {
         SLV_LAST_ADDR_W::new(self, 26)
     }
diff --git a/esp32s3/src/spi2/user.rs b/esp32s3/src/spi2/user.rs
index 3f4d00f5b9..666860f980 100644
--- a/esp32s3/src/spi2/user.rs
+++ b/esp32s3/src/spi2/user.rs
@@ -224,127 +224,106 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
         DOUTDIN_W::new(self, 0)
     }
     #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
         QPI_MODE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn opi_mode(&mut self) -> OPI_MODE_W<USER_SPEC> {
         OPI_MODE_W::new(self, 4)
     }
     #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
     #[inline(always)]
-    #[must_use]
     pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
         TSCK_I_EDGE_W::new(self, 5)
     }
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
         CS_HOLD_W::new(self, 6)
     }
     #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
         CS_SETUP_W::new(self, 7)
     }
     #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
     #[inline(always)]
-    #[must_use]
     pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
         RSCK_I_EDGE_W::new(self, 8)
     }
     #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
         CK_OUT_EDGE_W::new(self, 9)
     }
     #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
         FWRITE_DUAL_W::new(self, 12)
     }
     #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
         FWRITE_QUAD_W::new(self, 13)
     }
     #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<USER_SPEC> {
         FWRITE_OCT_W::new(self, 14)
     }
     #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<USER_SPEC> {
         USR_CONF_NXT_W::new(self, 15)
     }
     #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
         SIO_W::new(self, 17)
     }
     #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
         USR_MISO_HIGHPART_W::new(self, 24)
     }
     #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
         USR_MOSI_HIGHPART_W::new(self, 25)
     }
     #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
         USR_DUMMY_IDLE_W::new(self, 26)
     }
     #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
         USR_MOSI_W::new(self, 27)
     }
     #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
         USR_MISO_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
         USR_DUMMY_W::new(self, 29)
     }
     #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
         USR_ADDR_W::new(self, 30)
     }
     #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
         USR_COMMAND_W::new(self, 31)
     }
diff --git a/esp32s3/src/spi2/user1.rs b/esp32s3/src/spi2/user1.rs
index 95f635fa29..ebf323bb54 100644
--- a/esp32s3/src/spi2/user1.rs
+++ b/esp32s3/src/spi2/user1.rs
@@ -64,31 +64,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
         USR_DUMMY_CYCLELEN_W::new(self, 0)
     }
     #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_wfull_err_end_en(&mut self) -> MST_WFULL_ERR_END_EN_W<USER1_SPEC> {
         MST_WFULL_ERR_END_EN_W::new(self, 16)
     }
     #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<USER1_SPEC> {
         CS_SETUP_TIME_W::new(self, 17)
     }
     #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<USER1_SPEC> {
         CS_HOLD_TIME_W::new(self, 22)
     }
     #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
         USR_ADDR_BITLEN_W::new(self, 27)
     }
diff --git a/esp32s3/src/spi2/user2.rs b/esp32s3/src/spi2/user2.rs
index df58aa38b9..3508800e72 100644
--- a/esp32s3/src/spi2/user2.rs
+++ b/esp32s3/src/spi2/user2.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<USER2_SPEC> {
         USR_COMMAND_VALUE_W::new(self, 0)
     }
     #[doc = "Bit 27 - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."]
     #[inline(always)]
-    #[must_use]
     pub fn mst_rempty_err_end_en(&mut self) -> MST_REMPTY_ERR_END_EN_W<USER2_SPEC> {
         MST_REMPTY_ERR_END_EN_W::new(self, 27)
     }
     #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
-    #[must_use]
     pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<USER2_SPEC> {
         USR_COMMAND_BITLEN_W::new(self, 28)
     }
diff --git a/esp32s3/src/spi2/w.rs b/esp32s3/src/spi2/w.rs
index 938ceae002..dfd00d53e3 100644
--- a/esp32s3/src/spi2/w.rs
+++ b/esp32s3/src/spi2/w.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - data buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn buf(&mut self) -> BUF_W<W_SPEC> {
         BUF_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/bt_lpck_div_frac.rs b/esp32s3/src/system/bt_lpck_div_frac.rs
index fb446cb206..9f1a0f4556 100644
--- a/esp32s3/src/system/bt_lpck_div_frac.rs
+++ b/esp32s3/src/system/bt_lpck_div_frac.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_b(&mut self) -> BT_LPCK_DIV_B_W<BT_LPCK_DIV_FRAC_SPEC> {
         BT_LPCK_DIV_B_W::new(self, 0)
     }
     #[doc = "Bits 12:23 - This field is lower power clock frequent division factor a"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_a(&mut self) -> BT_LPCK_DIV_A_W<BT_LPCK_DIV_FRAC_SPEC> {
         BT_LPCK_DIV_A_W::new(self, 12)
     }
     #[doc = "Bit 24 - Set 1 to select rtc-slow clock as rtc low power clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_RTC_SLOW_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set 1 to select 8m clock as rtc low power clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_8M_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set 1 to select xtal clock as rtc low power clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set 1 to select xtal32k clock as low power clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_SEL_XTAL32K_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set 1 to enable RTC low power clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lpclk_rtc_en(&mut self) -> LPCLK_RTC_EN_W<BT_LPCK_DIV_FRAC_SPEC> {
         LPCLK_RTC_EN_W::new(self, 28)
     }
diff --git a/esp32s3/src/system/bt_lpck_div_int.rs b/esp32s3/src/system/bt_lpck_div_int.rs
index b9cfad9e72..9d2f7e3ec0 100644
--- a/esp32s3/src/system/bt_lpck_div_int.rs
+++ b/esp32s3/src/system/bt_lpck_div_int.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor"]
     #[inline(always)]
-    #[must_use]
     pub fn bt_lpck_div_num(&mut self) -> BT_LPCK_DIV_NUM_W<BT_LPCK_DIV_INT_SPEC> {
         BT_LPCK_DIV_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cache_control.rs b/esp32s3/src/system/cache_control.rs
index 421bee011e..5f17e007b8 100644
--- a/esp32s3/src/system/cache_control.rs
+++ b/esp32s3/src/system/cache_control.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable icache clock"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_clk_on(&mut self) -> ICACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
         ICACHE_CLK_ON_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to let icache reset"]
     #[inline(always)]
-    #[must_use]
     pub fn icache_reset(&mut self) -> ICACHE_RESET_W<CACHE_CONTROL_SPEC> {
         ICACHE_RESET_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to enable dcache clock"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_clk_on(&mut self) -> DCACHE_CLK_ON_W<CACHE_CONTROL_SPEC> {
         DCACHE_CLK_ON_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to let dcache reset"]
     #[inline(always)]
-    #[must_use]
     pub fn dcache_reset(&mut self) -> DCACHE_RESET_W<CACHE_CONTROL_SPEC> {
         DCACHE_RESET_W::new(self, 3)
     }
diff --git a/esp32s3/src/system/clock_gate.rs b/esp32s3/src/system/clock_gate.rs
index 6e4f99bd37..c562386a01 100644
--- a/esp32s3/src/system/clock_gate.rs
+++ b/esp32s3/src/system/clock_gate.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/comb_pvt_hvt_conf.rs b/esp32s3/src/system/comb_pvt_hvt_conf.rs
index 9a1f0d3ad2..477bcfc3cc 100644
--- a/esp32s3/src/system/comb_pvt_hvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_hvt_conf.rs
@@ -36,19 +36,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_path_len_hvt(&mut self) -> COMB_PATH_LEN_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
         COMB_PATH_LEN_HVT_W::new(self, 0)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_err_cnt_clr_hvt(&mut self) -> COMB_ERR_CNT_CLR_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
         COMB_ERR_CNT_CLR_HVT_W::new(self, 5)
     }
     #[doc = "Bit 6 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_pvt_monitor_en_hvt(&mut self) -> COMB_PVT_MONITOR_EN_HVT_W<COMB_PVT_HVT_CONF_SPEC> {
         COMB_PVT_MONITOR_EN_HVT_W::new(self, 6)
     }
diff --git a/esp32s3/src/system/comb_pvt_lvt_conf.rs b/esp32s3/src/system/comb_pvt_lvt_conf.rs
index 01e6f41306..987e4583ee 100644
--- a/esp32s3/src/system/comb_pvt_lvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_lvt_conf.rs
@@ -36,19 +36,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_path_len_lvt(&mut self) -> COMB_PATH_LEN_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
         COMB_PATH_LEN_LVT_W::new(self, 0)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_err_cnt_clr_lvt(&mut self) -> COMB_ERR_CNT_CLR_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
         COMB_ERR_CNT_CLR_LVT_W::new(self, 5)
     }
     #[doc = "Bit 6 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_pvt_monitor_en_lvt(&mut self) -> COMB_PVT_MONITOR_EN_LVT_W<COMB_PVT_LVT_CONF_SPEC> {
         COMB_PVT_MONITOR_EN_LVT_W::new(self, 6)
     }
diff --git a/esp32s3/src/system/comb_pvt_nvt_conf.rs b/esp32s3/src/system/comb_pvt_nvt_conf.rs
index adee92c0b9..c7327664f4 100644
--- a/esp32s3/src/system/comb_pvt_nvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_nvt_conf.rs
@@ -36,19 +36,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_path_len_nvt(&mut self) -> COMB_PATH_LEN_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
         COMB_PATH_LEN_NVT_W::new(self, 0)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_err_cnt_clr_nvt(&mut self) -> COMB_ERR_CNT_CLR_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
         COMB_ERR_CNT_CLR_NVT_W::new(self, 5)
     }
     #[doc = "Bit 6 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn comb_pvt_monitor_en_nvt(&mut self) -> COMB_PVT_MONITOR_EN_NVT_W<COMB_PVT_NVT_CONF_SPEC> {
         COMB_PVT_MONITOR_EN_NVT_W::new(self, 6)
     }
diff --git a/esp32s3/src/system/core_1_control_0.rs b/esp32s3/src/system/core_1_control_0.rs
index 33182b095d..be1a08cae7 100644
--- a/esp32s3/src/system/core_1_control_0.rs
+++ b/esp32s3/src/system/core_1_control_0.rs
@@ -47,13 +47,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to stall core1"]
     #[inline(always)]
-    #[must_use]
     pub fn control_core_1_runstall(&mut self) -> CONTROL_CORE_1_RUNSTALL_W<CORE_1_CONTROL_0_SPEC> {
         CONTROL_CORE_1_RUNSTALL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to open core1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn control_core_1_clkgate_en(
         &mut self,
     ) -> CONTROL_CORE_1_CLKGATE_EN_W<CORE_1_CONTROL_0_SPEC> {
@@ -61,7 +59,6 @@ impl W {
     }
     #[doc = "Bit 2 - Set 1 to let core1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn control_core_1_reseting(&mut self) -> CONTROL_CORE_1_RESETING_W<CORE_1_CONTROL_0_SPEC> {
         CONTROL_CORE_1_RESETING_W::new(self, 2)
     }
diff --git a/esp32s3/src/system/core_1_control_1.rs b/esp32s3/src/system/core_1_control_1.rs
index 1c666bd83c..e37e9e506c 100644
--- a/esp32s3/src/system/core_1_control_1.rs
+++ b/esp32s3/src/system/core_1_control_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - it's only a R/W register, no function, software can write any value"]
     #[inline(always)]
-    #[must_use]
     pub fn control_core_1_message(&mut self) -> CONTROL_CORE_1_MESSAGE_W<CORE_1_CONTROL_1_SPEC> {
         CONTROL_CORE_1_MESSAGE_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_0.rs b/esp32s3/src/system/cpu_intr_from_cpu_0.rs
index 4127c13fa3..cc43da8346 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_0(&mut self) -> CPU_INTR_FROM_CPU_0_W<CPU_INTR_FROM_CPU_0_SPEC> {
         CPU_INTR_FROM_CPU_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_1.rs b/esp32s3/src/system/cpu_intr_from_cpu_1.rs
index b41a6a4bde..8e061ea58c 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 1"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_1(&mut self) -> CPU_INTR_FROM_CPU_1_W<CPU_INTR_FROM_CPU_1_SPEC> {
         CPU_INTR_FROM_CPU_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_2.rs b/esp32s3/src/system/cpu_intr_from_cpu_2.rs
index 3dfaaee242..ef9f421fc3 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 2"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_2(&mut self) -> CPU_INTR_FROM_CPU_2_W<CPU_INTR_FROM_CPU_2_SPEC> {
         CPU_INTR_FROM_CPU_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_3.rs b/esp32s3/src/system/cpu_intr_from_cpu_3.rs
index d999f59e27..6e1faa2500 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 3"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_intr_from_cpu_3(&mut self) -> CPU_INTR_FROM_CPU_3_W<CPU_INTR_FROM_CPU_3_SPEC> {
         CPU_INTR_FROM_CPU_3_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/cpu_per_conf.rs b/esp32s3/src/system/cpu_per_conf.rs
index b9e8f34b0f..d03c3829f4 100644
--- a/esp32s3/src/system/cpu_per_conf.rs
+++ b/esp32s3/src/system/cpu_per_conf.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field used to sel cpu clock frequent."]
     #[inline(always)]
-    #[must_use]
     pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PER_CONF_SPEC> {
         CPUPERIOD_SEL_W::new(self, 0)
     }
     #[doc = "Bit 2 - This field used to sel pll frequent."]
     #[inline(always)]
-    #[must_use]
     pub fn pll_freq_sel(&mut self) -> PLL_FREQ_SEL_W<CPU_PER_CONF_SPEC> {
         PLL_FREQ_SEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to force cpu_waiti_clk enable."]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_wait_mode_force_on(&mut self) -> CPU_WAIT_MODE_FORCE_ON_W<CPU_PER_CONF_SPEC> {
         CPU_WAIT_MODE_FORCE_ON_W::new(self, 3)
     }
     #[doc = "Bits 4:7 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
     #[inline(always)]
-    #[must_use]
     pub fn cpu_waiti_delay_num(&mut self) -> CPU_WAITI_DELAY_NUM_W<CPU_PER_CONF_SPEC> {
         CPU_WAITI_DELAY_NUM_W::new(self, 4)
     }
diff --git a/esp32s3/src/system/cpu_peri_clk_en.rs b/esp32s3/src/system/cpu_peri_clk_en.rs
index bf13a8d3c9..6711c1be7f 100644
--- a/esp32s3/src/system/cpu_peri_clk_en.rs
+++ b/esp32s3/src/system/cpu_peri_clk_en.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 6 - Set 1 to open assist_debug module clock"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en_assist_debug(&mut self) -> CLK_EN_ASSIST_DEBUG_W<CPU_PERI_CLK_EN_SPEC> {
         CLK_EN_ASSIST_DEBUG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to open dedicated_gpio module clk"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en_dedicated_gpio(&mut self) -> CLK_EN_DEDICATED_GPIO_W<CPU_PERI_CLK_EN_SPEC> {
         CLK_EN_DEDICATED_GPIO_W::new(self, 7)
     }
diff --git a/esp32s3/src/system/cpu_peri_rst_en.rs b/esp32s3/src/system/cpu_peri_rst_en.rs
index 047df82979..db44d3a421 100644
--- a/esp32s3/src/system/cpu_peri_rst_en.rs
+++ b/esp32s3/src/system/cpu_peri_rst_en.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 6 - Set 1 to let assist_debug module reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_en_assist_debug(&mut self) -> RST_EN_ASSIST_DEBUG_W<CPU_PERI_RST_EN_SPEC> {
         RST_EN_ASSIST_DEBUG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to let dedicated_gpio module reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_en_dedicated_gpio(&mut self) -> RST_EN_DEDICATED_GPIO_W<CPU_PERI_RST_EN_SPEC> {
         RST_EN_DEDICATED_GPIO_W::new(self, 7)
     }
diff --git a/esp32s3/src/system/date.rs b/esp32s3/src/system/date.rs
index f2c3fd0092..882a543d3f 100644
--- a/esp32s3/src/system/date.rs
+++ b/esp32s3/src/system/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/edma_ctrl.rs b/esp32s3/src/system/edma_ctrl.rs
index 502b5767ce..6ea46f7988 100644
--- a/esp32s3/src/system/edma_ctrl.rs
+++ b/esp32s3/src/system/edma_ctrl.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable EDMA clock."]
     #[inline(always)]
-    #[must_use]
     pub fn edma_clk_on(&mut self) -> EDMA_CLK_ON_W<EDMA_CTRL_SPEC> {
         EDMA_CLK_ON_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to let EDMA reset"]
     #[inline(always)]
-    #[must_use]
     pub fn edma_reset(&mut self) -> EDMA_RESET_W<EDMA_CTRL_SPEC> {
         EDMA_RESET_W::new(self, 1)
     }
diff --git a/esp32s3/src/system/external_device_encrypt_decrypt_control.rs b/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
index 25435a3dbe..96c30e8959 100644
--- a/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
@@ -66,7 +66,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable the SPI manual encrypt."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_spi_manual_encrypt(
         &mut self,
     ) -> ENABLE_SPI_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -74,7 +73,6 @@ impl W {
     }
     #[doc = "Bit 1 - Set 1 to enable download DB encrypt."]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_db_encrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_DB_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -82,7 +80,6 @@ impl W {
     }
     #[doc = "Bit 2 - Set 1 to enable download G0CB decrypt"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_g0cb_decrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_G0CB_DECRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
@@ -90,7 +87,6 @@ impl W {
     }
     #[doc = "Bit 3 - Set 1 to enable download manual encrypt"]
     #[inline(always)]
-    #[must_use]
     pub fn enable_download_manual_encrypt(
         &mut self,
     ) -> ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
diff --git a/esp32s3/src/system/mem_pd_mask.rs b/esp32s3/src/system/mem_pd_mask.rs
index 3904214821..5e24766a79 100644
--- a/esp32s3/src/system/mem_pd_mask.rs
+++ b/esp32s3/src/system/mem_pd_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to mask memory power down."]
     #[inline(always)]
-    #[must_use]
     pub fn lslp_mem_pd_mask(&mut self) -> LSLP_MEM_PD_MASK_W<MEM_PD_MASK_SPEC> {
         LSLP_MEM_PD_MASK_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/mem_pvt.rs b/esp32s3/src/system/mem_pvt.rs
index 01e2cbd7f4..63016446cd 100644
--- a/esp32s3/src/system/mem_pvt.rs
+++ b/esp32s3/src/system/mem_pvt.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_path_len(&mut self) -> MEM_PATH_LEN_W<MEM_PVT_SPEC> {
         MEM_PATH_LEN_W::new(self, 0)
     }
     #[doc = "Bit 4 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_err_cnt_clr(&mut self) -> MEM_ERR_CNT_CLR_W<MEM_PVT_SPEC> {
         MEM_ERR_CNT_CLR_W::new(self, 4)
     }
     #[doc = "Bit 5 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn monitor_en(&mut self) -> MONITOR_EN_W<MEM_PVT_SPEC> {
         MONITOR_EN_W::new(self, 5)
     }
     #[doc = "Bits 22:23 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn mem_vt_sel(&mut self) -> MEM_VT_SEL_W<MEM_PVT_SPEC> {
         MEM_VT_SEL_W::new(self, 22)
     }
diff --git a/esp32s3/src/system/perip_clk_en0.rs b/esp32s3/src/system/perip_clk_en0.rs
index 6e15665560..5541c69cd2 100644
--- a/esp32s3/src/system/perip_clk_en0.rs
+++ b/esp32s3/src/system/perip_clk_en0.rs
@@ -334,193 +334,161 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable TIMERS clock"]
     #[inline(always)]
-    #[must_use]
     pub fn timers_clk_en(&mut self) -> TIMERS_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERS_CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI01_CLK_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to enable UART clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to enable WDG clock"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_clk_en(&mut self) -> WDG_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         WDG_CLK_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set 1 to enable I2S0 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_clk_en(&mut self) -> I2S0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2S0_CLK_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set 1 to enable UART1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART1_CLK_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set 1 to enable SPI2 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI2_CLK_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to enable I2C_EXT0 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2C_EXT0_CLK_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to enable UHCI0 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_clk_en(&mut self) -> UHCI0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UHCI0_CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set 1 to enable RMT clock"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_clk_en(&mut self) -> RMT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         RMT_CLK_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set 1 to enable PCNT clock"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_clk_en(&mut self) -> PCNT_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PCNT_CLK_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set 1 to enable LEDC clock"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         LEDC_CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set 1 to enable UHCI1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_clk_en(&mut self) -> UHCI1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UHCI1_CLK_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set 1 to enable TIMERGROUP clock"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERGROUP_CLK_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set 1 to enable EFUSE clock"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_clk_en(&mut self) -> EFUSE_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         EFUSE_CLK_EN_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set 1 to enable TIMERGROUP1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_clk_en(&mut self) -> TIMERGROUP1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TIMERGROUP1_CLK_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set 1 to enable SPI3 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_clk_en(&mut self) -> SPI3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI3_CLK_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set 1 to enable PWM0 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_clk_en(&mut self) -> PWM0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM0_CLK_EN_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set 1 to enable I2C_EXT1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_clk_en(&mut self) -> I2C_EXT1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2C_EXT1_CLK_EN_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set 1 to enable CAN clock"]
     #[inline(always)]
-    #[must_use]
     pub fn twai_clk_en(&mut self) -> TWAI_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         TWAI_CLK_EN_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set 1 to enable PWM1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_clk_en(&mut self) -> PWM1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM1_CLK_EN_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set 1 to enable I2S1 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_clk_en(&mut self) -> I2S1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         I2S1_CLK_EN_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set 1 to enable SPI2_DMA clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_clk_en(&mut self) -> SPI2_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI2_DMA_CLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set 1 to enable USB clock"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_clk_en(&mut self) -> USB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         USB_CLK_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set 1 to enable UART_MEM clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         UART_MEM_CLK_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set 1 to enable PWM2 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_clk_en(&mut self) -> PWM2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM2_CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set 1 to enable PWM3 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_clk_en(&mut self) -> PWM3_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         PWM3_CLK_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set 1 to enable SPI4 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_clk_en(&mut self) -> SPI3_DMA_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI3_DMA_CLK_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set 1 to enable APB_SARADC clock"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         APB_SARADC_CLK_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set 1 to enable SYSTEMTIMER clock"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SYSTIMER_CLK_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set 1 to enable ADC2_ARB clock"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         ADC2_ARB_CLK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set 1 to enable SPI4 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_clk_en(&mut self) -> SPI4_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
         SPI4_CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/system/perip_clk_en1.rs b/esp32s3/src/system/perip_clk_en1.rs
index 67b09026d0..ae8734f78a 100644
--- a/esp32s3/src/system/perip_clk_en1.rs
+++ b/esp32s3/src/system/perip_clk_en1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_backup_clk_en(&mut self) -> PERI_BACKUP_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         PERI_BACKUP_CLK_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to enable AES clock"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_aes_clk_en(&mut self) -> CRYPTO_AES_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_AES_CLK_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to enable SHA clock"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_sha_clk_en(&mut self) -> CRYPTO_SHA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_SHA_CLK_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to enable RSA clock"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_rsa_clk_en(&mut self) -> CRYPTO_RSA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_RSA_CLK_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set 1 to enable DS clock"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_ds_clk_en(&mut self) -> CRYPTO_DS_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_DS_CLK_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set 1 to enable HMAC clock"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_hmac_clk_en(&mut self) -> CRYPTO_HMAC_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         CRYPTO_HMAC_CLK_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set 1 to enable DMA clock"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         DMA_CLK_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to enable SDIO_HOST clock"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_host_clk_en(&mut self) -> SDIO_HOST_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         SDIO_HOST_CLK_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to enable LCD_CAM clock"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cam_clk_en(&mut self) -> LCD_CAM_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         LCD_CAM_CLK_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set 1 to enable UART2 clock"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         UART2_CLK_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set 1 to enable USB_DEVICE clock"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_device_clk_en(&mut self) -> USB_DEVICE_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
         USB_DEVICE_CLK_EN_W::new(self, 10)
     }
diff --git a/esp32s3/src/system/perip_rst_en0.rs b/esp32s3/src/system/perip_rst_en0.rs
index 17eb55de59..34915c24b7 100644
--- a/esp32s3/src/system/perip_rst_en0.rs
+++ b/esp32s3/src/system/perip_rst_en0.rs
@@ -334,193 +334,161 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to let TIMERS reset"]
     #[inline(always)]
-    #[must_use]
     pub fn timers_rst(&mut self) -> TIMERS_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERS_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to let SPI01 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi01_rst(&mut self) -> SPI01_RST_W<PERIP_RST_EN0_SPEC> {
         SPI01_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to let UART reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rst(&mut self) -> UART_RST_W<PERIP_RST_EN0_SPEC> {
         UART_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to let WDG reset"]
     #[inline(always)]
-    #[must_use]
     pub fn wdg_rst(&mut self) -> WDG_RST_W<PERIP_RST_EN0_SPEC> {
         WDG_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set 1 to let I2S0 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s0_rst(&mut self) -> I2S0_RST_W<PERIP_RST_EN0_SPEC> {
         I2S0_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set 1 to let UART1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_rst(&mut self) -> UART1_RST_W<PERIP_RST_EN0_SPEC> {
         UART1_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set 1 to let SPI2 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_rst(&mut self) -> SPI2_RST_W<PERIP_RST_EN0_SPEC> {
         SPI2_RST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to let I2C_EXT0 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext0_rst(&mut self) -> I2C_EXT0_RST_W<PERIP_RST_EN0_SPEC> {
         I2C_EXT0_RST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to let UHCI0 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci0_rst(&mut self) -> UHCI0_RST_W<PERIP_RST_EN0_SPEC> {
         UHCI0_RST_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set 1 to let RMT reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rmt_rst(&mut self) -> RMT_RST_W<PERIP_RST_EN0_SPEC> {
         RMT_RST_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set 1 to let PCNT reset"]
     #[inline(always)]
-    #[must_use]
     pub fn pcnt_rst(&mut self) -> PCNT_RST_W<PERIP_RST_EN0_SPEC> {
         PCNT_RST_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set 1 to let LEDC reset"]
     #[inline(always)]
-    #[must_use]
     pub fn ledc_rst(&mut self) -> LEDC_RST_W<PERIP_RST_EN0_SPEC> {
         LEDC_RST_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set 1 to let UHCI1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uhci1_rst(&mut self) -> UHCI1_RST_W<PERIP_RST_EN0_SPEC> {
         UHCI1_RST_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set 1 to let TIMERGROUP reset"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup_rst(&mut self) -> TIMERGROUP_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERGROUP_RST_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set 1 to let EFUSE reset"]
     #[inline(always)]
-    #[must_use]
     pub fn efuse_rst(&mut self) -> EFUSE_RST_W<PERIP_RST_EN0_SPEC> {
         EFUSE_RST_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set 1 to let TIMERGROUP1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn timergroup1_rst(&mut self) -> TIMERGROUP1_RST_W<PERIP_RST_EN0_SPEC> {
         TIMERGROUP1_RST_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set 1 to let SPI3 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_rst(&mut self) -> SPI3_RST_W<PERIP_RST_EN0_SPEC> {
         SPI3_RST_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set 1 to let PWM0 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm0_rst(&mut self) -> PWM0_RST_W<PERIP_RST_EN0_SPEC> {
         PWM0_RST_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set 1 to let I2C_EXT1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c_ext1_rst(&mut self) -> I2C_EXT1_RST_W<PERIP_RST_EN0_SPEC> {
         I2C_EXT1_RST_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set 1 to let CAN reset"]
     #[inline(always)]
-    #[must_use]
     pub fn twai_rst(&mut self) -> TWAI_RST_W<PERIP_RST_EN0_SPEC> {
         TWAI_RST_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set 1 to let PWM1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm1_rst(&mut self) -> PWM1_RST_W<PERIP_RST_EN0_SPEC> {
         PWM1_RST_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set 1 to let I2S1 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn i2s1_rst(&mut self) -> I2S1_RST_W<PERIP_RST_EN0_SPEC> {
         I2S1_RST_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set 1 to let SPI2 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi2_dma_rst(&mut self) -> SPI2_DMA_RST_W<PERIP_RST_EN0_SPEC> {
         SPI2_DMA_RST_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set 1 to let USB reset"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_rst(&mut self) -> USB_RST_W<PERIP_RST_EN0_SPEC> {
         USB_RST_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set 1 to let UART_MEM reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uart_mem_rst(&mut self) -> UART_MEM_RST_W<PERIP_RST_EN0_SPEC> {
         UART_MEM_RST_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set 1 to let PWM2 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm2_rst(&mut self) -> PWM2_RST_W<PERIP_RST_EN0_SPEC> {
         PWM2_RST_W::new(self, 25)
     }
     #[doc = "Bit 26 - Set 1 to let PWM3 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm3_rst(&mut self) -> PWM3_RST_W<PERIP_RST_EN0_SPEC> {
         PWM3_RST_W::new(self, 26)
     }
     #[doc = "Bit 27 - Set 1 to let SPI3 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi3_dma_rst(&mut self) -> SPI3_DMA_RST_W<PERIP_RST_EN0_SPEC> {
         SPI3_DMA_RST_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set 1 to let APB_SARADC reset"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_saradc_rst(&mut self) -> APB_SARADC_RST_W<PERIP_RST_EN0_SPEC> {
         APB_SARADC_RST_W::new(self, 28)
     }
     #[doc = "Bit 29 - Set 1 to let SYSTIMER reset"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_rst(&mut self) -> SYSTIMER_RST_W<PERIP_RST_EN0_SPEC> {
         SYSTIMER_RST_W::new(self, 29)
     }
     #[doc = "Bit 30 - Set 1 to let ADC2_ARB reset"]
     #[inline(always)]
-    #[must_use]
     pub fn adc2_arb_rst(&mut self) -> ADC2_ARB_RST_W<PERIP_RST_EN0_SPEC> {
         ADC2_ARB_RST_W::new(self, 30)
     }
     #[doc = "Bit 31 - Set 1 to let SPI4 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn spi4_rst(&mut self) -> SPI4_RST_W<PERIP_RST_EN0_SPEC> {
         SPI4_RST_W::new(self, 31)
     }
diff --git a/esp32s3/src/system/perip_rst_en1.rs b/esp32s3/src/system/perip_rst_en1.rs
index 04571b76cd..2b06da975e 100644
--- a/esp32s3/src/system/perip_rst_en1.rs
+++ b/esp32s3/src/system/perip_rst_en1.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to let BACKUP reset"]
     #[inline(always)]
-    #[must_use]
     pub fn peri_backup_rst(&mut self) -> PERI_BACKUP_RST_W<PERIP_RST_EN1_SPEC> {
         PERI_BACKUP_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to let CRYPTO_AES reset"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_aes_rst(&mut self) -> CRYPTO_AES_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_AES_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to let CRYPTO_SHA reset"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_sha_rst(&mut self) -> CRYPTO_SHA_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_SHA_RST_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set 1 to let CRYPTO_RSA reset"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_rsa_rst(&mut self) -> CRYPTO_RSA_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_RSA_RST_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set 1 to let CRYPTO_DS reset"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_ds_rst(&mut self) -> CRYPTO_DS_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_DS_RST_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set 1 to let CRYPTO_HMAC reset"]
     #[inline(always)]
-    #[must_use]
     pub fn crypto_hmac_rst(&mut self) -> CRYPTO_HMAC_RST_W<PERIP_RST_EN1_SPEC> {
         CRYPTO_HMAC_RST_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set 1 to let DMA reset"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_rst(&mut self) -> DMA_RST_W<PERIP_RST_EN1_SPEC> {
         DMA_RST_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set 1 to let SDIO_HOST reset"]
     #[inline(always)]
-    #[must_use]
     pub fn sdio_host_rst(&mut self) -> SDIO_HOST_RST_W<PERIP_RST_EN1_SPEC> {
         SDIO_HOST_RST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set 1 to let LCD_CAM reset"]
     #[inline(always)]
-    #[must_use]
     pub fn lcd_cam_rst(&mut self) -> LCD_CAM_RST_W<PERIP_RST_EN1_SPEC> {
         LCD_CAM_RST_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set 1 to let UART2 reset"]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_rst(&mut self) -> UART2_RST_W<PERIP_RST_EN1_SPEC> {
         UART2_RST_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set 1 to let USB_DEVICE reset"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_device_rst(&mut self) -> USB_DEVICE_RST_W<PERIP_RST_EN1_SPEC> {
         USB_DEVICE_RST_W::new(self, 10)
     }
diff --git a/esp32s3/src/system/redundant_eco_ctrl.rs b/esp32s3/src/system/redundant_eco_ctrl.rs
index de1a40fb15..0b15bff7d8 100644
--- a/esp32s3/src/system/redundant_eco_ctrl.rs
+++ b/esp32s3/src/system/redundant_eco_ctrl.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
-    #[must_use]
     pub fn redundant_eco_drive(&mut self) -> REDUNDANT_ECO_DRIVE_W<REDUNDANT_ECO_CTRL_SPEC> {
         REDUNDANT_ECO_DRIVE_W::new(self, 0)
     }
diff --git a/esp32s3/src/system/rsa_pd_ctrl.rs b/esp32s3/src/system/rsa_pd_ctrl.rs
index 751484e510..2400c433a8 100644
--- a/esp32s3/src/system/rsa_pd_ctrl.rs
+++ b/esp32s3/src/system/rsa_pd_ctrl.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_pd(&mut self) -> RSA_MEM_PD_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set 1 to force power up RSA memory, this bit has the second highest priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_force_pu(&mut self) -> RSA_MEM_FORCE_PU_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_FORCE_PU_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set 1 to force power down RSA memory,this bit has the highest priority."]
     #[inline(always)]
-    #[must_use]
     pub fn rsa_mem_force_pd(&mut self) -> RSA_MEM_FORCE_PD_W<RSA_PD_CTRL_SPEC> {
         RSA_MEM_FORCE_PD_W::new(self, 2)
     }
diff --git a/esp32s3/src/system/rtc_fastmem_config.rs b/esp32s3/src/system/rtc_fastmem_config.rs
index bd9a320e38..5b816e9037 100644
--- a/esp32s3/src/system/rtc_fastmem_config.rs
+++ b/esp32s3/src/system/rtc_fastmem_config.rs
@@ -52,19 +52,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 8 - Set 1 to start the CRC of RTC memory"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_start(&mut self) -> RTC_MEM_CRC_START_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_START_W::new(self, 8)
     }
     #[doc = "Bits 9:19 - This field is used to set address of RTC memory for CRC."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_addr(&mut self) -> RTC_MEM_CRC_ADDR_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_ADDR_W::new(self, 9)
     }
     #[doc = "Bits 20:30 - This field is used to set length of RTC memory for CRC based on start address."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_mem_crc_len(&mut self) -> RTC_MEM_CRC_LEN_W<RTC_FASTMEM_CONFIG_SPEC> {
         RTC_MEM_CRC_LEN_W::new(self, 20)
     }
diff --git a/esp32s3/src/system/sysclk_conf.rs b/esp32s3/src/system/sysclk_conf.rs
index cb5952bf5c..8ff829486e 100644
--- a/esp32s3/src/system/sysclk_conf.rs
+++ b/esp32s3/src/system/sysclk_conf.rs
@@ -50,13 +50,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL_CLK."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
         PRE_DIV_CNT_W::new(self, 0)
     }
     #[doc = "Bits 10:11 - This field is used to select soc clock."]
     #[inline(always)]
-    #[must_use]
     pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<SYSCLK_CONF_SPEC> {
         SOC_CLK_SEL_W::new(self, 10)
     }
diff --git a/esp32s3/src/systimer/comp_load.rs b/esp32s3/src/systimer/comp_load.rs
index 3194371312..65145bf616 100644
--- a/esp32s3/src/systimer/comp_load.rs
+++ b/esp32s3/src/systimer/comp_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<COMP_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - timer comp0 sync enable signal"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<COMP_LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/conf.rs b/esp32s3/src/systimer/conf.rs
index c1a033b0b5..ca76bf9c86 100644
--- a/esp32s3/src/systimer/conf.rs
+++ b/esp32s3/src/systimer/conf.rs
@@ -136,67 +136,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
-    #[must_use]
     pub fn systimer_clk_fo(&mut self) -> SYSTIMER_CLK_FO_W<CONF_SPEC> {
         SYSTIMER_CLK_FO_W::new(self, 0)
     }
     #[doc = "Bit 22 - target2 work enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target2_work_en(&mut self) -> TARGET2_WORK_EN_W<CONF_SPEC> {
         TARGET2_WORK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - target1 work enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target1_work_en(&mut self) -> TARGET1_WORK_EN_W<CONF_SPEC> {
         TARGET1_WORK_EN_W::new(self, 23)
     }
     #[doc = "Bit 24 - target0 work enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target0_work_en(&mut self) -> TARGET0_WORK_EN_W<CONF_SPEC> {
         TARGET0_WORK_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - If timer unit1 is stalled when core1 stalled"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit1_core1_stall_en(&mut self) -> TIMER_UNIT1_CORE1_STALL_EN_W<CONF_SPEC> {
         TIMER_UNIT1_CORE1_STALL_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - If timer unit1 is stalled when core0 stalled"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit1_core0_stall_en(&mut self) -> TIMER_UNIT1_CORE0_STALL_EN_W<CONF_SPEC> {
         TIMER_UNIT1_CORE0_STALL_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - If timer unit0 is stalled when core1 stalled"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit0_core1_stall_en(&mut self) -> TIMER_UNIT0_CORE1_STALL_EN_W<CONF_SPEC> {
         TIMER_UNIT0_CORE1_STALL_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - If timer unit0 is stalled when core0 stalled"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit0_core0_stall_en(&mut self) -> TIMER_UNIT0_CORE0_STALL_EN_W<CONF_SPEC> {
         TIMER_UNIT0_CORE0_STALL_EN_W::new(self, 28)
     }
     #[doc = "Bit 29 - timer unit1 work enable"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit1_work_en(&mut self) -> TIMER_UNIT1_WORK_EN_W<CONF_SPEC> {
         TIMER_UNIT1_WORK_EN_W::new(self, 29)
     }
     #[doc = "Bit 30 - timer unit0 work enable"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit0_work_en(&mut self) -> TIMER_UNIT0_WORK_EN_W<CONF_SPEC> {
         TIMER_UNIT0_WORK_EN_W::new(self, 30)
     }
     #[doc = "Bit 31 - register file clk gating"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/systimer/date.rs b/esp32s3/src/systimer/date.rs
index 85e0ef45c6..aec74d2d0c 100644
--- a/esp32s3/src/systimer/date.rs
+++ b/esp32s3/src/systimer/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - systimer register version"]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/int_clr.rs b/esp32s3/src/systimer/int_clr.rs
index 06260e5ca1..7a322a9bd7 100644
--- a/esp32s3/src/systimer/int_clr.rs
+++ b/esp32s3/src/systimer/int_clr.rs
@@ -13,7 +13,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self, n: u8) -> TARGET_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -21,19 +20,16 @@ impl W {
     }
     #[doc = "Bit 0 - interupt0 clear"]
     #[inline(always)]
-    #[must_use]
     pub fn target0(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 0)
     }
     #[doc = "Bit 1 - interupt1 clear"]
     #[inline(always)]
-    #[must_use]
     pub fn target1(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 1)
     }
     #[doc = "Bit 2 - interupt2 clear"]
     #[inline(always)]
-    #[must_use]
     pub fn target2(&mut self) -> TARGET_W<INT_CLR_SPEC> {
         TARGET_W::new(self, 2)
     }
@@ -47,7 +43,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s3/src/systimer/int_ena.rs b/esp32s3/src/systimer/int_ena.rs
index 23d45402ff..82161f02c6 100644
--- a/esp32s3/src/systimer/int_ena.rs
+++ b/esp32s3/src/systimer/int_ena.rs
@@ -53,7 +53,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self, n: u8) -> TARGET_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -61,19 +60,16 @@ impl W {
     }
     #[doc = "Bit 0 - interupt0 enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target0(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 0)
     }
     #[doc = "Bit 1 - interupt1 enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target1(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 1)
     }
     #[doc = "Bit 2 - interupt2 enable"]
     #[inline(always)]
-    #[must_use]
     pub fn target2(&mut self) -> TARGET_W<INT_ENA_SPEC> {
         TARGET_W::new(self, 2)
     }
diff --git a/esp32s3/src/systimer/int_raw.rs b/esp32s3/src/systimer/int_raw.rs
index ad619febb9..017321fd87 100644
--- a/esp32s3/src/systimer/int_raw.rs
+++ b/esp32s3/src/systimer/int_raw.rs
@@ -53,7 +53,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self, n: u8) -> TARGET_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 3][n as usize];
@@ -61,19 +60,16 @@ impl W {
     }
     #[doc = "Bit 0 - interupt0 raw"]
     #[inline(always)]
-    #[must_use]
     pub fn target0(&mut self) -> TARGET_W<INT_RAW_SPEC> {
         TARGET_W::new(self, 0)
     }
     #[doc = "Bit 1 - interupt1 raw"]
     #[inline(always)]
-    #[must_use]
     pub fn target1(&mut self) -> TARGET_W<INT_RAW_SPEC> {
         TARGET_W::new(self, 1)
     }
     #[doc = "Bit 2 - interupt2 raw"]
     #[inline(always)]
-    #[must_use]
     pub fn target2(&mut self) -> TARGET_W<INT_RAW_SPEC> {
         TARGET_W::new(self, 2)
     }
diff --git a/esp32s3/src/systimer/target_conf.rs b/esp32s3/src/systimer/target_conf.rs
index ad465124d5..9d3229b115 100644
--- a/esp32s3/src/systimer/target_conf.rs
+++ b/esp32s3/src/systimer/target_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
-    #[must_use]
     pub fn period(&mut self) -> PERIOD_W<TARGET_CONF_SPEC> {
         PERIOD_W::new(self, 0)
     }
     #[doc = "Bit 30 - Set target0 to period mode"]
     #[inline(always)]
-    #[must_use]
     pub fn period_mode(&mut self) -> PERIOD_MODE_W<TARGET_CONF_SPEC> {
         PERIOD_MODE_W::new(self, 30)
     }
     #[doc = "Bit 31 - select which unit to compare"]
     #[inline(always)]
-    #[must_use]
     pub fn timer_unit_sel(&mut self) -> TIMER_UNIT_SEL_W<TARGET_CONF_SPEC> {
         TIMER_UNIT_SEL_W::new(self, 31)
     }
diff --git a/esp32s3/src/systimer/trgt/hi.rs b/esp32s3/src/systimer/trgt/hi.rs
index 36b8397729..c34aac1756 100644
--- a/esp32s3/src/systimer/trgt/hi.rs
+++ b/esp32s3/src/systimer/trgt/hi.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - timer taget0 high 20 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn hi(&mut self) -> HI_W<HI_SPEC> {
         HI_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/trgt/lo.rs b/esp32s3/src/systimer/trgt/lo.rs
index 4b9aba9b31..3ac0a3df6b 100644
--- a/esp32s3/src/systimer/trgt/lo.rs
+++ b/esp32s3/src/systimer/trgt/lo.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - timer taget0 low 32 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn lo(&mut self) -> LO_W<LO_SPEC> {
         LO_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/unit_load.rs b/esp32s3/src/systimer/unit_load.rs
index d7131aea74..94a217b2b0 100644
--- a/esp32s3/src/systimer/unit_load.rs
+++ b/esp32s3/src/systimer/unit_load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<UNIT_LOAD_SPEC> {
 impl W {
     #[doc = "Bit 0 - timer unit0 sync enable signal"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<UNIT_LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/unit_op.rs b/esp32s3/src/systimer/unit_op.rs
index 89b506eb04..f4f5c65665 100644
--- a/esp32s3/src/systimer/unit_op.rs
+++ b/esp32s3/src/systimer/unit_op.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<UNIT_OP_SPEC> {
         UPDATE_W::new(self, 30)
     }
diff --git a/esp32s3/src/systimer/unitload/hi.rs b/esp32s3/src/systimer/unitload/hi.rs
index 63e3720842..ff49b6d094 100644
--- a/esp32s3/src/systimer/unitload/hi.rs
+++ b/esp32s3/src/systimer/unitload/hi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<HI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32s3/src/systimer/unitload/lo.rs b/esp32s3/src/systimer/unitload/lo.rs
index 9569a393b8..f8b0d7491b 100644
--- a/esp32s3/src/systimer/unitload/lo.rs
+++ b/esp32s3/src/systimer/unitload/lo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/int_clr.rs b/esp32s3/src/timg0/int_clr.rs
index 6fb011ddf5..afc4de795f 100644
--- a/esp32s3/src/timg0/int_clr.rs
+++ b/esp32s3/src/timg0/int_clr.rs
@@ -15,7 +15,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -23,19 +22,16 @@ impl W {
     }
     #[doc = "Bit 0 - Set this bit to clear the TIMG_T0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the TIMG_T1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the TIMG_WDT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 2)
     }
@@ -49,7 +45,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC {
 impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x05;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
 }
 #[doc = "`reset()` method sets INT_CLR to value 0"]
 impl crate::Resettable for INT_CLR_SPEC {
diff --git a/esp32s3/src/timg0/int_ena.rs b/esp32s3/src/timg0/int_ena.rs
index 66259c0741..be2a8a2375 100644
--- a/esp32s3/src/timg0/int_ena.rs
+++ b/esp32s3/src/timg0/int_ena.rs
@@ -57,7 +57,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -65,19 +64,16 @@ impl W {
     }
     #[doc = "Bit 0 - The interrupt enable bit for the TIMG_T0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the TIMG_T1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the TIMG_WDT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 2)
     }
diff --git a/esp32s3/src/timg0/int_raw.rs b/esp32s3/src/timg0/int_raw.rs
index 683c104008..2b393eb10f 100644
--- a/esp32s3/src/timg0/int_raw.rs
+++ b/esp32s3/src/timg0/int_raw.rs
@@ -57,7 +57,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn t(&mut self, n: u8) -> T_W<INT_RAW_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
@@ -65,19 +64,16 @@ impl W {
     }
     #[doc = "Bit 0 - The raw interrupt status bit for the TIMG_T0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t0(&mut self) -> T_W<INT_RAW_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw interrupt status bit for the TIMG_T1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn t1(&mut self) -> T_W<INT_RAW_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw interrupt status bit for the TIMG_WDT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt(&mut self) -> WDT_W<INT_RAW_SPEC> {
         WDT_W::new(self, 2)
     }
diff --git a/esp32s3/src/timg0/ntimers_date.rs b/esp32s3/src/timg0/ntimers_date.rs
index e305804d75..58a9ebf0a2 100644
--- a/esp32s3/src/timg0/ntimers_date.rs
+++ b/esp32s3/src/timg0/ntimers_date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
-    #[must_use]
     pub fn ntimers_date(&mut self) -> NTIMERS_DATE_W<NTIMERS_DATE_SPEC> {
         NTIMERS_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/regclk.rs b/esp32s3/src/timg0/regclk.rs
index 772094502d..72097b20a4 100644
--- a/esp32s3/src/timg0/regclk.rs
+++ b/esp32s3/src/timg0/regclk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<REGCLK_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/timg0/rtccalicfg.rs b/esp32s3/src/timg0/rtccalicfg.rs
index 1e6331aac4..71db54275d 100644
--- a/esp32s3/src/timg0/rtccalicfg.rs
+++ b/esp32s3/src/timg0/rtccalicfg.rs
@@ -62,25 +62,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start_cycling(&mut self) -> RTC_CALI_START_CYCLING_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_CYCLING_W::new(self, 12)
     }
     #[doc = "Bits 13:14 - 0:rtc slow clock. 1:clk_80m. 2:xtal_32k."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_clk_sel(&mut self) -> RTC_CALI_CLK_SEL_W<RTCCALICFG_SPEC> {
         RTC_CALI_CLK_SEL_W::new(self, 13)
     }
     #[doc = "Bits 16:30 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_max(&mut self) -> RTC_CALI_MAX_W<RTCCALICFG_SPEC> {
         RTC_CALI_MAX_W::new(self, 16)
     }
     #[doc = "Bit 31 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_start(&mut self) -> RTC_CALI_START_W<RTCCALICFG_SPEC> {
         RTC_CALI_START_W::new(self, 31)
     }
diff --git a/esp32s3/src/timg0/rtccalicfg2.rs b/esp32s3/src/timg0/rtccalicfg2.rs
index 9bcb8e66e3..c8e2a89280 100644
--- a/esp32s3/src/timg0/rtccalicfg2.rs
+++ b/esp32s3/src/timg0/rtccalicfg2.rs
@@ -42,13 +42,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_timeout_rst_cnt(&mut self) -> RTC_CALI_TIMEOUT_RST_CNT_W<RTCCALICFG2_SPEC> {
         RTC_CALI_TIMEOUT_RST_CNT_W::new(self, 3)
     }
     #[doc = "Bits 7:31 - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."]
     #[inline(always)]
-    #[must_use]
     pub fn rtc_cali_timeout_thres(&mut self) -> RTC_CALI_TIMEOUT_THRES_W<RTCCALICFG2_SPEC> {
         RTC_CALI_TIMEOUT_THRES_W::new(self, 7)
     }
diff --git a/esp32s3/src/timg0/t/alarmhi.rs b/esp32s3/src/timg0/t/alarmhi.rs
index 70bb1f899d..15a64592c0 100644
--- a/esp32s3/src/timg0/t/alarmhi.rs
+++ b/esp32s3/src/timg0/t/alarmhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_hi(&mut self) -> ALARM_HI_W<ALARMHI_SPEC> {
         ALARM_HI_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/t/alarmlo.rs b/esp32s3/src/timg0/t/alarmlo.rs
index ecc2e8aae8..392a0eb764 100644
--- a/esp32s3/src/timg0/t/alarmlo.rs
+++ b/esp32s3/src/timg0/t/alarmlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_lo(&mut self) -> ALARM_LO_W<ALARMLO_SPEC> {
         ALARM_LO_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/t/config.rs b/esp32s3/src/timg0/t/config.rs
index 937d5ad4b6..606f13cb21 100644
--- a/esp32s3/src/timg0/t/config.rs
+++ b/esp32s3/src/timg0/t/config.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
-    #[must_use]
     pub fn use_xtal(&mut self) -> USE_XTAL_W<CONFIG_SPEC> {
         USE_XTAL_W::new(self, 9)
     }
     #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_en(&mut self) -> ALARM_EN_W<CONFIG_SPEC> {
         ALARM_EN_W::new(self, 10)
     }
     #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."]
     #[inline(always)]
-    #[must_use]
     pub fn divider(&mut self) -> DIVIDER_W<CONFIG_SPEC> {
         DIVIDER_W::new(self, 13)
     }
     #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn autoreload(&mut self) -> AUTORELOAD_W<CONFIG_SPEC> {
         AUTORELOAD_W::new(self, 29)
     }
     #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
     #[inline(always)]
-    #[must_use]
     pub fn increase(&mut self) -> INCREASE_W<CONFIG_SPEC> {
         INCREASE_W::new(self, 30)
     }
     #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CONFIG_SPEC> {
         EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/timg0/t/load.rs b/esp32s3/src/timg0/t/load.rs
index 69f5fbf50d..a1165066ec 100644
--- a/esp32s3/src/timg0/t/load.rs
+++ b/esp32s3/src/timg0/t/load.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<LOAD_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value to trigger a timer %s time-base counter reload."]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/t/loadhi.rs b/esp32s3/src/timg0/t/loadhi.rs
index 8b4311cb8d..1f0e9e8016 100644
--- a/esp32s3/src/timg0/t/loadhi.rs
+++ b/esp32s3/src/timg0/t/loadhi.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
-    #[must_use]
     pub fn load_hi(&mut self) -> LOAD_HI_W<LOADHI_SPEC> {
         LOAD_HI_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/t/loadlo.rs b/esp32s3/src/timg0/t/loadlo.rs
index 31e71a74dc..b2d9c23dc7 100644
--- a/esp32s3/src/timg0/t/loadlo.rs
+++ b/esp32s3/src/timg0/t/loadlo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
-    #[must_use]
     pub fn load_lo(&mut self) -> LOAD_LO_W<LOADLO_SPEC> {
         LOAD_LO_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/t/update.rs b/esp32s3/src/timg0/t/update.rs
index fd82a22f6c..285c7475f3 100644
--- a/esp32s3/src/timg0/t/update.rs
+++ b/esp32s3/src/timg0/t/update.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
-    #[must_use]
     pub fn update(&mut self) -> UPDATE_W<UPDATE_SPEC> {
         UPDATE_W::new(self, 31)
     }
diff --git a/esp32s3/src/timg0/wdtconfig0.rs b/esp32s3/src/timg0/wdtconfig0.rs
index e02b025d8b..da6509aaf0 100644
--- a/esp32s3/src/timg0/wdtconfig0.rs
+++ b/esp32s3/src/timg0/wdtconfig0.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 12 - Reserved"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_APPCPU_RESET_EN_W::new(self, 12)
     }
     #[doc = "Bit 13 - WDT reset CPU enable."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
         WDT_PROCPU_RESET_EN_W::new(self, 13)
     }
     #[doc = "Bit 14 - When set, Flash boot protection is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
         WDT_FLASHBOOT_MOD_EN_W::new(self, 14)
     }
     #[doc = "Bits 15:17 - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_SYS_RESET_LENGTH_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
         WDT_CPU_RESET_LENGTH_W::new(self, 18)
     }
     #[doc = "Bits 23:24 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
         WDT_STG3_W::new(self, 23)
     }
     #[doc = "Bits 25:26 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
         WDT_STG2_W::new(self, 25)
     }
     #[doc = "Bits 27:28 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
         WDT_STG1_W::new(self, 27)
     }
     #[doc = "Bits 29:30 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
         WDT_STG0_W::new(self, 29)
     }
     #[doc = "Bit 31 - When set, MWDT is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
         WDT_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/timg0/wdtconfig1.rs b/esp32s3/src/timg0/wdtconfig1.rs
index b9bf04381d..d88a70c2f1 100644
--- a/esp32s3/src/timg0/wdtconfig1.rs
+++ b/esp32s3/src/timg0/wdtconfig1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_clk_prescale(&mut self) -> WDT_CLK_PRESCALE_W<WDTCONFIG1_SPEC> {
         WDT_CLK_PRESCALE_W::new(self, 16)
     }
diff --git a/esp32s3/src/timg0/wdtconfig2.rs b/esp32s3/src/timg0/wdtconfig2.rs
index d7aedad9be..2eb13ae372 100644
--- a/esp32s3/src/timg0/wdtconfig2.rs
+++ b/esp32s3/src/timg0/wdtconfig2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG2_SPEC> {
         WDT_STG0_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/wdtconfig3.rs b/esp32s3/src/timg0/wdtconfig3.rs
index 3eb96b1e93..353e861c97 100644
--- a/esp32s3/src/timg0/wdtconfig3.rs
+++ b/esp32s3/src/timg0/wdtconfig3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG3_SPEC> {
         WDT_STG1_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/wdtconfig4.rs b/esp32s3/src/timg0/wdtconfig4.rs
index c522268b4c..adb732fce4 100644
--- a/esp32s3/src/timg0/wdtconfig4.rs
+++ b/esp32s3/src/timg0/wdtconfig4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG4_SPEC> {
         WDT_STG2_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/wdtconfig5.rs b/esp32s3/src/timg0/wdtconfig5.rs
index 61c6bfb1e1..a56ba8caeb 100644
--- a/esp32s3/src/timg0/wdtconfig5.rs
+++ b/esp32s3/src/timg0/wdtconfig5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG5_SPEC> {
         WDT_STG3_HOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/wdtfeed.rs b/esp32s3/src/timg0/wdtfeed.rs
index 5b3ae9b1dc..cd788cbe3e 100644
--- a/esp32s3/src/timg0/wdtfeed.rs
+++ b/esp32s3/src/timg0/wdtfeed.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - Write any value to feed the MWDT. (WO)"]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
         WDT_FEED_W::new(self, 0)
     }
diff --git a/esp32s3/src/timg0/wdtwprotect.rs b/esp32s3/src/timg0/wdtwprotect.rs
index f3d13ea457..db5716850f 100644
--- a/esp32s3/src/timg0/wdtwprotect.rs
+++ b/esp32s3/src/timg0/wdtwprotect.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
         WDT_WKEY_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/bus_timing_0.rs b/esp32s3/src/twai0/bus_timing_0.rs
index 3acc8fe70a..eaaf1004d0 100644
--- a/esp32s3/src/twai0/bus_timing_0.rs
+++ b/esp32s3/src/twai0/bus_timing_0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:13 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
-    #[must_use]
     pub fn baud_presc(&mut self) -> BAUD_PRESC_W<BUS_TIMING_0_SPEC> {
         BAUD_PRESC_W::new(self, 0)
     }
     #[doc = "Bits 14:15 - Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide."]
     #[inline(always)]
-    #[must_use]
     pub fn sync_jump_width(&mut self) -> SYNC_JUMP_WIDTH_W<BUS_TIMING_0_SPEC> {
         SYNC_JUMP_WIDTH_W::new(self, 14)
     }
diff --git a/esp32s3/src/twai0/bus_timing_1.rs b/esp32s3/src/twai0/bus_timing_1.rs
index edd5e6575c..387797e218 100644
--- a/esp32s3/src/twai0/bus_timing_1.rs
+++ b/esp32s3/src/twai0/bus_timing_1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg1(&mut self) -> TIME_SEG1_W<BUS_TIMING_1_SPEC> {
         TIME_SEG1_W::new(self, 0)
     }
     #[doc = "Bits 4:6 - The width of PBS2."]
     #[inline(always)]
-    #[must_use]
     pub fn time_seg2(&mut self) -> TIME_SEG2_W<BUS_TIMING_1_SPEC> {
         TIME_SEG2_W::new(self, 4)
     }
     #[doc = "Bit 7 - The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times"]
     #[inline(always)]
-    #[must_use]
     pub fn time_samp(&mut self) -> TIME_SAMP_W<BUS_TIMING_1_SPEC> {
         TIME_SAMP_W::new(self, 7)
     }
diff --git a/esp32s3/src/twai0/clock_divider.rs b/esp32s3/src/twai0/clock_divider.rs
index 604cc61578..7c8b88d257 100644
--- a/esp32s3/src/twai0/clock_divider.rs
+++ b/esp32s3/src/twai0/clock_divider.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
-    #[must_use]
     pub fn cd(&mut self) -> CD_W<CLOCK_DIVIDER_SPEC> {
         CD_W::new(self, 0)
     }
     #[doc = "Bit 8 - This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin"]
     #[inline(always)]
-    #[must_use]
     pub fn clock_off(&mut self) -> CLOCK_OFF_W<CLOCK_DIVIDER_SPEC> {
         CLOCK_OFF_W::new(self, 8)
     }
diff --git a/esp32s3/src/twai0/cmd.rs b/esp32s3/src/twai0/cmd.rs
index 9dec5c5851..7f85b98347 100644
--- a/esp32s3/src/twai0/cmd.rs
+++ b/esp32s3/src/twai0/cmd.rs
@@ -19,31 +19,26 @@ impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set the bit to 1 to allow the driving nodes start transmission."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_req(&mut self) -> TX_REQ_W<CMD_SPEC> {
         TX_REQ_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set the bit to 1 to cancel a pending transmission request."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_tx(&mut self) -> ABORT_TX_W<CMD_SPEC> {
         ABORT_TX_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set the bit to 1 to release the RX buffer."]
     #[inline(always)]
-    #[must_use]
     pub fn release_buf(&mut self) -> RELEASE_BUF_W<CMD_SPEC> {
         RELEASE_BUF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set the bit to 1 to clear the data overrun status bit."]
     #[inline(always)]
-    #[must_use]
     pub fn clr_overrun(&mut self) -> CLR_OVERRUN_W<CMD_SPEC> {
         CLR_OVERRUN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously."]
     #[inline(always)]
-    #[must_use]
     pub fn self_rx_req(&mut self) -> SELF_RX_REQ_W<CMD_SPEC> {
         SELF_RX_REQ_W::new(self, 4)
     }
diff --git a/esp32s3/src/twai0/data_0.rs b/esp32s3/src/twai0/data_0.rs
index 9da54a5102..0d31668320 100644
--- a/esp32s3/src/twai0/data_0.rs
+++ b/esp32s3/src/twai0/data_0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_0(&mut self) -> TX_BYTE_0_W<DATA_0_SPEC> {
         TX_BYTE_0_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_1.rs b/esp32s3/src/twai0/data_1.rs
index 4fca4af070..b45d9c5e99 100644
--- a/esp32s3/src/twai0/data_1.rs
+++ b/esp32s3/src/twai0/data_1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_1(&mut self) -> TX_BYTE_1_W<DATA_1_SPEC> {
         TX_BYTE_1_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_10.rs b/esp32s3/src/twai0/data_10.rs
index d3a1181d8d..756d4b4006 100644
--- a/esp32s3/src/twai0/data_10.rs
+++ b/esp32s3/src/twai0/data_10.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_10(&mut self) -> TX_BYTE_10_W<DATA_10_SPEC> {
         TX_BYTE_10_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_11.rs b/esp32s3/src/twai0/data_11.rs
index a07192b292..80e75ecb8f 100644
--- a/esp32s3/src/twai0/data_11.rs
+++ b/esp32s3/src/twai0/data_11.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_11(&mut self) -> TX_BYTE_11_W<DATA_11_SPEC> {
         TX_BYTE_11_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_12.rs b/esp32s3/src/twai0/data_12.rs
index c6b1c97f51..20646c57b9 100644
--- a/esp32s3/src/twai0/data_12.rs
+++ b/esp32s3/src/twai0/data_12.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_12(&mut self) -> TX_BYTE_12_W<DATA_12_SPEC> {
         TX_BYTE_12_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_2.rs b/esp32s3/src/twai0/data_2.rs
index 3179326e84..0c7db88aa8 100644
--- a/esp32s3/src/twai0/data_2.rs
+++ b/esp32s3/src/twai0/data_2.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_2(&mut self) -> TX_BYTE_2_W<DATA_2_SPEC> {
         TX_BYTE_2_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_3.rs b/esp32s3/src/twai0/data_3.rs
index b639a7b9bf..e7df26464e 100644
--- a/esp32s3/src/twai0/data_3.rs
+++ b/esp32s3/src/twai0/data_3.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_3(&mut self) -> TX_BYTE_3_W<DATA_3_SPEC> {
         TX_BYTE_3_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_4.rs b/esp32s3/src/twai0/data_4.rs
index 4f473f3008..90ff6b33db 100644
--- a/esp32s3/src/twai0/data_4.rs
+++ b/esp32s3/src/twai0/data_4.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_4(&mut self) -> TX_BYTE_4_W<DATA_4_SPEC> {
         TX_BYTE_4_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_5.rs b/esp32s3/src/twai0/data_5.rs
index c622efb8c4..7f9f1e5590 100644
--- a/esp32s3/src/twai0/data_5.rs
+++ b/esp32s3/src/twai0/data_5.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_5(&mut self) -> TX_BYTE_5_W<DATA_5_SPEC> {
         TX_BYTE_5_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_6.rs b/esp32s3/src/twai0/data_6.rs
index 994c3b5883..73a15eebef 100644
--- a/esp32s3/src/twai0/data_6.rs
+++ b/esp32s3/src/twai0/data_6.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_6(&mut self) -> TX_BYTE_6_W<DATA_6_SPEC> {
         TX_BYTE_6_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_7.rs b/esp32s3/src/twai0/data_7.rs
index 28c5d98ef9..c637a8aa7b 100644
--- a/esp32s3/src/twai0/data_7.rs
+++ b/esp32s3/src/twai0/data_7.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_7(&mut self) -> TX_BYTE_7_W<DATA_7_SPEC> {
         TX_BYTE_7_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_8.rs b/esp32s3/src/twai0/data_8.rs
index 45046802aa..3d1d76d086 100644
--- a/esp32s3/src/twai0/data_8.rs
+++ b/esp32s3/src/twai0/data_8.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_8(&mut self) -> TX_BYTE_8_W<DATA_8_SPEC> {
         TX_BYTE_8_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/data_9.rs b/esp32s3/src/twai0/data_9.rs
index 09d489b574..7a9e68c967 100644
--- a/esp32s3/src/twai0/data_9.rs
+++ b/esp32s3/src/twai0/data_9.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_byte_9(&mut self) -> TX_BYTE_9_W<DATA_9_SPEC> {
         TX_BYTE_9_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/err_warning_limit.rs b/esp32s3/src/twai0/err_warning_limit.rs
index 4a0c61301c..df1aa0b277 100644
--- a/esp32s3/src/twai0/err_warning_limit.rs
+++ b/esp32s3/src/twai0/err_warning_limit.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warning_limit(&mut self) -> ERR_WARNING_LIMIT_W<ERR_WARNING_LIMIT_SPEC> {
         ERR_WARNING_LIMIT_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/int_ena.rs b/esp32s3/src/twai0/int_ena.rs
index 3b6932558a..d3977eaa4a 100644
--- a/esp32s3/src/twai0/int_ena.rs
+++ b/esp32s3/src/twai0/int_ena.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_int_ena(&mut self) -> RX_INT_ENA_W<INT_ENA_SPEC> {
         RX_INT_ENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to 1 to enable transmit interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_int_ena(&mut self) -> TX_INT_ENA_W<INT_ENA_SPEC> {
         TX_INT_ENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable error warning interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_warn_int_ena(&mut self) -> ERR_WARN_INT_ENA_W<INT_ENA_SPEC> {
         ERR_WARN_INT_ENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable data overrun interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn overrun_int_ena(&mut self) -> OVERRUN_INT_ENA_W<INT_ENA_SPEC> {
         OVERRUN_INT_ENA_W::new(self, 3)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable error passive interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INT_ENA_SPEC> {
         ERR_PASSIVE_INT_ENA_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to 1 to enable arbitration lost interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn arb_lost_int_ena(&mut self) -> ARB_LOST_INT_ENA_W<INT_ENA_SPEC> {
         ARB_LOST_INT_ENA_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to 1 to enable error interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INT_ENA_SPEC> {
         BUS_ERR_INT_ENA_W::new(self, 7)
     }
diff --git a/esp32s3/src/twai0/mode.rs b/esp32s3/src/twai0/mode.rs
index ddce5ed67c..deebf1574c 100644
--- a/esp32s3/src/twai0/mode.rs
+++ b/esp32s3/src/twai0/mode.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
-    #[must_use]
     pub fn reset_mode(&mut self) -> RESET_MODE_W<MODE_SPEC> {
         RESET_MODE_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter."]
     #[inline(always)]
-    #[must_use]
     pub fn listen_only_mode(&mut self) -> LISTEN_ONLY_MODE_W<MODE_SPEC> {
         LISTEN_ONLY_MODE_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command."]
     #[inline(always)]
-    #[must_use]
     pub fn self_test_mode(&mut self) -> SELF_TEST_MODE_W<MODE_SPEC> {
         SELF_TEST_MODE_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_filter_mode(&mut self) -> RX_FILTER_MODE_W<MODE_SPEC> {
         RX_FILTER_MODE_W::new(self, 3)
     }
diff --git a/esp32s3/src/twai0/rx_err_cnt.rs b/esp32s3/src/twai0/rx_err_cnt.rs
index 0e7eedf680..b421e30b14 100644
--- a/esp32s3/src/twai0/rx_err_cnt.rs
+++ b/esp32s3/src/twai0/rx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_err_cnt(&mut self) -> RX_ERR_CNT_W<RX_ERR_CNT_SPEC> {
         RX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32s3/src/twai0/tx_err_cnt.rs b/esp32s3/src/twai0/tx_err_cnt.rs
index 64ad2e844e..59fbc2d773 100644
--- a/esp32s3/src/twai0/tx_err_cnt.rs
+++ b/esp32s3/src/twai0/tx_err_cnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_err_cnt(&mut self) -> TX_ERR_CNT_W<TX_ERR_CNT_SPEC> {
         TX_ERR_CNT_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/at_cmd_char.rs b/esp32s3/src/uart0/at_cmd_char.rs
index 63f615f0bb..0cf119bced 100644
--- a/esp32s3/src/uart0/at_cmd_char.rs
+++ b/esp32s3/src/uart0/at_cmd_char.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W<AT_CMD_CHAR_SPEC> {
         AT_CMD_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to configure the num of continuous at_cmd chars received by receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn char_num(&mut self) -> CHAR_NUM_W<AT_CMD_CHAR_SPEC> {
         CHAR_NUM_W::new(self, 8)
     }
diff --git a/esp32s3/src/uart0/at_cmd_gaptout.rs b/esp32s3/src/uart0/at_cmd_gaptout.rs
index aeb0fab8c1..db829b172f 100644
--- a/esp32s3/src/uart0/at_cmd_gaptout.rs
+++ b/esp32s3/src/uart0/at_cmd_gaptout.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W<AT_CMD_GAPTOUT_SPEC> {
         RX_GAP_TOUT_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/at_cmd_postcnt.rs b/esp32s3/src/uart0/at_cmd_postcnt.rs
index a7bf7d2792..1ca8f0cec9 100644
--- a/esp32s3/src/uart0/at_cmd_postcnt.rs
+++ b/esp32s3/src/uart0/at_cmd_postcnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
-    #[must_use]
     pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W<AT_CMD_POSTCNT_SPEC> {
         POST_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/at_cmd_precnt.rs b/esp32s3/src/uart0/at_cmd_precnt.rs
index c49f64f592..762bf3e056 100644
--- a/esp32s3/src/uart0/at_cmd_precnt.rs
+++ b/esp32s3/src/uart0/at_cmd_precnt.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W<AT_CMD_PRECNT_SPEC> {
         PRE_IDLE_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/clk_conf.rs b/esp32s3/src/uart0/clk_conf.rs
index 1debfdc150..26cf2e7774 100644
--- a/esp32s3/src/uart0/clk_conf.rs
+++ b/esp32s3/src/uart0/clk_conf.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<CLK_CONF_SPEC> {
         SCLK_DIV_B_W::new(self, 0)
     }
     #[doc = "Bits 6:11 - The numerator of the frequency divider factor."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<CLK_CONF_SPEC> {
         SCLK_DIV_A_W::new(self, 6)
     }
     #[doc = "Bits 12:19 - The integral part of the frequency divider factor."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<CLK_CONF_SPEC> {
         SCLK_DIV_NUM_W::new(self, 12)
     }
     #[doc = "Bits 20:21 - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_sel(&mut self) -> SCLK_SEL_W<CLK_CONF_SPEC> {
         SCLK_SEL_W::new(self, 20)
     }
     #[doc = "Bit 22 - Set this bit to enable UART Tx/Rx clock."]
     #[inline(always)]
-    #[must_use]
     pub fn sclk_en(&mut self) -> SCLK_EN_W<CLK_CONF_SPEC> {
         SCLK_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_core(&mut self) -> RST_CORE_W<CLK_CONF_SPEC> {
         RST_CORE_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W<CLK_CONF_SPEC> {
         TX_SCLK_EN_W::new(self, 24)
     }
     #[doc = "Bit 25 - Set this bit to enable UART Rx clock."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W<CLK_CONF_SPEC> {
         RX_SCLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - Write 1 then write 0 to this bit, reset UART Tx."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W<CLK_CONF_SPEC> {
         TX_RST_CORE_W::new(self, 26)
     }
     #[doc = "Bit 27 - Write 1 then write 0 to this bit, reset UART Rx."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W<CLK_CONF_SPEC> {
         RX_RST_CORE_W::new(self, 27)
     }
diff --git a/esp32s3/src/uart0/clkdiv.rs b/esp32s3/src/uart0/clkdiv.rs
index f5fb653112..4706e2101c 100644
--- a/esp32s3/src/uart0/clkdiv.rs
+++ b/esp32s3/src/uart0/clkdiv.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SPEC> {
         CLKDIV_W::new(self, 0)
     }
     #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
     #[inline(always)]
-    #[must_use]
     pub fn frag(&mut self) -> FRAG_W<CLKDIV_SPEC> {
         FRAG_W::new(self, 20)
     }
diff --git a/esp32s3/src/uart0/conf0.rs b/esp32s3/src/uart0/conf0.rs
index c32c153634..7b36703aba 100644
--- a/esp32s3/src/uart0/conf0.rs
+++ b/esp32s3/src/uart0/conf0.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
-    #[must_use]
     pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
         PARITY_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable uart parity check."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
         PARITY_EN_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - This register is used to set the length of data."]
     #[inline(always)]
-    #[must_use]
     pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
         BIT_NUM_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
     #[inline(always)]
-    #[must_use]
     pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
         STOP_BIT_NUM_W::new(self, 4)
     }
     #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
         SW_RTS_W::new(self, 6)
     }
     #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF0_SPEC> {
         SW_DTR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
         TXD_BRK_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to enable IrDA loopback mode."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
         IRDA_DPLX_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the start enable bit for IrDA transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
         IRDA_TX_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
         IRDA_WCTL_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to invert the level of IrDA transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
         IRDA_TX_INV_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to invert the level of IrDA receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
         IRDA_RX_INV_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
     #[inline(always)]
-    #[must_use]
     pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
         LOOPBACK_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to enable flow control function for transmitter."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
         TX_FLOW_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to enable IrDA protocol."]
     #[inline(always)]
-    #[must_use]
     pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
         IRDA_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to reset the uart receive-FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
         RXFIFO_RST_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to reset the uart transmit-FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
         TXFIFO_RST_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
         RXD_INV_W::new(self, 19)
     }
     #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_inv(&mut self) -> CTS_INV_W<CONF0_SPEC> {
         CTS_INV_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF0_SPEC> {
         DSR_INV_W::new(self, 21)
     }
     #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
     #[inline(always)]
-    #[must_use]
     pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
         TXD_INV_W::new(self, 22)
     }
     #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rts_inv(&mut self) -> RTS_INV_W<CONF0_SPEC> {
         RTS_INV_W::new(self, 23)
     }
     #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF0_SPEC> {
         DTR_INV_W::new(self, 24)
     }
     #[doc = "Bit 25 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 25)
     }
     #[doc = "Bit 26 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
     #[inline(always)]
-    #[must_use]
     pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
         ERR_WR_MASK_W::new(self, 26)
     }
     #[doc = "Bit 27 - This is the enable bit for detecting baudrate."]
     #[inline(always)]
-    #[must_use]
     pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W<CONF0_SPEC> {
         AUTOBAUD_EN_W::new(self, 27)
     }
     #[doc = "Bit 28 - UART memory clock gate enable signal."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SPEC> {
         MEM_CLK_EN_W::new(self, 28)
     }
diff --git a/esp32s3/src/uart0/conf1.rs b/esp32s3/src/uart0/conf1.rs
index f7d472376b..b473ec00ad 100644
--- a/esp32s3/src/uart0/conf1.rs
+++ b/esp32s3/src/uart0/conf1.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<CONF1_SPEC> {
         RXFIFO_FULL_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<CONF1_SPEC> {
         TXFIFO_EMPTY_THRHD_W::new(self, 10)
     }
     #[doc = "Bit 20 - Disable UART Rx data overflow detect."]
     #[inline(always)]
-    #[must_use]
     pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W<CONF1_SPEC> {
         DIS_RX_DAT_OVF_W::new(self, 20)
     }
     #[doc = "Bit 21 - Set this bit to stop accumulating idle_cnt when hardware flow control works."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W<CONF1_SPEC> {
         RX_TOUT_FLOW_DIS_W::new(self, 21)
     }
     #[doc = "Bit 22 - This is the flow enable bit for UART receiver."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<CONF1_SPEC> {
         RX_FLOW_EN_W::new(self, 22)
     }
     #[doc = "Bit 23 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<CONF1_SPEC> {
         RX_TOUT_EN_W::new(self, 23)
     }
diff --git a/esp32s3/src/uart0/date.rs b/esp32s3/src/uart0/date.rs
index d89b3d5652..d17dca78f3 100644
--- a/esp32s3/src/uart0/date.rs
+++ b/esp32s3/src/uart0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/fifo.rs b/esp32s3/src/uart0/fifo.rs
index bbd207ed48..044c77bb18 100644
--- a/esp32s3/src/uart0/fifo.rs
+++ b/esp32s3/src/uart0/fifo.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_rd_byte(&mut self) -> RXFIFO_RD_BYTE_W<FIFO_SPEC> {
         RXFIFO_RD_BYTE_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/flow_conf.rs b/esp32s3/src/uart0/flow_conf.rs
index ec52fe16d3..0e7f83e9dc 100644
--- a/esp32s3/src/uart0/flow_conf.rs
+++ b/esp32s3/src/uart0/flow_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W<FLOW_CONF_SPEC> {
         SW_FLOW_CON_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to remove flow control char from the received data."]
     #[inline(always)]
-    #[must_use]
     pub fn xonoff_del(&mut self) -> XONOFF_DEL_W<FLOW_CONF_SPEC> {
         XONOFF_DEL_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable the transmitter to go on sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xon(&mut self) -> FORCE_XON_W<FLOW_CONF_SPEC> {
         FORCE_XON_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to stop the transmitter from sending data."]
     #[inline(always)]
-    #[must_use]
     pub fn force_xoff(&mut self) -> FORCE_XOFF_W<FLOW_CONF_SPEC> {
         FORCE_XOFF_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to send Xon char. It is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xon(&mut self) -> SEND_XON_W<FLOW_CONF_SPEC> {
         SEND_XON_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to send Xoff char. It is cleared by hardware automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn send_xoff(&mut self) -> SEND_XOFF_W<FLOW_CONF_SPEC> {
         SEND_XOFF_W::new(self, 5)
     }
diff --git a/esp32s3/src/uart0/id.rs b/esp32s3/src/uart0/id.rs
index 2e3ddb5969..8466c988d9 100644
--- a/esp32s3/src/uart0/id.rs
+++ b/esp32s3/src/uart0/id.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
     #[inline(always)]
-    #[must_use]
     pub fn id(&mut self) -> ID_W<ID_SPEC> {
         ID_W::new(self, 0)
     }
     #[doc = "Bit 30 - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers."]
     #[inline(always)]
-    #[must_use]
     pub fn high_speed(&mut self) -> HIGH_SPEED_W<ID_SPEC> {
         HIGH_SPEED_W::new(self, 30)
     }
     #[doc = "Bit 31 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
-    #[must_use]
     pub fn reg_update(&mut self) -> REG_UPDATE_W<ID_SPEC> {
         REG_UPDATE_W::new(self, 31)
     }
diff --git a/esp32s3/src/uart0/idle_conf.rs b/esp32s3/src/uart0/idle_conf.rs
index c3bcd173ed..3e67f9b8b2 100644
--- a/esp32s3/src/uart0/idle_conf.rs
+++ b/esp32s3/src/uart0/idle_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W<IDLE_CONF_SPEC> {
         RX_IDLE_THRHD_W::new(self, 0)
     }
     #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W<IDLE_CONF_SPEC> {
         TX_IDLE_NUM_W::new(self, 10)
     }
diff --git a/esp32s3/src/uart0/int_clr.rs b/esp32s3/src/uart0/int_clr.rs
index 83be88b461..40688a1933 100644
--- a/esp32s3/src/uart0/int_clr.rs
+++ b/esp32s3/src/uart0/int_clr.rs
@@ -49,121 +49,101 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the sw_xoff_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set this bit to clear the rs485_clash_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set this bit to clear the uart_wakeup_int_raw interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup(&mut self) -> WAKEUP_W<INT_CLR_SPEC> {
         WAKEUP_W::new(self, 19)
     }
diff --git a/esp32s3/src/uart0/int_ena.rs b/esp32s3/src/uart0/int_ena.rs
index dc9361e638..14f56e1ffd 100644
--- a/esp32s3/src/uart0/int_ena.rs
+++ b/esp32s3/src/uart0/int_ena.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_ENA_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_ENA_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_ENA_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_ENA_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_ENA_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_ENA_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_ENA_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_ENA_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_ENA_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_ENA_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_ENA_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_ENA_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_ENA_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_ENA_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
     #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup(&mut self) -> WAKEUP_W<INT_ENA_SPEC> {
         WAKEUP_W::new(self, 19)
     }
diff --git a/esp32s3/src/uart0/int_raw.rs b/esp32s3/src/uart0/int_raw.rs
index b38649fad2..38182da48b 100644
--- a/esp32s3/src/uart0/int_raw.rs
+++ b/esp32s3/src/uart0/int_raw.rs
@@ -214,121 +214,101 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_RAW_SPEC> {
         RXFIFO_FULL_W::new(self, 0)
     }
     #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_RAW_SPEC> {
         TXFIFO_EMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."]
     #[inline(always)]
-    #[must_use]
     pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_RAW_SPEC> {
         PARITY_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."]
     #[inline(always)]
-    #[must_use]
     pub fn frm_err(&mut self) -> FRM_ERR_W<INT_RAW_SPEC> {
         FRM_ERR_W::new(self, 3)
     }
     #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_RAW_SPEC> {
         RXFIFO_OVF_W::new(self, 4)
     }
     #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."]
     #[inline(always)]
-    #[must_use]
     pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_RAW_SPEC> {
         DSR_CHG_W::new(self, 5)
     }
     #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."]
     #[inline(always)]
-    #[must_use]
     pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_RAW_SPEC> {
         CTS_CHG_W::new(self, 6)
     }
     #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."]
     #[inline(always)]
-    #[must_use]
     pub fn brk_det(&mut self) -> BRK_DET_W<INT_RAW_SPEC> {
         BRK_DET_W::new(self, 7)
     }
     #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_RAW_SPEC> {
         RXFIFO_TOUT_W::new(self, 8)
     }
     #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xon(&mut self) -> SW_XON_W<INT_RAW_SPEC> {
         SW_XON_W::new(self, 9)
     }
     #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_RAW_SPEC> {
         SW_XOFF_W::new(self, 10)
     }
     #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_RAW_SPEC> {
         GLITCH_DET_W::new(self, 11)
     }
     #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_RAW_SPEC> {
         TX_BRK_DONE_W::new(self, 12)
     }
     #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_RAW_SPEC> {
         TX_BRK_IDLE_DONE_W::new(self, 13)
     }
     #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_done(&mut self) -> TX_DONE_W<INT_RAW_SPEC> {
         TX_DONE_W::new(self, 14)
     }
     #[doc = "Bit 15 - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_RAW_SPEC> {
         RS485_PARITY_ERR_W::new(self, 15)
     }
     #[doc = "Bit 16 - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_RAW_SPEC> {
         RS485_FRM_ERR_W::new(self, 16)
     }
     #[doc = "Bit 17 - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_RAW_SPEC> {
         RS485_CLASH_W::new(self, 17)
     }
     #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."]
     #[inline(always)]
-    #[must_use]
     pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_RAW_SPEC> {
         AT_CMD_CHAR_DET_W::new(self, 18)
     }
     #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."]
     #[inline(always)]
-    #[must_use]
     pub fn wakeup(&mut self) -> WAKEUP_W<INT_RAW_SPEC> {
         WAKEUP_W::new(self, 19)
     }
diff --git a/esp32s3/src/uart0/mem_conf.rs b/esp32s3/src/uart0/mem_conf.rs
index e2d967e4e9..c98ebba866 100644
--- a/esp32s3/src/uart0/mem_conf.rs
+++ b/esp32s3/src/uart0/mem_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_size(&mut self) -> RX_SIZE_W<MEM_CONF_SPEC> {
         RX_SIZE_W::new(self, 1)
     }
     #[doc = "Bits 4:6 - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_size(&mut self) -> TX_SIZE_W<MEM_CONF_SPEC> {
         TX_SIZE_W::new(self, 4)
     }
     #[doc = "Bits 7:16 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W<MEM_CONF_SPEC> {
         RX_FLOW_THRHD_W::new(self, 7)
     }
     #[doc = "Bits 17:26 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W<MEM_CONF_SPEC> {
         RX_TOUT_THRHD_W::new(self, 17)
     }
     #[doc = "Bit 27 - Set this bit to force power down UART memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<MEM_CONF_SPEC> {
         MEM_FORCE_PD_W::new(self, 27)
     }
     #[doc = "Bit 28 - Set this bit to force power up UART memory."]
     #[inline(always)]
-    #[must_use]
     pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<MEM_CONF_SPEC> {
         MEM_FORCE_PU_W::new(self, 28)
     }
diff --git a/esp32s3/src/uart0/rs485_conf.rs b/esp32s3/src/uart0/rs485_conf.rs
index 5ee32256ba..4e52a1709a 100644
--- a/esp32s3/src/uart0/rs485_conf.rs
+++ b/esp32s3/src/uart0/rs485_conf.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_en(&mut self) -> RS485_EN_W<RS485_CONF_SPEC> {
         RS485_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl0_en(&mut self) -> DL0_EN_W<RS485_CONF_SPEC> {
         DL0_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
-    #[must_use]
     pub fn dl1_en(&mut self) -> DL1_EN_W<RS485_CONF_SPEC> {
         DL1_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485tx_rx_en(&mut self) -> RS485TX_RX_EN_W<RS485_CONF_SPEC> {
         RS485TX_RX_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485rxby_tx_en(&mut self) -> RS485RXBY_TX_EN_W<RS485_CONF_SPEC> {
         RS485RXBY_TX_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - This register is used to delay the receiver's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_rx_dly_num(&mut self) -> RS485_RX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_RX_DLY_NUM_W::new(self, 5)
     }
     #[doc = "Bits 6:9 - This register is used to delay the transmitter's internal data signal."]
     #[inline(always)]
-    #[must_use]
     pub fn rs485_tx_dly_num(&mut self) -> RS485_TX_DLY_NUM_W<RS485_CONF_SPEC> {
         RS485_TX_DLY_NUM_W::new(self, 6)
     }
diff --git a/esp32s3/src/uart0/rx_filt.rs b/esp32s3/src/uart0/rx_filt.rs
index bbffbeca7c..dd54720849 100644
--- a/esp32s3/src/uart0/rx_filt.rs
+++ b/esp32s3/src/uart0/rx_filt.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value, the pulse is ignored."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_filt(&mut self) -> GLITCH_FILT_W<RX_FILT_SPEC> {
         GLITCH_FILT_W::new(self, 0)
     }
     #[doc = "Bit 8 - Set this bit to enable Rx signal filter."]
     #[inline(always)]
-    #[must_use]
     pub fn glitch_filt_en(&mut self) -> GLITCH_FILT_EN_W<RX_FILT_SPEC> {
         GLITCH_FILT_EN_W::new(self, 8)
     }
diff --git a/esp32s3/src/uart0/sleep_conf.rs b/esp32s3/src/uart0/sleep_conf.rs
index 768d10da66..eda255981a 100644
--- a/esp32s3/src/uart0/sleep_conf.rs
+++ b/esp32s3/src/uart0/sleep_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
-    #[must_use]
     pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W<SLEEP_CONF_SPEC> {
         ACTIVE_THRESHOLD_W::new(self, 0)
     }
diff --git a/esp32s3/src/uart0/swfc_conf0.rs b/esp32s3/src/uart0/swfc_conf0.rs
index fea87507ce..400a51386d 100644
--- a/esp32s3/src/uart0/swfc_conf0.rs
+++ b/esp32s3/src/uart0/swfc_conf0.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W<SWFC_CONF0_SPEC> {
         XOFF_THRESHOLD_W::new(self, 0)
     }
     #[doc = "Bits 10:17 - This register stores the Xoff flow control char."]
     #[inline(always)]
-    #[must_use]
     pub fn xoff_char(&mut self) -> XOFF_CHAR_W<SWFC_CONF0_SPEC> {
         XOFF_CHAR_W::new(self, 10)
     }
diff --git a/esp32s3/src/uart0/swfc_conf1.rs b/esp32s3/src/uart0/swfc_conf1.rs
index 0532d4d745..108427adbc 100644
--- a/esp32s3/src/uart0/swfc_conf1.rs
+++ b/esp32s3/src/uart0/swfc_conf1.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:9 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W<SWFC_CONF1_SPEC> {
         XON_THRESHOLD_W::new(self, 0)
     }
     #[doc = "Bits 10:17 - This register stores the Xon flow control char."]
     #[inline(always)]
-    #[must_use]
     pub fn xon_char(&mut self) -> XON_CHAR_W<SWFC_CONF1_SPEC> {
         XON_CHAR_W::new(self, 10)
     }
diff --git a/esp32s3/src/uart0/txbrk_conf.rs b/esp32s3/src/uart0/txbrk_conf.rs
index 3fd0ce2689..7772196638 100644
--- a/esp32s3/src/uart0/txbrk_conf.rs
+++ b/esp32s3/src/uart0/txbrk_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W<TXBRK_CONF_SPEC> {
         TX_BRK_NUM_W::new(self, 0)
     }
diff --git a/esp32s3/src/uhci0/ack_num.rs b/esp32s3/src/uhci0/ack_num.rs
index d6948d17bd..38bea880d6 100644
--- a/esp32s3/src/uhci0/ack_num.rs
+++ b/esp32s3/src/uhci0/ack_num.rs
@@ -26,13 +26,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - This ACK number used in software flow control."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_num(&mut self) -> ACK_NUM_W<ACK_NUM_SPEC> {
         ACK_NUM_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded."]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<ACK_NUM_SPEC> {
         LOAD_W::new(self, 3)
     }
diff --git a/esp32s3/src/uhci0/app_int_set.rs b/esp32s3/src/uhci0/app_int_set.rs
index 2e3a1fdc13..4824491352 100644
--- a/esp32s3/src/uhci0/app_int_set.rs
+++ b/esp32s3/src/uhci0/app_int_set.rs
@@ -13,13 +13,11 @@ impl core::fmt::Debug for crate::generic::Reg<APP_INT_SET_SPEC> {
 impl W {
     #[doc = "Bit 0 - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl0_int_set(&mut self) -> APP_CTRL0_INT_SET_W<APP_INT_SET_SPEC> {
         APP_CTRL0_INT_SET_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl1_int_set(&mut self) -> APP_CTRL1_INT_SET_W<APP_INT_SET_SPEC> {
         APP_CTRL1_INT_SET_W::new(self, 1)
     }
diff --git a/esp32s3/src/uhci0/conf0.rs b/esp32s3/src/uhci0/conf0.rs
index fd23d04359..cf0bf692b3 100644
--- a/esp32s3/src/uhci0/conf0.rs
+++ b/esp32s3/src/uhci0/conf0.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_rst(&mut self) -> TX_RST_W<CONF0_SPEC> {
         TX_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Write 1, then write 0 to this bit to reset encode state machine."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_rst(&mut self) -> RX_RST_W<CONF0_SPEC> {
         RX_RST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to link up HCI and UART0."]
     #[inline(always)]
-    #[must_use]
     pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
         UART0_CE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to link up HCI and UART1."]
     #[inline(always)]
-    #[must_use]
     pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
         UART1_CE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to link up HCI and UART2."]
     #[inline(always)]
-    #[must_use]
     pub fn uart2_ce(&mut self) -> UART2_CE_W<CONF0_SPEC> {
         UART2_CE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
         SEPER_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."]
     #[inline(always)]
-    #[must_use]
     pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
         HEAD_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
         CRC_REC_EN_W::new(self, 7)
     }
     #[doc = "Bit 8 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
         UART_IDLE_EOF_EN_W::new(self, 8)
     }
     #[doc = "Bit 9 - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
     #[inline(always)]
-    #[must_use]
     pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
         LEN_EOF_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
     #[inline(always)]
-    #[must_use]
     pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
         ENCODE_CRC_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
         CLK_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
     #[inline(always)]
-    #[must_use]
     pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
         UART_RX_BRK_EOF_EN_W::new(self, 12)
     }
diff --git a/esp32s3/src/uhci0/conf1.rs b/esp32s3/src/uhci0/conf1.rs
index f6c859ee38..c234adde8d 100644
--- a/esp32s3/src/uhci0/conf1.rs
+++ b/esp32s3/src/uhci0/conf1.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
         CHECK_SUM_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
         CHECK_SEQ_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
         CRC_DISABLE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to save the packet header when HCI receives a data packet."]
     #[inline(always)]
-    #[must_use]
     pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
         SAVE_HEAD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
         TX_CHECK_SUM_RE_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
         TX_ACK_NUM_RE_W::new(self, 5)
     }
     #[doc = "Bit 7 - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
         WAIT_SW_START_W::new(self, 7)
     }
     #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
     #[inline(always)]
-    #[must_use]
     pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
         SW_START_W::new(self, 8)
     }
diff --git a/esp32s3/src/uhci0/date.rs b/esp32s3/src/uhci0/date.rs
index ac8a48c0f1..db98f36b5b 100644
--- a/esp32s3/src/uhci0/date.rs
+++ b/esp32s3/src/uhci0/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/uhci0/esc_conf.rs b/esp32s3/src/uhci0/esc_conf.rs
index 4bf1ae0dd5..46dd1e8ae8 100644
--- a/esp32s3/src/uhci0/esc_conf.rs
+++ b/esp32s3/src/uhci0/esc_conf.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register is used to define the separate char that need to be encoded, default is 0xc0."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_char(&mut self) -> SEPER_CHAR_W<ESC_CONF_SPEC> {
         SEPER_CHAR_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR0_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc."]
     #[inline(always)]
-    #[must_use]
     pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W<ESC_CONF_SPEC> {
         SEPER_ESC_CHAR1_W::new(self, 16)
     }
diff --git a/esp32s3/src/uhci0/escape_conf.rs b/esp32s3/src/uhci0/escape_conf.rs
index a97dacc651..ebb97f62c1 100644
--- a/esp32s3/src/uhci0/escape_conf.rs
+++ b/esp32s3/src/uhci0/escape_conf.rs
@@ -94,49 +94,41 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to enable decoding char 0xc0 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_C0_ESC_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to enable decoding char 0xdb when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_DB_ESC_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to enable decoding flow control char 0x11 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_11_ESC_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to enable decoding flow control char 0x13 when DMA receives data."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         TX_13_ESC_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to enable replacing 0xc0 by special char when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_C0_ESC_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to enable replacing 0xdb by special char when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_DB_ESC_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_11_ESC_EN_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
         RX_13_ESC_EN_W::new(self, 7)
     }
diff --git a/esp32s3/src/uhci0/hung_conf.rs b/esp32s3/src/uhci0/hung_conf.rs
index d10eb06d17..fc2c11153b 100644
--- a/esp32s3/src/uhci0/hung_conf.rs
+++ b/esp32s3/src/uhci0/hung_conf.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - This register is used to configure the tick count maximum value."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_SHIFT_W::new(self, 8)
     }
     #[doc = "Bit 11 - This is the enable bit for Tx-FIFO receive-data timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         TXFIFO_TIMEOUT_ENA_W::new(self, 11)
     }
     #[doc = "Bits 12:19 - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_W::new(self, 12)
     }
     #[doc = "Bits 20:22 - This register is used to configure the tick count maximum value."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_SHIFT_W::new(self, 20)
     }
     #[doc = "Bit 23 - This is the enable bit for DMA send-data timeout."]
     #[inline(always)]
-    #[must_use]
     pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
         RXFIFO_TIMEOUT_ENA_W::new(self, 23)
     }
diff --git a/esp32s3/src/uhci0/int_clr.rs b/esp32s3/src/uhci0/int_clr.rs
index 20d4a23918..9ca3f42eb2 100644
--- a/esp32s3/src/uhci0/int_clr.rs
+++ b/esp32s3/src/uhci0/int_clr.rs
@@ -27,55 +27,46 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear UHCI_RX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear UHCI_TX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_CLR_SPEC> {
         SEND_S_REG_Q_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_CLR_SPEC> {
         SEND_A_REG_Q_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear UHCI_APP_CTRL0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_CLR_SPEC> {
         APP_CTRL0_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear UHCI_APP_CTRL1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_CLR_SPEC> {
         APP_CTRL1_W::new(self, 8)
     }
diff --git a/esp32s3/src/uhci0/int_ena.rs b/esp32s3/src/uhci0/int_ena.rs
index af804c69f6..e7b2a23457 100644
--- a/esp32s3/src/uhci0/int_ena.rs
+++ b/esp32s3/src/uhci0/int_ena.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_ENA_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_ENA_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_ENA_SPEC> {
         SEND_S_REG_Q_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_ENA_SPEC> {
         SEND_A_REG_Q_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_ENA_SPEC> {
         OUTLINK_EOF_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_ENA_SPEC> {
         APP_CTRL0_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_ENA_SPEC> {
         APP_CTRL1_W::new(self, 8)
     }
diff --git a/esp32s3/src/uhci0/int_raw.rs b/esp32s3/src/uhci0/int_raw.rs
index 98a2366abb..2d2cf2473c 100644
--- a/esp32s3/src/uhci0/int_raw.rs
+++ b/esp32s3/src/uhci0/int_raw.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This is the interrupt raw bit. Triggered when a separator char has been sent."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_start(&mut self) -> RX_START_W<INT_RAW_SPEC> {
         RX_START_W::new(self, 0)
     }
     #[doc = "Bit 1 - This is the interrupt raw bit. Triggered when UHCI detects a separator char."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_start(&mut self) -> TX_START_W<INT_RAW_SPEC> {
         TX_START_W::new(self, 1)
     }
     #[doc = "Bit 2 - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_RAW_SPEC> {
         RX_HUNG_W::new(self, 2)
     }
     #[doc = "Bit 3 - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_RAW_SPEC> {
         TX_HUNG_W::new(self, 3)
     }
     #[doc = "Bit 4 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers."]
     #[inline(always)]
-    #[must_use]
     pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_RAW_SPEC> {
         SEND_S_REG_Q_W::new(self, 4)
     }
     #[doc = "Bit 5 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers."]
     #[inline(always)]
-    #[must_use]
     pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_RAW_SPEC> {
         SEND_A_REG_Q_W::new(self, 5)
     }
     #[doc = "Bit 6 - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data."]
     #[inline(always)]
-    #[must_use]
     pub fn out_eof(&mut self) -> OUT_EOF_W<INT_RAW_SPEC> {
         OUT_EOF_W::new(self, 6)
     }
     #[doc = "Bit 7 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_RAW_SPEC> {
         APP_CTRL0_W::new(self, 7)
     }
     #[doc = "Bit 8 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET."]
     #[inline(always)]
-    #[must_use]
     pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_RAW_SPEC> {
         APP_CTRL1_W::new(self, 8)
     }
diff --git a/esp32s3/src/uhci0/pkt_thres.rs b/esp32s3/src/uhci0/pkt_thres.rs
index d31412ac4e..557230acbf 100644
--- a/esp32s3/src/uhci0/pkt_thres.rs
+++ b/esp32s3/src/uhci0/pkt_thres.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pkt_thrs(&mut self) -> PKT_THRS_W<PKT_THRES_SPEC> {
         PKT_THRS_W::new(self, 0)
     }
diff --git a/esp32s3/src/uhci0/quick_sent.rs b/esp32s3/src/uhci0/quick_sent.rs
index 01756c0df4..eaaf821a68 100644
--- a/esp32s3/src/uhci0/quick_sent.rs
+++ b/esp32s3/src/uhci0/quick_sent.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2 - This register is used to specify the single_send register."]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_NUM_W::new(self, 0)
     }
     #[doc = "Bit 3 - Set this bit to enable single_send mode to send short packet."]
     #[inline(always)]
-    #[must_use]
     pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W<QUICK_SENT_SPEC> {
         SINGLE_SEND_EN_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - This register is used to specify the always_send register."]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_NUM_W::new(self, 4)
     }
     #[doc = "Bit 7 - Set this bit to enable always_send mode to send short packet."]
     #[inline(always)]
-    #[must_use]
     pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W<QUICK_SENT_SPEC> {
         ALWAYS_SEND_EN_W::new(self, 7)
     }
diff --git a/esp32s3/src/uhci0/reg_q/word0.rs b/esp32s3/src/uhci0/reg_q/word0.rs
index 1358d24d3d..59919e992d 100644
--- a/esp32s3/src/uhci0/reg_q/word0.rs
+++ b/esp32s3/src/uhci0/reg_q/word0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD0_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32s3/src/uhci0/reg_q/word1.rs b/esp32s3/src/uhci0/reg_q/word1.rs
index c0ea812085..e5ae688da2 100644
--- a/esp32s3/src/uhci0/reg_q/word1.rs
+++ b/esp32s3/src/uhci0/reg_q/word1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
-    #[must_use]
     pub fn send_word(&mut self) -> SEND_WORD_W<WORD1_SPEC> {
         SEND_WORD_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0.rs b/esp32s3/src/usb0.rs
index 59eed2f399..7819d5d3ea 100644
--- a/esp32s3/src/usb0.rs
+++ b/esp32s3/src/usb0.rs
@@ -160,6 +160,8 @@ impl RegisterBlock {
         &self.hptxfsiz
     }
     #[doc = "0x104..0x114 - "]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `DIEPTXF1` register.</div>"]
     #[inline(always)]
     pub const fn dieptxf(&self, n: usize) -> &DIEPTXF {
         &self.dieptxf[n]
@@ -302,6 +304,8 @@ impl RegisterBlock {
         &self.in_ep0
     }
     #[doc = "0x920..0x9e0 - Device IN endpoints 1-6"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `IN_EP1` cluster.</div>"]
     #[inline(always)]
     pub const fn in_ep(&self, n: usize) -> &IN_EP {
         &self.in_ep[n]
@@ -348,6 +352,8 @@ impl RegisterBlock {
         &self.out_ep0
     }
     #[doc = "0xb20..0xbe0 - Device OUT endpoints 1-6"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `OUT_EP1` cluster.</div>"]
     #[inline(always)]
     pub const fn out_ep(&self, n: usize) -> &OUT_EP {
         &self.out_ep[n]
@@ -399,7 +405,7 @@ impl RegisterBlock {
         #[allow(clippy::no_effect)]
         [(); 16][n];
         unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(4096)
                 .add(4096 * n)
@@ -411,7 +417,7 @@ impl RegisterBlock {
     #[inline(always)]
     pub fn fifo_iter(&self) -> impl Iterator<Item = &FIFO> {
         (0..16).map(move |n| unsafe {
-            &*(self as *const Self)
+            &*core::ptr::from_ref(self)
                 .cast::<u8>()
                 .add(4096)
                 .add(4096 * n)
diff --git a/esp32s3/src/usb0/daintmsk.rs b/esp32s3/src/usb0/daintmsk.rs
index 231fa18130..e0075ce733 100644
--- a/esp32s3/src/usb0/daintmsk.rs
+++ b/esp32s3/src/usb0/daintmsk.rs
@@ -138,7 +138,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `INEPMSK0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk(&mut self, n: u8) -> INEPMSK_W<DAINTMSK_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 7][n as usize];
@@ -146,43 +145,36 @@ impl W {
     }
     #[doc = "Bit 0 - INEPMSK0"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk0(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 0)
     }
     #[doc = "Bit 1 - INEPMSK1"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk1(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 1)
     }
     #[doc = "Bit 2 - INEPMSK2"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk2(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 2)
     }
     #[doc = "Bit 3 - INEPMSK3"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk3(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 3)
     }
     #[doc = "Bit 4 - INEPMSK4"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk4(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 4)
     }
     #[doc = "Bit 5 - INEPMSK5"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk5(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 5)
     }
     #[doc = "Bit 6 - INEPMSK6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepmsk6(&mut self) -> INEPMSK_W<DAINTMSK_SPEC> {
         INEPMSK_W::new(self, 6)
     }
@@ -190,7 +182,6 @@ impl W {
     #[doc = ""]
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OUTEPMSK0` field.</div>"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk(&mut self, n: u8) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 7][n as usize];
@@ -198,43 +189,36 @@ impl W {
     }
     #[doc = "Bit 16 - OUTEPMSK0"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk0(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 16)
     }
     #[doc = "Bit 17 - OUTEPMSK1"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk1(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 17)
     }
     #[doc = "Bit 18 - OUTEPMSK2"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk2(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 18)
     }
     #[doc = "Bit 19 - OUTEPMSK3"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk3(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 19)
     }
     #[doc = "Bit 20 - OUTEPMSK4"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk4(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 20)
     }
     #[doc = "Bit 21 - OUTEPMSK5"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk5(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 21)
     }
     #[doc = "Bit 22 - OUTEPMSK6"]
     #[inline(always)]
-    #[must_use]
     pub fn outepmsk6(&mut self) -> OUTEPMSK_W<DAINTMSK_SPEC> {
         OUTEPMSK_W::new(self, 22)
     }
diff --git a/esp32s3/src/usb0/dcfg.rs b/esp32s3/src/usb0/dcfg.rs
index a6d0af1184..6488a1b902 100644
--- a/esp32s3/src/usb0/dcfg.rs
+++ b/esp32s3/src/usb0/dcfg.rs
@@ -124,67 +124,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn nzstsouthshk(&mut self) -> NZSTSOUTHSHK_W<DCFG_SPEC> {
         NZSTSOUTHSHK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ena32khzsusp(&mut self) -> ENA32KHZSUSP_W<DCFG_SPEC> {
         ENA32KHZSUSP_W::new(self, 3)
     }
     #[doc = "Bits 4:10"]
     #[inline(always)]
-    #[must_use]
     pub fn devaddr(&mut self) -> DEVADDR_W<DCFG_SPEC> {
         DEVADDR_W::new(self, 4)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn perfrlint(&mut self) -> PERFRLINT_W<DCFG_SPEC> {
         PERFRLINT_W::new(self, 11)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn endevoutnak(&mut self) -> ENDEVOUTNAK_W<DCFG_SPEC> {
         ENDEVOUTNAK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn xcvrdly(&mut self) -> XCVRDLY_W<DCFG_SPEC> {
         XCVRDLY_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn erraticintmsk(&mut self) -> ERRATICINTMSK_W<DCFG_SPEC> {
         ERRATICINTMSK_W::new(self, 15)
     }
     #[doc = "Bits 18:22"]
     #[inline(always)]
-    #[must_use]
     pub fn epmiscnt(&mut self) -> EPMISCNT_W<DCFG_SPEC> {
         EPMISCNT_W::new(self, 18)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn descdma(&mut self) -> DESCDMA_W<DCFG_SPEC> {
         DESCDMA_W::new(self, 23)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn perschintvl(&mut self) -> PERSCHINTVL_W<DCFG_SPEC> {
         PERSCHINTVL_W::new(self, 24)
     }
     #[doc = "Bits 26:31"]
     #[inline(always)]
-    #[must_use]
     pub fn resvalid(&mut self) -> RESVALID_W<DCFG_SPEC> {
         RESVALID_W::new(self, 26)
     }
diff --git a/esp32s3/src/usb0/dctl.rs b/esp32s3/src/usb0/dctl.rs
index e806259488..ca8528bace 100644
--- a/esp32s3/src/usb0/dctl.rs
+++ b/esp32s3/src/usb0/dctl.rs
@@ -128,79 +128,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn rmtwkupsig(&mut self) -> RMTWKUPSIG_W<DCTL_SPEC> {
         RMTWKUPSIG_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sftdiscon(&mut self) -> SFTDISCON_W<DCTL_SPEC> {
         SFTDISCON_W::new(self, 1)
     }
     #[doc = "Bits 4:6"]
     #[inline(always)]
-    #[must_use]
     pub fn tstctl(&mut self) -> TSTCTL_W<DCTL_SPEC> {
         TSTCTL_W::new(self, 4)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sgnpinnak(&mut self) -> SGNPINNAK_W<DCTL_SPEC> {
         SGNPINNAK_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn cgnpinnak(&mut self) -> CGNPINNAK_W<DCTL_SPEC> {
         CGNPINNAK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sgoutnak(&mut self) -> SGOUTNAK_W<DCTL_SPEC> {
         SGOUTNAK_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn cgoutnak(&mut self) -> CGOUTNAK_W<DCTL_SPEC> {
         CGOUTNAK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pwronprgdone(&mut self) -> PWRONPRGDONE_W<DCTL_SPEC> {
         PWRONPRGDONE_W::new(self, 11)
     }
     #[doc = "Bits 13:14"]
     #[inline(always)]
-    #[must_use]
     pub fn gmc(&mut self) -> GMC_W<DCTL_SPEC> {
         GMC_W::new(self, 13)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ignrfrmnum(&mut self) -> IGNRFRMNUM_W<DCTL_SPEC> {
         IGNRFRMNUM_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn nakonbble(&mut self) -> NAKONBBLE_W<DCTL_SPEC> {
         NAKONBBLE_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn encountonbna(&mut self) -> ENCOUNTONBNA_W<DCTL_SPEC> {
         ENCOUNTONBNA_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn deepsleepbeslreject(&mut self) -> DEEPSLEEPBESLREJECT_W<DCTL_SPEC> {
         DEEPSLEEPBESLREJECT_W::new(self, 18)
     }
diff --git a/esp32s3/src/usb0/diepempmsk.rs b/esp32s3/src/usb0/diepempmsk.rs
index 0f43f3df8c..b9f279ed78 100644
--- a/esp32s3/src/usb0/diepempmsk.rs
+++ b/esp32s3/src/usb0/diepempmsk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn d_ineptxfempmsk(&mut self) -> D_INEPTXFEMPMSK_W<DIEPEMPMSK_SPEC> {
         D_INEPTXFEMPMSK_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/diepmsk.rs b/esp32s3/src/usb0/diepmsk.rs
index 106eb330b5..02c6955f54 100644
--- a/esp32s3/src/usb0/diepmsk.rs
+++ b/esp32s3/src/usb0/diepmsk.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn di_xfercomplmsk(&mut self) -> DI_XFERCOMPLMSK_W<DIEPMSK_SPEC> {
         DI_XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn di_epdisbldmsk(&mut self) -> DI_EPDISBLDMSK_W<DIEPMSK_SPEC> {
         DI_EPDISBLDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn di_ahbermsk(&mut self) -> DI_AHBERMSK_W<DIEPMSK_SPEC> {
         DI_AHBERMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timeoutmsk(&mut self) -> TIMEOUTMSK_W<DIEPMSK_SPEC> {
         TIMEOUTMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn intkntxfempmsk(&mut self) -> INTKNTXFEMPMSK_W<DIEPMSK_SPEC> {
         INTKNTXFEMPMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn intknepmismsk(&mut self) -> INTKNEPMISMSK_W<DIEPMSK_SPEC> {
         INTKNEPMISMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepnakeffmsk(&mut self) -> INEPNAKEFFMSK_W<DIEPMSK_SPEC> {
         INEPNAKEFFMSK_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifoundrnmsk(&mut self) -> TXFIFOUNDRNMSK_W<DIEPMSK_SPEC> {
         TXFIFOUNDRNMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnainintrmsk(&mut self) -> BNAININTRMSK_W<DIEPMSK_SPEC> {
         BNAININTRMSK_W::new(self, 9)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn di_nakmsk(&mut self) -> DI_NAKMSK_W<DIEPMSK_SPEC> {
         DI_NAKMSK_W::new(self, 13)
     }
diff --git a/esp32s3/src/usb0/dieptxf.rs b/esp32s3/src/usb0/dieptxf.rs
index d59c42b2bb..63392a85e3 100644
--- a/esp32s3/src/usb0/dieptxf.rs
+++ b/esp32s3/src/usb0/dieptxf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn inep1txfstaddr(&mut self) -> INEP1TXFSTADDR_W<DIEPTXF_SPEC> {
         INEP1TXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn inep1txfdep(&mut self) -> INEP1TXFDEP_W<DIEPTXF_SPEC> {
         INEP1TXFDEP_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb0/doepmsk.rs b/esp32s3/src/usb0/doepmsk.rs
index 89b209f847..5496a246b0 100644
--- a/esp32s3/src/usb0/doepmsk.rs
+++ b/esp32s3/src/usb0/doepmsk.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<DOEPMSK_SPEC> {
         XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbldmsk(&mut self) -> EPDISBLDMSK_W<DOEPMSK_SPEC> {
         EPDISBLDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbermsk(&mut self) -> AHBERMSK_W<DOEPMSK_SPEC> {
         AHBERMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn setupmsk(&mut self) -> SETUPMSK_W<DOEPMSK_SPEC> {
         SETUPMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn outtknepdismsk(&mut self) -> OUTTKNEPDISMSK_W<DOEPMSK_SPEC> {
         OUTTKNEPDISMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn stsphsercvdmsk(&mut self) -> STSPHSERCVDMSK_W<DOEPMSK_SPEC> {
         STSPHSERCVDMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<DOEPMSK_SPEC> {
         BACK2BACKSETUP_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn outpkterrmsk(&mut self) -> OUTPKTERRMSK_W<DOEPMSK_SPEC> {
         OUTPKTERRMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaoutintrmsk(&mut self) -> BNAOUTINTRMSK_W<DOEPMSK_SPEC> {
         BNAOUTINTRMSK_W::new(self, 9)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerrmsk(&mut self) -> BBLEERRMSK_W<DOEPMSK_SPEC> {
         BBLEERRMSK_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakmsk(&mut self) -> NAKMSK_W<DOEPMSK_SPEC> {
         NAKMSK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetmsk(&mut self) -> NYETMSK_W<DOEPMSK_SPEC> {
         NYETMSK_W::new(self, 14)
     }
diff --git a/esp32s3/src/usb0/dthrctl.rs b/esp32s3/src/usb0/dthrctl.rs
index 9ab009ceb9..e1c5862ed7 100644
--- a/esp32s3/src/usb0/dthrctl.rs
+++ b/esp32s3/src/usb0/dthrctl.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn nonisothren(&mut self) -> NONISOTHREN_W<DTHRCTL_SPEC> {
         NONISOTHREN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn isothren(&mut self) -> ISOTHREN_W<DTHRCTL_SPEC> {
         ISOTHREN_W::new(self, 1)
     }
     #[doc = "Bits 2:10"]
     #[inline(always)]
-    #[must_use]
     pub fn txthrlen(&mut self) -> TXTHRLEN_W<DTHRCTL_SPEC> {
         TXTHRLEN_W::new(self, 2)
     }
     #[doc = "Bits 11:12"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbthrratio(&mut self) -> AHBTHRRATIO_W<DTHRCTL_SPEC> {
         AHBTHRRATIO_W::new(self, 11)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn rxthren(&mut self) -> RXTHREN_W<DTHRCTL_SPEC> {
         RXTHREN_W::new(self, 16)
     }
     #[doc = "Bits 17:25"]
     #[inline(always)]
-    #[must_use]
     pub fn rxthrlen(&mut self) -> RXTHRLEN_W<DTHRCTL_SPEC> {
         RXTHRLEN_W::new(self, 17)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn arbprken(&mut self) -> ARBPRKEN_W<DTHRCTL_SPEC> {
         ARBPRKEN_W::new(self, 27)
     }
diff --git a/esp32s3/src/usb0/dvbusdis.rs b/esp32s3/src/usb0/dvbusdis.rs
index 0aded180be..75c7ff65cf 100644
--- a/esp32s3/src/usb0/dvbusdis.rs
+++ b/esp32s3/src/usb0/dvbusdis.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn dvbusdis(&mut self) -> DVBUSDIS_W<DVBUSDIS_SPEC> {
         DVBUSDIS_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/dvbuspulse.rs b/esp32s3/src/usb0/dvbuspulse.rs
index e0ad68f11a..34da3344b2 100644
--- a/esp32s3/src/usb0/dvbuspulse.rs
+++ b/esp32s3/src/usb0/dvbuspulse.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
-    #[must_use]
     pub fn dvbuspulse(&mut self) -> DVBUSPULSE_W<DVBUSPULSE_SPEC> {
         DVBUSPULSE_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/fifo.rs b/esp32s3/src/usb0/fifo.rs
index f5e55135b2..3eb476d958 100644
--- a/esp32s3/src/usb0/fifo.rs
+++ b/esp32s3/src/usb0/fifo.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn word(&mut self) -> WORD_W<FIFO_SPEC> {
         WORD_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/gahbcfg.rs b/esp32s3/src/usb0/gahbcfg.rs
index 23ed6383db..17a6a7368d 100644
--- a/esp32s3/src/usb0/gahbcfg.rs
+++ b/esp32s3/src/usb0/gahbcfg.rs
@@ -104,55 +104,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn glbllntrmsk(&mut self) -> GLBLLNTRMSK_W<GAHBCFG_SPEC> {
         GLBLLNTRMSK_W::new(self, 0)
     }
     #[doc = "Bits 1:4"]
     #[inline(always)]
-    #[must_use]
     pub fn hbstlen(&mut self) -> HBSTLEN_W<GAHBCFG_SPEC> {
         HBSTLEN_W::new(self, 1)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaen(&mut self) -> DMAEN_W<GAHBCFG_SPEC> {
         DMAEN_W::new(self, 5)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfemplvl(&mut self) -> NPTXFEMPLVL_W<GAHBCFG_SPEC> {
         NPTXFEMPLVL_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfemplvl(&mut self) -> PTXFEMPLVL_W<GAHBCFG_SPEC> {
         PTXFEMPLVL_W::new(self, 8)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn remmemsupp(&mut self) -> REMMEMSUPP_W<GAHBCFG_SPEC> {
         REMMEMSUPP_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn notialldmawrit(&mut self) -> NOTIALLDMAWRIT_W<GAHBCFG_SPEC> {
         NOTIALLDMAWRIT_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ahbsingle(&mut self) -> AHBSINGLE_W<GAHBCFG_SPEC> {
         AHBSINGLE_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn invdescendianess(&mut self) -> INVDESCENDIANESS_W<GAHBCFG_SPEC> {
         INVDESCENDIANESS_W::new(self, 24)
     }
diff --git a/esp32s3/src/usb0/gdfifocfg.rs b/esp32s3/src/usb0/gdfifocfg.rs
index 6996405a7a..981246c611 100644
--- a/esp32s3/src/usb0/gdfifocfg.rs
+++ b/esp32s3/src/usb0/gdfifocfg.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gdfifocfg(&mut self) -> GDFIFOCFG_W<GDFIFOCFG_SPEC> {
         GDFIFOCFG_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn epinfobaseaddr(&mut self) -> EPINFOBASEADDR_W<GDFIFOCFG_SPEC> {
         EPINFOBASEADDR_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb0/gintmsk.rs b/esp32s3/src/usb0/gintmsk.rs
index 6b4555f22e..51c75a34e0 100644
--- a/esp32s3/src/usb0/gintmsk.rs
+++ b/esp32s3/src/usb0/gintmsk.rs
@@ -284,163 +284,136 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn modemismsk(&mut self) -> MODEMISMSK_W<GINTMSK_SPEC> {
         MODEMISMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn otgintmsk(&mut self) -> OTGINTMSK_W<GINTMSK_SPEC> {
         OTGINTMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sofmsk(&mut self) -> SOFMSK_W<GINTMSK_SPEC> {
         SOFMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn rxflvimsk(&mut self) -> RXFLVIMSK_W<GINTMSK_SPEC> {
         RXFLVIMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfempmsk(&mut self) -> NPTXFEMPMSK_W<GINTMSK_SPEC> {
         NPTXFEMPMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ginnakeffmsk(&mut self) -> GINNAKEFFMSK_W<GINTMSK_SPEC> {
         GINNAKEFFMSK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn goutnackeffmsk(&mut self) -> GOUTNACKEFFMSK_W<GINTMSK_SPEC> {
         GOUTNACKEFFMSK_W::new(self, 7)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn erlysuspmsk(&mut self) -> ERLYSUSPMSK_W<GINTMSK_SPEC> {
         ERLYSUSPMSK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn usbsuspmsk(&mut self) -> USBSUSPMSK_W<GINTMSK_SPEC> {
         USBSUSPMSK_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn usbrstmsk(&mut self) -> USBRSTMSK_W<GINTMSK_SPEC> {
         USBRSTMSK_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn enumdonemsk(&mut self) -> ENUMDONEMSK_W<GINTMSK_SPEC> {
         ENUMDONEMSK_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn isooutdropmsk(&mut self) -> ISOOUTDROPMSK_W<GINTMSK_SPEC> {
         ISOOUTDROPMSK_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn eopfmsk(&mut self) -> EOPFMSK_W<GINTMSK_SPEC> {
         EOPFMSK_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn epmismsk(&mut self) -> EPMISMSK_W<GINTMSK_SPEC> {
         EPMISMSK_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn iepintmsk(&mut self) -> IEPINTMSK_W<GINTMSK_SPEC> {
         IEPINTMSK_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn oepintmsk(&mut self) -> OEPINTMSK_W<GINTMSK_SPEC> {
         OEPINTMSK_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn incompisoinmsk(&mut self) -> INCOMPISOINMSK_W<GINTMSK_SPEC> {
         INCOMPISOINMSK_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn incompipmsk(&mut self) -> INCOMPIPMSK_W<GINTMSK_SPEC> {
         INCOMPIPMSK_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fetsuspmsk(&mut self) -> FETSUSPMSK_W<GINTMSK_SPEC> {
         FETSUSPMSK_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn resetdetmsk(&mut self) -> RESETDETMSK_W<GINTMSK_SPEC> {
         RESETDETMSK_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn prtlntmsk(&mut self) -> PRTLNTMSK_W<GINTMSK_SPEC> {
         PRTLNTMSK_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn hchintmsk(&mut self) -> HCHINTMSK_W<GINTMSK_SPEC> {
         HCHINTMSK_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfempmsk(&mut self) -> PTXFEMPMSK_W<GINTMSK_SPEC> {
         PTXFEMPMSK_W::new(self, 26)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn conidstschngmsk(&mut self) -> CONIDSTSCHNGMSK_W<GINTMSK_SPEC> {
         CONIDSTSCHNGMSK_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn disconnintmsk(&mut self) -> DISCONNINTMSK_W<GINTMSK_SPEC> {
         DISCONNINTMSK_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn sessreqintmsk(&mut self) -> SESSREQINTMSK_W<GINTMSK_SPEC> {
         SESSREQINTMSK_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn wkupintmsk(&mut self) -> WKUPINTMSK_W<GINTMSK_SPEC> {
         WKUPINTMSK_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/gintsts.rs b/esp32s3/src/usb0/gintsts.rs
index 62dddd5efc..e84b095398 100644
--- a/esp32s3/src/usb0/gintsts.rs
+++ b/esp32s3/src/usb0/gintsts.rs
@@ -272,103 +272,86 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn modemis(&mut self) -> MODEMIS_W<GINTSTS_SPEC> {
         MODEMIS_W::new(self, 1)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sof(&mut self) -> SOF_W<GINTSTS_SPEC> {
         SOF_W::new(self, 3)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn erlysusp(&mut self) -> ERLYSUSP_W<GINTSTS_SPEC> {
         ERLYSUSP_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn usbsusp(&mut self) -> USBSUSP_W<GINTSTS_SPEC> {
         USBSUSP_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn usbrst(&mut self) -> USBRST_W<GINTSTS_SPEC> {
         USBRST_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn enumdone(&mut self) -> ENUMDONE_W<GINTSTS_SPEC> {
         ENUMDONE_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn isooutdrop(&mut self) -> ISOOUTDROP_W<GINTSTS_SPEC> {
         ISOOUTDROP_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn eopf(&mut self) -> EOPF_W<GINTSTS_SPEC> {
         EOPF_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn epmis(&mut self) -> EPMIS_W<GINTSTS_SPEC> {
         EPMIS_W::new(self, 17)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn incompisoin(&mut self) -> INCOMPISOIN_W<GINTSTS_SPEC> {
         INCOMPISOIN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn incompip(&mut self) -> INCOMPIP_W<GINTSTS_SPEC> {
         INCOMPIP_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn fetsusp(&mut self) -> FETSUSP_W<GINTSTS_SPEC> {
         FETSUSP_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn resetdet(&mut self) -> RESETDET_W<GINTSTS_SPEC> {
         RESETDET_W::new(self, 23)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn conidstschng(&mut self) -> CONIDSTSCHNG_W<GINTSTS_SPEC> {
         CONIDSTSCHNG_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn disconnint(&mut self) -> DISCONNINT_W<GINTSTS_SPEC> {
         DISCONNINT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn sessreqint(&mut self) -> SESSREQINT_W<GINTSTS_SPEC> {
         SESSREQINT_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn wkupint(&mut self) -> WKUPINT_W<GINTSTS_SPEC> {
         WKUPINT_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/gnptxfsiz.rs b/esp32s3/src/usb0/gnptxfsiz.rs
index 64f666b6fe..b6ad1bc036 100644
--- a/esp32s3/src/usb0/gnptxfsiz.rs
+++ b/esp32s3/src/usb0/gnptxfsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfstaddr(&mut self) -> NPTXFSTADDR_W<GNPTXFSIZ_SPEC> {
         NPTXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn nptxfdep(&mut self) -> NPTXFDEP_W<GNPTXFSIZ_SPEC> {
         NPTXFDEP_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb0/gotgctl.rs b/esp32s3/src/usb0/gotgctl.rs
index c0500f1604..6b575cd5fb 100644
--- a/esp32s3/src/usb0/gotgctl.rs
+++ b/esp32s3/src/usb0/gotgctl.rs
@@ -200,79 +200,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sesreq(&mut self) -> SESREQ_W<GOTGCTL_SPEC> {
         SESREQ_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn vbvalidoven(&mut self) -> VBVALIDOVEN_W<GOTGCTL_SPEC> {
         VBVALIDOVEN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn vbvalidovval(&mut self) -> VBVALIDOVVAL_W<GOTGCTL_SPEC> {
         VBVALIDOVVAL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn avalidoven(&mut self) -> AVALIDOVEN_W<GOTGCTL_SPEC> {
         AVALIDOVEN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn avalidovval(&mut self) -> AVALIDOVVAL_W<GOTGCTL_SPEC> {
         AVALIDOVVAL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn bvalidoven(&mut self) -> BVALIDOVEN_W<GOTGCTL_SPEC> {
         BVALIDOVEN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn bvalidovval(&mut self) -> BVALIDOVVAL_W<GOTGCTL_SPEC> {
         BVALIDOVVAL_W::new(self, 7)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hnpreq(&mut self) -> HNPREQ_W<GOTGCTL_SPEC> {
         HNPREQ_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn hstsethnpen(&mut self) -> HSTSETHNPEN_W<GOTGCTL_SPEC> {
         HSTSETHNPEN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn devhnpen(&mut self) -> DEVHNPEN_W<GOTGCTL_SPEC> {
         DEVHNPEN_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ehen(&mut self) -> EHEN_W<GOTGCTL_SPEC> {
         EHEN_W::new(self, 12)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn dbncefltrbypass(&mut self) -> DBNCEFLTRBYPASS_W<GOTGCTL_SPEC> {
         DBNCEFLTRBYPASS_W::new(self, 15)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn otgver(&mut self) -> OTGVER_W<GOTGCTL_SPEC> {
         OTGVER_W::new(self, 20)
     }
diff --git a/esp32s3/src/usb0/gotgint.rs b/esp32s3/src/usb0/gotgint.rs
index 65bc5f1f82..b588af01dd 100644
--- a/esp32s3/src/usb0/gotgint.rs
+++ b/esp32s3/src/usb0/gotgint.rs
@@ -74,37 +74,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sesenddet(&mut self) -> SESENDDET_W<GOTGINT_SPEC> {
         SESENDDET_W::new(self, 2)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sesreqsucstschng(&mut self) -> SESREQSUCSTSCHNG_W<GOTGINT_SPEC> {
         SESREQSUCSTSCHNG_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hstnegsucstschng(&mut self) -> HSTNEGSUCSTSCHNG_W<GOTGINT_SPEC> {
         HSTNEGSUCSTSCHNG_W::new(self, 9)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn hstnegdet(&mut self) -> HSTNEGDET_W<GOTGINT_SPEC> {
         HSTNEGDET_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn adevtoutchg(&mut self) -> ADEVTOUTCHG_W<GOTGINT_SPEC> {
         ADEVTOUTCHG_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn dbncedone(&mut self) -> DBNCEDONE_W<GOTGINT_SPEC> {
         DBNCEDONE_W::new(self, 19)
     }
diff --git a/esp32s3/src/usb0/grstctl.rs b/esp32s3/src/usb0/grstctl.rs
index bdd666ef07..83ad580e3e 100644
--- a/esp32s3/src/usb0/grstctl.rs
+++ b/esp32s3/src/usb0/grstctl.rs
@@ -90,37 +90,31 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn csftrst(&mut self) -> CSFTRST_W<GRSTCTL_SPEC> {
         CSFTRST_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn piufssftrst(&mut self) -> PIUFSSFTRST_W<GRSTCTL_SPEC> {
         PIUFSSFTRST_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn frmcntrrst(&mut self) -> FRMCNTRRST_W<GRSTCTL_SPEC> {
         FRMCNTRRST_W::new(self, 2)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfflsh(&mut self) -> RXFFLSH_W<GRSTCTL_SPEC> {
         RXFFLSH_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn txfflsh(&mut self) -> TXFFLSH_W<GRSTCTL_SPEC> {
         TXFFLSH_W::new(self, 5)
     }
     #[doc = "Bits 6:10"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<GRSTCTL_SPEC> {
         TXFNUM_W::new(self, 6)
     }
diff --git a/esp32s3/src/usb0/grxfsiz.rs b/esp32s3/src/usb0/grxfsiz.rs
index 1b3760bac6..6fbfc23f7a 100644
--- a/esp32s3/src/usb0/grxfsiz.rs
+++ b/esp32s3/src/usb0/grxfsiz.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn rxfdep(&mut self) -> RXFDEP_W<GRXFSIZ_SPEC> {
         RXFDEP_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/gusbcfg.rs b/esp32s3/src/usb0/gusbcfg.rs
index 0cda2361ee..1351cb9c67 100644
--- a/esp32s3/src/usb0/gusbcfg.rs
+++ b/esp32s3/src/usb0/gusbcfg.rs
@@ -140,67 +140,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn toutcal(&mut self) -> TOUTCAL_W<GUSBCFG_SPEC> {
         TOUTCAL_W::new(self, 0)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn phyif(&mut self) -> PHYIF_W<GUSBCFG_SPEC> {
         PHYIF_W::new(self, 3)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn fsintf(&mut self) -> FSINTF_W<GUSBCFG_SPEC> {
         FSINTF_W::new(self, 5)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn srpcap(&mut self) -> SRPCAP_W<GUSBCFG_SPEC> {
         SRPCAP_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn hnpcap(&mut self) -> HNPCAP_W<GUSBCFG_SPEC> {
         HNPCAP_W::new(self, 9)
     }
     #[doc = "Bits 10:13"]
     #[inline(always)]
-    #[must_use]
     pub fn usbtrdtim(&mut self) -> USBTRDTIM_W<GUSBCFG_SPEC> {
         USBTRDTIM_W::new(self, 10)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn termseldlpulse(&mut self) -> TERMSELDLPULSE_W<GUSBCFG_SPEC> {
         TERMSELDLPULSE_W::new(self, 22)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn txenddelay(&mut self) -> TXENDDELAY_W<GUSBCFG_SPEC> {
         TXENDDELAY_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn forcehstmode(&mut self) -> FORCEHSTMODE_W<GUSBCFG_SPEC> {
         FORCEHSTMODE_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn forcedevmode(&mut self) -> FORCEDEVMODE_W<GUSBCFG_SPEC> {
         FORCEDEVMODE_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn corrupttxpkt(&mut self) -> CORRUPTTXPKT_W<GUSBCFG_SPEC> {
         CORRUPTTXPKT_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/haintmsk.rs b/esp32s3/src/usb0/haintmsk.rs
index eed276f53e..6779448c85 100644
--- a/esp32s3/src/usb0/haintmsk.rs
+++ b/esp32s3/src/usb0/haintmsk.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn haintmsk(&mut self) -> HAINTMSK_W<HAINTMSK_SPEC> {
         HAINTMSK_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/hc/char.rs b/esp32s3/src/usb0/hc/char.rs
index 8fa3c4a433..906fb5c5ea 100644
--- a/esp32s3/src/usb0/hc/char.rs
+++ b/esp32s3/src/usb0/hc/char.rs
@@ -114,61 +114,51 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<CHAR_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bits 11:14"]
     #[inline(always)]
-    #[must_use]
     pub fn epnum(&mut self) -> EPNUM_W<CHAR_SPEC> {
         EPNUM_W::new(self, 11)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn epdir(&mut self) -> EPDIR_W<CHAR_SPEC> {
         EPDIR_W::new(self, 15)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn lspddev(&mut self) -> LSPDDEV_W<CHAR_SPEC> {
         LSPDDEV_W::new(self, 17)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<CHAR_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ec(&mut self) -> EC_W<CHAR_SPEC> {
         EC_W::new(self, 21)
     }
     #[doc = "Bits 22:28"]
     #[inline(always)]
-    #[must_use]
     pub fn devaddr(&mut self) -> DEVADDR_W<CHAR_SPEC> {
         DEVADDR_W::new(self, 22)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn oddfrm(&mut self) -> ODDFRM_W<CHAR_SPEC> {
         ODDFRM_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn chdis(&mut self) -> CHDIS_W<CHAR_SPEC> {
         CHDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn chena(&mut self) -> CHENA_W<CHAR_SPEC> {
         CHENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/hc/dma.rs b/esp32s3/src/usb0/hc/dma.rs
index 43d5d40c9f..8f54073847 100644
--- a/esp32s3/src/usb0/hc/dma.rs
+++ b/esp32s3/src/usb0/hc/dma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/hc/int.rs b/esp32s3/src/usb0/hc/int.rs
index 4b1dea7eae..d8f78296bc 100644
--- a/esp32s3/src/usb0/hc/int.rs
+++ b/esp32s3/src/usb0/hc/int.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<INT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn chhltd(&mut self) -> CHHLTD_W<INT_SPEC> {
         CHHLTD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<INT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<INT_SPEC> {
         STALL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<INT_SPEC> {
         NACK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ack(&mut self) -> ACK_W<INT_SPEC> {
         ACK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn nyet(&mut self) -> NYET_W<INT_SPEC> {
         NYET_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn xacterr(&mut self) -> XACTERR_W<INT_SPEC> {
         XACTERR_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn bblerr(&mut self) -> BBLERR_W<INT_SPEC> {
         BBLERR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn frmovrun(&mut self) -> FRMOVRUN_W<INT_SPEC> {
         FRMOVRUN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn datatglerr(&mut self) -> DATATGLERR_W<INT_SPEC> {
         DATATGLERR_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<INT_SPEC> {
         BNAINTR_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn xcs_xact_err(&mut self) -> XCS_XACT_ERR_W<INT_SPEC> {
         XCS_XACT_ERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn desc_lst_rollintr(&mut self) -> DESC_LST_ROLLINTR_W<INT_SPEC> {
         DESC_LST_ROLLINTR_W::new(self, 13)
     }
diff --git a/esp32s3/src/usb0/hc/intmsk.rs b/esp32s3/src/usb0/hc/intmsk.rs
index ad418d26ff..794713f712 100644
--- a/esp32s3/src/usb0/hc/intmsk.rs
+++ b/esp32s3/src/usb0/hc/intmsk.rs
@@ -144,79 +144,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<INTMSK_SPEC> {
         XFERCOMPLMSK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<INTMSK_SPEC> {
         CHHLTDMSK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<INTMSK_SPEC> {
         AHBERRMSK_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn stallmsk(&mut self) -> STALLMSK_W<INTMSK_SPEC> {
         STALLMSK_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn nakmsk(&mut self) -> NAKMSK_W<INTMSK_SPEC> {
         NAKMSK_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ackmsk(&mut self) -> ACKMSK_W<INTMSK_SPEC> {
         ACKMSK_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetmsk(&mut self) -> NYETMSK_W<INTMSK_SPEC> {
         NYETMSK_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<INTMSK_SPEC> {
         XACTERRMSK_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<INTMSK_SPEC> {
         BBLERRMSK_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<INTMSK_SPEC> {
         FRMOVRUNMSK_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<INTMSK_SPEC> {
         DATATGLERRMSK_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintrmsk(&mut self) -> BNAINTRMSK_W<INTMSK_SPEC> {
         BNAINTRMSK_W::new(self, 11)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn desc_lst_rollintrmsk(&mut self) -> DESC_LST_ROLLINTRMSK_W<INTMSK_SPEC> {
         DESC_LST_ROLLINTRMSK_W::new(self, 13)
     }
diff --git a/esp32s3/src/usb0/hc/tsiz.rs b/esp32s3/src/usb0/hc/tsiz.rs
index c8693b771d..30558700fd 100644
--- a/esp32s3/src/usb0/hc/tsiz.rs
+++ b/esp32s3/src/usb0/hc/tsiz.rs
@@ -54,25 +54,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<TSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<TSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn pid(&mut self) -> PID_W<TSIZ_SPEC> {
         PID_W::new(self, 29)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn dopng(&mut self) -> DOPNG_W<TSIZ_SPEC> {
         DOPNG_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/hcfg.rs b/esp32s3/src/usb0/hcfg.rs
index a716d5c156..1ca636e59a 100644
--- a/esp32s3/src/usb0/hcfg.rs
+++ b/esp32s3/src/usb0/hcfg.rs
@@ -84,43 +84,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W<HCFG_SPEC> {
         FSLSPCLKSEL_W::new(self, 0)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn fslssupp(&mut self) -> FSLSSUPP_W<HCFG_SPEC> {
         FSLSSUPP_W::new(self, 2)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ena32khzs(&mut self) -> ENA32KHZS_W<HCFG_SPEC> {
         ENA32KHZS_W::new(self, 7)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn descdma(&mut self) -> DESCDMA_W<HCFG_SPEC> {
         DESCDMA_W::new(self, 23)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn frlisten(&mut self) -> FRLISTEN_W<HCFG_SPEC> {
         FRLISTEN_W::new(self, 24)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn perschedena(&mut self) -> PERSCHEDENA_W<HCFG_SPEC> {
         PERSCHEDENA_W::new(self, 26)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn modechtimen(&mut self) -> MODECHTIMEN_W<HCFG_SPEC> {
         MODECHTIMEN_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/hfir.rs b/esp32s3/src/usb0/hfir.rs
index e8a461ca6f..a9e241d9b8 100644
--- a/esp32s3/src/usb0/hfir.rs
+++ b/esp32s3/src/usb0/hfir.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn frint(&mut self) -> FRINT_W<HFIR_SPEC> {
         FRINT_W::new(self, 0)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn hfirrldctrl(&mut self) -> HFIRRLDCTRL_W<HFIR_SPEC> {
         HFIRRLDCTRL_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb0/hflbaddr.rs b/esp32s3/src/usb0/hflbaddr.rs
index c3545c961f..f49a43e827 100644
--- a/esp32s3/src/usb0/hflbaddr.rs
+++ b/esp32s3/src/usb0/hflbaddr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn hflbaddr(&mut self) -> HFLBADDR_W<HFLBADDR_SPEC> {
         HFLBADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/hprt.rs b/esp32s3/src/usb0/hprt.rs
index 08371ccc09..1aab1f1fb3 100644
--- a/esp32s3/src/usb0/hprt.rs
+++ b/esp32s3/src/usb0/hprt.rs
@@ -136,55 +136,46 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn prtconndet(&mut self) -> PRTCONNDET_W<HPRT_SPEC> {
         PRTCONNDET_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn prtena(&mut self) -> PRTENA_W<HPRT_SPEC> {
         PRTENA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn prtenchng(&mut self) -> PRTENCHNG_W<HPRT_SPEC> {
         PRTENCHNG_W::new(self, 3)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn prtovrcurrchng(&mut self) -> PRTOVRCURRCHNG_W<HPRT_SPEC> {
         PRTOVRCURRCHNG_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn prtres(&mut self) -> PRTRES_W<HPRT_SPEC> {
         PRTRES_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn prtsusp(&mut self) -> PRTSUSP_W<HPRT_SPEC> {
         PRTSUSP_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn prtrst(&mut self) -> PRTRST_W<HPRT_SPEC> {
         PRTRST_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn prtpwr(&mut self) -> PRTPWR_W<HPRT_SPEC> {
         PRTPWR_W::new(self, 12)
     }
     #[doc = "Bits 13:16"]
     #[inline(always)]
-    #[must_use]
     pub fn prttstctl(&mut self) -> PRTTSTCTL_W<HPRT_SPEC> {
         PRTTSTCTL_W::new(self, 13)
     }
diff --git a/esp32s3/src/usb0/hptxfsiz.rs b/esp32s3/src/usb0/hptxfsiz.rs
index 33af448539..9e9389cf89 100644
--- a/esp32s3/src/usb0/hptxfsiz.rs
+++ b/esp32s3/src/usb0/hptxfsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfstaddr(&mut self) -> PTXFSTADDR_W<HPTXFSIZ_SPEC> {
         PTXFSTADDR_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ptxfsize(&mut self) -> PTXFSIZE_W<HPTXFSIZ_SPEC> {
         PTXFSIZE_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb0/in_ep/diepctl.rs b/esp32s3/src/usb0/in_ep/diepctl.rs
index f1ccc75dc0..3edca046cf 100644
--- a/esp32s3/src/usb0/in_ep/diepctl.rs
+++ b/esp32s3/src/usb0/in_ep/diepctl.rs
@@ -100,67 +100,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DIEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn usbactep(&mut self) -> USBACTEP_W<DIEPCTL_SPEC> {
         USBACTEP_W::new(self, 15)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<DIEPCTL_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DIEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bits 22:25"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<DIEPCTL_SPEC> {
         TXFNUM_W::new(self, 22)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DIEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DIEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn setd0pid(&mut self) -> SETD0PID_W<DIEPCTL_SPEC> {
         SETD0PID_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn setd1pid(&mut self) -> SETD1PID_W<DIEPCTL_SPEC> {
         SETD1PID_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DIEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DIEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/in_ep/dieptsiz.rs b/esp32s3/src/usb0/in_ep/dieptsiz.rs
index b56d094260..d4b0862441 100644
--- a/esp32s3/src/usb0/in_ep/dieptsiz.rs
+++ b/esp32s3/src/usb0/in_ep/dieptsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DIEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DIEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
diff --git a/esp32s3/src/usb0/in_ep0/diepctl.rs b/esp32s3/src/usb0/in_ep0/diepctl.rs
index da2f3f3341..b5fffe659c 100644
--- a/esp32s3/src/usb0/in_ep0/diepctl.rs
+++ b/esp32s3/src/usb0/in_ep0/diepctl.rs
@@ -92,43 +92,36 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DIEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DIEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bits 22:25"]
     #[inline(always)]
-    #[must_use]
     pub fn txfnum(&mut self) -> TXFNUM_W<DIEPCTL_SPEC> {
         TXFNUM_W::new(self, 22)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DIEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DIEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DIEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DIEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/in_ep0/diepdma.rs b/esp32s3/src/usb0/in_ep0/diepdma.rs
index fda02a27d7..14e7e7eb4e 100644
--- a/esp32s3/src/usb0/in_ep0/diepdma.rs
+++ b/esp32s3/src/usb0/in_ep0/diepdma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DIEPDMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/in_ep0/diepint.rs b/esp32s3/src/usb0/in_ep0/diepint.rs
index 7717febbce..4b88eda259 100644
--- a/esp32s3/src/usb0/in_ep0/diepint.rs
+++ b/esp32s3/src/usb0/in_ep0/diepint.rs
@@ -152,79 +152,66 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<DIEPINT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbld(&mut self) -> EPDISBLD_W<DIEPINT_SPEC> {
         EPDISBLD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<DIEPINT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn timeout(&mut self) -> TIMEOUT_W<DIEPINT_SPEC> {
         TIMEOUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<DIEPINT_SPEC> {
         INTKNTXFEMP_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn intknepmis(&mut self) -> INTKNEPMIS_W<DIEPINT_SPEC> {
         INTKNEPMIS_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<DIEPINT_SPEC> {
         INEPNAKEFF_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<DIEPINT_SPEC> {
         TXFIFOUNDRN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<DIEPINT_SPEC> {
         BNAINTR_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<DIEPINT_SPEC> {
         PKTDRPSTS_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerr(&mut self) -> BBLEERR_W<DIEPINT_SPEC> {
         BBLEERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakintrpt(&mut self) -> NAKINTRPT_W<DIEPINT_SPEC> {
         NAKINTRPT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyetintrpt(&mut self) -> NYETINTRPT_W<DIEPINT_SPEC> {
         NYETINTRPT_W::new(self, 14)
     }
diff --git a/esp32s3/src/usb0/in_ep0/dieptsiz.rs b/esp32s3/src/usb0/in_ep0/dieptsiz.rs
index f13b9d4f8c..41e3a4167b 100644
--- a/esp32s3/src/usb0/in_ep0/dieptsiz.rs
+++ b/esp32s3/src/usb0/in_ep0/dieptsiz.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DIEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:20"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DIEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
diff --git a/esp32s3/src/usb0/out_ep/doepctl.rs b/esp32s3/src/usb0/out_ep/doepctl.rs
index 3f72a94784..8383da45f8 100644
--- a/esp32s3/src/usb0/out_ep/doepctl.rs
+++ b/esp32s3/src/usb0/out_ep/doepctl.rs
@@ -100,67 +100,56 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn mps(&mut self) -> MPS_W<DOEPCTL_SPEC> {
         MPS_W::new(self, 0)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn usbactep(&mut self) -> USBACTEP_W<DOEPCTL_SPEC> {
         USBACTEP_W::new(self, 15)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn eptype(&mut self) -> EPTYPE_W<DOEPCTL_SPEC> {
         EPTYPE_W::new(self, 18)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn snp(&mut self) -> SNP_W<DOEPCTL_SPEC> {
         SNP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DOEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DOEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DOEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn setd0pid(&mut self) -> SETD0PID_W<DOEPCTL_SPEC> {
         SETD0PID_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn setd1pid(&mut self) -> SETD1PID_W<DOEPCTL_SPEC> {
         SETD1PID_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn epdis(&mut self) -> EPDIS_W<DOEPCTL_SPEC> {
         EPDIS_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DOEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/out_ep/doeptsiz.rs b/esp32s3/src/usb0/out_ep/doeptsiz.rs
index d41c10a8e2..b8fd22ab01 100644
--- a/esp32s3/src/usb0/out_ep/doeptsiz.rs
+++ b/esp32s3/src/usb0/out_ep/doeptsiz.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DOEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bits 19:28"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DOEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn supcnt(&mut self) -> SUPCNT_W<DOEPTSIZ_SPEC> {
         SUPCNT_W::new(self, 29)
     }
diff --git a/esp32s3/src/usb0/out_ep0/doepctl.rs b/esp32s3/src/usb0/out_ep0/doepctl.rs
index 3a49f43156..2df4e16832 100644
--- a/esp32s3/src/usb0/out_ep0/doepctl.rs
+++ b/esp32s3/src/usb0/out_ep0/doepctl.rs
@@ -88,31 +88,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn snp(&mut self) -> SNP_W<DOEPCTL_SPEC> {
         SNP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<DOEPCTL_SPEC> {
         STALL_W::new(self, 21)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn cnak(&mut self) -> CNAK_W<DOEPCTL_SPEC> {
         CNAK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn snak(&mut self) -> SNAK_W<DOEPCTL_SPEC> {
         SNAK_W::new(self, 27)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn epena(&mut self) -> EPENA_W<DOEPCTL_SPEC> {
         EPENA_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb0/out_ep0/doepdma.rs b/esp32s3/src/usb0/out_ep0/doepdma.rs
index 9911f59651..ae7f29bae7 100644
--- a/esp32s3/src/usb0/out_ep0/doepdma.rs
+++ b/esp32s3/src/usb0/out_ep0/doepdma.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmaaddr(&mut self) -> DMAADDR_W<DOEPDMA_SPEC> {
         DMAADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/out_ep0/doepdmab.rs b/esp32s3/src/usb0/out_ep0/doepdmab.rs
index 09d2730336..9cd48daf0a 100644
--- a/esp32s3/src/usb0/out_ep0/doepdmab.rs
+++ b/esp32s3/src/usb0/out_ep0/doepdmab.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dmabufferaddr(&mut self) -> DMABUFFERADDR_W<DOEPDMAB_SPEC> {
         DMABUFFERADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb0/out_ep0/doepint.rs b/esp32s3/src/usb0/out_ep0/doepint.rs
index 240ab32605..56aa763dba 100644
--- a/esp32s3/src/usb0/out_ep0/doepint.rs
+++ b/esp32s3/src/usb0/out_ep0/doepint.rs
@@ -154,85 +154,71 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn xfercompl(&mut self) -> XFERCOMPL_W<DOEPINT_SPEC> {
         XFERCOMPL_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn epdisbld(&mut self) -> EPDISBLD_W<DOEPINT_SPEC> {
         EPDISBLD_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ahberr(&mut self) -> AHBERR_W<DOEPINT_SPEC> {
         AHBERR_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn setup(&mut self) -> SETUP_W<DOEPINT_SPEC> {
         SETUP_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<DOEPINT_SPEC> {
         OUTTKNEPDIS_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<DOEPINT_SPEC> {
         STSPHSERCVD_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<DOEPINT_SPEC> {
         BACK2BACKSETUP_W::new(self, 6)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn outpkterr(&mut self) -> OUTPKTERR_W<DOEPINT_SPEC> {
         OUTPKTERR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bnaintr(&mut self) -> BNAINTR_W<DOEPINT_SPEC> {
         BNAINTR_W::new(self, 9)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<DOEPINT_SPEC> {
         PKTDRPSTS_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bbleerr(&mut self) -> BBLEERR_W<DOEPINT_SPEC> {
         BBLEERR_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn nakintrpt(&mut self) -> NAKINTRPT_W<DOEPINT_SPEC> {
         NAKINTRPT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn nyepintrpt(&mut self) -> NYEPINTRPT_W<DOEPINT_SPEC> {
         NYEPINTRPT_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<DOEPINT_SPEC> {
         STUPPKTRCVD_W::new(self, 15)
     }
diff --git a/esp32s3/src/usb0/out_ep0/doeptsiz.rs b/esp32s3/src/usb0/out_ep0/doeptsiz.rs
index 5224d73bbe..9b13801902 100644
--- a/esp32s3/src/usb0/out_ep0/doeptsiz.rs
+++ b/esp32s3/src/usb0/out_ep0/doeptsiz.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
-    #[must_use]
     pub fn xfersize(&mut self) -> XFERSIZE_W<DOEPTSIZ_SPEC> {
         XFERSIZE_W::new(self, 0)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn pktcnt(&mut self) -> PKTCNT_W<DOEPTSIZ_SPEC> {
         PKTCNT_W::new(self, 19)
     }
     #[doc = "Bits 29:30"]
     #[inline(always)]
-    #[must_use]
     pub fn supcnt(&mut self) -> SUPCNT_W<DOEPTSIZ_SPEC> {
         SUPCNT_W::new(self, 29)
     }
diff --git a/esp32s3/src/usb0/pcgcctl.rs b/esp32s3/src/usb0/pcgcctl.rs
index c649b0ccab..06ebb2daad 100644
--- a/esp32s3/src/usb0/pcgcctl.rs
+++ b/esp32s3/src/usb0/pcgcctl.rs
@@ -80,31 +80,26 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn stoppclk(&mut self) -> STOPPCLK_W<PCGCCTL_SPEC> {
         STOPPCLK_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gatehclk(&mut self) -> GATEHCLK_W<PCGCCTL_SPEC> {
         GATEHCLK_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn pwrclmp(&mut self) -> PWRCLMP_W<PCGCCTL_SPEC> {
         PWRCLMP_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<PCGCCTL_SPEC> {
         RSTPDWNMODULE_W::new(self, 3)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<PCGCCTL_SPEC> {
         RESETAFTERSUSP_W::new(self, 8)
     }
diff --git a/esp32s3/src/usb_device/conf0.rs b/esp32s3/src/usb_device/conf0.rs
index b440b2729e..5e649c543f 100644
--- a/esp32s3/src/usb_device/conf0.rs
+++ b/esp32s3/src/usb_device/conf0.rs
@@ -164,91 +164,76 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
-    #[must_use]
     pub fn phy_sel(&mut self) -> PHY_SEL_W<CONF0_SPEC> {
         PHY_SEL_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable software control USB D+ D- exchange"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W<CONF0_SPEC> {
         EXCHG_PINS_OVERRIDE_W::new(self, 1)
     }
     #[doc = "Bit 2 - USB D+ D- exchange"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins(&mut self) -> EXCHG_PINS_W<CONF0_SPEC> {
         EXCHG_PINS_W::new(self, 2)
     }
     #[doc = "Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefh(&mut self) -> VREFH_W<CONF0_SPEC> {
         VREFH_W::new(self, 3)
     }
     #[doc = "Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefl(&mut self) -> VREFL_W<CONF0_SPEC> {
         VREFL_W::new(self, 5)
     }
     #[doc = "Bit 7 - Enable software control input threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn vref_override(&mut self) -> VREF_OVERRIDE_W<CONF0_SPEC> {
         VREF_OVERRIDE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Enable software control USB D+ D- pullup pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W<CONF0_SPEC> {
         PAD_PULL_OVERRIDE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Control USB D+ pull up."]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup(&mut self) -> DP_PULLUP_W<CONF0_SPEC> {
         DP_PULLUP_W::new(self, 9)
     }
     #[doc = "Bit 10 - Control USB D+ pull down."]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W<CONF0_SPEC> {
         DP_PULLDOWN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Control USB D- pull up."]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup(&mut self) -> DM_PULLUP_W<CONF0_SPEC> {
         DM_PULLUP_W::new(self, 11)
     }
     #[doc = "Bit 12 - Control USB D- pull down."]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W<CONF0_SPEC> {
         DM_PULLDOWN_W::new(self, 12)
     }
     #[doc = "Bit 13 - Control pull up value."]
     #[inline(always)]
-    #[must_use]
     pub fn pullup_value(&mut self) -> PULLUP_VALUE_W<CONF0_SPEC> {
         PULLUP_VALUE_W::new(self, 13)
     }
     #[doc = "Bit 14 - Enable USB pad function."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<CONF0_SPEC> {
         USB_PAD_ENABLE_W::new(self, 14)
     }
     #[doc = "Bit 15 - 0: TX output at clock negedge. 1: Tx output at clock posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W<CONF0_SPEC> {
         PHY_TX_EDGE_SEL_W::new(self, 15)
     }
     #[doc = "Bit 16 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_jtag_bridge_en(&mut self) -> USB_JTAG_BRIDGE_EN_W<CONF0_SPEC> {
         USB_JTAG_BRIDGE_EN_W::new(self, 16)
     }
diff --git a/esp32s3/src/usb_device/date.rs b/esp32s3/src/usb_device/date.rs
index 38aba9442b..2e18cb3610 100644
--- a/esp32s3/src/usb_device/date.rs
+++ b/esp32s3/src/usb_device/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - register version."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb_device/ep1.rs b/esp32s3/src/usb_device/ep1.rs
index 33361b40e1..64f2dc6194 100644
--- a/esp32s3/src/usb_device/ep1.rs
+++ b/esp32s3/src/usb_device/ep1.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn rdwr_byte(&mut self) -> RDWR_BYTE_W<EP1_SPEC> {
         RDWR_BYTE_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb_device/ep1_conf.rs b/esp32s3/src/usb_device/ep1_conf.rs
index 2d6cfbf003..e7e2b173ef 100644
--- a/esp32s3/src/usb_device/ep1_conf.rs
+++ b/esp32s3/src/usb_device/ep1_conf.rs
@@ -32,7 +32,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
-    #[must_use]
     pub fn wr_done(&mut self) -> WR_DONE_W<EP1_CONF_SPEC> {
         WR_DONE_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb_device/int_clr.rs b/esp32s3/src/usb_device/int_clr.rs
index 1dfebfc477..897bc31f0c 100644
--- a/esp32s3/src/usb_device/int_clr.rs
+++ b/esp32s3/src/usb_device/int_clr.rs
@@ -33,73 +33,61 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
 impl W {
     #[doc = "Bit 0 - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn jtag_in_flush(&mut self) -> JTAG_IN_FLUSH_W<INT_CLR_SPEC> {
         JTAG_IN_FLUSH_W::new(self, 0)
     }
     #[doc = "Bit 1 - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sof(&mut self) -> SOF_W<INT_CLR_SPEC> {
         SOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_out_recv_pkt(&mut self) -> SERIAL_OUT_RECV_PKT_W<INT_CLR_SPEC> {
         SERIAL_OUT_RECV_PKT_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_in_empty(&mut self) -> SERIAL_IN_EMPTY_W<INT_CLR_SPEC> {
         SERIAL_IN_EMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pid_err(&mut self) -> PID_ERR_W<INT_CLR_SPEC> {
         PID_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn crc5_err(&mut self) -> CRC5_ERR_W<INT_CLR_SPEC> {
         CRC5_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn crc16_err(&mut self) -> CRC16_ERR_W<INT_CLR_SPEC> {
         CRC16_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn stuff_err(&mut self) -> STUFF_ERR_W<INT_CLR_SPEC> {
         STUFF_ERR_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_token_rec_in_ep1(&mut self) -> IN_TOKEN_REC_IN_EP1_W<INT_CLR_SPEC> {
         IN_TOKEN_REC_IN_EP1_W::new(self, 8)
     }
     #[doc = "Bit 9 - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_bus_reset(&mut self) -> USB_BUS_RESET_W<INT_CLR_SPEC> {
         USB_BUS_RESET_W::new(self, 9)
     }
     #[doc = "Bit 10 - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep1_zero_payload(&mut self) -> OUT_EP1_ZERO_PAYLOAD_W<INT_CLR_SPEC> {
         OUT_EP1_ZERO_PAYLOAD_W::new(self, 10)
     }
     #[doc = "Bit 11 - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep2_zero_payload(&mut self) -> OUT_EP2_ZERO_PAYLOAD_W<INT_CLR_SPEC> {
         OUT_EP2_ZERO_PAYLOAD_W::new(self, 11)
     }
diff --git a/esp32s3/src/usb_device/int_ena.rs b/esp32s3/src/usb_device/int_ena.rs
index c44aa82a84..7b0cfe0184 100644
--- a/esp32s3/src/usb_device/int_ena.rs
+++ b/esp32s3/src/usb_device/int_ena.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn jtag_in_flush(&mut self) -> JTAG_IN_FLUSH_W<INT_ENA_SPEC> {
         JTAG_IN_FLUSH_W::new(self, 0)
     }
     #[doc = "Bit 1 - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn sof(&mut self) -> SOF_W<INT_ENA_SPEC> {
         SOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_out_recv_pkt(&mut self) -> SERIAL_OUT_RECV_PKT_W<INT_ENA_SPEC> {
         SERIAL_OUT_RECV_PKT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_in_empty(&mut self) -> SERIAL_IN_EMPTY_W<INT_ENA_SPEC> {
         SERIAL_IN_EMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4 - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn pid_err(&mut self) -> PID_ERR_W<INT_ENA_SPEC> {
         PID_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn crc5_err(&mut self) -> CRC5_ERR_W<INT_ENA_SPEC> {
         CRC5_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn crc16_err(&mut self) -> CRC16_ERR_W<INT_ENA_SPEC> {
         CRC16_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn stuff_err(&mut self) -> STUFF_ERR_W<INT_ENA_SPEC> {
         STUFF_ERR_W::new(self, 7)
     }
     #[doc = "Bit 8 - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn in_token_rec_in_ep1(&mut self) -> IN_TOKEN_REC_IN_EP1_W<INT_ENA_SPEC> {
         IN_TOKEN_REC_IN_EP1_W::new(self, 8)
     }
     #[doc = "Bit 9 - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_bus_reset(&mut self) -> USB_BUS_RESET_W<INT_ENA_SPEC> {
         USB_BUS_RESET_W::new(self, 9)
     }
     #[doc = "Bit 10 - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep1_zero_payload(&mut self) -> OUT_EP1_ZERO_PAYLOAD_W<INT_ENA_SPEC> {
         OUT_EP1_ZERO_PAYLOAD_W::new(self, 10)
     }
     #[doc = "Bit 11 - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep2_zero_payload(&mut self) -> OUT_EP2_ZERO_PAYLOAD_W<INT_ENA_SPEC> {
         OUT_EP2_ZERO_PAYLOAD_W::new(self, 11)
     }
diff --git a/esp32s3/src/usb_device/int_raw.rs b/esp32s3/src/usb_device/int_raw.rs
index ca5a01f513..f209aa676c 100644
--- a/esp32s3/src/usb_device/int_raw.rs
+++ b/esp32s3/src/usb_device/int_raw.rs
@@ -134,73 +134,61 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
-    #[must_use]
     pub fn jtag_in_flush(&mut self) -> JTAG_IN_FLUSH_W<INT_RAW_SPEC> {
         JTAG_IN_FLUSH_W::new(self, 0)
     }
     #[doc = "Bit 1 - The raw interrupt bit turns to high level when SOF frame is received."]
     #[inline(always)]
-    #[must_use]
     pub fn sof(&mut self) -> SOF_W<INT_RAW_SPEC> {
         SOF_W::new(self, 1)
     }
     #[doc = "Bit 2 - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_out_recv_pkt(&mut self) -> SERIAL_OUT_RECV_PKT_W<INT_RAW_SPEC> {
         SERIAL_OUT_RECV_PKT_W::new(self, 2)
     }
     #[doc = "Bit 3 - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty."]
     #[inline(always)]
-    #[must_use]
     pub fn serial_in_empty(&mut self) -> SERIAL_IN_EMPTY_W<INT_RAW_SPEC> {
         SERIAL_IN_EMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4 - The raw interrupt bit turns to high level when pid error is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn pid_err(&mut self) -> PID_ERR_W<INT_RAW_SPEC> {
         PID_ERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - The raw interrupt bit turns to high level when CRC5 error is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn crc5_err(&mut self) -> CRC5_ERR_W<INT_RAW_SPEC> {
         CRC5_ERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - The raw interrupt bit turns to high level when CRC16 error is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn crc16_err(&mut self) -> CRC16_ERR_W<INT_RAW_SPEC> {
         CRC16_ERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - The raw interrupt bit turns to high level when stuff error is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn stuff_err(&mut self) -> STUFF_ERR_W<INT_RAW_SPEC> {
         STUFF_ERR_W::new(self, 7)
     }
     #[doc = "Bit 8 - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received."]
     #[inline(always)]
-    #[must_use]
     pub fn in_token_rec_in_ep1(&mut self) -> IN_TOKEN_REC_IN_EP1_W<INT_RAW_SPEC> {
         IN_TOKEN_REC_IN_EP1_W::new(self, 8)
     }
     #[doc = "Bit 9 - The raw interrupt bit turns to high level when usb bus reset is detected."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_bus_reset(&mut self) -> USB_BUS_RESET_W<INT_RAW_SPEC> {
         USB_BUS_RESET_W::new(self, 9)
     }
     #[doc = "Bit 10 - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep1_zero_payload(&mut self) -> OUT_EP1_ZERO_PAYLOAD_W<INT_RAW_SPEC> {
         OUT_EP1_ZERO_PAYLOAD_W::new(self, 10)
     }
     #[doc = "Bit 11 - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload."]
     #[inline(always)]
-    #[must_use]
     pub fn out_ep2_zero_payload(&mut self) -> OUT_EP2_ZERO_PAYLOAD_W<INT_RAW_SPEC> {
         OUT_EP2_ZERO_PAYLOAD_W::new(self, 11)
     }
diff --git a/esp32s3/src/usb_device/jfifo_st.rs b/esp32s3/src/usb_device/jfifo_st.rs
index e9f8ff45d9..bd6d30da46 100644
--- a/esp32s3/src/usb_device/jfifo_st.rs
+++ b/esp32s3/src/usb_device/jfifo_st.rs
@@ -82,13 +82,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn in_fifo_reset(&mut self) -> IN_FIFO_RESET_W<JFIFO_ST_SPEC> {
         IN_FIFO_RESET_W::new(self, 8)
     }
     #[doc = "Bit 9 - Write 1 to reset JTAG out fifo."]
     #[inline(always)]
-    #[must_use]
     pub fn out_fifo_reset(&mut self) -> OUT_FIFO_RESET_W<JFIFO_ST_SPEC> {
         OUT_FIFO_RESET_W::new(self, 9)
     }
diff --git a/esp32s3/src/usb_device/mem_conf.rs b/esp32s3/src/usb_device/mem_conf.rs
index 215c196888..ca51b75f61 100644
--- a/esp32s3/src/usb_device/mem_conf.rs
+++ b/esp32s3/src/usb_device/mem_conf.rs
@@ -34,13 +34,11 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_mem_pd(&mut self) -> USB_MEM_PD_W<MEM_CONF_SPEC> {
         USB_MEM_PD_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Force clock on for usb memory."]
     #[inline(always)]
-    #[must_use]
     pub fn usb_mem_clk_en(&mut self) -> USB_MEM_CLK_EN_W<MEM_CONF_SPEC> {
         USB_MEM_CLK_EN_W::new(self, 1)
     }
diff --git a/esp32s3/src/usb_device/misc_conf.rs b/esp32s3/src/usb_device/misc_conf.rs
index b3a8aa2992..a2cca44672 100644
--- a/esp32s3/src/usb_device/misc_conf.rs
+++ b/esp32s3/src/usb_device/misc_conf.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
         CLK_EN_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb_device/test.rs b/esp32s3/src/usb_device/test.rs
index 071d92dfa1..051397a2ce 100644
--- a/esp32s3/src/usb_device/test.rs
+++ b/esp32s3/src/usb_device/test.rs
@@ -78,25 +78,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<TEST_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - USB pad oen in test"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_oe(&mut self) -> USB_OE_W<TEST_SPEC> {
         USB_OE_W::new(self, 1)
     }
     #[doc = "Bit 2 - USB D+ tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dp(&mut self) -> TX_DP_W<TEST_SPEC> {
         TX_DP_W::new(self, 2)
     }
     #[doc = "Bit 3 - USB D- tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dm(&mut self) -> TX_DM_W<TEST_SPEC> {
         TX_DM_W::new(self, 3)
     }
diff --git a/esp32s3/src/usb_wrap/date.rs b/esp32s3/src/usb_wrap/date.rs
index be3aa8c786..cfa07ba774 100644
--- a/esp32s3/src/usb_wrap/date.rs
+++ b/esp32s3/src/usb_wrap/date.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Date register"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_wrap_date(&mut self) -> USB_WRAP_DATE_W<DATE_SPEC> {
         USB_WRAP_DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/usb_wrap/otg_conf.rs b/esp32s3/src/usb_wrap/otg_conf.rs
index e0c91f9dd3..c438ca8f25 100644
--- a/esp32s3/src/usb_wrap/otg_conf.rs
+++ b/esp32s3/src/usb_wrap/otg_conf.rs
@@ -234,133 +234,111 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
     #[inline(always)]
-    #[must_use]
     pub fn srp_sessend_override(&mut self) -> SRP_SESSEND_OVERRIDE_W<OTG_CONF_SPEC> {
         SRP_SESSEND_OVERRIDE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Software over-ride value of srp session end signal."]
     #[inline(always)]
-    #[must_use]
     pub fn srp_sessend_value(&mut self) -> SRP_SESSEND_VALUE_W<OTG_CONF_SPEC> {
         SRP_SESSEND_VALUE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
     #[inline(always)]
-    #[must_use]
     pub fn phy_sel(&mut self) -> PHY_SEL_W<OTG_CONF_SPEC> {
         PHY_SEL_W::new(self, 2)
     }
     #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
     #[inline(always)]
-    #[must_use]
     pub fn dfifo_force_pd(&mut self) -> DFIFO_FORCE_PD_W<OTG_CONF_SPEC> {
         DFIFO_FORCE_PD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
     #[inline(always)]
-    #[must_use]
     pub fn dbnce_fltr_bypass(&mut self) -> DBNCE_FLTR_BYPASS_W<OTG_CONF_SPEC> {
         DBNCE_FLTR_BYPASS_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W<OTG_CONF_SPEC> {
         EXCHG_PINS_OVERRIDE_W::new(self, 5)
     }
     #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
     #[inline(always)]
-    #[must_use]
     pub fn exchg_pins(&mut self) -> EXCHG_PINS_W<OTG_CONF_SPEC> {
         EXCHG_PINS_W::new(self, 6)
     }
     #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefh(&mut self) -> VREFH_W<OTG_CONF_SPEC> {
         VREFH_W::new(self, 7)
     }
     #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
     #[inline(always)]
-    #[must_use]
     pub fn vrefl(&mut self) -> VREFL_W<OTG_CONF_SPEC> {
         VREFL_W::new(self, 9)
     }
     #[doc = "Bit 11 - Enable software controlle input threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn vref_override(&mut self) -> VREF_OVERRIDE_W<OTG_CONF_SPEC> {
         VREF_OVERRIDE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W<OTG_CONF_SPEC> {
         PAD_PULL_OVERRIDE_W::new(self, 12)
     }
     #[doc = "Bit 13 - Controlle USB D+ pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup(&mut self) -> DP_PULLUP_W<OTG_CONF_SPEC> {
         DP_PULLUP_W::new(self, 13)
     }
     #[doc = "Bit 14 - Controlle USB D+ pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W<OTG_CONF_SPEC> {
         DP_PULLDOWN_W::new(self, 14)
     }
     #[doc = "Bit 15 - Controlle USB D+ pullup"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup(&mut self) -> DM_PULLUP_W<OTG_CONF_SPEC> {
         DM_PULLUP_W::new(self, 15)
     }
     #[doc = "Bit 16 - Controlle USB D+ pulldown"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W<OTG_CONF_SPEC> {
         DM_PULLDOWN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
     #[inline(always)]
-    #[must_use]
     pub fn pullup_value(&mut self) -> PULLUP_VALUE_W<OTG_CONF_SPEC> {
         PULLUP_VALUE_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enable USB pad function"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<OTG_CONF_SPEC> {
         USB_PAD_ENABLE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Force ahb clock always on"]
     #[inline(always)]
-    #[must_use]
     pub fn ahb_clk_force_on(&mut self) -> AHB_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
         AHB_CLK_FORCE_ON_W::new(self, 19)
     }
     #[doc = "Bit 20 - Force phy clock always on"]
     #[inline(always)]
-    #[must_use]
     pub fn phy_clk_force_on(&mut self) -> PHY_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
         PHY_CLK_FORCE_ON_W::new(self, 20)
     }
     #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
     #[inline(always)]
-    #[must_use]
     pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W<OTG_CONF_SPEC> {
         PHY_TX_EDGE_SEL_W::new(self, 21)
     }
     #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
     #[inline(always)]
-    #[must_use]
     pub fn dfifo_force_pu(&mut self) -> DFIFO_FORCE_PU_W<OTG_CONF_SPEC> {
         DFIFO_FORCE_PU_W::new(self, 22)
     }
     #[doc = "Bit 31 - Disable auto clock gating of CSR registers"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<OTG_CONF_SPEC> {
         CLK_EN_W::new(self, 31)
     }
diff --git a/esp32s3/src/usb_wrap/test_conf.rs b/esp32s3/src/usb_wrap/test_conf.rs
index 914f0057a7..fafff78a2a 100644
--- a/esp32s3/src/usb_wrap/test_conf.rs
+++ b/esp32s3/src/usb_wrap/test_conf.rs
@@ -78,25 +78,21 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
-    #[must_use]
     pub fn test_enable(&mut self) -> TEST_ENABLE_W<TEST_CONF_SPEC> {
         TEST_ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - USB pad oen in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_usb_oe(&mut self) -> TEST_USB_OE_W<TEST_CONF_SPEC> {
         TEST_USB_OE_W::new(self, 1)
     }
     #[doc = "Bit 2 - USB D+ tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_tx_dp(&mut self) -> TEST_TX_DP_W<TEST_CONF_SPEC> {
         TEST_TX_DP_W::new(self, 2)
     }
     #[doc = "Bit 3 - USB D- tx value in test"]
     #[inline(always)]
-    #[must_use]
     pub fn test_tx_dm(&mut self) -> TEST_TX_DM_W<TEST_CONF_SPEC> {
         TEST_TX_DM_W::new(self, 3)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_10_addr.rs b/esp32s3/src/wcl/core_0_entry_10_addr.rs
index 14e9d28ea3..0bc0a62e45 100644
--- a/esp32s3/src/wcl/core_0_entry_10_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_10_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 10 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_10_addr(&mut self) -> CORE_0_ENTRY_10_ADDR_W<CORE_0_ENTRY_10_ADDR_SPEC> {
         CORE_0_ENTRY_10_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_11_addr.rs b/esp32s3/src/wcl/core_0_entry_11_addr.rs
index 0717576f41..fb746c3ddc 100644
--- a/esp32s3/src/wcl/core_0_entry_11_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_11_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 11 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_11_addr(&mut self) -> CORE_0_ENTRY_11_ADDR_W<CORE_0_ENTRY_11_ADDR_SPEC> {
         CORE_0_ENTRY_11_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_12_addr.rs b/esp32s3/src/wcl/core_0_entry_12_addr.rs
index df31350b0c..6e491ccdb0 100644
--- a/esp32s3/src/wcl/core_0_entry_12_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_12_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 12 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_12_addr(&mut self) -> CORE_0_ENTRY_12_ADDR_W<CORE_0_ENTRY_12_ADDR_SPEC> {
         CORE_0_ENTRY_12_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_13_addr.rs b/esp32s3/src/wcl/core_0_entry_13_addr.rs
index a0604bb41f..3aec82c593 100644
--- a/esp32s3/src/wcl/core_0_entry_13_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_13_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 13 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_13_addr(&mut self) -> CORE_0_ENTRY_13_ADDR_W<CORE_0_ENTRY_13_ADDR_SPEC> {
         CORE_0_ENTRY_13_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_1_addr.rs b/esp32s3/src/wcl/core_0_entry_1_addr.rs
index d363a450d7..e433c14ba2 100644
--- a/esp32s3/src/wcl/core_0_entry_1_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 1 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_1_addr(&mut self) -> CORE_0_ENTRY_1_ADDR_W<CORE_0_ENTRY_1_ADDR_SPEC> {
         CORE_0_ENTRY_1_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_2_addr.rs b/esp32s3/src/wcl/core_0_entry_2_addr.rs
index 555ebf5995..6e81c45a8e 100644
--- a/esp32s3/src/wcl/core_0_entry_2_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 2 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_2_addr(&mut self) -> CORE_0_ENTRY_2_ADDR_W<CORE_0_ENTRY_2_ADDR_SPEC> {
         CORE_0_ENTRY_2_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_3_addr.rs b/esp32s3/src/wcl/core_0_entry_3_addr.rs
index ea031dc1ec..4148a7ba50 100644
--- a/esp32s3/src/wcl/core_0_entry_3_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 3 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_3_addr(&mut self) -> CORE_0_ENTRY_3_ADDR_W<CORE_0_ENTRY_3_ADDR_SPEC> {
         CORE_0_ENTRY_3_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_4_addr.rs b/esp32s3/src/wcl/core_0_entry_4_addr.rs
index c0acbb3efe..0aaa8a5857 100644
--- a/esp32s3/src/wcl/core_0_entry_4_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_4_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 4 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_4_addr(&mut self) -> CORE_0_ENTRY_4_ADDR_W<CORE_0_ENTRY_4_ADDR_SPEC> {
         CORE_0_ENTRY_4_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_5_addr.rs b/esp32s3/src/wcl/core_0_entry_5_addr.rs
index 8ee8192b4e..c1d6b81a5a 100644
--- a/esp32s3/src/wcl/core_0_entry_5_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_5_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 5 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_5_addr(&mut self) -> CORE_0_ENTRY_5_ADDR_W<CORE_0_ENTRY_5_ADDR_SPEC> {
         CORE_0_ENTRY_5_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_6_addr.rs b/esp32s3/src/wcl/core_0_entry_6_addr.rs
index c417758ce8..0dd33460f2 100644
--- a/esp32s3/src/wcl/core_0_entry_6_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_6_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 6 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_6_addr(&mut self) -> CORE_0_ENTRY_6_ADDR_W<CORE_0_ENTRY_6_ADDR_SPEC> {
         CORE_0_ENTRY_6_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_7_addr.rs b/esp32s3/src/wcl/core_0_entry_7_addr.rs
index 0b33a3765d..b06ea9ef9f 100644
--- a/esp32s3/src/wcl/core_0_entry_7_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_7_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 7 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_7_addr(&mut self) -> CORE_0_ENTRY_7_ADDR_W<CORE_0_ENTRY_7_ADDR_SPEC> {
         CORE_0_ENTRY_7_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_8_addr.rs b/esp32s3/src/wcl/core_0_entry_8_addr.rs
index 9efe0490e4..8e6ac5f83b 100644
--- a/esp32s3/src/wcl/core_0_entry_8_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_8_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 8 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_8_addr(&mut self) -> CORE_0_ENTRY_8_ADDR_W<CORE_0_ENTRY_8_ADDR_SPEC> {
         CORE_0_ENTRY_8_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_9_addr.rs b/esp32s3/src/wcl/core_0_entry_9_addr.rs
index 3ec6d66bb7..b334f10489 100644
--- a/esp32s3/src/wcl/core_0_entry_9_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_9_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 9 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_9_addr(&mut self) -> CORE_0_ENTRY_9_ADDR_W<CORE_0_ENTRY_9_ADDR_SPEC> {
         CORE_0_ENTRY_9_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_entry_check.rs b/esp32s3/src/wcl/core_0_entry_check.rs
index 496225859d..9d78758b04 100644
--- a/esp32s3/src/wcl/core_0_entry_check.rs
+++ b/esp32s3/src/wcl/core_0_entry_check.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:13 - This filed is used to enable entry address check"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_entry_check(&mut self) -> CORE_0_ENTRY_CHECK_W<CORE_0_ENTRY_CHECK_SPEC> {
         CORE_0_ENTRY_CHECK_W::new(self, 1)
     }
diff --git a/esp32s3/src/wcl/core_0_message_addr.rs b/esp32s3/src/wcl/core_0_message_addr.rs
index 76295368bd..59a748a22b 100644
--- a/esp32s3/src/wcl/core_0_message_addr.rs
+++ b/esp32s3/src/wcl/core_0_message_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This field is used to set address that need to write when enter WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_message_addr(&mut self) -> CORE_0_MESSAGE_ADDR_W<CORE_0_MESSAGE_ADDR_SPEC> {
         CORE_0_MESSAGE_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_message_max.rs b/esp32s3/src/wcl/core_0_message_max.rs
index 32d52f1515..a5ae4c6d82 100644
--- a/esp32s3/src/wcl/core_0_message_max.rs
+++ b/esp32s3/src/wcl/core_0_message_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - This filed is used to set the max value of clear write_buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_message_max(&mut self) -> CORE_0_MESSAGE_MAX_W<CORE_0_MESSAGE_MAX_SPEC> {
         CORE_0_MESSAGE_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_nmi_mask.rs b/esp32s3/src/wcl/core_0_nmi_mask.rs
index 043c7a9be5..d4778e5e44 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - this bit is used to mask NMI interrupt,it can directly mask NMI interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_nmi_mask(&mut self) -> CORE_0_NMI_MASK_W<CORE_0_NMI_MASK_SPEC> {
         CORE_0_NMI_MASK_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_cancle.rs b/esp32s3/src/wcl/core_0_nmi_mask_cancle.rs
index 5c678f3ebf..30cd98540d 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_cancle.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_cancle.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_CANCLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to cancel NMI mask disable function."]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_nmi_mask_cancel(
         &mut self,
     ) -> CORE_0_NMI_MASK_CANCEL_W<CORE_0_NMI_MASK_CANCLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_disable.rs b/esp32s3/src/wcl/core_0_nmi_mask_disable.rs
index 09c82f4f55..c5a4bf8e56 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_disable.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_disable.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_DISABLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_nmi_mask_disable(
         &mut self,
     ) -> CORE_0_NMI_MASK_DISABLE_W<CORE_0_NMI_MASK_DISABLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_enable.rs b/esp32s3/src/wcl/core_0_nmi_mask_enable.rs
index b6361be346..13f1d0e10f 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_enable.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_enable.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_ENABLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_nmi_mask_enable(
         &mut self,
     ) -> CORE_0_NMI_MASK_ENABLE_W<CORE_0_NMI_MASK_ENABLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs b/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
index a9e60ca430..bba542687f 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_nmi_mask_trigger_addr(
         &mut self,
     ) -> CORE_0_NMI_MASK_TRIGGER_ADDR_W<CORE_0_NMI_MASK_TRIGGER_ADDR_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_statustable1.rs b/esp32s3/src/wcl/core_0_statustable1.rs
index b78a12a739..df88cdf3b6 100644
--- a/esp32s3/src/wcl/core_0_statustable1.rs
+++ b/esp32s3/src/wcl/core_0_statustable1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_1(&mut self) -> CORE_0_FROM_WORLD_1_W<CORE_0_STATUSTABLE1_SPEC> {
         CORE_0_FROM_WORLD_1_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_1(&mut self) -> CORE_0_FROM_ENTRY_1_W<CORE_0_STATUSTABLE1_SPEC> {
         CORE_0_FROM_ENTRY_1_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_1(&mut self) -> CORE_0_CURRENT_1_W<CORE_0_STATUSTABLE1_SPEC> {
         CORE_0_CURRENT_1_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable10.rs b/esp32s3/src/wcl/core_0_statustable10.rs
index c4d1296025..53485412de 100644
--- a/esp32s3/src/wcl/core_0_statustable10.rs
+++ b/esp32s3/src/wcl/core_0_statustable10.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_10(&mut self) -> CORE_0_FROM_WORLD_10_W<CORE_0_STATUSTABLE10_SPEC> {
         CORE_0_FROM_WORLD_10_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_10(&mut self) -> CORE_0_FROM_ENTRY_10_W<CORE_0_STATUSTABLE10_SPEC> {
         CORE_0_FROM_ENTRY_10_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_10(&mut self) -> CORE_0_CURRENT_10_W<CORE_0_STATUSTABLE10_SPEC> {
         CORE_0_CURRENT_10_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable11.rs b/esp32s3/src/wcl/core_0_statustable11.rs
index 2e95d1e0f9..6e578f5230 100644
--- a/esp32s3/src/wcl/core_0_statustable11.rs
+++ b/esp32s3/src/wcl/core_0_statustable11.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_11(&mut self) -> CORE_0_FROM_WORLD_11_W<CORE_0_STATUSTABLE11_SPEC> {
         CORE_0_FROM_WORLD_11_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_11(&mut self) -> CORE_0_FROM_ENTRY_11_W<CORE_0_STATUSTABLE11_SPEC> {
         CORE_0_FROM_ENTRY_11_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_11(&mut self) -> CORE_0_CURRENT_11_W<CORE_0_STATUSTABLE11_SPEC> {
         CORE_0_CURRENT_11_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable12.rs b/esp32s3/src/wcl/core_0_statustable12.rs
index 6cdbaf5717..2aa8fb06c1 100644
--- a/esp32s3/src/wcl/core_0_statustable12.rs
+++ b/esp32s3/src/wcl/core_0_statustable12.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_12(&mut self) -> CORE_0_FROM_WORLD_12_W<CORE_0_STATUSTABLE12_SPEC> {
         CORE_0_FROM_WORLD_12_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_12(&mut self) -> CORE_0_FROM_ENTRY_12_W<CORE_0_STATUSTABLE12_SPEC> {
         CORE_0_FROM_ENTRY_12_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_12(&mut self) -> CORE_0_CURRENT_12_W<CORE_0_STATUSTABLE12_SPEC> {
         CORE_0_CURRENT_12_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable13.rs b/esp32s3/src/wcl/core_0_statustable13.rs
index 3e117ebcdf..e4a2d75513 100644
--- a/esp32s3/src/wcl/core_0_statustable13.rs
+++ b/esp32s3/src/wcl/core_0_statustable13.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_13(&mut self) -> CORE_0_FROM_WORLD_13_W<CORE_0_STATUSTABLE13_SPEC> {
         CORE_0_FROM_WORLD_13_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_13(&mut self) -> CORE_0_FROM_ENTRY_13_W<CORE_0_STATUSTABLE13_SPEC> {
         CORE_0_FROM_ENTRY_13_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_13(&mut self) -> CORE_0_CURRENT_13_W<CORE_0_STATUSTABLE13_SPEC> {
         CORE_0_CURRENT_13_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable2.rs b/esp32s3/src/wcl/core_0_statustable2.rs
index aefcf1e647..e8993ae75f 100644
--- a/esp32s3/src/wcl/core_0_statustable2.rs
+++ b/esp32s3/src/wcl/core_0_statustable2.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_2(&mut self) -> CORE_0_FROM_WORLD_2_W<CORE_0_STATUSTABLE2_SPEC> {
         CORE_0_FROM_WORLD_2_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_2(&mut self) -> CORE_0_FROM_ENTRY_2_W<CORE_0_STATUSTABLE2_SPEC> {
         CORE_0_FROM_ENTRY_2_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_2(&mut self) -> CORE_0_CURRENT_2_W<CORE_0_STATUSTABLE2_SPEC> {
         CORE_0_CURRENT_2_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable3.rs b/esp32s3/src/wcl/core_0_statustable3.rs
index 01f4c1e20f..6945d2a704 100644
--- a/esp32s3/src/wcl/core_0_statustable3.rs
+++ b/esp32s3/src/wcl/core_0_statustable3.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_3(&mut self) -> CORE_0_FROM_WORLD_3_W<CORE_0_STATUSTABLE3_SPEC> {
         CORE_0_FROM_WORLD_3_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_3(&mut self) -> CORE_0_FROM_ENTRY_3_W<CORE_0_STATUSTABLE3_SPEC> {
         CORE_0_FROM_ENTRY_3_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_3(&mut self) -> CORE_0_CURRENT_3_W<CORE_0_STATUSTABLE3_SPEC> {
         CORE_0_CURRENT_3_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable4.rs b/esp32s3/src/wcl/core_0_statustable4.rs
index 7588f05db0..7640c5c837 100644
--- a/esp32s3/src/wcl/core_0_statustable4.rs
+++ b/esp32s3/src/wcl/core_0_statustable4.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_4(&mut self) -> CORE_0_FROM_WORLD_4_W<CORE_0_STATUSTABLE4_SPEC> {
         CORE_0_FROM_WORLD_4_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_4(&mut self) -> CORE_0_FROM_ENTRY_4_W<CORE_0_STATUSTABLE4_SPEC> {
         CORE_0_FROM_ENTRY_4_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_4(&mut self) -> CORE_0_CURRENT_4_W<CORE_0_STATUSTABLE4_SPEC> {
         CORE_0_CURRENT_4_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable5.rs b/esp32s3/src/wcl/core_0_statustable5.rs
index 9ca8062d83..d422bae9bd 100644
--- a/esp32s3/src/wcl/core_0_statustable5.rs
+++ b/esp32s3/src/wcl/core_0_statustable5.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_5(&mut self) -> CORE_0_FROM_WORLD_5_W<CORE_0_STATUSTABLE5_SPEC> {
         CORE_0_FROM_WORLD_5_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_5(&mut self) -> CORE_0_FROM_ENTRY_5_W<CORE_0_STATUSTABLE5_SPEC> {
         CORE_0_FROM_ENTRY_5_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_5(&mut self) -> CORE_0_CURRENT_5_W<CORE_0_STATUSTABLE5_SPEC> {
         CORE_0_CURRENT_5_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable6.rs b/esp32s3/src/wcl/core_0_statustable6.rs
index 51436753bd..0b2f6497a6 100644
--- a/esp32s3/src/wcl/core_0_statustable6.rs
+++ b/esp32s3/src/wcl/core_0_statustable6.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_6(&mut self) -> CORE_0_FROM_WORLD_6_W<CORE_0_STATUSTABLE6_SPEC> {
         CORE_0_FROM_WORLD_6_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_6(&mut self) -> CORE_0_FROM_ENTRY_6_W<CORE_0_STATUSTABLE6_SPEC> {
         CORE_0_FROM_ENTRY_6_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_6(&mut self) -> CORE_0_CURRENT_6_W<CORE_0_STATUSTABLE6_SPEC> {
         CORE_0_CURRENT_6_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable7.rs b/esp32s3/src/wcl/core_0_statustable7.rs
index 4d2b1a57f9..2fe5ed753e 100644
--- a/esp32s3/src/wcl/core_0_statustable7.rs
+++ b/esp32s3/src/wcl/core_0_statustable7.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_7(&mut self) -> CORE_0_FROM_WORLD_7_W<CORE_0_STATUSTABLE7_SPEC> {
         CORE_0_FROM_WORLD_7_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_7(&mut self) -> CORE_0_FROM_ENTRY_7_W<CORE_0_STATUSTABLE7_SPEC> {
         CORE_0_FROM_ENTRY_7_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_7(&mut self) -> CORE_0_CURRENT_7_W<CORE_0_STATUSTABLE7_SPEC> {
         CORE_0_CURRENT_7_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable8.rs b/esp32s3/src/wcl/core_0_statustable8.rs
index cd3228a500..7e2b9b8691 100644
--- a/esp32s3/src/wcl/core_0_statustable8.rs
+++ b/esp32s3/src/wcl/core_0_statustable8.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_8(&mut self) -> CORE_0_FROM_WORLD_8_W<CORE_0_STATUSTABLE8_SPEC> {
         CORE_0_FROM_WORLD_8_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_8(&mut self) -> CORE_0_FROM_ENTRY_8_W<CORE_0_STATUSTABLE8_SPEC> {
         CORE_0_FROM_ENTRY_8_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_8(&mut self) -> CORE_0_CURRENT_8_W<CORE_0_STATUSTABLE8_SPEC> {
         CORE_0_CURRENT_8_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable9.rs b/esp32s3/src/wcl/core_0_statustable9.rs
index 86e8314a7c..8fc18bc233 100644
--- a/esp32s3/src/wcl/core_0_statustable9.rs
+++ b/esp32s3/src/wcl/core_0_statustable9.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_world_9(&mut self) -> CORE_0_FROM_WORLD_9_W<CORE_0_STATUSTABLE9_SPEC> {
         CORE_0_FROM_WORLD_9_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_from_entry_9(&mut self) -> CORE_0_FROM_ENTRY_9_W<CORE_0_STATUSTABLE9_SPEC> {
         CORE_0_FROM_ENTRY_9_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_current_9(&mut self) -> CORE_0_CURRENT_9_W<CORE_0_STATUSTABLE9_SPEC> {
         CORE_0_CURRENT_9_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_0_statustable_current.rs b/esp32s3/src/wcl/core_0_statustable_current.rs
index 2518c2af22..4ec790e74a 100644
--- a/esp32s3/src/wcl/core_0_statustable_current.rs
+++ b/esp32s3/src/wcl/core_0_statustable_current.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:13 - This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_statustable_current(
         &mut self,
     ) -> CORE_0_STATUSTABLE_CURRENT_W<CORE_0_STATUSTABLE_CURRENT_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_world_cancel.rs b/esp32s3/src/wcl/core_0_world_cancel.rs
index e5e2000463..1cf2625777 100644
--- a/esp32s3/src/wcl/core_0_world_cancel.rs
+++ b/esp32s3/src/wcl/core_0_world_cancel.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_CANCEL_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_world_cancel(&mut self) -> CORE_0_WORLD_CANCEL_W<CORE_0_WORLD_CANCEL_SPEC> {
         CORE_0_WORLD_CANCEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_world_dram0_pif.rs b/esp32s3/src/wcl/core_0_world_dram0_pif.rs
index 22d955bd62..895de22892 100644
--- a/esp32s3/src/wcl/core_0_world_dram0_pif.rs
+++ b/esp32s3/src/wcl/core_0_world_dram0_pif.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Dram0 bus and PIF bus"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_world_dram0_pif(
         &mut self,
     ) -> CORE_0_WORLD_DRAM0_PIF_W<CORE_0_WORLD_DRAM0_PIF_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_world_iram0.rs b/esp32s3/src/wcl/core_0_world_iram0.rs
index 7ef401788e..3c24640c3f 100644
--- a/esp32s3/src/wcl/core_0_world_iram0.rs
+++ b/esp32s3/src/wcl/core_0_world_iram0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Iram0 bus"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_world_iram0(&mut self) -> CORE_0_WORLD_IRAM0_W<CORE_0_WORLD_IRAM0_SPEC> {
         CORE_0_WORLD_IRAM0_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_world_prepare.rs b/esp32s3/src/wcl/core_0_world_prepare.rs
index 7d4bb9a8ef..7bfa7c4b41 100644
--- a/esp32s3/src/wcl/core_0_world_prepare.rs
+++ b/esp32s3/src/wcl/core_0_world_prepare.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_world_prepare(&mut self) -> CORE_0_WORLD_PREPARE_W<CORE_0_WORLD_PREPARE_SPEC> {
         CORE_0_WORLD_PREPARE_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_0_world_trigger_addr.rs b/esp32s3/src/wcl/core_0_world_trigger_addr.rs
index 4b748d6e10..d91093ea2b 100644
--- a/esp32s3/src/wcl/core_0_world_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_0_world_trigger_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_world_trigger_addr(
         &mut self,
     ) -> CORE_0_WORLD_TRIGGER_ADDR_W<CORE_0_WORLD_TRIGGER_ADDR_SPEC> {
diff --git a/esp32s3/src/wcl/core_0_world_update.rs b/esp32s3/src/wcl/core_0_world_update.rs
index 6839dd97cd..b1f5d29224 100644
--- a/esp32s3/src/wcl/core_0_world_update.rs
+++ b/esp32s3/src/wcl/core_0_world_update.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_UPDATE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_0_update(&mut self) -> CORE_0_UPDATE_W<CORE_0_WORLD_UPDATE_SPEC> {
         CORE_0_UPDATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_10_addr.rs b/esp32s3/src/wcl/core_1_entry_10_addr.rs
index 15531da485..63cdbea2e0 100644
--- a/esp32s3/src/wcl/core_1_entry_10_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_10_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 10 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_10_addr(&mut self) -> CORE_1_ENTRY_10_ADDR_W<CORE_1_ENTRY_10_ADDR_SPEC> {
         CORE_1_ENTRY_10_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_11_addr.rs b/esp32s3/src/wcl/core_1_entry_11_addr.rs
index a44bb2f238..ebdc3f2bd2 100644
--- a/esp32s3/src/wcl/core_1_entry_11_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_11_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 11 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_11_addr(&mut self) -> CORE_1_ENTRY_11_ADDR_W<CORE_1_ENTRY_11_ADDR_SPEC> {
         CORE_1_ENTRY_11_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_12_addr.rs b/esp32s3/src/wcl/core_1_entry_12_addr.rs
index 8f09531acf..2aa392b704 100644
--- a/esp32s3/src/wcl/core_1_entry_12_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_12_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 12 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_12_addr(&mut self) -> CORE_1_ENTRY_12_ADDR_W<CORE_1_ENTRY_12_ADDR_SPEC> {
         CORE_1_ENTRY_12_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_13_addr.rs b/esp32s3/src/wcl/core_1_entry_13_addr.rs
index 0b5f871c64..d229187540 100644
--- a/esp32s3/src/wcl/core_1_entry_13_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_13_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 13 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_13_addr(&mut self) -> CORE_1_ENTRY_13_ADDR_W<CORE_1_ENTRY_13_ADDR_SPEC> {
         CORE_1_ENTRY_13_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_1_addr.rs b/esp32s3/src/wcl/core_1_entry_1_addr.rs
index 2ed8bb514d..9e46f65fe3 100644
--- a/esp32s3/src/wcl/core_1_entry_1_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_1_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 1 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_1_addr(&mut self) -> CORE_1_ENTRY_1_ADDR_W<CORE_1_ENTRY_1_ADDR_SPEC> {
         CORE_1_ENTRY_1_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_2_addr.rs b/esp32s3/src/wcl/core_1_entry_2_addr.rs
index 98f8bef47b..e14c5e1ffa 100644
--- a/esp32s3/src/wcl/core_1_entry_2_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_2_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 2 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_2_addr(&mut self) -> CORE_1_ENTRY_2_ADDR_W<CORE_1_ENTRY_2_ADDR_SPEC> {
         CORE_1_ENTRY_2_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_3_addr.rs b/esp32s3/src/wcl/core_1_entry_3_addr.rs
index 45bf78b682..5d58268d90 100644
--- a/esp32s3/src/wcl/core_1_entry_3_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_3_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 3 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_3_addr(&mut self) -> CORE_1_ENTRY_3_ADDR_W<CORE_1_ENTRY_3_ADDR_SPEC> {
         CORE_1_ENTRY_3_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_4_addr.rs b/esp32s3/src/wcl/core_1_entry_4_addr.rs
index 4dfe43e65d..2792328d5f 100644
--- a/esp32s3/src/wcl/core_1_entry_4_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_4_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 4 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_4_addr(&mut self) -> CORE_1_ENTRY_4_ADDR_W<CORE_1_ENTRY_4_ADDR_SPEC> {
         CORE_1_ENTRY_4_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_5_addr.rs b/esp32s3/src/wcl/core_1_entry_5_addr.rs
index 90bc526548..00c11be28e 100644
--- a/esp32s3/src/wcl/core_1_entry_5_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_5_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 5 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_5_addr(&mut self) -> CORE_1_ENTRY_5_ADDR_W<CORE_1_ENTRY_5_ADDR_SPEC> {
         CORE_1_ENTRY_5_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_6_addr.rs b/esp32s3/src/wcl/core_1_entry_6_addr.rs
index 922c8a0c40..bcb12ad333 100644
--- a/esp32s3/src/wcl/core_1_entry_6_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_6_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 6 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_6_addr(&mut self) -> CORE_1_ENTRY_6_ADDR_W<CORE_1_ENTRY_6_ADDR_SPEC> {
         CORE_1_ENTRY_6_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_7_addr.rs b/esp32s3/src/wcl/core_1_entry_7_addr.rs
index 102f677df3..3b2cb4c50e 100644
--- a/esp32s3/src/wcl/core_1_entry_7_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_7_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 7 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_7_addr(&mut self) -> CORE_1_ENTRY_7_ADDR_W<CORE_1_ENTRY_7_ADDR_SPEC> {
         CORE_1_ENTRY_7_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_8_addr.rs b/esp32s3/src/wcl/core_1_entry_8_addr.rs
index 50c6775250..eaae97dceb 100644
--- a/esp32s3/src/wcl/core_1_entry_8_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_8_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 8 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_8_addr(&mut self) -> CORE_1_ENTRY_8_ADDR_W<CORE_1_ENTRY_8_ADDR_SPEC> {
         CORE_1_ENTRY_8_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_9_addr.rs b/esp32s3/src/wcl/core_1_entry_9_addr.rs
index 90d9721d50..408cf3a528 100644
--- a/esp32s3/src/wcl/core_1_entry_9_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_9_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 9 address from WORLD1 to WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_9_addr(&mut self) -> CORE_1_ENTRY_9_ADDR_W<CORE_1_ENTRY_9_ADDR_SPEC> {
         CORE_1_ENTRY_9_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_entry_check.rs b/esp32s3/src/wcl/core_1_entry_check.rs
index add6ee9875..8d8900f0e9 100644
--- a/esp32s3/src/wcl/core_1_entry_check.rs
+++ b/esp32s3/src/wcl/core_1_entry_check.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:13 - This filed is used to enable entry address check"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_entry_check(&mut self) -> CORE_1_ENTRY_CHECK_W<CORE_1_ENTRY_CHECK_SPEC> {
         CORE_1_ENTRY_CHECK_W::new(self, 1)
     }
diff --git a/esp32s3/src/wcl/core_1_message_addr.rs b/esp32s3/src/wcl/core_1_message_addr.rs
index 4b595e7eea..d6b40fdb87 100644
--- a/esp32s3/src/wcl/core_1_message_addr.rs
+++ b/esp32s3/src/wcl/core_1_message_addr.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This field is used to set address that need to write when enter WORLD0"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_message_addr(&mut self) -> CORE_1_MESSAGE_ADDR_W<CORE_1_MESSAGE_ADDR_SPEC> {
         CORE_1_MESSAGE_ADDR_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_message_max.rs b/esp32s3/src/wcl/core_1_message_max.rs
index 52e7882334..61ba79aa6b 100644
--- a/esp32s3/src/wcl/core_1_message_max.rs
+++ b/esp32s3/src/wcl/core_1_message_max.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:3 - This filed is used to set the max value of clear write_buffer"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_message_max(&mut self) -> CORE_1_MESSAGE_MAX_W<CORE_1_MESSAGE_MAX_SPEC> {
         CORE_1_MESSAGE_MAX_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_nmi_mask.rs b/esp32s3/src/wcl/core_1_nmi_mask.rs
index 484b6639df..7b1c51cc0d 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - this bit is used to mask NMI interrupt,it can directly mask NMI interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_nmi_mask(&mut self) -> CORE_1_NMI_MASK_W<CORE_1_NMI_MASK_SPEC> {
         CORE_1_NMI_MASK_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_cancle.rs b/esp32s3/src/wcl/core_1_nmi_mask_cancle.rs
index e5ef3e50fc..ddc8e50da1 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_cancle.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_cancle.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_CANCLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to cancel NMI mask disable function."]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_nmi_mask_cancel(
         &mut self,
     ) -> CORE_1_NMI_MASK_CANCEL_W<CORE_1_NMI_MASK_CANCLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_disable.rs b/esp32s3/src/wcl/core_1_nmi_mask_disable.rs
index 4f63cd565d..d35b019ffd 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_disable.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_disable.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_DISABLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_nmi_mask_disable(
         &mut self,
     ) -> CORE_1_NMI_MASK_DISABLE_W<CORE_1_NMI_MASK_DISABLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_enable.rs b/esp32s3/src/wcl/core_1_nmi_mask_enable.rs
index 40d68b2c4c..0a7330a0c7 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_enable.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_enable.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_ENABLE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_nmi_mask_enable(
         &mut self,
     ) -> CORE_1_NMI_MASK_ENABLE_W<CORE_1_NMI_MASK_ENABLE_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs b/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
index 2608bc5205..9d9c6a40c0 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - this field to used to set trigger address"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_nmi_mask_trigger_addr(
         &mut self,
     ) -> CORE_1_NMI_MASK_TRIGGER_ADDR_W<CORE_1_NMI_MASK_TRIGGER_ADDR_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_statustable1.rs b/esp32s3/src/wcl/core_1_statustable1.rs
index bc5cdd0859..733fada8d2 100644
--- a/esp32s3/src/wcl/core_1_statustable1.rs
+++ b/esp32s3/src/wcl/core_1_statustable1.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_1(&mut self) -> CORE_1_FROM_WORLD_1_W<CORE_1_STATUSTABLE1_SPEC> {
         CORE_1_FROM_WORLD_1_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_1(&mut self) -> CORE_1_FROM_ENTRY_1_W<CORE_1_STATUSTABLE1_SPEC> {
         CORE_1_FROM_ENTRY_1_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_1(&mut self) -> CORE_1_CURRENT_1_W<CORE_1_STATUSTABLE1_SPEC> {
         CORE_1_CURRENT_1_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable10.rs b/esp32s3/src/wcl/core_1_statustable10.rs
index 86ce8013a1..516e3cbd2a 100644
--- a/esp32s3/src/wcl/core_1_statustable10.rs
+++ b/esp32s3/src/wcl/core_1_statustable10.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_10(&mut self) -> CORE_1_FROM_WORLD_10_W<CORE_1_STATUSTABLE10_SPEC> {
         CORE_1_FROM_WORLD_10_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_10(&mut self) -> CORE_1_FROM_ENTRY_10_W<CORE_1_STATUSTABLE10_SPEC> {
         CORE_1_FROM_ENTRY_10_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 10"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_10(&mut self) -> CORE_1_CURRENT_10_W<CORE_1_STATUSTABLE10_SPEC> {
         CORE_1_CURRENT_10_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable11.rs b/esp32s3/src/wcl/core_1_statustable11.rs
index b22bae9595..94d343cecc 100644
--- a/esp32s3/src/wcl/core_1_statustable11.rs
+++ b/esp32s3/src/wcl/core_1_statustable11.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_11(&mut self) -> CORE_1_FROM_WORLD_11_W<CORE_1_STATUSTABLE11_SPEC> {
         CORE_1_FROM_WORLD_11_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_11(&mut self) -> CORE_1_FROM_ENTRY_11_W<CORE_1_STATUSTABLE11_SPEC> {
         CORE_1_FROM_ENTRY_11_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 11"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_11(&mut self) -> CORE_1_CURRENT_11_W<CORE_1_STATUSTABLE11_SPEC> {
         CORE_1_CURRENT_11_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable12.rs b/esp32s3/src/wcl/core_1_statustable12.rs
index 51eb882fae..34c2454550 100644
--- a/esp32s3/src/wcl/core_1_statustable12.rs
+++ b/esp32s3/src/wcl/core_1_statustable12.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_12(&mut self) -> CORE_1_FROM_WORLD_12_W<CORE_1_STATUSTABLE12_SPEC> {
         CORE_1_FROM_WORLD_12_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_12(&mut self) -> CORE_1_FROM_ENTRY_12_W<CORE_1_STATUSTABLE12_SPEC> {
         CORE_1_FROM_ENTRY_12_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 12"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_12(&mut self) -> CORE_1_CURRENT_12_W<CORE_1_STATUSTABLE12_SPEC> {
         CORE_1_CURRENT_12_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable13.rs b/esp32s3/src/wcl/core_1_statustable13.rs
index bca19d0efb..9831aaa0c7 100644
--- a/esp32s3/src/wcl/core_1_statustable13.rs
+++ b/esp32s3/src/wcl/core_1_statustable13.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_13(&mut self) -> CORE_1_FROM_WORLD_13_W<CORE_1_STATUSTABLE13_SPEC> {
         CORE_1_FROM_WORLD_13_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_13(&mut self) -> CORE_1_FROM_ENTRY_13_W<CORE_1_STATUSTABLE13_SPEC> {
         CORE_1_FROM_ENTRY_13_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 13"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_13(&mut self) -> CORE_1_CURRENT_13_W<CORE_1_STATUSTABLE13_SPEC> {
         CORE_1_CURRENT_13_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable2.rs b/esp32s3/src/wcl/core_1_statustable2.rs
index 6b86b37401..6fab25227c 100644
--- a/esp32s3/src/wcl/core_1_statustable2.rs
+++ b/esp32s3/src/wcl/core_1_statustable2.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_2(&mut self) -> CORE_1_FROM_WORLD_2_W<CORE_1_STATUSTABLE2_SPEC> {
         CORE_1_FROM_WORLD_2_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_2(&mut self) -> CORE_1_FROM_ENTRY_2_W<CORE_1_STATUSTABLE2_SPEC> {
         CORE_1_FROM_ENTRY_2_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 2"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_2(&mut self) -> CORE_1_CURRENT_2_W<CORE_1_STATUSTABLE2_SPEC> {
         CORE_1_CURRENT_2_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable3.rs b/esp32s3/src/wcl/core_1_statustable3.rs
index d315477c24..f3eda00236 100644
--- a/esp32s3/src/wcl/core_1_statustable3.rs
+++ b/esp32s3/src/wcl/core_1_statustable3.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_3(&mut self) -> CORE_1_FROM_WORLD_3_W<CORE_1_STATUSTABLE3_SPEC> {
         CORE_1_FROM_WORLD_3_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_3(&mut self) -> CORE_1_FROM_ENTRY_3_W<CORE_1_STATUSTABLE3_SPEC> {
         CORE_1_FROM_ENTRY_3_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 3"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_3(&mut self) -> CORE_1_CURRENT_3_W<CORE_1_STATUSTABLE3_SPEC> {
         CORE_1_CURRENT_3_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable4.rs b/esp32s3/src/wcl/core_1_statustable4.rs
index f8c01d98c4..9717d07993 100644
--- a/esp32s3/src/wcl/core_1_statustable4.rs
+++ b/esp32s3/src/wcl/core_1_statustable4.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_4(&mut self) -> CORE_1_FROM_WORLD_4_W<CORE_1_STATUSTABLE4_SPEC> {
         CORE_1_FROM_WORLD_4_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_4(&mut self) -> CORE_1_FROM_ENTRY_4_W<CORE_1_STATUSTABLE4_SPEC> {
         CORE_1_FROM_ENTRY_4_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 4"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_4(&mut self) -> CORE_1_CURRENT_4_W<CORE_1_STATUSTABLE4_SPEC> {
         CORE_1_CURRENT_4_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable5.rs b/esp32s3/src/wcl/core_1_statustable5.rs
index a7e7341f13..6495914bae 100644
--- a/esp32s3/src/wcl/core_1_statustable5.rs
+++ b/esp32s3/src/wcl/core_1_statustable5.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_5(&mut self) -> CORE_1_FROM_WORLD_5_W<CORE_1_STATUSTABLE5_SPEC> {
         CORE_1_FROM_WORLD_5_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_5(&mut self) -> CORE_1_FROM_ENTRY_5_W<CORE_1_STATUSTABLE5_SPEC> {
         CORE_1_FROM_ENTRY_5_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 5"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_5(&mut self) -> CORE_1_CURRENT_5_W<CORE_1_STATUSTABLE5_SPEC> {
         CORE_1_CURRENT_5_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable6.rs b/esp32s3/src/wcl/core_1_statustable6.rs
index 22409737b7..416b3e5c4c 100644
--- a/esp32s3/src/wcl/core_1_statustable6.rs
+++ b/esp32s3/src/wcl/core_1_statustable6.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_6(&mut self) -> CORE_1_FROM_WORLD_6_W<CORE_1_STATUSTABLE6_SPEC> {
         CORE_1_FROM_WORLD_6_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_6(&mut self) -> CORE_1_FROM_ENTRY_6_W<CORE_1_STATUSTABLE6_SPEC> {
         CORE_1_FROM_ENTRY_6_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 6"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_6(&mut self) -> CORE_1_CURRENT_6_W<CORE_1_STATUSTABLE6_SPEC> {
         CORE_1_CURRENT_6_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable7.rs b/esp32s3/src/wcl/core_1_statustable7.rs
index 035c8cbd8e..055149a69e 100644
--- a/esp32s3/src/wcl/core_1_statustable7.rs
+++ b/esp32s3/src/wcl/core_1_statustable7.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_7(&mut self) -> CORE_1_FROM_WORLD_7_W<CORE_1_STATUSTABLE7_SPEC> {
         CORE_1_FROM_WORLD_7_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_7(&mut self) -> CORE_1_FROM_ENTRY_7_W<CORE_1_STATUSTABLE7_SPEC> {
         CORE_1_FROM_ENTRY_7_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 7"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_7(&mut self) -> CORE_1_CURRENT_7_W<CORE_1_STATUSTABLE7_SPEC> {
         CORE_1_CURRENT_7_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable8.rs b/esp32s3/src/wcl/core_1_statustable8.rs
index 1038fba5fb..14452e4aab 100644
--- a/esp32s3/src/wcl/core_1_statustable8.rs
+++ b/esp32s3/src/wcl/core_1_statustable8.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_8(&mut self) -> CORE_1_FROM_WORLD_8_W<CORE_1_STATUSTABLE8_SPEC> {
         CORE_1_FROM_WORLD_8_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_8(&mut self) -> CORE_1_FROM_ENTRY_8_W<CORE_1_STATUSTABLE8_SPEC> {
         CORE_1_FROM_ENTRY_8_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 8"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_8(&mut self) -> CORE_1_CURRENT_8_W<CORE_1_STATUSTABLE8_SPEC> {
         CORE_1_CURRENT_8_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable9.rs b/esp32s3/src/wcl/core_1_statustable9.rs
index 26e2a97614..25ce7379ed 100644
--- a/esp32s3/src/wcl/core_1_statustable9.rs
+++ b/esp32s3/src/wcl/core_1_statustable9.rs
@@ -44,19 +44,16 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_world_9(&mut self) -> CORE_1_FROM_WORLD_9_W<CORE_1_STATUSTABLE9_SPEC> {
         CORE_1_FROM_WORLD_9_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - This filed is used to confirm in which entry before enter entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_from_entry_9(&mut self) -> CORE_1_FROM_ENTRY_9_W<CORE_1_STATUSTABLE9_SPEC> {
         CORE_1_FROM_ENTRY_9_W::new(self, 1)
     }
     #[doc = "Bit 5 - This bit is used to confirm whether the current state is in entry 9"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_current_9(&mut self) -> CORE_1_CURRENT_9_W<CORE_1_STATUSTABLE9_SPEC> {
         CORE_1_CURRENT_9_W::new(self, 5)
     }
diff --git a/esp32s3/src/wcl/core_1_statustable_current.rs b/esp32s3/src/wcl/core_1_statustable_current.rs
index e734dd41d0..6369ec5e7b 100644
--- a/esp32s3/src/wcl/core_1_statustable_current.rs
+++ b/esp32s3/src/wcl/core_1_statustable_current.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 1:13 - This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_statustable_current(
         &mut self,
     ) -> CORE_1_STATUSTABLE_CURRENT_W<CORE_1_STATUSTABLE_CURRENT_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_world_cancel.rs b/esp32s3/src/wcl/core_1_world_cancel.rs
index 3d9f9e4730..a5fb925db8 100644
--- a/esp32s3/src/wcl/core_1_world_cancel.rs
+++ b/esp32s3/src/wcl/core_1_world_cancel.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_CANCEL_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_world_cancel(&mut self) -> CORE_1_WORLD_CANCEL_W<CORE_1_WORLD_CANCEL_SPEC> {
         CORE_1_WORLD_CANCEL_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_world_dram0_pif.rs b/esp32s3/src/wcl/core_1_world_dram0_pif.rs
index e342e3cfb5..634afc0e7c 100644
--- a/esp32s3/src/wcl/core_1_world_dram0_pif.rs
+++ b/esp32s3/src/wcl/core_1_world_dram0_pif.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Dram0 bus and PIF bus"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_world_dram0_pif(
         &mut self,
     ) -> CORE_1_WORLD_DRAM0_PIF_W<CORE_1_WORLD_DRAM0_PIF_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_world_iram0.rs b/esp32s3/src/wcl/core_1_world_iram0.rs
index 4afb8419ef..fba2183c85 100644
--- a/esp32s3/src/wcl/core_1_world_iram0.rs
+++ b/esp32s3/src/wcl/core_1_world_iram0.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Iram0 bus"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_world_iram0(&mut self) -> CORE_1_WORLD_IRAM0_W<CORE_1_WORLD_IRAM0_SPEC> {
         CORE_1_WORLD_IRAM0_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_world_prepare.rs b/esp32s3/src/wcl/core_1_world_prepare.rs
index 8afee0e841..189c3e90a0 100644
--- a/esp32s3/src/wcl/core_1_world_prepare.rs
+++ b/esp32s3/src/wcl/core_1_world_prepare.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:1 - This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_world_prepare(&mut self) -> CORE_1_WORLD_PREPARE_W<CORE_1_WORLD_PREPARE_SPEC> {
         CORE_1_WORLD_PREPARE_W::new(self, 0)
     }
diff --git a/esp32s3/src/wcl/core_1_world_trigger_addr.rs b/esp32s3/src/wcl/core_1_world_trigger_addr.rs
index 65ffe9c0a9..8b07d71814 100644
--- a/esp32s3/src/wcl/core_1_world_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_1_world_trigger_addr.rs
@@ -27,7 +27,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_world_trigger_addr(
         &mut self,
     ) -> CORE_1_WORLD_TRIGGER_ADDR_W<CORE_1_WORLD_TRIGGER_ADDR_SPEC> {
diff --git a/esp32s3/src/wcl/core_1_world_update.rs b/esp32s3/src/wcl/core_1_world_update.rs
index 24b73ea60c..f892ab2927 100644
--- a/esp32s3/src/wcl/core_1_world_update.rs
+++ b/esp32s3/src/wcl/core_1_world_update.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_UPDATE_SPEC> {
 impl W {
     #[doc = "Bits 0:31 - This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value"]
     #[inline(always)]
-    #[must_use]
     pub fn core_1_update(&mut self) -> CORE_1_UPDATE_W<CORE_1_WORLD_UPDATE_SPEC> {
         CORE_1_UPDATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/date.rs b/esp32s3/src/xts_aes/date.rs
index af76386bc7..b8311d9821 100644
--- a/esp32s3/src/xts_aes/date.rs
+++ b/esp32s3/src/xts_aes/date.rs
@@ -22,7 +22,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Manual Encryption block version information."]
     #[inline(always)]
-    #[must_use]
     pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
         DATE_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/destination.rs b/esp32s3/src/xts_aes/destination.rs
index 550d09c1a2..ff10d887f6 100644
--- a/esp32s3/src/xts_aes/destination.rs
+++ b/esp32s3/src/xts_aes/destination.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
     #[inline(always)]
-    #[must_use]
     pub fn destination(&mut self) -> DESTINATION_W<DESTINATION_SPEC> {
         DESTINATION_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/destroy.rs b/esp32s3/src/xts_aes/destroy.rs
index 0f41ea092a..acee7344d8 100644
--- a/esp32s3/src/xts_aes/destroy.rs
+++ b/esp32s3/src/xts_aes/destroy.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<DESTROY_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to destroy encrypted result."]
     #[inline(always)]
-    #[must_use]
     pub fn destroy(&mut self) -> DESTROY_W<DESTROY_SPEC> {
         DESTROY_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/linesize.rs b/esp32s3/src/xts_aes/linesize.rs
index 3deadeb5fd..6bd4be3197 100644
--- a/esp32s3/src/xts_aes/linesize.rs
+++ b/esp32s3/src/xts_aes/linesize.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bit 0 - Configures the data size of one encryption."]
     #[inline(always)]
-    #[must_use]
     pub fn linesize(&mut self) -> LINESIZE_W<LINESIZE_SPEC> {
         LINESIZE_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/physical_address.rs b/esp32s3/src/xts_aes/physical_address.rs
index 40e7968868..664e0272fc 100644
--- a/esp32s3/src/xts_aes/physical_address.rs
+++ b/esp32s3/src/xts_aes/physical_address.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn physical_address(&mut self) -> PHYSICAL_ADDRESS_W<PHYSICAL_ADDRESS_SPEC> {
         PHYSICAL_ADDRESS_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/plain_.rs b/esp32s3/src/xts_aes/plain_.rs
index 18571b16f4..86e3826afd 100644
--- a/esp32s3/src/xts_aes/plain_.rs
+++ b/esp32s3/src/xts_aes/plain_.rs
@@ -24,7 +24,6 @@ impl core::fmt::Debug for R {
 impl W {
     #[doc = "Bits 0:31 - Stores the nth 32-bit piece of plaintext."]
     #[inline(always)]
-    #[must_use]
     pub fn plain(&mut self) -> PLAIN_W<PLAIN__SPEC> {
         PLAIN_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/release.rs b/esp32s3/src/xts_aes/release.rs
index 5109bfa19f..e161362a4e 100644
--- a/esp32s3/src/xts_aes/release.rs
+++ b/esp32s3/src/xts_aes/release.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<RELEASE_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to grant SPI1 access to encrypted result."]
     #[inline(always)]
-    #[must_use]
     pub fn release(&mut self) -> RELEASE_W<RELEASE_SPEC> {
         RELEASE_W::new(self, 0)
     }
diff --git a/esp32s3/src/xts_aes/trigger.rs b/esp32s3/src/xts_aes/trigger.rs
index ec3037f7de..0f164f3e85 100644
--- a/esp32s3/src/xts_aes/trigger.rs
+++ b/esp32s3/src/xts_aes/trigger.rs
@@ -11,7 +11,6 @@ impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
 impl W {
     #[doc = "Bit 0 - Write 1 to activate manual encryption."]
     #[inline(always)]
-    #[must_use]
     pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
         TRIGGER_W::new(self, 0)
     }
diff --git a/xtask/src/main.rs b/xtask/src/main.rs
index 249c97e8bb..7c6cd183c2 100644
--- a/xtask/src/main.rs
+++ b/xtask/src/main.rs
@@ -72,7 +72,7 @@ enum Commands {
 
     /// Generate the specified package(s)
     ///
-    /// Additionally patches the releavant SVD(s) prior to generating the
+    /// Additionally patches the relevant SVD(s) prior to generating the
     /// package(s).
     Generate {
         /// Package(s) to target
@@ -272,22 +272,13 @@ fn build_package(workspace: &Path, chip: &Chip) -> Result<()> {
 
     if target.starts_with("riscv") {
         Command::new("rustup")
-            .args([
-                "target",
-                "add",
-                &target,
-            ])
+            .args(["target", "add", &target])
             .current_dir(&path)
             .stdout(Stdio::inherit())
             .stderr(Stdio::inherit())
             .output()?;
         Command::new("cargo")
-            .args([
-                &format!("+{channel}"),
-                "build",
-                "--target",
-                &target,
-            ])
+            .args([&format!("+{channel}"), "build", "--target", &target])
             .current_dir(path)
             .stdout(Stdio::inherit())
             .stderr(Stdio::inherit())