strip _CH in AHB_DMA fields

esp32p4/src/ahb_dma/ch/in_conf0.rs

@@ -2,87 +2,84 @@
 pub type R = crate::R<IN_CONF0_SPEC>;
 #[doc = "Register `IN_CONF0` writer"]
 pub type W = crate::W<IN_CONF0_SPEC>;
-#[doc = "Field `IN_RST_CH` reader - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
-pub type IN_RST_CH_R = crate::BitReader;
-#[doc = "Field `IN_RST_CH` writer - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
-pub type IN_RST_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `IN_LOOP_TEST_CH` reader - reserved"]
-pub type IN_LOOP_TEST_CH_R = crate::BitReader;
-#[doc = "Field `IN_LOOP_TEST_CH` writer - reserved"]
-pub type IN_LOOP_TEST_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `INDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
-pub type INDSCR_BURST_EN_CH_R = crate::BitReader;
-#[doc = "Field `INDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
-pub type INDSCR_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `IN_DATA_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
-pub type IN_DATA_BURST_EN_CH_R = crate::BitReader;
-#[doc = "Field `IN_DATA_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
-pub type IN_DATA_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `MEM_TRANS_EN_CH` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
-pub type MEM_TRANS_EN_CH_R = crate::BitReader;
-#[doc = "Field `MEM_TRANS_EN_CH` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
-pub type MEM_TRANS_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `IN_ETM_EN_CH` reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
-pub type IN_ETM_EN_CH_R = crate::BitReader;
-#[doc = "Field `IN_ETM_EN_CH` writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
-pub type IN_ETM_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_RST` reader - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_R = crate::BitReader;
+#[doc = "Field `IN_RST` writer - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_LOOP_TEST` reader - reserved"]
+pub type IN_LOOP_TEST_R = crate::BitReader;
+#[doc = "Field `IN_LOOP_TEST` writer - reserved"]
+pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_R = crate::BitReader;
+#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_R = crate::BitReader;
+#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
+pub type MEM_TRANS_EN_R = crate::BitReader;
+#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
+pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_ETM_EN` reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
+pub type IN_ETM_EN_R = crate::BitReader;
+#[doc = "Field `IN_ETM_EN` writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
+pub type IN_ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
-    pub fn in_rst_ch(&self) -> IN_RST_CH_R {
-        IN_RST_CH_R::new((self.bits & 1) != 0)
+    pub fn in_rst(&self) -> IN_RST_R {
+        IN_RST_R::new((self.bits & 1) != 0)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
-    pub fn in_loop_test_ch(&self) -> IN_LOOP_TEST_CH_R {
-        IN_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0)
+    pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
+        IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
-    pub fn indscr_burst_en_ch(&self) -> INDSCR_BURST_EN_CH_R {
-        INDSCR_BURST_EN_CH_R::new(((self.bits >> 2) & 1) != 0)
+    pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
+        INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
     #[inline(always)]
-    pub fn in_data_burst_en_ch(&self) -> IN_DATA_BURST_EN_CH_R {
-        IN_DATA_BURST_EN_CH_R::new(((self.bits >> 3) & 1) != 0)
+    pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R {
+        IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0)
     }
     #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
     #[inline(always)]
-    pub fn mem_trans_en_ch(&self) -> MEM_TRANS_EN_CH_R {
-        MEM_TRANS_EN_CH_R::new(((self.bits >> 4) & 1) != 0)
+    pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
+        MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
     #[inline(always)]
-    pub fn in_etm_en_ch(&self) -> IN_ETM_EN_CH_R {
-        IN_ETM_EN_CH_R::new(((self.bits >> 5) & 1) != 0)
+    pub fn in_etm_en(&self) -> IN_ETM_EN_R {
+        IN_ETM_EN_R::new(((self.bits >> 5) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst_ch", &format_args!("{}", self.in_rst_ch().bit()))
+            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
             .field(
-                "in_loop_test_ch",
-                &format_args!("{}", self.in_loop_test_ch().bit()),
+                "in_loop_test",
+                &format_args!("{}", self.in_loop_test().bit()),
             )
             .field(
-                "indscr_burst_en_ch",
-                &format_args!("{}", self.indscr_burst_en_ch().bit()),
+                "indscr_burst_en",
+                &format_args!("{}", self.indscr_burst_en().bit()),
             )
             .field(
-                "in_data_burst_en_ch",
-                &format_args!("{}", self.in_data_burst_en_ch().bit()),
+                "in_data_burst_en",
+                &format_args!("{}", self.in_data_burst_en().bit()),
             )
             .field(
-                "mem_trans_en_ch",
-                &format_args!("{}", self.mem_trans_en_ch().bit()),
-            )
-            .field(
-                "in_etm_en_ch",
-                &format_args!("{}", self.in_etm_en_ch().bit()),
+                "mem_trans_en",
+                &format_args!("{}", self.mem_trans_en().bit()),
             )
+            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
             .finish()
     }
 }
@@ -96,38 +93,38 @@ impl W {
     #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
     #[must_use]
-    pub fn in_rst_ch(&mut self) -> IN_RST_CH_W<IN_CONF0_SPEC> {
-        IN_RST_CH_W::new(self, 0)
+    pub fn in_rst(&mut self) -> IN_RST_W<IN_CONF0_SPEC> {
+        IN_RST_W::new(self, 0)
     }
     #[doc = "Bit 1 - reserved"]
     #[inline(always)]
     #[must_use]
-    pub fn in_loop_test_ch(&mut self) -> IN_LOOP_TEST_CH_W<IN_CONF0_SPEC> {
-        IN_LOOP_TEST_CH_W::new(self, 1)
+    pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<IN_CONF0_SPEC> {
+        IN_LOOP_TEST_W::new(self, 1)
     }
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
     #[inline(always)]
     #[must_use]
-    pub fn indscr_burst_en_ch(&mut self) -> INDSCR_BURST_EN_CH_W<IN_CONF0_SPEC> {
-        INDSCR_BURST_EN_CH_W::new(self, 2)
+    pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<IN_CONF0_SPEC> {
+        INDSCR_BURST_EN_W::new(self, 2)
     }
     #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
     #[inline(always)]
     #[must_use]
-    pub fn in_data_burst_en_ch(&mut self) -> IN_DATA_BURST_EN_CH_W<IN_CONF0_SPEC> {
-        IN_DATA_BURST_EN_CH_W::new(self, 3)
+    pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<IN_CONF0_SPEC> {
+        IN_DATA_BURST_EN_W::new(self, 3)
     }
     #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA."]
     #[inline(always)]
     #[must_use]
-    pub fn mem_trans_en_ch(&mut self) -> MEM_TRANS_EN_CH_W<IN_CONF0_SPEC> {
-        MEM_TRANS_EN_CH_W::new(self, 4)
+    pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<IN_CONF0_SPEC> {
+        MEM_TRANS_EN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."]
     #[inline(always)]
     #[must_use]
-    pub fn in_etm_en_ch(&mut self) -> IN_ETM_EN_CH_W<IN_CONF0_SPEC> {
-        IN_ETM_EN_CH_W::new(self, 5)
+    pub fn in_etm_en(&mut self) -> IN_ETM_EN_W<IN_CONF0_SPEC> {
+        IN_ETM_EN_W::new(self, 5)
     }
 }
 #[doc = "Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]

esp32p4/src/ahb_dma/ch/in_conf1.rs

@@ -2,24 +2,24 @@
 pub type R = crate::R<IN_CONF1_SPEC>;
 #[doc = "Register `IN_CONF1` writer"]
 pub type W = crate::W<IN_CONF1_SPEC>;
-#[doc = "Field `IN_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
-pub type IN_CHECK_OWNER_CH_R = crate::BitReader;
-#[doc = "Field `IN_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
-pub type IN_CHECK_OWNER_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_R = crate::BitReader;
+#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
-    pub fn in_check_owner_ch(&self) -> IN_CHECK_OWNER_CH_R {
-        IN_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0)
+    pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R {
+        IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
             .field(
-                "in_check_owner_ch",
-                &format_args!("{}", self.in_check_owner_ch().bit()),
+                "in_check_owner",
+                &format_args!("{}", self.in_check_owner().bit()),
             )
             .finish()
     }
@@ -34,8 +34,8 @@ impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
     #[must_use]
-    pub fn in_check_owner_ch(&mut self) -> IN_CHECK_OWNER_CH_W<IN_CONF1_SPEC> {
-        IN_CHECK_OWNER_CH_W::new(self, 12)
+    pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<IN_CONF1_SPEC> {
+        IN_CHECK_OWNER_W::new(self, 12)
     }
 }
 #[doc = "Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]

esp32p4/src/ahb_dma/ch/in_dscr.rs

@@ -1,21 +1,21 @@
 #[doc = "Register `IN_DSCR` reader"]
 pub type R = crate::R<IN_DSCR_SPEC>;
-#[doc = "Field `INLINK_DSCR_CH` reader - The address of the current inlink descriptor x."]
-pub type INLINK_DSCR_CH_R = crate::FieldReader<u32>;
+#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."]
+pub type INLINK_DSCR_R = crate::FieldReader<u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the current inlink descriptor x."]
     #[inline(always)]
-    pub fn inlink_dscr_ch(&self) -> INLINK_DSCR_CH_R {
-        INLINK_DSCR_CH_R::new(self.bits)
+    pub fn inlink_dscr(&self) -> INLINK_DSCR_R {
+        INLINK_DSCR_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
             .field(
-                "inlink_dscr_ch",
-                &format_args!("{}", self.inlink_dscr_ch().bits()),
+                "inlink_dscr",
+                &format_args!("{}", self.inlink_dscr().bits()),
             )
             .finish()
     }

esp32p4/src/ahb_dma/ch/in_dscr_bf0.rs

@@ -1,21 +1,21 @@
 #[doc = "Register `IN_DSCR_BF0` reader"]
 pub type R = crate::R<IN_DSCR_BF0_SPEC>;
-#[doc = "Field `INLINK_DSCR_BF0_CH` reader - The address of the last inlink descriptor x-1."]
-pub type INLINK_DSCR_BF0_CH_R = crate::FieldReader<u32>;
+#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."]
+pub type INLINK_DSCR_BF0_R = crate::FieldReader<u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."]
     #[inline(always)]
-    pub fn inlink_dscr_bf0_ch(&self) -> INLINK_DSCR_BF0_CH_R {
-        INLINK_DSCR_BF0_CH_R::new(self.bits)
+    pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R {
+        INLINK_DSCR_BF0_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
             .field(
-                "inlink_dscr_bf0_ch",
-                &format_args!("{}", self.inlink_dscr_bf0_ch().bits()),
+                "inlink_dscr_bf0",
+                &format_args!("{}", self.inlink_dscr_bf0().bits()),
             )
             .finish()
     }

esp32p4/src/ahb_dma/ch/in_dscr_bf1.rs

@@ -1,21 +1,21 @@
 #[doc = "Register `IN_DSCR_BF1` reader"]
 pub type R = crate::R<IN_DSCR_BF1_SPEC>;
-#[doc = "Field `INLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."]
-pub type INLINK_DSCR_BF1_CH_R = crate::FieldReader<u32>;
+#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."]
+pub type INLINK_DSCR_BF1_R = crate::FieldReader<u32>;
 impl R {
     #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."]
     #[inline(always)]
-    pub fn inlink_dscr_bf1_ch(&self) -> INLINK_DSCR_BF1_CH_R {
-        INLINK_DSCR_BF1_CH_R::new(self.bits)
+    pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R {
+        INLINK_DSCR_BF1_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
             .field(
-                "inlink_dscr_bf1_ch",
-                &format_args!("{}", self.inlink_dscr_bf1_ch().bits()),
+                "inlink_dscr_bf1",
+                &format_args!("{}", self.inlink_dscr_bf1().bits()),
             )
             .finish()
     }

esp32p4/src/ahb_dma/ch/in_err_eof_des_addr.rs

@@ -1,21 +1,21 @@
 #[doc = "Register `IN_ERR_EOF_DES_ADDR` reader"]
 pub type R = crate::R<IN_ERR_EOF_DES_ADDR_SPEC>;
-#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
-pub type IN_ERR_EOF_DES_ADDR_CH_R = crate::FieldReader<u32>;
+#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
+pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader<u32>;
 impl R {
     #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
     #[inline(always)]
-    pub fn in_err_eof_des_addr_ch(&self) -> IN_ERR_EOF_DES_ADDR_CH_R {
-        IN_ERR_EOF_DES_ADDR_CH_R::new(self.bits)
+    pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R {
+        IN_ERR_EOF_DES_ADDR_R::new(self.bits)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
             .field(
-                "in_err_eof_des_addr_ch",
-                &format_args!("{}", self.in_err_eof_des_addr_ch().bits()),
+                "in_err_eof_des_addr",
+                &format_args!("{}", self.in_err_eof_des_addr().bits()),
             )
             .finish()
     }